Josephson junction element and method for manufacturing the same

Abstract

To improve the characteristics of Josephson junction elements. [Solution] The Josephson junction element comprises a first superconducting layer, a second superconducting layer located on the first superconducting layer, an insulating layer located between the first superconducting layer and the second superconducting layer, and a first capping layer located between the insulating layer and the second superconducting layer, which has superconductivity and oxidation resistance.

Description

Technical Field

[0001] The present invention relates to a Josephson junction device and a method for manufacturing the same.

Background Art

[0002] A Josephson junction device is a superconducting device and has attracted attention as an arithmetic element of a superconducting quantum computer. Various methods for improving the characteristics (for example, coherence time) of the Josephson junction device have been proposed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to a first aspect of the disclosure, a Josephson junction device includes a first superconducting layer, a second superconducting layer located above the first superconducting layer, an insulating layer located between the first superconducting layer and the second superconducting layer, and a first cap layer located between the insulating layer and the second superconducting layer and having superconductivity and oxidation resistance.

[0005] According to a second aspect of the disclosure, a method for manufacturing a Josephson junction device includes forming a first superconducting layer on a substrate, forming an insulating layer on the first superconducting layer, and forming a first cap layer having superconductivity and oxidation resistance on the insulating layer, wherein forming the first superconducting layer, forming the insulating layer, and forming the first cap layer are continuously performed in an environment in which a pressure lower than atmospheric pressure is maintained in the same chamber.

[0006] Furthermore, the configuration of the embodiments described later may be modified as appropriate, and at least a part of it may be replaced with other components. Moreover, the configuration elements whose arrangement is not particularly limited may be arranged in positions that can achieve their function, not limited to the arrangement disclosed in the embodiments. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1(A) is a perspective view of the Josephson junction element according to the first embodiment, Figure 1(B) is a plan view of the Josephson junction element according to the first embodiment, and Figure 1(C) is a cross-sectional view taken along line AA of Figure 1(B). [Figure 2] Figure 2 is a flowchart showing a method for manufacturing a Josephson junction element according to the first embodiment. [Figure 3] Figures 3(A) and 3(B) are diagrams (part 1) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 4] Figures 4(A) and 4(B) are diagrams (part 2) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 5] Figures 5(A) and 5(B) are diagrams (part 3) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 6] Figures 6(A) and 6(B) are diagrams (part 4) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 7] Figures 7(A) and 7(B) are diagrams (part 5) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 8] Figures 8(A) and 8(B) are diagrams (part 6) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 9] Figures 9(A) and 9(B) are diagrams (part 7) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 10]Figures 10(A) and 10(B) are diagrams (number 8) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 11] Figures 11(A) and 11(B) are diagrams (the ninth of their kind) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 12] Figures 12(A) and 12(B) are diagrams (number 10) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 13] Figures 13(A) and 13(B) are diagrams (number 11) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 14] Figures 14(A) and 14(B) are diagrams (the 12th of their kind) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 15] Figures 15(A) and 15(B) are diagrams (part 13) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 16] Figures 16(A) and 16(B) are diagrams (number 14) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 17] Figures 17(A) and 17(B) are diagrams (number 15) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 18] Figures 18(A) and 18(B) are diagrams (number 16) illustrating the manufacturing process of a Josephson junction element according to the first embodiment. [Figure 19] Figure 19 is a cross-sectional TEM (transmission electron microscope) image of a Josephson junction element manufactured by the manufacturing method according to the first embodiment. [Figure 20] Figure 20 is a graph showing the room-temperature resistance value as a function of the Josephson junction area for a Josephson junction element manufactured by the manufacturing method according to the first embodiment. [Figure 21] Figure 21(A) is a perspective view of a Josephson junction element according to a comparative example, and Figure 21(B) is a cross-sectional view of Figure 21(A) along line AA. [Figure 22] Figures 22(A) and 22(B) are diagrams (Part 1) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 23] Figures 23(A) and 23(B) are diagrams (Part 2) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 24] Figures 24(A) and 24(B) are diagrams (Part 3) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 25] Figures 25(A) and 25(B) are diagrams (Part 4) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 26] Figures 26(A) and 26(B) are diagrams (Part 5) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 27] Figures 27(A) and 27(B) are diagrams (Part 6) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 28] Figures 28(A) and 28(B) are diagrams (Part 7) for explaining a method of manufacturing a Josephson junction device according to a comparative example. [Figure 29] Figure 29(A) is a surface SEM (scanning electron microscope) image of a Josephson junction device manufactured by the manufacturing method according to the first embodiment, and Figure 29(B) is a surface SEM image of a Josephson junction device manufactured by the manufacturing method according to the comparative example. [Figure 30] Figure 30(A) is a cross-sectional view showing the configuration of a Josephson junction device according to Modification 1, and Figure 30(B) is a cross-sectional view showing the configuration of a Josephson junction device according to Modification 2. [Figure 31] Figure 31(A) is a perspective view of a Josephson junction device according to the second embodiment, Figure 31(B) is a plan view of the Josephson junction device according to the second embodiment, and Figure 31(C) is a cross-sectional view taken along line A-A of Figure 31(B). [Figure 32] Figure 32 is a flowchart showing a method of manufacturing a Josephson junction device according to the second embodiment. [Modes for carrying out the invention]

[0008] 《First Embodiment》 The configuration of the Josephson junction element 100 according to the first embodiment will be described with reference to Figures 1(A) to 1(C). Figure 1(A) is a perspective view of the Josephson junction element according to the first embodiment, Figure 1(B) is a plan view of the Josephson junction element according to the first embodiment, and Figure 1(C) is a cross-sectional view taken along line AA of Figure 1(B). In Figures 1(A) to 1(C), the direction perpendicular to the surface of the substrate 10 is defined as the Z direction, and the two perpendicular directions within the plane perpendicular to the Z direction are defined as the X direction and the Y direction. The same applies to subsequent figures.

[0009] The Josephson junction element 100 comprises a laminate 20, a second superconducting layer 31, and a second capping layer 32.

[0010] As shown in Figure 1(A), the laminate 20 is located on the substrate 10. The substrate 10 is, for example, a silicon (Si) or sapphire (Al2O3) substrate. In Figures 1(A) and 1(C), the laminate 20 is in contact with the substrate 10, but other materials (e.g., an insulating layer) may be provided between the substrate 10 and the laminate 20. The material provided between the substrate 10 and the laminate 20 is preferably an insulator and not a dielectric.

[0011] As shown in Figure 1(A), the laminate 20 is formed to extend in a direction (Y direction) perpendicular to the stacking direction (Z direction) of the first superconducting layer 21, the insulating layer 22, and the first capping layer 23.

[0012] As shown in Figure 1(C), the laminate 20 comprises a first superconducting layer 21 located on the substrate 10, an insulating layer 22 located between the first superconducting layer 21 and the second superconducting layer 31, and a first cap layer 23 located between the insulating layer 22 and the second superconducting layer 31. The first superconducting layer 21, the insulating layer 22, and the first cap layer 23 are laminated in order from the substrate 10 side, and the uppermost layer of the laminate 20 is the first cap layer 23. In this embodiment, the first cap layer 23 is in contact with the insulating layer 22.

[0013] The first superconducting layer 21 contains a superconducting material and is superconducting. The first superconducting layer 21 is, for example, an aluminum (Al) film. The first superconducting layer 21 has a film thickness of, for example, 30 nm to 100 nm. A native oxide film 25 of the first superconducting layer 21 is formed on the side surface of the first superconducting layer 21. In Figure 1(A), the native oxide film 25 formed on the side surface of the first superconducting layer 21 is shown by hatching.

[0014] The insulating layer 22 is made of, for example, aluminum oxide (Al2O x The film is, for example, 1 nm to 6 nm thick. The insulating layer 22 is an artificial oxide film formed by artificially oxidizing the first superconducting layer 21.

[0015] The first cap layer 23 has superconductivity and oxidation resistance. The oxidation resistance of the first cap layer 23 is higher than that of the first superconducting layer 21. As a result, the first cap layer 23 covers the upper surface of the first superconducting layer 21 via the insulating layer 22, thereby suppressing spontaneous oxidation of the upper surface of the first superconducting layer 21. The first cap layer 23 is, for example, a titanium (Ti) film, a titanium nitride (TiN) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, or a platinum (Pt) film, and has a thickness of, for example, 0.5 nm to 5 nm. However, the thickness of the first cap layer 23 is not limited to this, and any thickness that does not change the physical properties of the superconducting material contained in the second superconducting layer 31, or does not affect the physical properties of the superconducting material contained in the second superconducting layer 31, is acceptable. Alternatively, any thickness that does not affect the operation of the Josephson junction element 100 as a qubit is acceptable.

[0016] The second superconducting layer 31 is formed extending in the X direction intersecting the Y direction and in contact with a portion of the upper surface of the laminate 20. Specifically, in this embodiment, the second superconducting layer 31 is in contact with a portion of the upper surface of the first cap layer 23 of the laminate 20.

[0017] Furthermore, the second superconducting layer 31 is in contact with the upper surface of the substrate 10. As a result, a space (void) SP is formed between the laminate 20, the second superconducting layer 31, and the substrate 10. Due to the space SP, the second superconducting layer 31 does not come into contact with the side surface of the laminate 20. In other words, the native oxide film 25 formed on the side surface of the first superconducting layer 21 does not come into contact with the second superconducting layer 31. This allows the insulating layer 22 to function as a tunnel barrier.

[0018] The second superconducting layer 31 contains a superconducting material and is superconducting. The second superconducting layer 31 is, for example, an aluminum (Al) film. The second superconducting layer 31 has a film thickness of, for example, 30 nm to 100 nm. Here, the film thickness of the second superconducting layer 31 is the thickness of the second superconducting layer 31 formed on the first cap layer 23. From the viewpoint of suppressing disconnection of the second superconducting layer 31, it is preferable that the film thickness of the second superconducting layer 31 is greater than the film thickness of the first superconducting layer 21.

[0019] The second cap layer 32 is located on the second superconducting layer 31 and has oxidation resistance. The oxidation resistance of the second cap layer 32 is stronger than that of the second superconducting layer 31. The second cap layer 32 is, for example, a titanium (Ti) film, a titanium nitride (TiN) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, or a platinum (Pt) film, and has a thickness of, for example, 0.5 nm to 5 nm. The oxidation resistance of the second cap layer 32 may be the same as or different from that of the first cap layer 23. Since the second cap layer 32 covers the upper surface of the second superconducting layer 31, spontaneous oxidation of the upper surface of the second superconducting layer 31 can be suppressed. Note that another material (for example, another superconducting layer) may be provided between the second superconducting layer 31 and the second cap layer 32.

[0020] As described in detail above, the Josephson junction element 100 according to the first embodiment comprises a first superconducting layer 21, a second superconducting layer 31 located on the first superconducting layer 21, an insulating layer 22 located between the first superconducting layer 21 and the second superconducting layer 31, and a first cap layer 23 located between the insulating layer 22 and the second superconducting layer 31, which has superconductivity and oxidation resistance. As a result, the first cap layer 23 can suppress the spontaneous oxidation of the first superconducting layer 21.

[0021] Furthermore, in the first embodiment, the Josephson junction element 100 has a laminate 20 formed by stacking a first superconducting layer 21, an insulating layer 22, and a first capping layer 23 in that order, and extending in the Y direction perpendicular to the stacking direction. The second superconducting layer 31 is formed extending in the X direction, contacting a part of the upper surface of the laminate 20 but not contacting the side surface of the laminate 20. Since the second superconducting layer 31 does not contact the native oxide film 25 formed on the side surface of the first superconducting layer 21, the insulating layer 22 can function as a tunnel barrier, and a Josephson junction can be formed in the portion where a part of the upper surface of the laminate 20 and the second superconducting layer 31 are in contact.

[0022] Furthermore, in the first embodiment, the Josephson junction element 100 further comprises a substrate 10, the laminate 20 is located on the substrate 10, the second superconducting layer 31 is in contact with the upper surface of the substrate 10, and a space SP is formed by the laminate 20, the second superconducting layer 31 and the substrate 10. This prevents the second superconducting layer 31 from contacting the side surface of the laminate 20, allowing the insulating layer 22 to function as a tunnel barrier, and enabling the Josephson junction element 100 to operate as a Josephson junction.

[0023] Furthermore, in the first embodiment, the Josephson junction element 100 is located on the second superconducting layer 31 and includes a second cap layer 32 that is oxidation-resistant. This makes it possible to suppress the spontaneous oxidation of the second superconducting layer 31.

[0024] Furthermore, in the first embodiment, the thickness of the first cap layer 23 is 5 nanometers or less. This allows the physical properties of the superconducting material in the second superconducting layer 31 to be maintained.

[0025] (Manufacturing method) Next, a method for manufacturing the Josephson junction element 100 according to the first embodiment will be described. Figure 2 is a flowchart illustrating the method for manufacturing the Josephson junction element 100 according to the first embodiment. Figures 3(A) to 18(B) are diagrams illustrating the manufacturing process of the Josephson junction element 100 according to the first embodiment. Figures 3(B) to 18(B) are cross-sectional views along line AA of Figures 3(A) to 18(A), respectively.

[0026] First, a laminate 20 is formed on the substrate 10 (step S10). Specifically, as shown in Figures 3(A) and 3(B), a first superconducting layer 21 with a thickness of, for example, 30 nm to 100 nm is formed on the substrate 10 (Figure 2: step S11). The first superconducting layer 21 is deposited by sputtering in the chamber of a sputtering apparatus. At this time, the pressure inside the chamber is set to a pressure lower than atmospheric pressure (vacuum state). As a result, there is less oxygen inside the chamber, which suppresses spontaneous oxidation of the surface of the first superconducting layer 21.

[0027] Next, as shown in Figures 4(A) and 4(B), an insulating layer 22 is formed on the first superconducting layer 21 (Figure 2: Step S12). The insulating layer 22 is formed by introducing oxygen (O2) gas into the sputtering chamber and artificially oxidizing the surface of the first superconducting layer 21, without removing the substrate 10 on which the first superconducting layer 21 is formed from outside the sputtering chamber (while it remains in the sputtering chamber maintained at a pressure lower than atmospheric pressure). The oxygen gas pressure is, for example, 1.5 Pa to 600 Pa, and the oxidation time is, for example, 5 to 10 minutes, but is not limited to these values. The oxygen gas pressure and oxidation time should be determined according to the specifications of the sputtering apparatus so that the resistance value of the Josephson junction at room temperature is in the range of approximately 4,000 Ω to 12,000 Ω.

[0028] Next, as shown in Figures 5(A) and 5(B), a first cap layer 23 with a thickness of 0.5 nm to 5 nm is formed on the insulating layer 22 (Figure 2: Step S13). The first cap layer 23 is deposited by sputtering without removing the substrate 10 on which the first superconducting layer 21 and the insulating layer 22 are formed from the sputtering apparatus (while it remains in the sputtering apparatus chamber, which is maintained at a pressure lower than atmospheric pressure). At this time, the pressure inside the chamber is set to a pressure lower than atmospheric pressure.

[0029] By forming the first cap layer 23, spontaneous oxidation of the upper surface of the first superconducting layer 21 can be suppressed.

[0030] Thus, the formation of the first superconducting layer 21, the insulating layer 22, and the first capping layer 23 is carried out continuously within the same chamber while maintaining a pressure lower than atmospheric pressure. In other words, the formation of the first superconducting layer 21, the insulating layer 22, and the first capping layer 23 is carried out without removing the substrate 10 from the chamber.

[0031] Next, the first superconducting layer 21, the insulating layer 22, and the first cap layer 23 are patterned (Figure 2: Step S14). Specifically, the substrate 10 on which the first superconducting layer 21, the insulating layer 22, and the first cap layer 23 are formed is removed from the chamber of the sputtering apparatus, a resist is applied to the first cap layer 23, and a resist layer 50 is formed on the first cap layer 23 as shown in Figures 6(A) and 6(B). Next, the resist layer 50 is exposed to light using, for example, an ArF line, a KrF line, or an i line to transfer a linear pattern extending in the Y direction to the resist layer 50. For example, an immersion lithography apparatus can be used to expose the resist layer 50.

[0032] Subsequently, as shown in Figures 7(A) and 7(B), the resist layer 50 is developed, and then, as shown in Figures 8(A) and 8(B), the first superconducting layer 21, the insulating layer 22, and the first cap layer 23 are etched using the resist layer 50 as a mask. As a result, the first superconducting layer 21, the insulating layer 22, and the first cap layer 23 are patterned in a linear shape extending in the Y direction.

[0033] Subsequently, as shown in Figures 9(A) and 9(B), the resist layer 50 is removed, for example, using an ashing device. Through these steps, the laminate 20 is formed.

[0034] The first superconducting layer 21, the insulating layer 22, and the first capping layer 23 are patterned in a linear shape extending in the Y direction. During the period between this patterning and the removal of the resist layer 50 using an ashing device, the substrate 10 moves through the atmosphere. As a result, the side surface of the first superconducting layer 21 undergoes spontaneous oxidation, and a native oxide film 25 is formed on the side surface of the first superconducting layer 21, as shown in Figure 9(B). If the second superconducting layer 31 comes into contact with the native oxide film 25, the insulating layer 22 will cease to function as a tunnel barrier. Therefore, in this embodiment, a sacrificial layer 40 is formed to prevent contact between the side surface of the laminate 20 (native oxide film 25) and the second superconducting layer 31.

[0035] After the formation of the laminate 20, a sacrificial layer 40 is formed that contacts the substrate 10 and the side surface of the laminate 20 (Figure 2: Step S20). Specifically, first, the sacrificial layer 40 is formed as shown in Figures 10(A) and 10(B). The sacrificial layer 40 is, for example, a silicon oxide (SiO2) film or a silicon nitride (SiN) film. The sacrificial layer 40 can be formed, for example, by chemical vapor deposition, sputtering, or TEOS (tetraethoxysilane).

[0036] Subsequently, as shown in Figures 11(A) and 11(B), the sacrificial layer 40 is removed, for example, by inductively coupled plasma reactive ion etching (ICP-RIE), so that the upper surface of the first cap layer 23 is exposed. This forms a sacrificial layer 40 that contacts the substrate 10 and the side surface of the laminate 20, as shown in Figure 11(B). Note that the sacrificial layer 40 only needs to be in contact with at least the side surface of the first superconducting layer 21 of the laminate 20.

[0037] Next, the second superconducting layer 31 is formed (Figure 2: Step S30). Specifically, as shown in Figures 12(A) and 12(B), the second superconducting layer 31 with a thickness of 30 nm to 100 nm is formed on the substrate 10, the sacrificial layer 40, and the first cap layer 23. The second superconducting layer 31 is deposited by sputtering in the chamber of a sputtering apparatus. At this time, the pressure inside the chamber is set to a pressure lower than atmospheric pressure.

[0038] Next, without removing the substrate 10 from the chamber of the sputtering apparatus, a second cap layer 32 with a thickness of 0.5 nm to 5 nm is formed as shown in Figures 13(A) and 13(B) (Figure 2: Step S40). The second cap layer 32 is deposited by sputtering inside the chamber of the sputtering apparatus. At this time, the pressure inside the chamber is set to a pressure lower than atmospheric pressure. The second cap layer 32 can suppress the spontaneous oxidation of the second superconducting layer 31. The sputtering apparatus used to form the second superconducting layer 31 and the second cap layer 32 may be the same as or different from the sputtering apparatus used to form the first superconducting layer 21, the insulating layer 22, and the first cap layer 23.

[0039] Subsequently, the substrate 10 is removed from the sputtering apparatus chamber, and a resist layer 51 is formed on the second cap layer 32 as shown in Figures 14(A) and 14(B). Next, the resist layer 51 is exposed to light using, for example, an ArF line, a KrF line, or an i line, to transfer a linear pattern extending in the X direction to the resist layer 51. For example, an immersion lithography apparatus can be used to expose the resist layer 51.

[0040] Subsequently, as shown in Figures 15(A) and 15(B), the resist layer 51 is developed, and then, as shown in Figures 16(A) and 16(B), the second superconducting layer 31 and the second cap layer 32 are etched using the resist layer 51 as a mask. As a result, the second superconducting layer 31 and the second cap layer 32 are patterned in a linear shape extending in the X direction.

[0041] Subsequently, as shown in Figures 17(A) and 17(B), the resist layer 51 is removed, for example, using an ashing apparatus. Through these steps, a second superconducting layer 31 is formed that contacts the substrate 10, the sacrificial layer 40, and the first cap layer 23 and extends in the X direction.

[0042] Next, the sacrificial layer 40 is removed (Figure 2: Step S50). Specifically, the sacrificial layer 40 is etched using hydrogen fluoride (HF) vapor or buffered hydrogen fluoride (BHF). As a result, as shown in Figures 18(A) and 18(B), a space (void) SP is formed between the side surface of the laminate 20 and the second superconducting layer 31, preventing contact between the side surface of the laminate 20 and the second superconducting layer 31.

[0043] Through the above process, the Josephson junction element 100 according to the first embodiment is completed.

[0044] Figure 19 is a cross-sectional TEM (transmission electron microscope) image of a Josephson junction element manufactured by the manufacturing method according to the first embodiment. As shown in Figure 19, it was confirmed that a space is formed between the side surface of the laminate 20 (first superconducting layer 21) and the second superconducting layer 31 by the manufacturing method according to the first embodiment.

[0045] The room-temperature resistance of a Josephson junction element manufactured by the manufacturing method according to the first embodiment was measured. Figure 20 is a graph showing the room-temperature resistance of a Josephson junction element manufactured by the manufacturing method according to the first embodiment as a function of the Josephson junction area. In Figure 20, the horizontal axis represents the Josephson junction area of ​​the Josephson junction element, and the vertical axis represents the measured value of the room-temperature resistance. Black circles indicate measured values, and the curves indicate approximate curves.

[0046] If S is the Josephson junction area of ​​a Josephson junction, ρ is the resistivity, and d is the thickness of the tunnel barrier, then the room-temperature resistance R of the Josephson junction is expressed by the following formula. R = ρd / S

[0047] As shown in Figure 20, the measured room-temperature resistance of the Josephson junction element manufactured by the manufacturing method according to the first embodiment changes inversely proportional to the Josephson junction area, satisfying the above equation. This confirms that the Josephson junction element manufactured by the manufacturing method according to the first embodiment functions as a Josephson junction.

[0048] (Comparative example) Next, a Josephson junction element 1000 relating to a comparative example will be described. Figure 21(A) is a perspective view of the Josephson junction element 1000 relating to a comparative example, and Figure 21(B) is a cross-sectional view taken along line AA of Figure 21(A).

[0049] As shown in Figures 21(A) and 21(B), the Josephson junction element 1000 comprises a laminate 200 and a second superconducting layer 31.

[0050] As shown in Figure 21(B), the laminate 200 is provided on a substrate 10 which is a silicon (Si) substrate. As shown in Figure 21(B), the laminate 200 comprises a first superconducting layer 21 provided on the substrate 10 and an insulating layer 22 provided on the first superconducting layer 21.

[0051] The first superconducting layer 21 contains a superconducting material and is superconducting. The first superconducting layer 21 is, for example, an aluminum (Al) film with a thickness of 30 nm to 100 nm.

[0052] The insulating layer 22 is made of, for example, aluminum oxide (Al2O x The insulating layer is a film, for example, having a thickness of 2 nm to 3 nm. The insulating layer 22 in the comparative example differs from the insulating layer 22 of the first embodiment in that it covers the upper and side surfaces of the first superconducting layer 21. The insulating layer 22 is not a naturally occurring oxide film, but an oxide film formed by artificially oxidizing the first superconducting layer 21. Therefore, unlike a naturally occurring oxide film, the insulating layer 22, being an artificial oxide film, functions as a tunnel barrier.

[0053] The second superconducting layer 31 is formed extending in the X direction and is in contact with a portion of the substrate 10 and a portion of the insulating layer 22. The second superconducting layer 31 contains a superconducting material and is superconducting. The second superconducting layer 31 is, for example, an aluminum (Al) film with a thickness of 30 nm to 100 nm.

[0054] Next, a method for manufacturing the Josephson junction element 1000 according to the comparative example will be described. Figures 22(A) to 28(B) illustrate the method for manufacturing the Josephson junction element according to the comparative example.

[0055] In the manufacturing method of the comparative example, first, as shown in Figure 22(A), a first superconducting layer 21 with a thickness of, for example, 30 nm to 100 nm is formed on the substrate 10. The first superconducting layer 21 is deposited by sputtering in the chamber of a sputtering apparatus. At this time, the pressure inside the chamber is set to a pressure lower than atmospheric pressure.

[0056] Next, the substrate 10 is removed from the sputtering chamber. At this time, the upper surface of the first superconducting layer 21 undergoes spontaneous oxidation. In Figure 22(B), the surface of the spontaneously oxidized first superconducting layer 21 is shown with hatching. The same applies to Figures 23(B) and 24(B).

[0057] Next, as shown in Figure 23(A), a resist layer 50 is formed on the first superconducting layer 21. Then, the resist layer 50 is exposed to light, for example, an ArF line, a KrF line, or an i line, to transfer a linear pattern extending in the Y direction to the resist layer 50. For example, an immersion lithography apparatus can be used to expose the resist layer 50.

[0058] Subsequently, as shown in Figure 23(B), the resist layer 50 is developed, and then, as shown in Figure 24(A), the first superconducting layer 21 is etched using the resist layer 50 as a mask. This results in the first superconducting layer 21 being patterned in a linear shape extending in the Y direction.

[0059] Subsequently, as shown in Figure 24(B), the resist layer 50 is removed, for example, by an ashing apparatus. At this time, the sides of the first superconducting layer 21 undergo spontaneous oxidation. Since the spontaneous oxide film formed on the surface of the first superconducting layer 21 does not function as a tunnel barrier, the spontaneous oxide film is removed, for example, by ion beam etching, as shown in Figure 25(A).

[0060] Next, the substrate 10 is placed, for example, in the chamber of a sputtering apparatus, and the first superconducting layer 21 is artificially oxidized with O2 gas. As a result, an insulating layer 22 is formed, as shown in Figure 25(B). Unlike a naturally occurring oxide film, the insulating layer 22, being an artificial oxide film, can function as a tunnel barrier.

[0061] Through the above steps, the laminate 200 according to the comparative example is formed.

[0062] Next, as shown in Figure 26(A), a second superconducting layer 31 with a thickness of 30 nm to 100 nm is formed on the insulating layer 22.

[0063] Next, the substrate 10 is removed from the sputtering chamber. At this time, as shown in Figure 26(B), the surface of the second superconducting layer 31 undergoes spontaneous oxidation. In Figure 26(B), the spontaneously oxidized surface of the second superconducting layer 31 is shown with hatching.

[0064] Next, as shown in Figure 27(A), a resist layer 51 is formed on the second superconducting layer 31. Then, the resist layer 51 is exposed to light, for example, an ArF line, a KrF line, or an i line, to transfer a linear pattern extending in the X direction to the resist layer 51. For example, an immersion lithography apparatus can be used to expose the resist layer 51.

[0065] Subsequently, as shown in Figure 27(B), the resist layer 51 is developed, and then, as shown in Figure 28(A), the second superconducting layer 31 is etched using the resist layer 51 as a mask. This results in the second superconducting layer 31 being patterned in a linear shape extending in the X direction.

[0066] Subsequently, as shown in Figure 28(B), the resist layer 51 is removed using, for example, an ashing device. Through these steps, the Josephson junction element 1000 according to the comparative example is completed.

[0067] A Josephson junction element manufactured by the manufacturing method according to the first embodiment was compared with a Josephson junction element manufactured by the manufacturing method according to the comparative example. Figure 29(A) is a surface SEM (scanning electron microscope) image of the Josephson junction element manufactured by the manufacturing method according to the first embodiment, and Figure 29(B) is a surface SEM image of the Josephson junction element manufactured by the manufacturing method according to the comparative example. Note that the Josephson junction element shown in Figure 29(A) does not have a second cap layer 32.

[0068] A comparison of Figure 29(A) and Figure 29(B) shows that the surface of the Josephson junction element manufactured by the manufacturing method of the comparative example is rougher than the surface of the Josephson junction element manufactured by the manufacturing method of the first embodiment. This is thought to be because, in the comparative example, the first superconducting layer 21 is damaged by ion beam etching (reverse sputtering) to remove the native oxide film on the surface of the first superconducting layer 21. It is known that damage to the first superconducting layer 21 degrades the coherence time.

[0069] On the other hand, in the manufacturing method according to the first embodiment, ion beam etching is not performed to remove the native oxide film on the surface of the first superconducting layer 21. Therefore, the surface of the laminate 20 can be made smoother than that of the Josephson junction produced by the manufacturing method according to the comparative example. For this reason, the Josephson junction produced by the manufacturing method according to the first embodiment can have a better coherence time than the Josephson junction produced by the manufacturing method according to the comparative example.

[0070] As described in detail above, the manufacturing method of the Josephson junction element 100 according to the first embodiment includes forming a first superconducting layer 21 on a substrate 10, forming an insulating layer 22 on the first superconducting layer 21, and forming a first cap layer 23 having superconductivity and oxidation resistance on the insulating layer 22. The formation of the first superconducting layer 21, the formation of the insulating layer 22, and the formation of the first cap layer 23 are carried out continuously in the same chamber while maintaining a pressure lower than atmospheric pressure. Since the first cap layer 23 can suppress the spontaneous oxidation of the insulating layer 22, there is no need to remove the spontaneous oxide film by ion beam etching. Since the film surface is not roughened by ion beam etching, the coherence time as a qubit can be improved.

[0071] Furthermore, the manufacturing method according to the first embodiment includes forming a laminate 20 that extends in the Y direction by forming a first superconducting layer 21, forming an insulating layer 22, and forming a first cap layer 23; forming a sacrificial layer 40 that contacts the substrate 10 and the side surface of the laminate 20; forming a second superconducting layer 31 that contacts the substrate 10, the sacrificial layer 40, and the first cap layer and extends in the X direction intersecting the Y direction; and removing the sacrificial layer 40 after forming the second superconducting layer 31. This allows a space (void) SP to be formed between the side surface of the laminate 20 and the second superconducting layer 31, preventing contact between the native oxide film 25 formed on the side surface of the first superconducting layer 21 and the second superconducting layer 31, thus allowing the insulating layer 22 to function as a tunnel barrier.

[0072] (Variation 1) Figure 30(A) shows the configuration of the Josephson junction element 100A according to Modification 1. The Josephson junction element 100A according to Modification 1 differs from the first embodiment in that the laminate 20A includes a third superconducting layer 24 between the first cap layer 23 and the insulating layer 22.

[0073] The third superconducting layer 24 contains a superconducting material and is superconducting. The third superconducting layer 24 is, for example, an aluminum (Al) film. The thickness of the third superconducting layer 24 is, for example, 0.5 nm to 100 nm.

[0074] As shown in Modification 1, the laminate 20A may include a third superconducting layer 24 between the first cap layer 23 and the insulating layer 22. In this case, in step S12 of Figure 2, after forming the insulating layer 22, the substrate 10 can be formed on the insulating layer 22 without removing it from the chamber of the sputtering apparatus, and then the first cap layer 23 can be formed on the third superconducting layer 24 by sputtering. That is, the third superconducting layer 24 can be formed on the insulating layer 22 before forming the first cap layer 23. If the first cap layer 23 of the laminate 20A is the uppermost layer, other layers may be formed between the first cap layer 23 and the insulating layer 22 in addition to the third superconducting layer 24.

[0075] The other components are the same as in the first embodiment, so a detailed explanation is omitted. In Modification 1, the second cap layer 32 may be omitted, as shown in Modification 2 described later.

[0076] (Modification 2) In the first embodiment described above, the second cap layer 32 may be omitted.

[0077] Figure 30(B) is a cross-sectional view showing the configuration of the Josephson junction element 100B according to Modification 2. As shown in Figure 30(B), the Josephson junction element 100B according to Modification 2 differs from the first embodiment in that the second cap layer 32 is omitted. In this case, step S40 in Figure 2 is omitted, and after the formation of the second superconducting layer 31 (step S30), the second superconducting layer 31 can be linearly patterned using lithography and etching techniques. The other configurations are the same as in the first embodiment, so a detailed explanation is omitted. In Modification 2, the laminate 20 may include a third superconducting layer 24 between the first cap layer 23 and the insulating layer 22, as in Modification 1.

[0078] ≪Second Embodiment≫ Next, the Josephson junction element 100C according to the second embodiment will be described. Figure 31(A) is a perspective view of the Josephson junction element 100C according to the second embodiment, Figure 31(B) is a plan view of the Josephson junction element 100C according to the second embodiment, and Figure 31(C) is a cross-sectional view taken along line AA of Figure 31(B).

[0079] As shown in Figure 31(C), in the second embodiment, a protective layer 40C is formed in the space SP (see Figure 1(C)) formed by the substrate 10, the laminate 20, and the second superconducting layer 31, such that the side surface of the laminate 20 does not come into contact with the second superconducting layer 31. The protective layer 40C is, for example, a silicon nitride (SiN) film. The material of the protective layer 40C should be selected from materials that do not affect the properties of the Josephson junction element 100C.

[0080] Figure 32 is a flowchart showing the manufacturing method of the Josephson junction element 100C according to the second embodiment.

[0081] The process of forming the laminate 20 (step S10) is the same as in the first embodiment, so a detailed explanation is omitted.

[0082] After the formation of the laminate 20, a protective layer 40C is formed in place of the sacrificial layer 40 (step S20C). The protective layer 40C is, for example, a silicon nitride (SiN) film. The method for forming the protective layer 40C is the same as the method for forming the sacrificial layer 40, so a detailed explanation is omitted.

[0083] Next, a second superconducting layer 31 is formed (step S30), and a second cap layer 32 is formed (step S40). The process of forming the second superconducting layer 31 and the process of forming the second cap layer 32 are the same as in the first embodiment, so a detailed explanation is omitted.

[0084] In the second embodiment, the protective layer 40C is not removed after the formation of the second cap layer 32. Because the protective layer 40C prevents contact between the side surface of the laminate 20 and the second superconducting layer 31, the insulating layer 22 can function as a tunnel barrier, and the Josephson junction element 100C can operate as a Josephson junction. In addition, in the second embodiment, the step of removing the sacrificial layer 40 in the first embodiment can be omitted, so the manufacturing time of the Josephson junction element can be shortened compared to the first embodiment. Damage to the surface of the Josephson junction element 100C due to etching of the sacrificial layer 40 can also be suppressed, so the coherence time can be further improved.

[0085] Furthermore, the configurations of Modifications 1 and 2 of the first embodiment may be applied to the second embodiment.

[0086] In the manufacturing process of the first and second embodiments and their modified forms described above, by using an exposure apparatus or immersion exposure apparatus with ArF line (193 nm), KrF line (248 nm), or i-line (365 nm) light sources for exposure of the resist layers 50 and 51, multiple Josephson junction elements 100 can be manufactured on the same substrate at once.

[0087] For example, when using a scanner-type exposure system, a single substrate is scanned sequentially in multiple steps, and linear patterns extending in the Y and X directions are transferred to the resist layers 50 and 51 for each scanned area (exposure area). Therefore, patterns for multiple Josephson junction elements can be exposed on a single substrate simultaneously. For example, a 300mm silicon wafer substrate is scanned sequentially in 64 steps, each covering a 33mm x 26mm area.

[0088] Specifically, multiple sections are provided on a substrate on which a first superconducting layer 21, an insulating layer 22, a first cap layer 23, and a resist layer 50 are formed, and a desired pattern is transferred to the resist layer 50 in each section. By patterning the first superconducting layer 21, the insulating layer 22, and the first cap layer 23 using the resist layer 50 on which the pattern has been transferred as a mask, multiple laminates 20 extending in the Y direction can be formed simultaneously on the same substrate. Furthermore, multiple sections are provided on a substrate on which a second superconducting layer 31 and a second cap layer 32 are formed on the laminate 20, and a desired pattern is transferred to the resist layer 51 in each section. Using the resist layer 51 on which the pattern has been transferred as a mask, multiple second superconducting layers 31 and multiple second cap layers 32 can be patterned simultaneously in a linear shape extending in the X direction on the same substrate.

[0089] In this way, multiple Josephson junction elements 100 can be manufactured simultaneously on the same substrate.

[0090] The embodiments described above are preferred examples of the present invention and can be combined as appropriate. However, the invention is not limited thereto, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0091] 10 circuit boards 20 Laminate 21. First Superconducting Layer 22 Insulating layer 23. First cap layer 24 Third Superconducting Layer 31. Second Superconducting Layer 32 Second cap layer 40 layers of victims 40C protective layer 100, 100A, 100B, 100C Josephson junction element SP space (void)

Claims

1. The first superconducting layer, A second superconducting layer located on the first superconducting layer, An insulating layer located between the first superconducting layer and the second superconducting layer, A first cap layer is located between the insulating layer and the second superconducting layer and has superconductivity and oxidation resistance, A Josephson junction element equipped with the features described above.

2. The first cap layer has stronger oxidation resistance than the first superconducting layer. The Josephson junction element according to claim 1.

3. The laminate is formed by stacking the first superconducting layer, the insulating layer, and the first cap layer in that order, and extending in a first direction perpendicular to the stacking direction. The second superconducting layer is formed extending in a second direction intersecting the first direction, and is in contact with a portion of the upper surface of the laminate but not with the side surface of the laminate. The Josephson junction element according to claim 1 or claim 2.

4. The uppermost layer of the laminate is the first cap layer. The Josephson junction element according to claim 3.

5. The circuit board is further equipped, The laminate is located on the substrate, The second superconducting layer is in contact with the upper surface of the substrate, A space is formed by the laminate, the second superconducting layer, and the substrate. The Josephson junction element according to claim 3 or claim 4.

6. The laminate is provided with a protective layer formed in the space such that the side surface of the laminate and the second superconducting layer do not come into contact. The Josephson junction element according to claim 5.

7. The laminate further comprises a third superconducting layer located between the insulating layer and the first capping layer. The Josephson junction element according to any one of claims 3 to 6.

8. The laminate is formed in which the first cap layer is laminated in contact with the insulating layer. The Josephson junction element according to any one of claims 3 to 6.

9. The second superconducting layer is located on the aforementioned second superconducting layer and comprises a second capping layer which is oxidation resistant. A Josephson junction element according to any one of claims 1 to 8.

10. The oxidation resistance of the second cap layer is different from that of the first cap layer. The Josephson junction element according to claim 9.

11. The thickness of the first cap layer is 5 nanometers or less. A Josephson junction element according to any one of claims 1 to 10.

12. The thickness of the second superconducting layer is greater than the thickness of the first superconducting layer. A Josephson junction element according to any one of claims 1 to 11.

13. Forming a first superconducting layer on the substrate, Forming an insulating layer on the first superconducting layer, A first cap layer having superconductivity and oxidation resistance is formed on the insulating layer. Includes, The formation of the first superconducting layer, the formation of the insulating layer, and the formation of the first cap layer are carried out continuously in the same chamber under an environment where a pressure lower than atmospheric pressure is maintained. A method for manufacturing a Josephson junction.

14. By forming the first superconducting layer, forming the insulating layer, and forming the first cap layer, a laminate stretched in a first direction is formed. To form a sacrificial layer that contacts the substrate and the side surface of the laminate, A second superconducting layer is formed that contacts the substrate, the sacrificial layer, and the first cap layer, and extends in a direction intersecting the first direction. After forming the second superconducting layer, the sacrificial layer is removed, A method for manufacturing a Josephson junction element according to claim 13, including the method described in claim 13.

15. A method for manufacturing a Josephson junction element according to claim 14, wherein a space is formed between the laminate, the second superconducting layer and the substrate by removing the sacrificial layer.

16. By forming the first superconducting layer, forming the insulating layer, and forming the first cap layer, a laminate stretched in a first direction is formed. A protective layer is formed that contacts the substrate and the side surface of the first superconducting layer. A second superconducting layer is formed that contacts the substrate, the protective layer, and the first cap layer, and extends in a direction intersecting the first direction. A method for manufacturing a Josephson junction element according to claim 13, including the method described in claim 13.

17. Before forming the first cap layer on the insulating layer, a third superconducting layer is formed on the insulating layer. The first cap layer is formed on the third superconducting layer. A method for manufacturing a Josephson junction element according to any one of claims 13 to 16.

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