Inspection apparatus and inspection method for side electrodes of chip stacked devices

Abstract

To provide an inspection device capable of inspecting the side electrodes of a chip stacking device. [Solution] An inspection apparatus for side electrodes of a chip stacked device, wherein the chip stacked device includes a first to fourth surface, the first surface having side electrodes and edge marks at predetermined positions relative to the side electrodes, and the apparatus includes a quantitative phase microscope and an inspection unit, the inspection unit comprising an optical information acquisition unit that acquires optical information measured by the quantitative phase microscope, and the optical information includes first information including information relating to the side electrodes or the edge marks in a direction along the first surface or the surface where the edge marks are exposed, based on reflected light from the first surface where the side electrodes are exposed or reflected light from the surface where the edge marks are exposed, and second information including information relating to the side electrodes or the edge marks in a direction intersecting the first surface or the surface where the edge marks are exposed.

Description

Technical Field

[0001] The present invention relates to an inspection apparatus and an inspection method for a side electrode of a chip stacking device by a quantitative phase microscope.

Background Art

[0002] In recent years, the data communication volume in electronic computers such as data centers has been increasing. Along with the increase in data communication volume, the power consumption of electronic computers has increased rapidly, the memory capacity of electronic computers has increased, and the demand for low power consumption and large capacity of electronic computers has been expanding. For example, an electronic computer includes a plurality of logic chips and a plurality of memory chips electrically connected to the plurality of logic chips. A logic chip is, for example, an IC (Integrated Circuit) chip on which a logic circuit is mounted, and a memory chip is a semiconductor chip on which a memory circuit is mounted. Data communication in an electronic computer is, for example, executed between a logic chip and a memory chip. For example, stacking logic chips and memory chips for three-dimensional mounting is one of the effective solutions for reducing the power consumption of an electronic computer and increasing the memory capacity.

[0003] Patent Document 1 discloses, as an example of a three-dimensional mounting method, a semiconductor module in which a structure (pancake-type memory cube) in which a plurality of memory chips are stacked is arranged on a substrate or a logic chip so that the main surfaces of the plurality of memory chips are parallel to the main surface of the substrate or the logic chip.

[0004] Patent Documents 2 to 5 disclose semiconductor modules in which a structure (slice bread-type memory cube) in which a plurality of memory chips are stacked is vertically provided (vertically erected) on a substrate or a logic chip so that the main surfaces of the plurality of memory chips are perpendicular to the main surface of the substrate or the logic chip.

[0005] Such stacked memory chip structures are expected to consist of dozens or more layers of chips with a thickness of about 10 μm. Therefore, it is necessary to check the stacking accuracy and defects of the stacked chips. Patent document 6 states that a phase-contrast microscope may be used as a tool for detecting internal defects in multilayer semiconductors. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2012-156478 [Patent Document 2] Special Publication No. 3-501428 [Patent Document 3] International Publication No. 2021 / 095083 [Patent Document 4] International Publication No. 2021 / 199447 [Patent Document 5] International Publication No. 2024 / 057707 [Patent Document 6] Japanese Patent Publication No. 2019-208039 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] However, conventional inspections, such as those described in Patent Document 6, are performed from the top side of the multilayer semiconductor, which is a chip stacking device, and no inspection method has been established for the minute side electrodes where various materials are located in close proximity. Therefore, there is a need for an inspection technology that can inspect the side electrodes of chip stacking devices. [Means for solving the problem]

[0008] The gist of this invention is as follows: (1) An inspection apparatus for the side electrodes of a chip stacking device, The chip stacking device includes a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface parallel to the first surface, a third surface perpendicular to the first and second surfaces, and a fourth surface opposite to the third surface with respect to the second direction and parallel to the third surface, and is a stacking body including a plurality of memory chips stacked in the first direction, each having a semiconductor layer, an insulating layer, and side electrodes in the insulating layer, with the side electrodes located on the first surface, The memory chip has an edge mark located at a predetermined relative position to the side electrode, The side electrode is exposed on the first surface, or the edge mark, which is at a predetermined relative position to the side electrode, is exposed on at least one surface selected from the group consisting of the first surface, the second surface, the third surface, and the fourth surface. Includes a quantitative phase microscope and inspection unit, The inspection unit includes an optical information acquisition unit that acquires optical information measured by the quantitative phase microscope, The optical information includes first information, which includes information about the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, based on reflected light from the first surface on which the side electrode is exposed or reflected light from the surface on which the edge mark is exposed, and second information, which includes information about the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed. Inspection device. (2) The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection device described in (1) above. (3) The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection unit calculates the amount of protrusion of the side electrode or the edge mark from the end face position of the insulating layer based on the first position information, the insulating layer end face position information, and the second position information. The inspection apparatus described in (1) or (2) above. (4) The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection unit calculates the shape of the side electrode or the edge mark based on the first position information, the insulating layer end face position information, and the second position information. The inspection device described in any of (1) to (3) above. (5) The first information includes first position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction along the first surface or the surface on which the edge marks are exposed, The second information includes second position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection unit calculates the positional deviation of each of the side electrodes or edge marks of the plurality of memory chips relative to a predetermined reference position based on the first position information and the second position information. The inspection device described in any of (1) to (4) above. (6) The second information further includes end face position information of the first surface or the surface on which the edge mark is exposed, relating to the end face position of the first surface or the surface on which the edge mark is exposed in a direction intersecting with the first surface or the surface on which the edge mark is exposed, The inspection unit determines, based on the end face position information of the first surface or the surface on which the edge mark is exposed, whether or not there is foreign matter, a crack, or both on the first surface or the surface on which the edge mark is exposed. The inspection device described in any of (1) to (5) above. (7) A method for inspecting the side electrodes of a chip stacking device, The chip stacking device includes a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface parallel to the first surface, a third surface perpendicular to the first and second surfaces, and a fourth surface opposite to the third surface with respect to the second direction and parallel to the third surface, and is a stacking body including a plurality of memory chips stacked in the first direction, each having a semiconductor layer, an insulating layer, and side electrodes in the insulating layer, with the side electrodes located on the first surface, The memory chip has an edge mark located at a predetermined relative position to the side electrode, The side electrode is exposed on the first surface, or the edge mark, which is at a predetermined relative position to the side electrode, is exposed on at least one surface selected from the group consisting of the first surface, the second surface, the third surface, and the fourth surface. Using a quantitative phase microscope, optical information is obtained having first information including information about the side electrode or the edge mark in a direction along the first surface or the surface where the edge mark is exposed, based on reflected light from the first surface where the side electrode is exposed or reflected light from the surface where the edge mark is exposed, and second information including information about the side electrode or the edge mark in a direction intersecting the first surface or the surface where the edge mark is exposed. Testing methods, including those mentioned above. (8) The first information includes first position information regarding the position of the side surface electrode or the edge mark in a direction along the first surface or the surface where the edge mark is exposed. The second information includes second position information regarding the position of the side surface electrode or the edge mark in a direction intersecting the first surface or the surface where the edge mark is exposed. The inspection method according to (7) above. (9) The first information includes first position information regarding the position of the side surface electrode or the edge mark in a direction along the first surface or the surface where the edge mark is exposed. The second information includes insulating layer end face position information regarding the end face position of the insulating layer in a direction intersecting the first surface or the surface where the edge mark is exposed, and second position information regarding the position of the side surface electrode or the edge mark in a direction intersecting the first surface or the surface where the edge mark is exposed. Calculating the protruding amount of the side surface electrode or the edge mark from the end face position based on the first position information, the insulating layer end face position information, and the second position information. The inspection method according to (7) or (8) above, including this. (10) The first information includes first position information regarding the position of the side surface electrode or the edge mark in a direction along the first surface or the surface where the edge mark is exposed. The second information includes insulating layer end face position information regarding the end face position of the insulating layer in a direction intersecting the first surface or the surface where the edge mark is exposed, and second position information regarding the position of the side surface electrode or the edge mark in a direction intersecting the first surface or the surface where the edge mark is exposed. Calculating the shape of the side surface electrode or the edge mark based on the first position information, the insulating layer end face position information, and the second position information. The inspection method according to any one of (7) to (9) above, including this. (11) The first information includes first position information regarding the positions of the respective side electrodes or the edge marks of the plurality of memory chips in a direction along the first surface or the surface where the edge marks are exposed. The second information includes second position information regarding the positions of the respective side electrodes or the edge marks of the plurality of memory chips in a direction intersecting the first surface or the surface where the edge marks are exposed. Calculating a displacement of the respective side electrodes or the edge marks of the plurality of memory chips from a predetermined reference position based on the first position information and the second position information The inspection method according to any one of (7) to (10) above, including this. (12) The second information further includes end face position information of the surface where the first surface or the edge marks are exposed, regarding an end face position of the surface where the first surface or the edge marks are exposed in a direction intersecting the first surface or the surface where the edge marks are exposed. Determining the presence or absence of foreign matter, cracks, or both on the surface where the first surface or the edge marks are exposed, based on the end face position information of the surface where the first surface or the edge marks are exposed. The inspection method according to any one of (7) to (11) above, including this.

Advantages of the Invention

[0009] According to the present invention, it becomes possible to inspect the side electrodes of a chip stack device.

Brief Description of the Drawings

[0010] [Figure 1] FIG. 1 is a perspective view showing a configuration example of a semiconductor module including a chip stack device. [Figure 2] FIG. 2 is a perspective view showing a configuration example of a memory chip constituting a chip stack device. [Figure 3] FIG. 3 is a cross-sectional view showing a cross-sectional structure of the memory chip along line A1 - A2 shown in FIG. 2. [Figure 4] Figure 4 is a perspective view showing inductors included in multiple memory chips of a stacked chip device and inductors included in the inductor layer of a logic chip. [Figure 5] Figure 5 is a schematic diagram of the side view of a chip stacking device when three memory chips are stacked. [Figure 6] Figure 6 is a schematic top view of an example of a stacked memory chip. [Figure 7] Figure 7 is a schematic diagram of an example of edge mark design. [Figure 8] Figure 8 shows a schematic side view of a stacked device with edge marks numbered 1 to 24 displayed in a 3x8 grid, and a magnified microscope image of edge mark number 24. [Figure 9] Figure 9 shows (A) a color scale image consisting of 25 QPM (Quantitative Phase Microscopy) images arranged in a 5x5 grid, and (B) a grayscale image consisting of 25 QPM images arranged in a 5x5 grid. [Figure 10] Figure 10 is a magnified QPM colorscale image of the area corresponding to edge mark number 24 in Figure 8. [Figure 11] Figure 11 shows the height profiles of a1-a2 perpendicular to the interfaces of the semiconductor layer, insulating layer, side electrodes, and adhesive layer in Figure 10. [Figure 12] Figure 12 shows the height profile of b1-b2 along the three edge marks in Figure 10. [Figure 13] Figure 13 shows the height profile of c1-c2 perpendicular to the central edge mark of the three edge marks in Figure 10. [Figure 14] Figure 14 is a schematic diagram showing the overall structure of the inspection device. [Figure 15] Figure 15 shows an example of the configuration of the inspection unit. [Modes for carrying out the invention]

[0011] This disclosure relates to an inspection apparatus for side electrodes of a chip stacked device, wherein the chip stacked device includes a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface parallel to the first surface, a third surface perpendicular to the first and second surfaces, and a fourth surface opposite to the third surface with respect to the second direction and parallel to the third surface, and comprises a semiconductor layer, an insulating layer, and side electrodes in the insulating layer, and the side electrodes are located on the first surface, and the stacked device includes a plurality of memory chips stacked in the first direction, wherein the memory chips have edge marks at predetermined relative positions with respect to the side electrodes, and the side electrodes are exposed on the first surface or selected from the group consisting of the first surface, the second surface, the third surface, and the fourth surface. The present invention relates to an inspection device (hereinafter also referred to as "this inspection device") in which at least one surface exposes the edge mark located at a predetermined relative position to the side electrode, and includes a quantitative phase microscope and an inspection unit, wherein the inspection unit comprises an optical information acquisition unit that acquires optical information measured by the quantitative phase microscope, and the optical information includes first information which includes information about the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, based on reflected light from the first surface on which the side electrode is exposed or reflected light from the surface on which the edge mark is exposed, and second information which includes information about the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed.

[0012] Around the side electrodes of a chip stacking device, different materials such as semiconductor layers, insulating layers, and adhesive layers are located in close proximity. Figure 5 shows a schematic diagram of the side view of a chip stacking device (hereinafter also referred to as a stacking device) 100 when three memory chips 110 are stacked. The memory chips 110 are joined to each other by adhesive layers 125, etc. The memory chip 110 has an insulating layer 120 on a semiconductor layer 130 such as Si, and the insulating layer 120 contains side electrodes 172A. In the example shown in Figure 5, the side electrodes 172A are exposed, but they do not have to be exposed. Also, the side electrodes 172A can be a fine pattern with a width of several tens of μm and a height of 1 μm or less. The semiconductor layer 130 can be made of any semiconductor, for example, silicon (Si). The insulating layer 120 is conventionally used in semiconductor integrated circuits and can be silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), low-k film, etc. The electrode 172A can be made of materials conventionally used in semiconductor integrated circuits, such as Al or Cu. The adhesive layer 125 can be made of an adhesive. The overall dimensions of the stacked device 100 are not particularly limited, but for example, the length MCBZ in the D1 direction (see Figure 1) is 1 to 25 mm, the length MCBY in the D2 direction (see Figure 1) is 1 to 25 mm, and the length MCBX in the D3 direction (see Figure 1) is 1 to 10 mm. This inspection device allows for the inspection of minute side electrodes of chip stacked devices where different materials are located in close proximity, with submicron accuracy, by utilizing a quantitative phase microscope (QPM). Since QPM can acquire not only in-plane positional information but also height information, high-precision inspection of the side electrodes of chip stacked devices is possible.

[0013] This inspection device can acquire optical information relating to a side electrode exposed on the first surface of the stacked device 100 or an edge mark located at a predetermined relative position to the side electrode.

[0014] The chip stacked device is a stacked structure comprising a plurality of memory chips stacked in the first direction, each having a semiconductor layer, an insulating layer, and side electrodes in the insulating layer, and including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface. The first direction intersects the second direction, and the third direction intersects the first and second directions (the first-second-direction plane). The first direction is also called the D1 direction, the second direction is also called the D2 direction, the third direction is also called the D3 direction, and the first-second-direction plane is also called the D1D2 plane.

[0015] An example of a stacked device 100 including side electrodes will be described with reference to Figures 1 to 3. Figure 1 is a perspective view showing the configuration of an example of a semiconductor module 10 including the stacked device 100. Figure 2 is a perspective view showing the configuration of an example of a memory chip 110 constituting the stacked device 100. Figure 3 is a cross-sectional view showing the cross-sectional structure of the memory chip 110 along the line A1-A2 shown in Figure 2.

[0016] As shown in Figure 1, the stacked device 100 may be included in the semiconductor module 10 together with the logic chip 200. The stacked device 100 is sometimes called a memory cube, and the logic chip 200 is sometimes called a semiconductor chip.

[0017] As shown in Figure 1, the stacked device 100 includes a slice-bread type configuration in which a plurality of memory chips 110 are stacked in the D1 direction. The stacked device 100 is a chip stacked device that includes a first surface 146 parallel to the D2 direction intersecting the D1 direction and the D1 direction, and a second surface 148 that is opposite to the first surface 146 with respect to the D3 direction and is parallel to the first surface 146.

[0018] The stacked device 100 also includes a third surface 145 perpendicular to the first surface 146 and the second surface 148, and a fourth surface 147 opposite to the third surface 145 with respect to the D2 direction and parallel to the third surface 145.

[0019] The stacked device 100 also includes a fifth surface 142 parallel to the D2 and D3 directions, and a sixth surface 144 opposite to the fifth surface 142 with respect to the D1 direction and parallel to the fifth surface 142.

[0020] As shown in Figures 1 to 3, each of the multiple memory chips 110 has a semiconductor layer 130, an insulating layer 120, and an inductor 172 including an electrode 172A in the insulating layer 120. The electrode 172A is located on a first surface 146 parallel to the D2 direction which intersects the D1 direction, and the multiple memory chips 110 stacked in the D1 direction constitute a stack. The semiconductor layer 130 can be a transistor layer. The insulating layer 120 can include a wiring layer 150 and an inductor layer 170. The electrode 172A is a side electrode and only needs to be located on the first surface 146 so that the inductors can communicate with each other by magnetic field coupling, as described later. It may or may not be exposed on the first surface 146.

[0021] Each of the multiple memory chips 110 may or may not be distinguished. Each of the multiple memory chips 110 may have the same configuration or a different configuration.

[0022] As shown in Figure 2, the memory chip 110 includes a first surface 102 parallel to the D2 and D3 directions, and a second surface 104 opposite to the first surface 102 with respect to the D1 direction. The first surface 102 is the surface opposite to the surface on which the insulating layer 120 of the semiconductor layer 130 is located, and the second surface 104 is the surface opposite to the surface on which the semiconductor layer 130 of the insulating layer 120 is located. The first surface 102 and the second surface 104 of the memory chip 110 are parallel to the fifth surface 142 and the sixth surface 144 of the stacked device 100.

[0023] The memory chip 110 also includes a third face 105 perpendicular to the first face 102 and the second face 104, a fourth face 106 adjacent to the third face 105, a fifth face 107 adjacent to the fourth face 106, and a sixth face 108 adjacent to the fifth face 107 and the third face 105. The third face 105 of the memory chip 110 is part of the third face 145 of the stacked device 100, the fourth face 106 of the memory chip 110 is part of the first face 146 of the stacked device 100, the fifth face 107 of the memory chip 110 is part of the fourth face 147 of the stacked device 100, and the sixth face 108 of the memory chip 110 is part of the second face 148 of the stacked device 100.

[0024] As shown in Figure 3, the semiconductor layer 130 includes, for example, a substrate 173, an element isolation region 174, an activation region 175, a transistor 176, an insulating layer 177, and part of the wiring 178. The substrate 173 is, for example, a Si substrate or a Si-wafer. The wiring layer 150 included in the insulating layer 120 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. The wiring layer 150 includes, for example, part of the wiring 178, an insulating layer 179, wiring 180, and an insulating layer 181.

[0025] The memory chip 110 includes an inductor layer 170 having an electrode 172A located on the fourth surface 106. The inductor layer 170 includes, for example, an insulating layer 182 and one or more inductors 172. The inductor 172 includes an electrode 172A which is a straight side. The inductor 172 may be positioned perpendicular to the first surface 146 of the stacked device 100.

[0026] The electrode 172A is located on the fourth surface 106 of the memory chip 110, which is part of the first surface 146 of the stacked device 100, and can be close to and parallel to the second surface 204 of the logic chip. The electrode 172A only needs to be located on the fourth surface 106 so that it can communicate with the inductors by magnetic field coupling, as described later, and may or may not be exposed to the fourth surface 106.

[0027] If each inductor layer contains multiple inductors 172, the multiple inductors 172 are arranged parallel to each other in the D2 direction. The inductors 172 may include terminals A and B. The inductors 172 can be electrically connected to the transmit / receive circuit using terminals A and B.

[0028] Figure 4 is a perspective view showing inductors 172 included in multiple memory chips 110 of the stacked device 100 and inductors 272 included in the inductor layer 270 of the logic chip 200. As shown in Figure 1, the first surface 146 of the stacked device 100 may be placed on the second surface 204 of the logic chip 200.

[0029] The logic chip 200 may include, for example, a transistor layer 230, a wiring layer 250, and an inductor layer 270, and may include a first surface 202 parallel to the D2 direction intersecting the D1 direction and a second surface 204 opposite to the first surface 202. The first surface 202 is the surface opposite to the surface on which the wiring layer 250 is arranged relative to the transistor layer 230, and the second surface 204 is the surface opposite to the surface on which the wiring layer 250 is arranged relative to the inductor layer 270. The laminated device 100 and the logic chip 200 may be joined via an adhesive layer 300. The adhesive layer 300 is placed between the first surface 146 of the laminated device 100 and the second surface 204 of the logic chip 200, and can connect the laminated device 100 and the logic chip 200.

[0030] The inductor 272 may be one or more and may be arranged in a matrix in the D1 and D2 directions at the positions corresponding to the inductor 172. The inductor 272 may include electrodes 272A. The inductor 272 may include terminals C and D. The inductor 272 may be electrically connected to the transmit / receive circuit using terminals C and D.

[0031] As shown in Figure 1, the memory chip 110 can be positioned perpendicular to the logic chip 200, so that, as shown in Figure 4, the inductor 172 can face the inductor 272 at a 90-degree angle. Two inductors 172 and 272 facing each other can communicate one-to-one by magnetically coupling at a 90-degree angle. Inductors may also be formed on the side of the stacked device 100 so that the inductors of the memory chip 110 and the inductors of the logic chip 200 face each other (in the same direction). For example, coil wiring may be formed on the first surface 146 of the stacked device 100 facing the logic chip 200. The communication between inductors due to magnetic field coupling is called, for example, inductor communication, signal communication, or data communication.

[0032] The shapes of inductors 172 and 272 are not limited to triangular shapes as shown in Figures 2 and 4, but can be trapezoidal, pentagonal, circular, etc., as long as they are shapes that enable inductor communication. Inductor 272 may have the same configuration and function as inductor 172.

[0033] Effective inductor communication can be performed by the electrode 172A of inductor 172 and the electrode 272A of inductor 272 superimposed on electrode 172A.

[0034] As described above, the stacked device 100 is placed on the second surface 204 of the logic chip 200, and non-contact signal transmission can be performed between them by magnetic field coupled inductor communication. Therefore, it is necessary to precisely align the position of the inductor 172 of the stacked device 100 with the position of the inductor 272 of the logic chip 200.

[0035] For example, while the position of the entire stacked device 100 relative to the logic chip 200 can be aligned using conventional flip-chip bonding, the stacked device 100 is composed of a stack of multiple memory chips stacked in multiple layers. Therefore, it is not possible to confirm whether it conforms to production standards without checking the positional misalignment of each chip in the multiple layers. For example, if there is thickness variation relative to the design thickness of the memory chips, each memory chip will have a positional misalignment relative to its design position in the D1 direction, and the electrode positions will also be misaligned. Furthermore, due to variations in the processing of the memory chips and misalignment of the stacking position, the memory chips may also have positional misalignments relative to their design position in the D2 and D3 directions, and the electrode positions may also be misaligned. For example, if inductors are separated in the D3 direction, the signal communication quality will deteriorate. Therefore, inspection of the position in three directions—D1, D2, and D3—is required.

[0036] Either the side electrode 172A is exposed on the first surface 146 of the stacked device 100, or an edge mark at a predetermined relative position to the side electrode 172A is exposed on at least one surface selected from the group consisting of the first surface 146, second surface 148, third surface 145, and fourth surface 147 of the stacked device 100. The stacked device 100 may have edge marks positioned at a predetermined position relative to the side electrode on some or all of the multiple memory chips 110. Even if the electrode 172A, which is a side electrode, is not exposed on the first surface 146 of the stacked device 100, the side electrode positioned at a predetermined position relative to the edge mark can be inspected by inspecting the exposed edge mark instead.

[0037] Figure 6 shows a schematic top view of an example of a memory chip 110. The memory chip 110, which is a stacking chip, may have stacking alignment marks 165. The memory chip 110 has multiple inductors 172 having side electrodes 172A arranged in the D2 direction along an edge that is part of the first surface 146 of the stacking device 100. Edge marks 160 are formed at predetermined positions relative to the side electrodes 172A. In Figure 6, the edge marks are arranged at two locations (two sets) on both sides of the multiple inductors 172 on the edge where the multiple inductors 172 are arranged, and at three locations (three sets) on each of the other edges. The chip frame shown in Figure 6 is an example of the final chip shape after polishing. Before polishing, the chip size is slightly larger than this frame and includes the edge marks, and after polishing, it can become the size of the chip frame shown in Figure 6. In Figure 6, the edge marks 160 protrude from the chip frame, but this is simply to show the edge marks before polishing for illustrative purposes.

[0038] Since the side electrode 172A and the edge mark 160 are created on the memory chip at the same time using the same lithography process, the edge mark 160 is positioned in a predetermined location relative to the side electrode 172A. Therefore, by inspecting the edge mark 160 on the surface or polished surface of the stacked memory chip 110, the position of the side electrode 172A relative to the edge mark 160 can be determined.

[0039] Figure 7 shows a schematic diagram of an example of the design of the edge marks 160. Figure 7(A) is a schematic diagram of each of the two sets of edge marks placed on both sides of the multiple inductors 172 shown in Figure 6. Figure 7(B) is a schematic diagram of each of the three sets of edge marks placed on each of the three sides shown in Figure 6.

[0040] As shown in Figure 7, the edge mark 160 has multiple thin edge marks between thick edge marks. Since the multiple thin edge marks are arranged so that their positions change in stages, the appearance of the edge marks on the polished surface changes depending on the polishing position of the stacked memory chips.

[0041] Thick edge marks may be placed one or more times on either side of multiple thin edge marks. The thick edge marks on either side are placed for the purpose of being visible from the side of the memory chip regardless of polishing variations, and are used to confirm the position of the edge marks. In addition, by using a different number of thick edge marks on the left and right sides, it is possible to distinguish between left and right edge marks (easily distinguishable even when observed from the opposite direction), to determine which of the four sides is being observed, or to identify the top surface of the stacked device (memory cube) 100. By looking at the thin edge marks sandwiched between the thick edge marks, it is possible to determine whether the polishing is shallow or deep. For example, as illustrated in Figure 7(A), seven thin edge marks may be placed between the two thick edge marks on the left and the one thick edge mark on the right. In the edge marks of Figure 7(A), the presence of the three thick edge marks (two on the left and one on the right) and the fourth (center) thin edge mark indicates the optimal polishing position. If the polishing is insufficient or excessive, the central edge mark among the thin edge marks will not appear, and one or more edge marks closer to the edge, near the thicker edge marks, will appear.

[0042] The number of edge mark pairs (rows) on one side of the memory chip 110 can be a number corresponding to the arrangement of the side electrodes and the size of the memory chip. For example, on sides where side electrodes are placed, there may be one pair at each end for a total of two pairs (two rows), and on sides where side electrodes are not placed, there may be one pair at each of the three locations (both ends and the center) for a total of three pairs (three rows). If the chip size is large, there may be four pairs (four rows) or more. The number of rows of edge marks on the stacked device 100 can be a number corresponding to the number of stacked chips. Figure 8 shows a schematic side view of a stacked device 100 with edge marks numbered 1 to 24 arranged in 3 rows x 8 columns, and a magnified microscope image of the location of edge mark number 24.

[0043] Figure 14 shows a schematic diagram illustrating the overall structure of an inspection device 1 according to one embodiment of the present invention. The inspection device 1 can acquire information regarding the side electrode 172A or edge mark 160 exposed on the side surface 40a of the laminated device 100. The side surface 40a is the first surface 146 of the laminated device 100 where the side electrode 172A is exposed, or the first surface 146, second surface 148, third surface 145, or fourth surface 147 of the laminated device 100 where the edge mark is exposed.

[0044] The inspection device 1 may include a white light interferometer capable of measuring first information regarding the side electrode 172A or edge mark 160 in a direction along the side surface 40a of the stacked device 100 (hereinafter referred to as the "planar direction"), and second information regarding the side electrode 172A or edge mark 160 in a direction intersecting the side surface 40a of the chip stacked device 40 (a direction intersecting the planar direction; hereinafter referred to as the "depth direction").

[0045] The first information is information relating to the side electrode 172A or edge mark 160 when the side surface 40a of the stacked device 100 is viewed from above (hereinafter simply referred to as "view from above"). The first information is, for example, information relating to the position, area, shape, or combination thereof of the side electrode 172A or edge mark 160 in the planar direction, and / or information relating to the position, area, shape, or combination thereof of foreign matter or cracks on or around the side electrode 172A or edge mark 160 in the planar direction.

[0046] The second piece of information concerns the side electrode 172A or edge mark 160 in the depth direction, for example, the position, thickness, shape, or combination thereof of the side electrode 172A or edge mark 160 in the depth direction, and / or the position, thickness, shape, or combination thereof of foreign matter or cracks on or around the side electrode 172A or edge mark 160 in the depth direction.

[0047] The inspection device 1 can detect depth-direction information of the side surface 40a from the continuous interference fringe image obtained when the quantitative phase microscope 2 is scanned in the depth direction. The depth-direction information can be position, thickness, shape, or a combination thereof. The inspection device 1 may also be a white light interferometer of a type called vertical scanning low coherence interferometry.

[0048] Specifically, the inspection device 1 superimposes the light reflected by the reference mirror of the interference objective lens 23 (described later) and the light reflected by the surface of the side surface 40a to obtain interference fringes that appear as a spatial interference pattern. These interference fringes become brighter when the phases of the two superimposed lights match and darker when they are half a wavelength apart. By utilizing this, data on the surface shape of the side surface 40a is obtained by analyzing the contrast and phase changes of the interference fringes that appear when the interference objective lens 23 is scanned in the depth direction. White light is low-coherence light with a broad wavelength range, and its coherence distance (coherence length) is shorter than that of monochromatic light, so the region in which interference fringes of white light appear is narrow. For this reason, the inspection device 1, which is a white light interferometer, can obtain higher resolution in the depth direction.

[0049] The inspection device 1 according to one aspect of the present invention is not limited to a white light interferometer, as long as it can measure information in the planar direction and information in the depth direction of the side surface 40a. For example, the inspection device 1 according to one aspect of the present invention may be an interferometer of a type called phase-shift interferometry, which uses monochromatic light as a light source. An interferometer using phase-shift interferometry scans in the depth direction at predetermined intervals, and from the multiple images obtained when the optical path difference between the reference plane and the surface of the side surface 40a is shifted, the phase difference between the reference plane and the surface of the side surface 40a is determined, and from this phase difference, information in the depth direction of the side surface 40a, such as position and thickness, is calculated. Alternatively, the inspection device 1 according to one aspect of the present invention may be a confocal microscope that has a higher resolution in the depth direction than a normal optical microscope by receiving only the reflected light at the focal point.

[0050] The inspection apparatus 1 comprises a quantitative phase microscope 2, a stage 30, and an inspection unit 50. The stage 30 may be integrated with or separate from the quantitative phase microscope 2. In the following description, the surface of the stage 30 will be described as an XY plane composed of the X-axis and Y-axis directions, and the vertical direction intersecting the XY plane will be described as the Z-axis direction.

[0051] The quantitative phase microscope 2 can detect reflected light from the side surface 40a of the stacked device 100. The quantitative phase microscope 2 may include a light source 11, an image sensor 12, lenses 21 and 24, a mirror 22, and an interference objective lens 23.

[0052] The light source 11 emits light of a specific wavelength. The light source 11 is an example of a light-emitting unit that projects light onto the side surface 40a of the stacked device 100, and is, for example, a white light source. The light-emitting unit is not limited to the above and is appropriately selected according to the inspection method of the side surface 40a. For example, the light-emitting unit may be a monochromatic light source. The light-emitting unit may be an incoherent light source that projects normal light, or a coherent light source that projects a laser.

[0053] Lens 21 is a collimating lens that collimates the light from light source 11. The interference objective lens 23 splits the light incident from mirror 22 into measurement light and reference light using its built-in internal beam splitter. The interference objective lens 23 projects the split measurement light onto the side surface 40a of the stacked device 100 and the split reference light onto its built-in internal reference mirror. Mirror 22 can be a beam splitter or a half-mirror. The reflected measurement light from side surface 40a of the stacked device 100 is superimposed with the reflected reference light from the internal reference mirror. The interference objective lens 23 is configured to be driveable (movable up and down) along the Z-axis direction, which intersects with side surface 40a of the stacked device 100.

[0054] The measurement light and reference light, superimposed by the interference objective lens 23, are incident on the image sensor 12 via the lens 24. The image sensor 12 images the interference fringes (spatial interference patterns) generated by the interference of the measurement light and the reference light. The image sensor 12 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) camera or a CCD (Charge Coupled Device) camera. The processing unit 56 of the inspection unit 50, described later, can store the image of the interference fringes imaged by the image sensor 12 in the storage unit 55. The display unit 57 can display the image of the interference fringes imaged by the image sensor 12. The image sensor 12 is an example of a light receiving unit that receives reflected light reflected from the side surface 40a of the stacked device 100. The light receiving unit is not limited to the above and is appropriately selected according to the inspection method of the side surface 40a.

[0055] Instead of the interference objective lens 23, a first objective lens and a second objective lens which may be positioned at a 90-degree angle to the first objective lens may be used. When the first and second objective lenses are used, the light emitted from the light source 11 is split by a beam splitter or half mirror, and one of the split beams passes through the first objective lens and illuminates the side surface 40a of the stacked device 100 held on the stage 30. The light reflected from the side surface 40a of the stacked device 100 passes through the first objective lens, beam splitter or half mirror, and lens 24 and enters the image sensor 12 to form an image. On the other hand, the other split beam passes through the second objective lens and illuminates the surface of a second mirror positioned in front of the second objective lens. The light reflected by the second mirror passes through the second objective lens, beam splitter or half mirror, and lens 24 and enters the image sensor 12 to form an image. Interference fringes are formed by the phase difference between the reflected light from the side surface 40a of the stacked device 100 and the reflected light from the second mirror, depending on the unevenness of the side surface 40a of the stacked device 100. The image sensor 12 can detect an image of these interference fringes and output it to the processing unit 56.

[0056] The quantitative phase microscope 2 may also include optical elements other than those described above. For example, when a beam splitter is used as the mirror 22, the quantitative phase microscope 2 may further include polarizing elements such as a λ / 2 plate or a λ / 4 plate between the lens 21 and the mirror 22, between the mirror 22 and the interference objective lens 23, and / or between the mirror 22 and the lens 24.

[0057] The stage 30 holds the stacked device 100, which is the object to be inspected, on its upper surface. The stage 30 may have a holding mechanism such as a vacuum chuck or an electrostatic chuck to fix the stacked device 100 to the stage 30. The stage 30 may have a drive mechanism that drives the stacked device 100 in the X-axis and Y-axis directions parallel to the side surface 40a.

[0058] The inspection unit 50 may be connected to the quantitative phase microscope 2 and / or stage 30 so as to be able to send and receive signals. The inspection unit 50 inspects the side surface 40a by controlling the quantitative phase microscope 2 and stage 30 and processing the optical information acquired from the quantitative phase microscope 2. The inspection unit 50 may include a microscope control unit 51, a stage control unit 52, an optical information acquisition unit 53, a storage unit 55, a processing unit 56, a display unit 57, and an input unit 58.

[0059] The microscope control unit 51 controls the optical elements of the quantitative phase microscope 2. For example, the microscope control unit 51 may control the on / off switching of light emission of a specific wavelength from the light source 11, the light intensity, the timing of imaging by the image sensor 12, the position of the mirror 22, the vertical movement of the interference objective lens 23, etc. The microscope control unit 51 may adjust the position of the interference objective lens or mirror and acquire image data of multiple types of interference fringes from the image sensor 12. The microscope control unit 51 can be a computer equipped with a CPU (Central Processing Unit) and memory for storing control data, control programs, etc. The inspection unit 50 can detect the height profile of the side surface 40a of the stacked device 100 based on the acquired image data of multiple interference fringes. The inspection unit 50 can display the detected height profile of the side surface 40a of the stacked device 100 on the display unit 57, with the color continuously changing according to the height.

[0060] The stage control unit 52 controls the stage 30. For example, the stage control unit 52 may control the holding mechanism for the stacked device 100 in the stage 30, the drive mechanism that drives the stage 30 in the X-axis and Y-axis directions, or both.

[0061] The inspection unit 50 includes an optical information acquisition unit 53 that acquires optical information measured by the quantitative phase microscope 2. The optical information acquired by the optical information acquisition unit 53 includes first information, which includes information about the side electrodes or edge marks in the XY plane direction along the side 40a of the stacked device 100, based on the reflected light of the measurement light from the surface on which the side electrodes or edge marks of the side 40a of the stacked device 100 are exposed, and second information, which includes information about the side electrodes or edge marks in the Z axis direction intersecting the side 40a of the stacked device 100.

[0062] Figure 15 shows an example of the configuration of the inspection unit 50. The inspection unit 50 comprises a keyboard 91, an LCD (Liquid Crystal Display) 92, a CPU (Central Processing Unit) 93, a RAM (Random Access Memory) 94, a ROM (Read Only Memory) 95, and a communication module 96. Each of these components is connected to each other via a bus so that data can be sent and received from one another. The communication module 96 can communicate between the quantitative phase microscope 2 and the inspection unit 50. The communication module 96 can also communicate between the stage 30 and the inspection unit 50. The inspection unit 50 is configured by, for example, a single computer, but it may also be realized by a combination of multiple distributed computers. The inspection unit 50 functions the microscope control unit 51, stage control unit 52, optical information acquisition unit 53, storage unit 55, processing unit 56, display unit 57, and input unit 58 by executing a predetermined program stored in the RAM 94 or ROM 95 using the CPU 93.

[0063] The keyboard 91 corresponds to an example of the input unit 58. The LCD 92 corresponds to an example of the display unit 57. The RAM 94 or ROM 95 corresponds to an example of the storage unit 55. The communication module 96 corresponds to an example of the microscope control unit 51 and the stage control unit 52. The CPU 93 corresponds to an example of the optical information acquisition unit 53 and the processing unit 56.

[0064] The input unit 58 is not limited to a keyboard, but may also be a touch panel, switch, button, or voice input device. The display unit 57 is not limited to an LCD, but may also be a CRT (Cathode Ray Tube) display, LED (Light Emitting Diode) display, OLED (Organic LED) display, plasma display, projector, aerial projection display, or voice output device. The communication module 96 is, for example, a wired communication terminal connected to a communication cable, but is not limited to this, and may also be a wireless communication terminal.

[0065] The optical information may include positional information when the interference objective lens 23 is scanned in the Z-axis direction, and information regarding the contrast change of the interference fringes imaged by the image sensor 12 when the interference objective lens 23 is scanned in the Z-axis direction.

[0066] This inspection device can be used to perform QPM observation and acquire QPM images, which are images of interference fringes. When performing QPM observation with this inspection device, QPM images can be acquired by continuously performing QPM observation while scanning each part of the first surface or the surface where the edge marks are exposed on the stacked device 100. Figure 8 shows an example in which QPM images, which are images of interference fringes, were acquired by continuously performing QPM observation while scanning each part of the surface of the stacked device 100 with edge marks numbered 1 to 24 as shown in Figure 8. Figure 9(A) shows a color scale image with a total of 25 QPM images arranged in a 5x5 grid. Figure 9(B) shows a grayscale image with a total of 25 QPM images arranged in a 5x5 grid. The QPM images may be either color scale images or grayscale images.

[0067] Figure 10 shows a magnified QPM image of the acquired color scale image, specifically the area corresponding to edge mark number 24 in Figure 8. Figure 10 corresponds to the field of view of the magnified microscope image of the area corresponding to edge mark number 24 in Figure 8. The surface from which the QPM image was acquired corresponds to the surface viewed from the orientation indicated as "Observation surface in Figure 10" in Figure 6, and the edge marks schematically shown in Figure 7(A) were located there.

[0068] In Figure 10, three edge marks are visible on the right side and two on the left side, appearing as white contrast. The edge marks in the QPM image in Figure 10 show two thick edge marks on the left side, and three edge marks are visible to the right, separated from the left edge marks, indicating that the polishing was insufficient.

[0069] Around the edge mark, the Si semiconductor layer 130, adhesive layer 125, and insulating layer 120 are visible. In the color scale image, differences in height are displayed in different colors. In Figure 10, the edge mark 160, semiconductor layer 130, adhesive layer 125, and insulating layer 120 have differences in height, and minute differences in height are displayed in different colors.

[0070] Preferably, the first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, and the second information includes second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed. The first and second position information can be relative positions with respect to a predetermined reference position. The first and second position information may be relative positions with respect to either the side electrode of the first surface or the edge mark of the surface on which the edge mark is exposed as the reference position, or they may be relative positions with respect to the edge or corner of the first surface or the surface on which the edge mark is exposed as the reference position. Optical information including the first and second position information measured by the quantitative phase microscope 2 can be acquired by the optical information acquisition unit 53 of the inspection unit 50 and stored in the storage unit 55.

[0071] The processing unit 56 can calculate the position of the side electrode or edge mark based on optical information including first position information and second position information stored in the storage unit 55. If the first position information and second position information are related to the position of the side electrode, the position of the side electrode may be calculated directly. If the first position information and second position information are related to the position of the edge mark, the position of the edge mark may be calculated directly, or the position of the side electrode may be calculated based on a predetermined relative positional relationship between the side electrode and the edge mark that has been previously stored in the storage unit 55. The processing unit 56 can display the calculated position of the edge mark or the position of the side electrode on the display unit 57.

[0072] The processing unit 56 can acquire positional information regarding the position of the side electrode or edge mark based on the optical information acquired by the optical information acquisition unit 53. Depending on the position of the interference objective lens 23 in the Z-axis direction, the optical path difference between the measurement light and the reference light changes, and the contrast and phase of the interference fringes imaged by the image sensor 12 change. By utilizing the fact that the contrast of the interference fringes is maximized when the optical path lengths of the measurement light and the reference light match, the processing unit 56 analyzes the positional information of the interference objective lens 23 in relation to the information regarding the contrast change. Through this analysis, the processing unit 56 can derive the position of the surface of the side electrode or edge mark. That is, the processing unit 56 can derive first positional information and second positional information regarding the position of the side electrode or edge mark from the optical information.

[0073] Preferably, the first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, and the second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting with the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting with the first surface or the surface on which the edge mark is exposed. Optical information including the first position information, insulating layer end face position information, and second position information measured by the quantitative phase microscope 2 can be acquired by the optical information acquisition unit 53 of the inspection unit 50 and stored in the storage unit 55.

[0074] The inspection unit 50 can calculate the amount of protrusion from the end face position of the side electrode or edge mark based on the first position information, the insulating layer end face position information, and the second position information. Preferably, the processing unit 56 can calculate the amount of protrusion from the end face position of the side electrode or edge mark based on optical information including the first position information, the insulating layer end face position information, and the second position information stored in the storage unit 55. The side electrode or edge mark may protrude or recess from the end face of the insulating layer, but the amount of protrusion from the end face of the insulating layer can be inspected with submicron accuracy. The amount of protrusion means, for example, that a positive value means it protrudes from the end face of the insulating layer, and a negative value means it is recessed from the end face of the insulating layer. A calibration curve may be created for each material to calibrate the amount of protrusion.

[0075] Figures 11-13 show graphs of the height profiles along the lines a1-a2, b1-b2, and c1-c2 shown in Figure 10, respectively. In Figures 11-13, each division on the vertical axis corresponds to approximately 1 nm.

[0076] Figure 11 shows the height profile a1-a2 perpendicular to the interface between the semiconductor layer 130, the insulating layer 120, the side electrode 172A, and the adhesive layer 125, and it can be seen that the adhesive layer 125 protrudes 5-10 nm relative to the semiconductor layer 130.

[0077] Figure 12 shows the height profiles of b1-b2 along the three edge marks 160, and it can be seen that each of the three edge marks 160 protrudes 10-15 nm from the insulating layer 120.

[0078] Figure 13 shows the height profile of c1-c2 perpendicular to the central edge mark of the three edge marks 160, indicating that the edge mark 160 protrudes 10-15 nm from the semiconductor layer 130 and the adhesive layer 125. Thus, this inspection device can measure surface irregularities on a surface where inorganic and organic materials are mixed on a nanometer scale.

[0079] Preferably, the first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, and the second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting with the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting with the first surface or the surface on which the edge mark is exposed, and the inspection unit calculates the shape of the side electrode or the edge mark based on the first position information, the insulating layer end face position information, and the second position information.

[0080] The shape of the side electrode or edge mark may include, for example, the area of ​​the side electrode or edge mark when the side surface 40a of the stacked device 100 is viewed from above, dimensions such as the maximum and average dimensions of the side electrode or edge mark in the X-axis direction, dimensions such as the maximum and average dimensions of the side electrode or edge mark in the Y-axis direction, and the aspect ratio, contour, and shape of the side electrode or edge mark in the XY plane direction.

[0081] Preferably, the first information includes first position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction along the first surface or the surface on which the edge marks are exposed, and the second information includes second position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction intersecting the first surface or the surface on which the edge marks are exposed, and the inspection unit calculates the positional deviation of each of the side electrodes or edge marks of the plurality of memory chips with respect to a predetermined reference position based on the first position information and the second position information. As a result, the positional deviation of each of the side electrodes or edge marks of the plurality of memory chips with respect to a predetermined reference position can be calculated, and the relative positional accuracy of the memory chips can also be measured.

[0082] Preferably, the second information further includes end face position information of the first surface or the surface on which the edge mark is exposed, relating to the end face position of the first surface or the surface on which the edge mark is exposed in a direction intersecting with the first surface or the surface on which the edge mark is exposed, and the inspection unit determines the presence or absence of foreign matter, cracks, or both on the first surface or the surface on which the edge mark is exposed based on the end face position information of the first surface or the surface on which the edge mark is exposed. This makes it possible to detect foreign matter 41 adhering to the side surface 40a of the laminated device 100.

[0083] The foreign matter may be generated during the manufacturing process of the stacked device 100. The foreign matter may include, for example, silicon, silicon nitride, silicon oxide, silicide, gallium arsenide (GaAs), indium phosphide (InP), indium gallium nitride (InGaN), silicon carbide (SiC), gallium nitride (GaN), glass, acrylic resin, epoxy resin, silicone resin, phenolic resin, urethane resin, vinyl resin, ester resin, imide resin, amide resin, platinum (Pt), gold (Au), silver (Ag), copper (Cu), iron (Fe), zinc (Zn), tin (Sn), lead (Pb), chromium (Cr), nickel (Ni), titanium (Ti), aluminum (Al), tungsten (W), or molybdenum (Mo).

[0084] Organic foreign matter can be generated in the process of applying or removing adhesives or organic thin film layers to the multilayer device 100. Inorganic foreign matter can be generated in the process of applying or removing silicon substrates, silicon oxide layers, metal thin film layers, etc., to the multilayer device 100. Therefore, if the amount of foreign matter increases, by determining whether the increased foreign matter is organic or inorganic, it is possible to narrow down the process that caused the increase in foreign matter.

[0085] In QPM, for example, transparent or translucent organic materials and opaque inorganic materials have different degrees of light penetration and reflection angles, which appear as interference fringes, allowing for the identification of material differences. The reflection characteristics of each material can be measured in advance and recorded in a storage unit 55 that the inspection device 1 may have. The inspection device 1 can identify materials by comparing the reflection characteristics actually measured with the reflection characteristics associated with the materials recorded in the storage unit 55. The comparison of reflection characteristics can be performed by a processing unit 56 that the inspection device 1 may have. The processing unit 56 can select the material with the closest reflection characteristics by comparing the reflection characteristics measured by the inspection device 1 with the reflection characteristics associated with the materials recorded in advance in the storage unit 55.

[0086] The optical information acquisition unit 53 may acquire optical information based on the reflected light of measurement light from the side surface 40a of the stacked device 100, which includes first dimensional information of the foreign object 41 in the XY plane direction along the side surface 40a of the stacked device 100, and second dimensional information of the foreign object 41 in the Z axis direction intersecting the side surface 40a of the stacked device 100. This optical information includes position information when the interference objective lens 23 is scanned in the Z axis direction, and information regarding the contrast change of the interference fringes imaged by the image sensor 12 when the interference objective lens 23 is scanned in the Z axis direction.

[0087] The processing unit 56 may acquire trend information regarding the aspect ratio of the foreign object 41 based on the optical information acquired by the optical information acquisition unit 53. Depending on the position of the interference objective lens 23 in the Z-axis direction, the optical path difference between the measurement light and the reference light changes, and the contrast and phase of the interference fringes imaged by the image sensor 12 change. By utilizing the fact that the contrast of the interference fringes is maximized when the optical path lengths of the measurement light and the reference light match, the processing unit 56 can analyze the position information of the interference objective lens 23 in association with the information regarding the contrast change. Through this analysis, the processing unit 56 can derive the position of the surface of the foreign object 41. That is, the processing unit 56 can derive first dimensional information and second dimensional information of the foreign object 41 from the optical information. The derived first dimensional information and second dimensional information can be recorded in the storage unit 55. The processing unit 56 can calculate the ratio of the first dimensional information to the second dimensional information of the foreign object 41 as the aspect ratio, and acquire trend information regarding the aspect ratio of the foreign object 41 from the aspect ratios of multiple foreign objects 41. Trend information can be recorded in the memory unit 55.

[0088] The trend information is, for example, information showing the dimensional ratio between the area or particle size of foreign matter 41 when the side surface 40a of the laminated device 100 is viewed from above, and the average thickness of the foreign matter 41 in a direction intersecting the side surface 40a of the laminated device 100. The dimensional ratio of foreign matter 41 shows different trends depending on whether the foreign matter 41 is organic or inorganic. For example, when the area or particle size is small, the average thickness of organic foreign matter and the average thickness of inorganic foreign matter are approximately equal, but when the area or particle size is large, the average thickness of inorganic foreign matter is greater than the average thickness of organic foreign matter. In other words, the increase in average thickness when the area or particle size increases in organic foreign matter is smaller than the increase in average thickness when the area or particle size increases in inorganic foreign matter. Therefore, when the area or particle size is small, the difference between the dimensional ratio of organic foreign matter and the dimensional ratio of inorganic foreign matter is small, but when the area or particle size is large, the difference between the dimensional ratio of organic foreign matter and the dimensional ratio of inorganic foreign matter is large. Therefore, the trend information indicating the dimensional ratio when the area or particle size is large includes information that makes it possible to determine whether the foreign matter 41 is an inorganic or organic foreign matter.

[0089] The trend information may, for example, be information showing the slope of the average thickness of the foreign matter 41 in the direction intersecting the side surface 40a of the laminated device 100, with respect to the area or particle size of the foreign matter 41 when the side surface 40a of the laminated device 100 is viewed from above. As described above, the slope of the average thickness with respect to area or particle size for organic foreign matter is smaller than the slope of the average thickness with respect to area or particle size for inorganic foreign matter. Therefore, the trend information showing the slope of the average thickness with respect to area or particle size includes information that makes it possible to determine whether the foreign matter 41 is inorganic or organic.

[0090] The trend information may also be information relating to the volume of the foreign matter 41. The volume of the foreign matter 41 is calculated in the processing unit 56 based on the first dimension information and the second dimension information recorded in the storage unit 55. For example, the volume of the foreign matter 41 is calculated by multiplying the area of ​​the foreign matter 41 by its average thickness. The trend information relating to the volume of the foreign matter 41 may also be information showing a volume histogram. The peak volume at which the volume histogram of an inorganic foreign matter shows a peak may be smaller than the peak volume at which the volume histogram of an organic foreign matter shows a peak. Also, the symmetry of the shape relative to the peak volume in the volume histogram of an inorganic foreign matter may be lower than the symmetry of the shape relative to the peak volume in the volume histogram of an organic foreign matter. In other words, the volume histogram of an inorganic foreign matter may show a more asymmetrical histogram shape than the volume histogram of an organic foreign matter. Therefore, the trend information showing a volume histogram may include information that makes it possible to determine whether the foreign matter 41 is an inorganic or organic foreign matter.

[0091] The memory unit 55 stores reference information regarding the dimensions of the foreign object 41. The reference information is used to determine the type of foreign object 41 by comparing it with trend information acquired by the processing unit 56. In other words, the reference information is trend information regarding known types of foreign objects. The reference information is, for example, information acquired by the processing unit 56, but it may also be information input by the input unit 58, which will be described later.

[0092] The processing unit 56 determines the type of foreign matter 41 based on trend information. As described above, the trend information may include information that allows for the determination of whether the foreign matter 41 is inorganic or organic. Therefore, the processing unit 56 can determine whether the foreign matter 41 is organic or inorganic. For example, it can determine the ratio of organic to inorganic foreign matter in the foreign matter 41. Furthermore, if the amount of foreign matter 41 increases, it can determine whether the increase is due to organic or inorganic foreign matter.

[0093] Cracks may occur during the manufacturing process of the multilayer device 100. These cracks can be microcracks with a width of several hundred nanometers or less (0.5 to 0.6 μm or less). Cracks may occur in semiconductor layers, insulating layers, etc.

[0094] This inspection device 1 can detect the height profile of the surface of the side 40a of the chip stacking device 100, extract raised areas on the surface based on the detected height profile, and identify the extracted raised areas on the surface as areas where microcracks exist. This utilizes the characteristic that when microcracks occur, the area around the microcrack bulges slightly.

[0095] The area surrounding microcracks may be raised by approximately 20-30 nm to 100 nm in the range of 10 μm to 20 μm (10,000 nm to 20,000 nm). Such elevations can be detected using the quantitative phase microscope in this inspection device 1.

[0096] The surfaces on both sides of a microcrack may be raised above the surrounding surface. The height of this raised area is approximately 20-30 nm to 100 nm. Furthermore, this raised area forms along the direction in which the microcrack extends, with a width of 10 μm to 20 μm (10,000 nm to 20,000 nm). Thus, when a microcrack occurs, a raised region can be formed around it, where the surrounding surface is raised by approximately 20-30 nm to 100 nm in a range of 10 μm to 20 μm (10,000 nm to 20,000 nm).

[0097] The height of the raised area where microcracks exist tends to increase gradually from the periphery towards the central area where the microcracks originate, and then drop in a V-shape at the location of the microcracks.

[0098] The location and shape of microcracks may be identified based on the discontinuities in the height profile contained within the extracted raised region. The height of a microcrack may differ by approximately 20-30 nm to 100 nm between one side and the other. If the heights on both sides of a microcrack differ, for example, if the height on the left side of the microcrack is higher than the height on the right side, the height of the raised region will change discontinuously between the left and right sides of the microcrack. Since quantitative phase microscopy can detect height with high precision on the order of a few nanometers, observing microcracks with quantitative phase microscopy allows for the detection of microcracks as discontinuities in the height profile, thereby identifying the location and shape of the microcracks.

[0099] The detected height profile can be displayed on a screen with continuously changing colors according to the height. Areas where the color is discontinuous may be identified as discontinuous areas. Based on the color image displayed on the screen, the location and shape of microcracks can be easily detected.

[0100] A grid-like array of detection regions can be set on the surface of the side 40a of the chip stacking device 100, and if the difference in detection height between adjacent detection regions is greater than or equal to a threshold, it may be determined that a microcrack exists at the boundary of adjacent detection regions. This enables automatic detection of microcracks.

[0101] Each grid-like detection region array has a detection region R(i,j) with coordinates (i,j), and may have lengths Xs in the X direction and Ys in the Y direction. Xs and Ys may be set to lengths similar to the horizontal resolution of a quantitative phase microscope, for example, about 1 μm.

[0102] This inspection device 1 can detect the height of each detection region R(i,j). Each detection region R(i,j) may represent the detection height H(i,j) detected by a quantitative phase microscope.

[0103] Based on the optical information acquired by the optical information acquisition unit 53, the inspection unit 50 can calculate the difference between the detection height H(i,j) and the detection height H(i+1,j) between adjacent detection regions, for example, detection region R(i,j) and detection region R(i+1,j).

[0104] If a difference of a threshold, for example several nanometers or more, is detected between the detection height H(i,j) of detection region R(i,j) and the detection height H(i+1,j) of the adjacent detection region R(i+1,j), the inspection unit 50 can determine that a microcrack 34 exists at the boundary between the adjacent detection region R(i,j) and detection region R(i+1,j). Similarly, if there is a difference of a threshold or more between the detection height H(i,j+1) and detection height H(i+1,j+1) of adjacent detection region R(i,j+1) and detection region R(i+1,j+1), the processing unit 56 can determine that a microcrack 34 exists at the boundary between the adjacent detection region R(i,j+1) and detection region R(i+1,j+1).

[0105] On the other hand, if there is no difference in height between the detection height H(i,j) of adjacent detection region R(i,j) and the detection height H(i,j+1) of adjacent detection region R(i,j+1), and between the detection height H(i+1,j) of adjacent detection region R(i+1,j) and the detection height H(i+1,j+1) of detection region R(i+1,j+1), the inspection unit 50 can determine that no microcracks 34 exist at the boundaries between adjacent detection region R(i,j) and detection region R(i,j+1), and between adjacent detection region R(i+1,j) and detection region R(i+1,j+1).

[0106] The inspection unit 50 can then identify the location and shape of microcracks extending in the Y direction along the boundary between adjacent detection regions R(i,j) and R(i+1,j), and along the boundary between adjacent detection regions R(i,j+1) and R(i+1,j+1).

[0107] The disclosure also relates to a method for inspecting side electrodes of a chip stacked device, the chip stacked device comprising a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface parallel to the first surface, a third surface perpendicular to the first and second surfaces, and a fourth surface opposite to the third surface with respect to the second direction and parallel to the third surface, and comprising a plurality of memory chips stacked in the first direction, wherein the side electrodes are located on the first surface, and the memory chips have edge marks at predetermined relative positions to the side electrodes, and the side electrodes are exposed on the first surface or on the first surface, second surface, third surface, etc. The present invention relates to an inspection method (hereinafter also referred to as "this inspection method") in which an edge mark at a predetermined relative position to the side electrode is exposed on at least one surface selected from the group consisting of a surface and the fourth surface, and optical information is obtained using a quantitative phase microscope, based on reflected light from the first surface on which the side electrode is exposed or the surface on which the edge mark is exposed, having first information including information about the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, and second information including information about the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed.

[0108] The descriptions of each component in the above-mentioned inspection apparatus can also be applied to the common components in this inspection method. [Explanation of symbols]

[0109] 1. Inspection device 2. Quantitative Phase Microscopy 10 Semiconductor Modules 11 Light source 12 Image Sensors 21,24 lenses 22 Mirror 23 Interferometric objective lens 30 stages 40a Side view of a chip stacking device 41 Foreign object 50 Inspection Department 51 Microscope Control Unit 52 Stage Scanning Unit 53 Optical information acquisition section 54 Trend information acquisition section 55 Storage section 56 Judgment section 57 Display section 58 Input section 91-key keyboard 92 LCD 93 CPU 94 RAM 95 ROM 96 Communication Module 100-chip stacking devices 102 First side of a memory chip 104 Second side of the memory chip 105 Third side of the memory chip 106 Fourth side of a memory chip 107 The fifth side of the memory chip 108 Memory chip, 6th side 110 memory chips 120 Insulating layer 125 Adhesive layer 130 Semiconductor layer 142 Fifth face of a stacked chip device 144 Sixth face of a stacked chip device 145 Third surface of a stacked chip device 146. First surface of a stacked chip device. 147 Fourth surface of a stacked chip device 148. Second surface of a stacked chip device. 150 wiring layers of a chip stacking device 160 Edge Marks 165 Alignment marks for lamination 170 Inductor layer of a chip stacking device 172 Inductors for Stacked Chip Devices 172A Inductor electrodes for chip stacked devices 173 circuit boards 174 element isolation region 175 Activation area 176 transistors 177 Insulating layer 178 Wiring 179 Insulating layer 180 Wiring 181 Insulating layer 182 Insulating layer 200 logic chips 202 Logic Chip, Front Side 204 Logic chip, second side 230 transistor layers of logic chip 250 logic chip wiring layers 270 logic chip inductor layer 272 Logic Chip Inductors Electrodes of the inductor in the 272A logic chip 300 adhesive layer

Claims

1. An inspection device for the side electrodes of a chip stacking device, The chip stacking device includes a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface parallel to the first surface, a third surface perpendicular to the first and second surfaces, and a fourth surface opposite to the third surface with respect to the second direction and parallel to the third surface, and is a stacking body including a plurality of memory chips stacked in the first direction, each having a semiconductor layer, an insulating layer, and side electrodes in the insulating layer, with the side electrodes located on the first surface, The memory chip has an edge mark located at a predetermined relative position to the side electrode, The side electrode is exposed on the first surface, or the edge mark, which is at a predetermined relative position to the side electrode, is exposed on at least one surface selected from the group consisting of the first surface, the second surface, the third surface, and the fourth surface. Includes a quantitative phase microscope and inspection unit, The inspection unit includes an optical information acquisition unit that acquires optical information measured by the quantitative phase microscope, The optical information includes first information, which includes information about the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, based on reflected light from the first surface on which the side electrode is exposed or reflected light from the surface on which the edge mark is exposed, and second information, which includes information about the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed. Inspection device.

2. The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection apparatus according to claim 1.

3. The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection unit calculates the amount of protrusion of the side electrode or the edge mark from the end face position of the insulating layer based on the first position information, the insulating layer end face position information, and the second position information. The inspection apparatus according to claim 1.

4. The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection unit calculates the shape of the side electrode or the edge mark based on the first position information, the insulating layer end face position information, and the second position information. The inspection apparatus according to claim 1.

5. The first information includes first position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes second position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection unit calculates the positional deviation of each of the side electrodes or edge marks of the plurality of memory chips relative to a predetermined reference position based on the first position information and the second position information. The inspection apparatus according to claim 1.

6. The second information further includes end face position information of the first surface or the surface on which the edge mark is exposed, relating to the end face position of the first surface or the surface on which the edge mark is exposed in a direction intersecting with the first surface or the surface on which the edge mark is exposed, The inspection unit determines, based on the end face position information of the first surface or the surface on which the edge mark is exposed, whether or not there is foreign matter, a crack, or both on the first surface or the surface on which the edge mark is exposed. The inspection apparatus according to claim 1.

7. A method for inspecting the side electrodes of a chip stacking device, The chip stacking device includes a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface parallel to the first surface, a third surface perpendicular to the first and second surfaces, and a fourth surface opposite to the third surface with respect to the second direction and parallel to the third surface, and is a stacking body including a plurality of memory chips stacked in the first direction, each having a semiconductor layer, an insulating layer, and side electrodes in the insulating layer, with the side electrodes located on the first surface, The memory chip has an edge mark located at a predetermined relative position to the side electrode, The side electrode is exposed on the first surface, or the edge mark, which is at a predetermined relative position to the side electrode, is exposed on at least one surface selected from the group consisting of the first surface, the second surface, the third surface, and the fourth surface. Using a quantitative phase microscope, optical information is obtained having first information including information about the side electrode or the edge mark in a direction along the first surface or the surface where the edge mark is exposed, based on reflected light from the first surface where the side electrode is exposed or reflected light from the surface where the edge mark is exposed, and second information including information about the side electrode or the edge mark in a direction intersecting the first surface or the surface where the edge mark is exposed. Testing methods, including those mentioned above.

8. The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The inspection method according to claim 7.

9. The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, Based on the first position information, the insulating layer end face position information, and the second position information, the amount of protrusion of the side electrode or the edge mark from the end face position is calculated. The inspection method according to claim 7, including the method described in claim 7.

10. The first information includes first position information relating to the position of the side electrode or the edge mark in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes insulating layer end face position information relating to the position of the end face of the insulating layer in a direction intersecting the first surface or the surface on which the edge mark is exposed, and second position information relating to the position of the side electrode or the edge mark in a direction intersecting the first surface or the surface on which the edge mark is exposed, The shape of the side electrode or the edge mark is calculated based on the first position information, the insulating layer end face position information, and the second position information. The inspection method according to claim 7, including the method described in claim 7.

11. The first information includes first position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction along the first surface or the surface on which the edge mark is exposed, The second information includes second position information relating to the position of each of the side electrodes or edge marks of the plurality of memory chips in a direction intersecting the first surface or the surface on which the edge mark is exposed, Based on the first position information and the second position information, the positional deviation of each of the side electrodes or edge marks of the plurality of memory chips with respect to a predetermined reference position is calculated. The inspection method according to claim 7, including the method described in claim 7.

12. The second information further includes end face position information of the first surface or the surface on which the edge mark is exposed, relating to the end face position of the first surface or the surface on which the edge mark is exposed in a direction intersecting with the first surface or the surface on which the edge mark is exposed, Based on the end face position information of the first surface or the surface where the edge mark is exposed, it is determined whether or not there is foreign matter, a crack, or both on the first surface or the surface where the edge mark is exposed. The inspection method according to claim 7, including the method described in claim 7.

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