High-bandwidth memory

Abstract

It provides high-bandwidth memory that can reduce warping. [Solution] The high-bandwidth memory according to the present invention includes a base die including a first surface and a second surface opposite to the first surface, wherein the first surface includes a first region and a second region surrounding the first region, and comprises one or more dummy structures disposed on the first region, a plurality of bump structures disposed on the second region and next to the one or more dummy structures, and a semiconductor stack comprising a plurality of core dies disposed on the second surface of the base die.

Description

Technical Field

[0001] The present invention relates to a high-bandwidth memory, and more particularly to a high-bandwidth memory capable of reducing warpage.

Background Art

[0002] In the semiconductor industry field, in accordance with the requirements for miniaturization and weight reduction of electronic devices, while miniaturizing, weight-reducing, and thinning the semiconductor packages mounted on the electronic devices, at the same time, high speed, multi-functionality, and large capacity are pursued. Therefore, the need for a packaging technology that can store more data and transfer data at a higher speed has increased, and a high-bandwidth memory (High Bandwidth Memory: HBM) formed by stacking a plurality of individual semiconductor chips has been developed and used as such a packaging technology.

[0003] The high-bandwidth memory HBM is manufactured by forming a memory stack in which memory dies are stacked on a base die, and has the characteristic that signals can be transferred at a high bandwidth using through-silicon vias (TSVs) disposed in the base die and in the memory dies. The height of the high-bandwidth memory HBM, the number and arrangement of through-silicon vias TSVs, the arrangement of bump structures, the IEEE 1500 standard, and PHY, etc. are defined by standard conventions such as JEDEC standards.

[0004] The high-bandwidth memory HBM100C according to the JEDEC standard and the lower surface 120AC of the conventional base die are shown in FIGS. 1 and 2. FIG. 1 is a cross-sectional view of the high-bandwidth memory HBM100C in which the lower surface 120AC of the base die 120 in FIG. 2 is cut along the line C-C, and FIG. 2 is a plan view showing the lower surface 120AC of the base die 120. Referring to Figures 1 and 2, the base die 120 and the memory die 130 include multiple through-silicon vias (TSVs) (123, 133) to electrically connect the memory die 130 to the base die 120, and multiple bump structures 110 are arranged on the lower surface 120AC of the base die 120 to connect the base die 120 to an external processor.

[0005] The lower surface 120AC of the base die 120 includes a TSV region TR in which the horizontal (X and Y) cross-sections of through-silicon vias TSVs (123, 133) extending vertically (Z direction) within the base die 120 and the memory die 130 overlap. The footprints of the through-silicon vias (TSVs) (123, 133) included in the base die 120 and memory die 130 are contained within the TSV region TR. The TSV region TR is formed to be elongated along the first horizontal direction (X direction) and is located in the center with respect to the second horizontal direction (Y direction). With the second horizontal direction (Y direction) as the reference, the PHY region is located on the TSV region TR, and the DA (Direct Access) region is located below the TSV region TR. The PHY area is the region connected to an external processor, where addresses and data are transferred. The DA area is the region where the logic controlling the memory die 130 is located.

[0006] To test the reliability of the signal and power through-pass silicon via TSVs (123, 133), test pads 125 connected to the signal and power through-pass silicon via TSVs (123, 133) are placed within the wiring layer of the base die 120. The test pad 125 is exposed to the outside in the center of the TSV area TR, and no solder balls 112 are placed around where the test pad 125 is located. The region R defined as blank space from the perspective of the solder ball 112 will be located in the central part of the lower surface 120AC of the base die 120, due to the location of the test pad 125 for testing the signal and power through silicon via TSV (123, 133), and the location of the TSV region TR. The test pad 125 can be directly electrically connected to a test circuit formed within the base die 120.

[0007] Since no solder balls are placed in region R, the metal specific gravity in region R is significantly lower than in other regions. As a result, the warpage value in region R is larger than the warpage value in other regions where solder balls 112 are placed. Depending on the characteristics of the semiconductor package manufacturing process, whether it involves a room temperature process or a high-temperature process, warpage may occur in the semiconductor package due to differences in the coefficient of thermal expansion (CTE) between materials. However, the amount of warpage displacement in region R where solder balls are not placed will be larger than in other regions where solder balls 112 are relatively uniformly distributed.

[0008] Therefore, stress due to warpage is concentrated in region R of the base die 120, and cracks may occur on the surface of region R where the warpage is most pronounced. Cracks may propagate from the surface of region R to the wiring layer or element layer of the base die 120. Cracks that have propagated to the wiring layer or element layer of the base die 120 may affect the integrated circuit or wiring, potentially causing malfunctions in the high-bandwidth memory HBM100C or reducing its reliability. Furthermore, the generational shift in semiconductor products has resulted in thinner semiconductor chips, increasing the frequency of cracks occurring in the base die 120, which in turn has increased the risk of cracks in the high-bandwidth memory HBM100C. [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] The present invention has been made in view of the problems in the above-mentioned conventional high-bandwidth memory, and the object of the present invention is to provide a high-bandwidth memory (HBM) that can reduce warpage. [Means for solving the problem]

[0010] To achieve the above objective, the high-bandwidth memory according to the present invention is characterized by comprising: a base die including a first surface and a second surface opposite to the first surface, wherein the first surface includes a first region and a second region surrounding the first region, and comprises one or more dummy structures disposed on the first region, a plurality of bump structures disposed on the second region and next to the one or more dummy structures, and a semiconductor stack comprising a plurality of core dies disposed on the second surface of the base die.

[0011] Furthermore, a high-bandwidth memory according to the present invention, made to achieve the above objective, is characterized by comprising: a buffer die, wherein the buffer die comprises a die base including a front surface and a back surface facing the front surface; an element layer disposed on the front surface of the die base; and a wiring layer disposed on the element layer, wherein the wiring layer comprises a first region and a second region around the first region, and the wiring layer comprises a plurality of test pads in the first region and a plurality of conductive pads in the second region; one or more dummy structures on the first region; and a plurality of bump structures on the second region, wherein each of the plurality of bump structures is disposed on a corresponding conductive pad of the plurality of conductive pads, and is disposed on the back surface of the die base, and comprises a memory stack including a plurality of memory dies.

[0012] Furthermore, a high-bandwidth memory according to an embodiment of the present invention includes a logic die including a first surface and a second surface opposite the first surface, wherein the first surface includes one or more dummy structures on the first region, including a first region and a second region around the first region, and a plurality of bump structures on the second region and lateral to the one or more dummy structures, and a memory stack on the second surface of the logic die, wherein the memory stack includes a plurality of memory dies and a plurality of interconnection structures, the plurality of memory dies and the plurality of interconnection structures are stacked alternately, and a molding material covers the memory stack on the second surface of the logic die.

[0013] A high-bandwidth memory manufacturing method according to an embodiment of the present invention includes the steps of: providing a buffer die in which a plurality of test pads are formed in a first region of a wiring layer and a plurality of conductive pads are formed in a second region around the first region of the wiring layer; forming one or more dummy structures on the first region; forming a plurality of bump structures on the second region, wherein each of the plurality of bump structures is formed on a corresponding conductive pad among the plurality of conductive pads, and forming a memory stack on the buffer die. [Effects of the Invention]

[0014] According to the high-bandwidth memory of the present invention, a dummy structure can be placed in an area where solder balls are not placed beneath the base die of the high-bandwidth memory HBM, thereby enabling the metal content on the lower surface of the base die to be uniformly set. This reduces warpage of the high-bandwidth memory HBM, preventing crack formation in areas where solder balls are not placed beneath the base die due to stress concentration associated with warpage. As a result, it prevents crack propagation to the wiring layer or element layer of the base die. [Brief explanation of the drawing]

[0015] [Figure 1]It is a cross-sectional view showing a schematic configuration of a conventional high-bandwidth memory. [Figure 2] It is a plan view showing the lower surface of a conventional base die. [Figure 3] It is a plan view showing the lower surface of a base die according to an embodiment of the present invention. [Figure 4] It is a cross-sectional view showing a schematic configuration of a high-bandwidth memory according to an embodiment of the present invention. [Figure 5] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 6] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 7] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 8] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 9] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 10] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 11] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 12] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 13] It is an enlarged view of an embodiment of region E in FIG. 3 and region F in FIG. 4. [Figure 14] It is a cross-sectional view for explaining a method of forming a dummy structure on a base die of a high-bandwidth memory in FIG. 4 according to an embodiment of the present invention. [Figure 15] It is a cross-sectional view for explaining a method of forming a dummy structure on a base die of a high-bandwidth memory in FIG. 4 according to an embodiment of the present invention. [Figure 16] It is a cross-sectional view for explaining a method of forming a dummy structure on a base die of a high-bandwidth memory in FIG. 4 according to an embodiment of the present invention. [Figure 17]This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 18] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 19] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 20] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 21] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 22] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 23] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 24] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 25] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 26] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 27] This is a cross-sectional view illustrating a method for forming a dummy structure on the base die of a high-bandwidth memory shown in Figure 4, according to an embodiment of the present invention. [Figure 28] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 4 according to an embodiment of the present invention. [Figure 29]This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 4 according to an embodiment of the present invention. [Figure 30] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 4 according to an embodiment of the present invention. [Figure 31] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 4 according to an embodiment of the present invention. [Figure 32] This is a cross-sectional view showing a schematic configuration of a high-bandwidth memory according to one embodiment of the present invention. [Figure 33] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 32 according to an embodiment of the present invention. [Figure 34] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 32 according to an embodiment of the present invention. [Figure 35] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 32 according to an embodiment of the present invention. [Figure 36] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 32 according to an embodiment of the present invention. [Figure 37] This is a cross-sectional view showing a schematic configuration of a high-bandwidth memory according to one embodiment of the present invention. [Figure 38] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 37 according to an embodiment of the present invention. [Figure 39] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 37 according to an embodiment of the present invention. [Figure 40] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 37 according to an embodiment of the present invention. [Figure 41] This is a cross-sectional view illustrating a method for forming the high-bandwidth memory shown in Figure 37 according to an embodiment of the present invention. [Modes for carrying out the invention]

[0016] Next, specific examples of embodiments for implementing the high-bandwidth memory according to the present invention will be described with reference to the drawings.

[0017] The present invention can be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, irrelevant parts have been omitted in order to clearly illustrate the disclosure, and the same or similar reference numerals have been used throughout the specification for identical or similar components. Furthermore, the dimensions and thicknesses of each component shown in the drawings are arbitrarily provided for explanatory purposes, and this disclosure is not necessarily limited to those shown. In the specification as a whole, when a part is described as being "connected" to another part, this includes not only cases where it is "directly connected," but also cases where it is "indirectly connected" through other components. Furthermore, when we say that a part "includes" a certain component, unless otherwise specified, this does not mean that it excludes other components, but rather that it may include other components. Furthermore, when we say that a layer, membrane, region, plate, or other part is "on top of" another part, this includes not only cases where it is "directly on top" of the other part, but also cases where the other part is in between them. Conversely, when one part is "directly above" another part, it means that there is no other part in between. Furthermore, being "above" the reference point means being located above or below the reference point, and does not necessarily mean being located "above" in the opposite direction of gravity. Furthermore, throughout the specification, "on a plane" means when the subject is viewed from above, and "on a cross-section" means when the subject is viewed from the side of a cross-section obtained by cutting the subject perpendicularly.

[0018] Hereinafter, with reference to the drawings, a high-bandwidth memory HBM100A and a method for manufacturing the high-bandwidth memory HBM100A according to embodiments of the present invention will be described. Figure 3 is a plan view showing the lower surface (first surface) 120A of the base die 120 of the high-bandwidth memory HBM100A shown in Figure 4 according to an embodiment of the present invention. Referring to Figure 3, the high-bandwidth memory HBM100A includes a bump structure 110 positioned on the lower surface 120A of the base die 120, a test pad 125 exposed from the lower surface 120A of the base die 120, and one or more dummy structures 127 positioned on the base die 120.

[0019] Figure 4 shows the solder ball 112 within the bump structure 110. The test pad 125 on the plane is separated from the solder balls 112 of the bump structure 110. The lower surface 120A of the base die 120 includes a TSV region TR in which the horizontal (X and Y direction) cross-sections of the first through-silicon via TSV 123, which extends vertically (Z direction, see Figure 4) within the base die 120, overlap, and the horizontal (X and Y direction) cross-sections of the second through-silicon via TSV 133, which extends vertically (Z direction, see Figure 4) within each of the memory dies 130, overlap.

[0020] The footprints of the first through-silicon via TSV123 and the second through-silicon via TSV133 are contained within the TSV region TR. The TSV region TR is formed to be elongated along the first horizontal direction (X direction) and is centrally located with respect to the second horizontal direction (Y direction). Using the second horizontal direction (Y direction) as a reference, the PHY region is positioned on the TSV region TR, and the DA (Direct Access) region is positioned below the TSV region TR. The PHY area is the region connected to an external processor, where addresses and data are transferred. The DA area is the area where the logic for controlling the memory die 130 is located. The lower surface 120A of the base die 120 includes a first region R1 within the TSV region TR where the bump structure 110 is not located, and a second region R2 other than the first region R1. Since the first region R1 is located in the center of the lower surface 120A of the base die 120, the second region R2 surrounds the first region R1 around it.

[0021] The bump structure 110 is positioned to connect the high-bandwidth memory HBM100A to an external processor. The bump structure 110 is directly electrically connected to the circuit located outside the high-bandwidth memory. The bump structure 110, positioned within the TSV region TR of the bump structure 110, is electrically connected to the first through-silicon via TSV 123, which extends vertically (Z direction, see Figure 4) within the base die 120, and to the second through-silicon via TSV 133, which extends vertically (Z direction, see Figure 4) within each of the memory die 130. The bump structure 110 is not located within the first region R1. The first region R1 can be defined as a blank space from the perspective of the solder balls 112.

[0022] The test pad 125 is positioned within the wiring layer of the base die 120 and is exposed to the outside on the lower surface 120A of the base die 120. In one embodiment, the test pad 125 includes an EDS (Electrical Die Sorting) test pad. The first region R1 does not include the bump structure 110 but includes the test pad 125. A test pad 125 located within the first region R1 is electrically connected to the first through-silicon via TSV 123 and the second through-silicon via TSV 133 in order to test the reliability of the first through-silicon via TSV 123 and the second through-silicon via TSV 133.

[0023] One or more dummy structures 127 are placed on the lower surface 120A of the base die 120. One or more dummy structures 127 do not perform any electrical functions and are electrically isolated from the other components. One or more dummy structures 127 are electrically isolated from the other components of the wiring layer and from the conductive pads 124. One or more dummy structures 127 are placed within the first region R1. The first region R1 does not include the bump structure 110, but includes one or more dummy structures 127. By placing one or more dummy structures 127 in a first region R1 on the lower surface 120A of the base die 120 of the high-bandwidth memory HBM100A where the bump structure 110 is not located, the metal ratio on the lower surface 120A of the base die 120 can be uniformly adjusted. This reduces the warpage of the high-bandwidth memory HBM100A, preventing crack formation in the first region R1 due to stress concentration corresponding to the warpage, and consequently preventing the crack from propagating to the wiring layer or element layer of the base die 120.

[0024] Figure 4 is a cross-sectional view showing a schematic configuration of the high-bandwidth memory HBM100A according to an embodiment of the present invention. Figure 4 is a cross-sectional view of the high-bandwidth memory HBM100A obtained by cutting the lower surface 120A of the base die 120 in Figure 3 along line AA. Referring to Figure 4, the high-bandwidth memory HBM100A includes a bump structure 110, a base die (logic die, buffer die) 120, one or more dummy structures 127, a first interconnect structure 140A, a memory stack (semiconductor stack) S, an adhesive member 150, a dummy die 160, and a molding material 170.

[0025] The high-bandwidth memory HBM100A is a high-performance three-dimensional stacked dynamic random-access memory (DRAM). The high-bandwidth memory HBM100A features multiple memory channels via a memory stack S manufactured by vertically stacking memory dies 130. Compared to conventional DRAM products, it can simultaneously achieve short latency and high bandwidth, reducing the total area occupied by individual DRAMs on the substrate. This offers advantages in terms of high bandwidth relative to area and reduced power consumption.

[0026] The bump structure 110 is positioned between the base die 120 and the external device. Each of the bump structures 110 is positioned on each of the conductive pads 124 of the base die 120, thereby electrically connecting the conductive pads 124 of the base die 120 to an external device. Each of the bump structures 110 includes a bump pillar 111 and a solder ball 112. In one embodiment, the bump structure 110 includes microbumps. The bump pillar 111 is positioned between the corresponding conductive pad 124 and the solder ball 112. For example, the dummy structure 127 and the bump pillar 111 can be formed from the same material. The conductive pad 124 is directly electrically connected to a circuit located outside the high-bandwidth memory. The dummy structure 127 includes a bump pillar 111, and no corresponding solder ball is formed on the bump pillar 111.

[0027] An underbump metallurgy (UBM) layer 113 is interposed between the bump pillar 111 and the conductive pad 124. The underbump metal radiate (UBM) layer 113 includes a diffusion barrier layer 113U (see Figure 18) and a seed metal layer SL (see Figure 18). The diffusion barrier layer 113U and the seed metal layer SL line the space between the bump pillar 111 and the conductive pad 124, and between the bump pillar 111 and the protective layer 126. The diffusion barrier layer 113U improves the electrical properties between the bump pillar 111 and the conductive pad 124. The diffusion barrier layer 113U acts as an adhesive layer. The seed metal layer SL is indistinguishable from the bump pillar 111.

[0028] The base die 120 is positioned between the memory stack S and the external device. The base die 120 is a buffer die. When exchanging data between devices with different data processing speeds, processing units, and usage times, data loss may occur due to differences in data processing speed, processing units, and usage time between the devices. To prevent such losses, the base die 120 is placed between the memory die 130 and the external device, allowing information exchanged between the memory die 130 and the external device to be temporarily stored on the base die 120. When transferring data to or receiving data from the memory die 130, the base die 120 can sort the data and then pass the data through in order. The base die 120 includes a die base 121, a front side structure 122, a first through-hole silicon via TSV 123, a conductive pad 124, a test pad 125, and a protective layer 126. The base die 120 includes a first surface 120A and a second surface 120B facing the first surface 120A. The die base 121 is positioned so that its front surface faces the bump structure 110. The die base 121 is a die formed from a wafer. In one embodiment, the die base 121 includes silicon or another semiconductor material.

[0029] The front structure 122 is positioned between the die base 121 and the bump structure 110. The front structure 122 includes an active layer and a wiring layer. The active layer is positioned on the front surface of the die base 121. The active layer includes an integrated circuit structure having an integrated circuit region. In one embodiment, the integrated circuit structure includes at least one of an active device and a passive device. In one embodiment, the integrated circuit structure includes a gate structure, a source region, and a drain region. In one embodiment, the integrated circuit structure includes at least one of a transistor, a diode, a capacitor, an inductor, and a resistor. The wiring layer is placed on top of the active layer. The wiring layer includes signal wiring lines, power wiring lines, contact plugs, and inter-metal dielectric (IMD). The first region R1 and the second region R2 around the first region R1, defined by dividing the lower surface 120A of the base die 120, are similarly applied to the wiring layer.

[0030] The first through-hole silicon via TSV123 is located within the die base 121. Each of the first through-silicon vias TSV 123 is positioned between the wiring layer of the front structure 122 and each of the first bonding pads 143 of the first interconnect structure 140A on the back side 121B of the die base 121. Each of the first through-silicon vias TSV 123 electrically connects the wiring layer of the front structure 122 to the corresponding first bonding pad 143 of the first interconnect structure 140A on the back surface 121B of the die base 121. The first through-silicon via TSV123 includes a first signal through-silicon via and a first power through-silicon via. In one embodiment, the first through-silicon via TSV123 may include at least one of tungsten, aluminum, copper, and alloys thereof.

[0031] The conductive pad 124 is placed within or on the wiring layer. The conductive pad 124 is located within the second region R2. Each of the conductive pads 124 is electrically connected to the corresponding bump structure 110 within the bump structure 110. The test pad 125 is placed within or on the wiring layer. The test pad 125 is located within the first region R1. Each of the test pads is electrically connected to the corresponding first signal feed-through silicon via in the first signal feed-through silicon via or the corresponding first power feed-through silicon via in the plurality of first power feed-through silicon vias. The test pad 125 is exposed to the outside. Test pad 125 includes probe marks. For example, multiple test pads 125 are directly electrically connected to corresponding signal-through silicon vias or power silicon vias. Each surface of the test pad 125 has a recessed shape. The test pad 125 includes probe marks as an indication of mechanical contact with the pins of the probe card for high-bandwidth memory testing.

[0032] The protective layer 126 is placed on top of the wiring layer. The protective layer 126 covers a portion of the upper surface and the sides of the conductive pad 124. The protective layer 126 does not cover the remaining portion of the upper surface of the conductive pad 124. The conductive pad 124 contacts and electrically connects with the bump pillar 111 through the remaining portion of the upper surface of the uncovered conductive pad 124. The protective layer 126 contains an organic dielectric. In one embodiment, the protective layer 126 includes a photoimaging dielectric (photo-sensitive dielectric, PID). In one embodiment, the photoimaging dielectric PID may include a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, a polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer.

[0033] One or more dummy structures 127 are placed on the wiring layer. One or more dummy structures 127 are positioned next to the bump structure 110. One or more dummy structures 127 are placed on top of at least one of the protective layer 126 and the test pad 125. One or more dummy structures 127 are located within the first region R1. One or more dummy structures 127 are electrically isolated from the base die 120. In one embodiment, one or more dummy structures 127 may include at least one of metal, silicon, and epoxy. The first interconnection structure 140A is positioned between the back surface 121B of the die base 121 and the memory stack S. The first interconnection structure 140A includes a back silicon layer 141 on the back surface 121B of the die base 121, a front silicon layer 142 on the front structure 132 of the memory die 130, a back bonding pad 143 on the back surface 121B of the die base 121, and a front bonding pad 144 on the front structure 132 of the memory die 130.

[0034] The back silicone layer 141 is directly bonded to the front silicone layer 142. The back silicone layer 141 surrounds and insulates the back bonding pad 143. The front silicone layer 142 surrounds and insulates the front bonding pad 144. In one embodiment, the back silicon layer 141 and the front silicon layer 142 include at least one of silicon oxide and silicon nitride. In one embodiment, the back silicon layer 141 and the front silicon layer 142 may contain SiO2, SiN, or SiCN.

[0035] The back bonding pad 143 is positioned to penetrate the back silicone layer 141. The bonding surface level of the back bonding pad 143 is the same as the bonding surface level of the back silicone layer 141. The sides of the back bonding pad 143 are surrounded by the back silicone layer 141. Each of the rear bonding pads 143 is electrically connected to the corresponding first through-hole silicon via TSV 123 of the first through-hole silicon via TSV 123. Each of the rear bonding pads 143 is directly bonded to the corresponding front bonding pad 144 of the front bonding pads 144. The front bonding pad 144 is positioned to penetrate the front silicone layer 142. The bonding surface level of the front bonding pad 144 is the same as the bonding surface level of the front silicone layer 142. The sides of the front bonding pad 144 are surrounded by the front silicone layer 142. Each of the front bonding pads 144 is electrically connected to the corresponding wiring in the wiring of the front structure 132 of the memory die 130. Direct bonding between the rear bonding pad 143 and the front bonding pad 144 provides an electrical connection between the base die 120 and the memory stack S. In one embodiment, the rear bonding pad 143 and the front bonding pad 144 include a conductive material to which copper or hybrid bonding can be applied.

[0036] The memory stack S is located on the second surface 120B of the base die 120 (the back surface 121B of the die base 121). The memory stack S includes vertically stacked memory dies 130 and second interconnection structures 140 arranged alternately with the memory dies 130. Figure 4 discloses a memory stack S including four memory dies 130, but the invention is not limited thereto, and memory stacks S including more or fewer memory dies 130 may be included in the scope of the present invention. For example, the memory stack S may include 4, 8, 12, 16, or 20 memory dies 130.

[0037] The memory die (semiconductor die, core die) 130 includes a memory die base 131, a front structure 132, and a second through-silicon via TSV 133. The memory die 130T, located at the top of the memory stack S, does not include the second through-hole silicon via TSV133. In one embodiment, the memory die 130 includes DRAM. The memory die base 131 is positioned so that its front surface 131F faces the bump structure 110. The memory die base 131 is a die formed from a wafer. In one embodiment, the memory die base 131 includes silicon or other semiconductor material.

[0038] The front structure 132 is positioned on the front surface 131F of the memory die base 131. The front structure 132 includes an active layer and a wiring layer. The active layer is positioned on the front surface of the memory die base 131. The active layer includes an integrated circuit structure having an integrated circuit region. In one embodiment, the integrated circuit structure includes at least one of an active device and a passive device. In one embodiment, the integrated circuit structure may include a gate structure, a source region, and a drain region. In one embodiment, the integrated circuit structure may include at least one of a transistor, a diode, a capacitor, an inductor, and a resistor. The wiring layer is placed on top of the active layer. The wiring layer includes signal wiring lines, power wiring lines, contact plugs, and intermetallic dielectrics (IMDs).

[0039] The second through-hole silicon via TSV133 is located within the memory die base 131. Each of the second through-silicon vias TSV 133 is positioned between the wiring layer of the front structure 132 and each of the first bonding pads 143 of the second interconnect structure 140 on the back side 131B of the memory die base 131. Each of the second through-silicon vias TSV 133 electrically connects the wiring layer of the front structure 132 to the corresponding first bonding pad 143 of the second interconnect structure 140 on the back surface 131B of the memory die base 131. The second through-silicon via TSV133 includes a second signal through-silicon via and a second power through-silicon via. In one embodiment, the second through-silicon via TSV133 may include at least one of tungsten, aluminum, copper, and alloys thereof.

[0040] The second interconnection structures 140 are stacked alternately on the memory dies 130. Each of the second interconnection structures 140 is positioned between the back surface 131B of the memory die base 131 of the memory die 130 and the front surface structure 132 of the adjacent memory die 130. Each of the second interconnection structures 140 includes a first silicon layer (back silicon layer) 141 on the back surface 121B of the memory die base 131, a second silicon layer (front silicon layer) 142 on the front structure 132 of the memory die 130, a first bonding pad (back bonding pad) 143 on the back surface 131B of the memory die base 131, and a second bonding pad (front bonding pad) 144 on the front structure 132 of the memory die 130. The first silicon layer 141 is directly bonded to the second silicon layer 142. The first silicon layer 141 surrounds and insulates the first bonding pad 143. The second silicon layer 142 surrounds and insulates the second bonding pad 144. In one embodiment, the first silicon layer 141 and the second silicon layer 142 include at least one of silicon oxide and silicon nitride. In one embodiment, the first silicon layer 141 and the second silicon layer 142 may contain SiO2, SiN, or SiCN.

[0041] The first bonding pad 143 is positioned to penetrate the first silicon layer 141. The bonding surface level of the first bonding pad 143 is the same as the bonding surface level of the first silicon layer 141. The sides of the first bonding pad 143 are surrounded by the first silicone layer 141. Each of the first bonding pads 143 is electrically connected to the corresponding second through-silicon via 133 of the second through-silicon via TSV 133. Each of the first bonding pads 143 is directly bonded to the corresponding second bonding pad 144 among the second bonding pads 144. The second bonding pad 144 is positioned to penetrate the second silicon layer 142. The bonding surface level of the second bonding pad 144 is the same as the bonding surface level of the second silicon layer 142. The sides of the second bonding pad 144 are surrounded by the second silicone layer 142. Each of the second bonding pads 144 is electrically connected to the corresponding wiring in the wiring of the memory die 130. Direct bonding between the first bonding pad 143 and the second bonding pad 144 provides an electrical connection between the memory dies 130. In one embodiment, the first bonding pad 143 and the second bonding pad 144 include copper or a conductive material to which hybrid bonding can be applied.

[0042] The adhesive member 150 is placed between the memory stack S and the dummy die 160. The adhesive member 150 attaches the dummy die 160 to the memory die 130T located at the top of the memory stack S. In one embodiment, the adhesive member 150 includes a thermal interface material (TIM). The thermal interface material (TIM) is inserted between the memory stack S and the dummy die 160 to improve the thermal coupling between the memory stack S and the dummy die 160. The thermal interface material TIM fills the air layer at the contact surface between the memory stack S and the dummy die 160, thereby reducing thermal contact resistance.

[0043] The dummy die (dummy structure) 160 is placed on the memory stack S. The dummy die 160 may be attached to the memory stack S by an adhesive member 150. The dummy die 160 is thermally connected to the memory stack S. In one embodiment, the dummy die 160 includes a heat dissipation structure. In one embodiment, the heat dissipation structure may include a heat slag, a heat sink, or a heat spreader. In one embodiment, the heat dissipation structure includes a conductive material having high thermal conductivity. In one embodiment, the dummy die 160 may contain at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. The molding material 170 covers the memory stack S, the adhesive member 150, and the dummy die 160 on the second surface 120B of the base die 120. The upper surface of the dummy die 160 is exposed from the molding material 170 and is at the same level as the upper surface of the molding material 170.

[0044] Figure 5 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F1 in Figure 5 is a cross-sectional view taken along line BB of E1 in Figure 5. Referring to E1 in Figure 5, multiple dummy structures 127 are placed on the protective layer 126 within the first region R1.

[0045] Multiple dummy structures 127 are arranged in one or more columns. Multiple dummy structures 127 are arranged in an alternating (staggered) pattern. Multiple dummy structures 127 are positioned so as to be separated from the test pad 125. The multiple dummy structures 127 do not overlap with the test pad 125 in the vertical direction (Z direction). The footprints of the multiple dummy structures 127 do not overlap with the footprint of the test pad 125. In Figure 5E1, each of the multiple dummy structures 127 is shown as having a circular planar shape, but the invention is not limited to this, and in one embodiment, each of the multiple dummy structures 127 may include a circular, elliptical, elongated, rectangular, or polygonal planar shape.

[0046] Referring to F1 in Figure 5, each of the multiple dummy structures 127 is placed on the protective layer 126 within the first region R1. Each of the multiple dummy structures 127 has a first thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first thickness T1, or it may be greater than the first thickness T1. The thickness of the underbump metal radiator UBM layer 113 on the dummy structure 127 and on the bump pillar 111 is significantly smaller than the thickness of the dummy structure 127 and the thickness of the bump pillar 111, and can therefore be ignored.

[0047] Figure 6 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F2 in Figure 6 is a cross-sectional view taken along line BB at E2 in Figure 6. Referring to E2 in Figure 6, one dummy structure 127 is placed on the protective layer 126 within the first region R1.

[0048] One dummy structure 127 fills at least a portion of the first region R1, excluding the test pad 125. One dummy structure 127 is placed around the test pad 125. One dummy structure 127 may conformally extend along the side of the test pad 125. One dummy structure 127 has a single, integrated structure. One dummy structure 127 can be alternately extended along a first horizontal direction (X direction) and along a second horizontal direction (Y direction). One dummy structure 127 is positioned so as to be separated from the test pad 125. One dummy structure 127 does not overlap with the test pad 125 in the vertical direction (Z direction). The footprint of one dummy structure 127 does not overlap with the footprint of the test pad 125. In Figure 6, E2, one dummy structure 127 is shown as having a planar shape in which a rectangle is continuously extended, but it is not limited to this, and in one embodiment, one dummy structure 127 may include a planar shape in which a circle, ellipse, elongated shape, rectangle, or polygon is continuously extended.

[0049] Referring to F2 in Figure 6, the dummy structure 127 is placed on the protective layer 126 within the first region R1. The dummy structure 127 has a first thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first thickness T1, or it may be greater than the first thickness T1.

[0050] Figure 7 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F3 in Figure 7 is a cross-sectional view taken along line BB at E3 in Figure 7. Referring to E3 in Figure 7, a single elongated dummy structure 127 is placed on the protective layer 126 within the first region R1.

[0051] One dummy structure 127 is placed around the test pad 125. One dummy structure 127 can be conformally extended along the side of the test pad 125. One dummy structure 127 has a single, integrated structure. One dummy structure 127 can be alternately extended along a first horizontal direction (X direction) and along a second horizontal direction (Y direction). One dummy structure 127 is positioned so as to be separated from the test pad 125. One dummy structure 127 does not overlap with the test pad 125 in the vertical direction (Z direction). The footprint of one dummy structure 127 does not overlap with the footprint of the test pad 125. In Figure 7, E3, one dummy structure 127 is shown as having a planar shape in which an elongated shape is continuously extended, but it is not limited to this, and in one embodiment, one dummy structure 127 may include a planar shape in which a circle, ellipse, elongated shape, rectangle, or polygon is continuously extended. Furthermore, the scope of the present invention can include not just one dummy structure 127, but multiple dummy structures 127 having a shape that is continuously extended while being arranged side by side.

[0052] Referring to F3 in Figure 7, the dummy structure 127 is placed on the protective layer 126 within the first region R1. The dummy structure 127 has a first thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first thickness T1, or it may be greater than the first thickness T1.

[0053] Figure 8 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F4 in Figure 8 is a cross-sectional view taken along line BB at E4 in Figure 8. Referring to E4 in Figure 8, multiple dummy structures 127 are placed within the first region R1.

[0054] Each of the multiple dummy structures 127 is placed on the corresponding test pad 125 among the test pads 125. Multiple dummy structures 127 are arranged in one or more columns. Multiple dummy structures 127 are arranged in an alternating (staggered) pattern. Each of the multiple dummy structures 127 is positioned to contact the test pad 125. Multiple dummy structures 127 overlap the test pad 125 in the vertical direction (Z direction). The test pad 125 is electrically connected directly to the corresponding dummy structure 127 among the multiple dummy structures 127. The footprints of the multiple dummy structures 127 overlap the footprint of the test pad 125. In Figure 8, E4 is shown as having a circular planar shape for each of the multiple dummy structures 127, but is not limited to this, and in one embodiment, each of the multiple dummy structures 127 may include a circular, elliptical, elongated, rectangular, or polygonal planar shape.

[0055] Referring to F4 in Figure 8, each of the multiple dummy structures 127 is placed on the corresponding test pad 125 within the first region R1. Each of the multiple dummy structures 127 is a dummy pillar. There may be no solder balls on any of the dummy structures 127 of the dummy pillar. Each of the multiple dummy structures 127 has a fourth thickness T4 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The fourth thickness T4 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The fourth thickness T4 is the same as the third thickness T3.

[0056] Figure 9 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F5 in Figure 9 is a cross-sectional view taken along line BB at E5 in Figure 9. Referring to E5 in Figure 9, multiple dummy structures 127 are placed within the first region R1.

[0057] Multiple dummy structures 127 are arranged in one or more columns. The multiple dummy structures 127 include dummy structures 127A that are not placed on the test pad 125 and dummy structures 127B that are placed on the test pad 125. The dummy structure 127A, which is not placed on the test pad 125, does not overlap with the test pad 125 in the vertical direction (Z direction). The dummy structures 127A that are not placed on the test pad 125 are arranged in an alternating (staggered) pattern. The dummy structures 127B placed on the test pad 125 are arranged in an alternating (staggered) pattern. Each of the dummy structures 127B placed on the test pad 125 is positioned to contact the corresponding test pad 125 on the test pad 125. The dummy structure 127B, which is placed on the test pad 125, overlaps the test pad 125 in the vertical direction (Z direction). The footprint of the dummy structure 127B, which is placed on the test pad 125, overlaps with the footprint of the test pad 125. In Figure 9, E5 shows that each of the multiple dummy structures 127 has a circular planar shape, but is not limited to this, and in one embodiment, each of the multiple dummy structures 127 may include a circular, elliptical, elongated, rectangular, or polygonal planar shape.

[0058] Referring to F5 in Figure 9, each of the dummy structures 127A that are not placed on the test pad 125 is placed on the protective layer 126. Each of the dummy structures 127A that are not placed on the test pad 125 has a first thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first thickness T1, or it may be greater than the first thickness T1. Each of the dummy structures 127B placed on the test pad 125 is placed on the corresponding test pad 125 within the first region R1. Each of the dummy structures 127B placed on the test pad 125 is a dummy pillar. There may be no solder balls on each of the dummy structures 127B of the dummy pillar. Each of the dummy structures 127B placed on the test pad 125 has a fourth thickness T4 in the vertical direction (Z direction). The fourth thickness T4 is smaller than the second thickness T2. The fourth thickness T4 is the same as the third thickness T3.

[0059] Figure 10 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F6 in Figure 10 is a cross-sectional view taken along line BB at E6 in Figure 11. Referring to E6 in Figure 10, one dummy structure 127 covers at least a portion of the first region R1, including the test pad 125.

[0060] One dummy structure 127 is positioned to contact the test pad 125. One dummy structure 127 overlaps the test pad 125 in the vertical direction (Z direction). The footprint of one dummy structure 127 overlaps with the footprint of the test pad 125. In Figure 10, E6, one dummy structure 127 is shown as having a rectangular planar shape, but is not limited to this, and in one embodiment, one dummy structure 127 may include a circular, elliptical, rectangular, or polygonal planar shape.

[0061] Referring to F6 in Figure 10, the dummy structure 127 is placed on the protective layer 126 and on the test pad 125 within the first region R1. The dummy structure 127 has a first maximum thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first maximum thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first maximum thickness T1, or it may be greater than the first maximum thickness T1.

[0062] Figure 11 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F7 in Figure 11 is a cross-sectional view taken along line BB at E7 in Figure 11. Referring to E7 in Figure 11, the multiple dummy structures 127, including the test pad 125, cover at least a portion of the first region R1.

[0063] Multiple dummy structures 127 are positioned to contact the test pad 125. Multiple dummy structures 127 overlap the test pad 125 in the vertical direction (Z direction). The footprints of the multiple dummy structures 127 overlap the footprint of the test pad 125. In Figure 11, E7 shows that each of the multiple dummy structures 127 has a rectangular planar shape, but is not limited to this, and in one embodiment, each of the multiple dummy structures 127 may include a circular, elliptical, rectangular, or polygonal planar shape.

[0064] Referring to F7 in Figure 11, the dummy structure 127 is placed on the protective layer 126 and on the test pad 125 within the first region R1. The dummy structure 127 has a first maximum thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first maximum thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first maximum thickness T1, or it may be greater than the first maximum thickness T1.

[0065] Figure 12 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F8 in Figure 12 is a cross-sectional view taken along line BB at E8 in Figure 12. Referring to E8 in Figure 12, the multiple dummy structures 127, including the test pad 125, cover at least a portion of the first region R1.

[0066] Multiple dummy structures 127 are positioned to contact the test pad 125. Multiple dummy structures 127 are arranged so as to extend in the first horizontal direction (X direction). Multiple dummy structures 127 overlap the test pad 125 in the vertical direction (Z direction). The footprints of the multiple dummy structures 127 overlap the footprint of the test pad 125. In Figure 12, E8 shows that each of the multiple dummy structures 127 has a rectangular planar shape, but is not limited to this, and in one embodiment, each of the multiple dummy structures 127 may include a circular, elliptical, rectangular, or polygonal planar shape.

[0067] Referring to F8 in Figure 12, the dummy structure 127 is placed on the protective layer 126 and on the test pad 125 within the first region R1. The dummy structure 127 has a first maximum thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first maximum thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first maximum thickness T1, or it may be greater than the first maximum thickness T1.

[0068] Figure 13 is an enlarged view of one embodiment of region E in Figure 3 and region F in Figure 4. Region F9 in Figure 13 is a cross-sectional view taken along line BB at E9 in Figure 13. Referring to E9 in Figure 13, the multiple dummy structures 127, including the test pad 125, cover at least a portion of the first region R1.

[0069] Multiple dummy structures 127 are arranged in one or more columns. Multiple dummy structures 127 are positioned to contact the test pad 125. Multiple dummy structures 127 are arranged to extend in the second horizontal direction (Y direction). Multiple dummy structures 127 overlap one or more of the test pads 125 in the vertical direction (Z direction). The footprints of the multiple dummy structures 127 overlap the footprint of the test pad 125. In Figure 13, E9 is shown as having a rectangular, elongated planar shape, but is not limited to this, and in one embodiment, each of the multiple dummy structures 127 may include an elliptical, elongated, or polygonal, elongated planar shape.

[0070] Referring to F9 in Figure 13, each of the multiple dummy structures 127 is placed on the protective layer 126 and on the test pad 125 within the first region R1. Each of the multiple dummy structures 127 has a first maximum thickness T1 in the vertical direction (Z direction). The bump structure 110 includes a bump pillar 111 and a solder ball 112. The bump structure 110 has a second thickness T2 in the vertical direction (Z direction). The first maximum thickness T1 is smaller than the second thickness T2. The bump pillar 111 has a third thickness T3 in the vertical direction (Z direction). The third thickness T3 may be the same as the first maximum thickness T1, or it may be greater than the first maximum thickness T1.

[0071] Figures 14 to 27 are cross-sectional views illustrating a method for forming a dummy structure 127 on the base die 120 of the high-bandwidth memory HBM100A of Figure 4 according to an embodiment of the present invention.

[0072] Figure 14 is a cross-sectional view showing the step of providing the die base 121 of the base die 120. Referring to Figure 14, a base die 120 is provided in which a first through-silicon via TSV 123 is formed within the die base 121, a test pad 125 is formed in a first region R1 of the wiring layer of the front structure 122 of the base die 120, and a conductive pad 124 is formed in a second region R2 of the wiring layer.

[0073] Figure 15 is a cross-sectional view showing the process of forming the diffusion barrier layer 113U within the underbump metal radiator UBM layer 113. Referring to Figure 15, the diffusion barrier layer 113U is formed continuously and conformally along the protective layer 126 of the base die 120, along the surface of the conductive pad 124 exposed from the protective layer 126, and along the surface of the test pad 125 exposed from the protective layer 126. In one embodiment, the diffusion barrier layer 113U is formed by a sputtering process. In one embodiment, the diffusion barrier layer may include at least one of tantalum nitride, titanium nitride, tantalum, titanium, and alloys thereof. In one embodiment, the diffusion barrier layer has a thickness in the range of about 50 nm to about 500 nm. In one embodiment, a test process using a probe card is performed before forming the underbump metal radiator UBM layer 113 or before forming the dummy structure 127. This test leaves a recess shape as an indication that the probe card pins have made mechanical contact with the test pad 125.

[0074] Figure 16 is a cross-sectional view showing the step of forming the seed metal layer SL on the diffusion barrier layer 113U. Referring to Figure 16, the seed metal layer SL is formed on the diffusion barrier layer 113U. The seed metal layer SL is formed continuously and conformally along the diffusion barrier layer 113U. In one embodiment, the seed metal layer SL is formed by a sputtering process or an electroless plating process. In one embodiment, the seed metal layer has a thickness in the range of about 200 nm to about 800 nm. In one embodiment, the seed metal layer is formed from a copper alloy containing silver, chromium, nickel, tin, gold, and combinations thereof, or from copper.

[0075] Figure 17 is a cross-sectional view showing the process of forming the first photoresist PR1 on the seed metal layer SL. Referring to Figure 17, the first photoresist PR1 is coated onto the seed metal layer SL. In one embodiment, the first photoresist PR1 is formed by a spin coating process. In one embodiment, the first photoresist PR1 comprises an organic polymer resin containing a photosensitive substance.

[0076] Figure 18 is a cross-sectional view showing the steps involved in forming the first photoresist pattern PRP1. Referring to Figure 18, the first photoresist PR1 is exposed and developed to form the first photoresist pattern PRP1. The seed metal layer SL is exposed through the first photoresist pattern PRP1.

[0077] Figure 19 is a cross-sectional view showing the steps involved in forming one or more dummy structures 127. Referring to Figure 19, first, a metal film is grown from the formed seed metal layer SL by electroplating to form one or more dummy structures 127. One or more dummy structures 127 are formed within the first region R1. A dummy structure 127 of the dummy pillar is formed on the test pad 125. The seed metal layer SL is indistinguishable from one or more dummy structures 127. In one embodiment, the dummy structure 127 is formed from a copper alloy containing silver, chromium, nickel, tin, gold, and combinations thereof, or from copper.

[0078] Figure 20 is a cross-sectional view showing the step of removing the first photoresist pattern PRP1. Referring to Figure 20, the first photoresist pattern PRP1 is removed. In one embodiment, the first photoresist pattern PRP1 is removed by performing at least one of the following steps: etching, ashing, and stripping.

[0079] Figure 21 is a cross-sectional view showing the steps of forming the second photoresist PR2 on the seed metal layer SL and on one or more dummy structures 127. Referring to Figure 21, the second photoresist PR2 is coated onto the seed metal layer SL and onto one or more dummy structures 127. In one embodiment, the second photoresist PR2 is formed by a spin coating process. In one embodiment, the second photoresist PR2 comprises an organic polymer resin containing a photosensitive substance.

[0080] Figure 22 is a cross-sectional view showing the steps involved in forming the second photoresist pattern PRP2. Referring to Figure 22, the second photoresist PR2 is exposed and developed to form the second photoresist pattern PRP2. The seed metal layer SL is exposed through the second photoresist pattern PRP2.

[0081] Figure 23 is a cross-sectional view showing the steps involved in forming the bump pillar 111. Referring to Figure 23, the bump pillar 111 is formed by growing a metal film from the previously formed seed metal layer SL by electroplating. The bump pillar 111 is formed within the second region R2. Each of the bump pillars 111 is formed on the corresponding conductive pad 124 of the conductive pads 124. The seed metal layer SL is indistinguishable from the bump pillar 111. In one embodiment, the bump pillar 111 is formed from a copper alloy containing chromium, nickel, tin, gold, and combinations thereof, or from copper. In one embodiment, the dummy structure 127 and the bump pillar 111 are formed from the same material.

[0082] Figure 24 is a cross-sectional view showing the steps involved in forming the solder ball 112. Referring to Figure 24, a metal film is grown by electroplating to form solder balls 112. Each of the solder balls 112 is formed on the corresponding bump pillar 111 of the bump pillars 111. In one embodiment, the solder ball 112 may contain at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0083] Figure 25 is a cross-sectional view showing the step of removing the second photoresist pattern PRP2. Referring to Figure 25, the second photoresist pattern PRP2 is removed. In one embodiment, the second photoresist pattern PRP2 is removed by performing at least one of the following steps: etching, ashing, and stripping.

[0084] Figure 26 is a cross-sectional view showing the steps for removing the seed metal layer SL and the diffusion barrier layer 113U. Referring to Figure 26, the exposed seed metal layer SL and the diffusion barrier layer 113U are removed. In one embodiment, the seed metal layer SL and the diffusion barrier layer 113U are removed by an etching process.

[0085] Figure 27 is a cross-sectional view showing the reflow process of the solder balls 112. Referring to Figure 27, the solder ball 112 is formed in a hemispherical shape by the reflow process.

[0086] Figures 28 to 31 are cross-sectional views illustrating a method for forming the high-bandwidth memory HBM100A shown in Figure 4 according to an embodiment of the present invention.

[0087] Figure 28 is a cross-sectional view showing the steps of sequentially stacking memory dies 130 on the base die 120. Referring to Figure 28, the hybrid bonding process is carried out sequentially, and the memory dies 130 are stacked sequentially on the base die 120. The following describes the hybrid bonding process between the base die 120 and the memory die 130. The explanation for the hybrid bonding process between the base die 120 and the memory die 130 also applies to the hybrid bonding process in a process in which the memory dies 130 are stacked sequentially.

[0088] A chemical mechanical polishing (CMP) process is performed before hybrid bonding. In one embodiment, the surface roughness of each bonding surface on which hybrid bonding is performed is approximately 10 Å or less. Subsequently, the bonding surface of the back silicon layer 141 of the base die 120 and the bonding surface of the front silicon layer 142 of the memory die 130 are activated. In one embodiment, the bonding surface of the back silicon layer 141 and the bonding surface of the front silicon layer 142 are surface-treated by plasma activation. Subsequently, the first base die 120 and the memory die 130 are aligned for hybrid bonding. Subsequently, pre-bonding is performed by bringing the activated bonding surface of the back silicon layer 141 of the base die 120 into contact with the activated bonding surface of the front silicon layer 142 of the memory die 130.

[0089] Subsequently, the base die 120 and the memory die 130 are subjected to hybrid bonding. First, the back silicone layer 141 of the base die 120 and the front silicone layer 142 of the memory die 130 are bonded together by treatment. The treatment strengthens the bonding between the back silicone layer 141 of the pre-bonded base die 120 and the front silicone layer 142 of the memory die 130. Subsequently, each of the rear bonding pads 143 of the base die 120 and each of the front bonding pads 144 of the memory die 130 are bonded by annealing. Subsequently, the same hybrid process is performed to sequentially stack the memory dies 130.

[0090] Figure 29 is a cross-sectional view showing the step of attaching a dummy die 160 onto the memory stack S. Referring to Figure 29, a dummy die 160 is attached to the memory stack S. The dummy die 160 may be attached to the memory stack S by an adhesive member 150. In one embodiment, the adhesive member 150 includes a thermal interface material TIM. In one embodiment, the adhesive member 150 may include a thermal paste, a thermal pad, a PCM (Phase Change Material), a metallic material, or grease.

[0091] Figure 30 is a cross-sectional view showing the steps of molding the memory stack S, the adhesive member 150, and the dummy die 160 on the base die 120. Referring to Figure 30, the memory stack S is molded on the base die 120 using the adhesive member 150, and the dummy die 160 is molded using the molding material 170. In one embodiment, the molding process using the molding material 170 includes a compression molding process or a transfer molding process. In one embodiment, the molding material 170 includes an epoxy molding compound (EMC).

[0092] Figure 31 is a cross-sectional view showing the stage in which the molding material 170 undergoes a chemical mechanical polishing (CMP) process. Referring to Figure 31, a chemical mechanical polishing (CMP) process is performed to level the upper surface of the molding material 170. After the chemical mechanical polishing (CMP) process, the upper surface of the dummy die 160 is exposed.

[0093] Figure 32 is a cross-sectional view showing a schematic configuration of a high-bandwidth memory HBM100B1 according to one embodiment of the present invention. The details regarding the lower surface 120A of the base die 120 of the high-bandwidth memory HBM100A of one embodiment shown in Figure 4, as described in Figure 3, also apply to the high-bandwidth memory HBM100B1 of one embodiment shown in Figure 32.

[0094] Referring to Figure 32, the first interconnection structure 140A is positioned between the back surface 121B of the die base 121 and the memory stack S. The second interconnection structure 140 is stacked alternately with the memory die 130. Each of the second interconnection structures 140 is positioned between the back surface 131B of the memory die base 131 of the memory die 130 and the front surface structure 132 of the adjacent memory die 130. The first interconnection structure 140A and the second interconnection structure 140 each include a bonding pad 145, a second bump structure 146, and an insulating member 149, respectively. With the new definition of the second bump structure 146, the bump structure 110 shall be referred to as the first bump structure 110.

[0095] Each of the bonding pads 145 of the first interconnection structure 140A is positioned between the corresponding first through-silicon via TSV 123 of the first through-silicon via TSV 123 and the corresponding second bump structure 146 of the second bump structure 146. Each of the bonding pads 145 of the first interconnection structure 140A electrically connects the corresponding first through-silicon via TSV 123 of the first through-silicon via TSV 123 to the corresponding second bump structure 146 of the second bump structure 146. Each of the bonding pads 145 of the second interconnection structure 140 is positioned between the corresponding second through-silicon via TSV 133 and the corresponding second bump structure 146 of the second through-silicon via TSV 133. Each of the bonding pads 145 of the second interconnection structure 140 electrically connects the corresponding second through-silicon via TSV 133 of the second through-silicon via TSV 133 to the corresponding second bump structure 146 of the second bump structure 146. In one embodiment, the bonding pad 145 may contain at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0096] The second bump structure 146 is positioned between the base die 120 and the memory stack S, or between one memory die 130 and another adjacent memory die 130. Each of the second bump structures 146 is positioned between the corresponding bonding pad 145 of the bonding pads 145 and the corresponding wiring of the front structure 132 of the memory die 130. Each of the second bump structures 146 includes a bump pillar 147 and a solder ball 148. In one embodiment, the second bump structure 146 includes microbumps. Each of the bump pillars 147 is positioned between the corresponding solder ball 148 and the corresponding wiring of the front structure 132 of the memory die 130. Each of the bump pillars 147 electrically connects the corresponding wiring of the front structure 132 of the memory die 130 to the corresponding solder ball 148.

[0097] Each of the solder balls 148 is positioned between the corresponding bonding pad 145 and the corresponding bump pillar 147. Each of the solder balls 148 electrically connects the corresponding bump pillar 147 of the bump pillars 147 to the corresponding bonding pad 145 of the bonding pads 145. In one embodiment, the bump pillar 147 is formed from a copper alloy containing silver, chromium, nickel, tin, gold, and combinations thereof, or from copper. In one embodiment, the solder ball 148 may contain at least one of tin, silver, lead, nickel, copper, and alloys thereof. Each of the insulating members 149 is placed between the base die 120 and the memory stack S, or between one memory die 130 and another adjacent memory die 130. Each of the insulating members 149 surrounds and insulates the bonding pad 145 and the second bump structure 146. In one embodiment, the insulating member 149 includes a non-conductive film (NCF). For the high-bandwidth memory HBM100B1 shown in Figure 32, other than what has been described above, the same information as that provided for the high-bandwidth memory HBM100A in Figures 3 to 27 applies.

[0098] Figures 33 to 36 are cross-sectional views illustrating a method for forming the high-bandwidth memory HBM100B1 of Figure 32 according to an embodiment of the present invention.

[0099] Figure 33 is a cross-sectional view showing the steps of sequentially stacking memory dies 130 on the base die 120. Referring to Figure 33, each memory die 130 is sequentially bonded onto the base die 120 by a thermocompression bonding (TC) process. An insulating member 149 is attached to the lower surface of each memory die 130, and the second bump structure 146 on the lower surface of the memory die 130 is surrounded by the insulating member 149. The thermocompression bonding (TC) process bonds each of the second bump structures 146 to the corresponding bonding pad 145 of the bonding pads 145. The insulating member 149 is in a gel state before the thermocompression bonding (TC) process. During the thermocompression bonding (TC) process, heat is applied, changing it from a gel state to a liquid state, and finally it becomes a hardened state.

[0100] Figure 34 is a cross-sectional view showing the step of attaching the dummy die 160 onto the memory stack S. Referring to Figure 34, a dummy die 160 is attached to the memory stack S. The dummy die 160 is attached to the memory stack S by an adhesive member 150. In one embodiment, the adhesive member 150 includes a thermal interface material TIM. In one embodiment, the adhesive member 150 may include a thermal paste, a thermal pad, a PCM (Phase Change Material), a metallic material, or grease.

[0101] Figure 35 is a cross-sectional view showing the steps of molding the memory stack S, the adhesive member 150, and the dummy die 160 on the base die 120. Referring to Figure 35, the memory stack S is molded on the base die 120 with the adhesive member 150, and the dummy die 160 is molded with the molding material 170. In one embodiment, the process of molding with the molding material 170 includes a compression molding process or a transfer molding process. In one embodiment, the molding material 170 includes epoxy molding compound EMC.

[0102] Figure 36 is a cross-sectional view showing the stage in which the molding material 170 undergoes a chemical mechanical polishing (CMP) process. Referring to Figure 36, a chemical mechanical polishing (CMP) process is performed to level the upper surface of the molding material 170. After the chemical mechanical polishing (CMP) process, the upper surface of the dummy die 160 is exposed.

[0103] Figure 37 is a cross-sectional view showing a schematic configuration of a high-bandwidth memory HBM100B2 according to one embodiment of the present invention. The details regarding the lower surface 120A of the base die 120 of the high-bandwidth memory HBM100A of one embodiment shown in Figure 4, as described in Figure 3, also apply to the high-bandwidth memory HBM100B2 of one embodiment shown in Figure 37.

[0104] Referring to Figure 37, the insulating member 149 includes MUF (Molded Underfill). The insulating member 149 may contain the same material as the molding material 170 and be formed integrally with the molding material 170. In one embodiment, the insulating member 149 includes epoxy molding compound EMC. The information regarding the high-bandwidth memory HBM100B2 in Figure 7, other than what has been described above, can be applied by referring to the high-bandwidth memory HBM100B1 in Figure 32.

[0105] Figures 38 to 41 are cross-sectional views illustrating a method for forming the high-bandwidth memory HBM100B2 of Figure 37 according to an embodiment of the present invention.

[0106] Figure 38 is a cross-sectional view showing the steps of sequentially stacking memory dies 130 on the base die 120. Referring to Figure 38, each memory die 130 is sequentially stacked on the base die 120 by a flip-chip bonding process.

[0107] Figure 39 is a cross-sectional view showing the step of attaching a dummy die 160 onto the stacked memory die 130. Referring to Figure 39, a dummy die 160 is attached to the stacked memory die 130. The dummy die 160 may be attached to the memory die 130 which is stacked by the adhesive member 150. In one embodiment, the adhesive member 150 includes a thermal interface material TIM. In one embodiment, the adhesive member 150 may include a thermal paste, a thermal pad, a PCM (Phase Change Material), a metallic material, or grease.

[0108] Figure 40 is a cross-sectional view showing the steps of molding the memory die 130, which is stacked on the base die 120, the adhesive member 150, and the dummy die 160. Referring to Figure 40, the stacked memory dies 130 are molded on the base die 120 with an adhesive member 150, and the dummy die 160 is molded with a molding material 170. While the molding process is being carried out, the molding material 170 simultaneously functions as an insulating member 149, filling the space between the base die 120 and the memory die 130 adjacent to the base die 120, and between one memory die 130 and another memory die 130 adjacent to it. The insulating material 149 is made of the same material as the molding material 170. The insulating member 149 and the molding material 170 will be in a hardened state after the molding process is completed. In one embodiment, the process of molding with the molding material 170 includes a compression molding process or a transfer molding process. In one embodiment, the molding material 170 includes epoxy molding compound EMC.

[0109] Figure 41 is a cross-sectional view showing the stage in which the molding material 170 undergoes a chemical mechanical polishing (CMP) process. Referring to Figure 41, a chemical mechanical polishing (CMP) process is performed to level the upper surface of the molding material 170. After the chemical mechanical polishing (CMP) process, the upper surface of the dummy die 160 is exposed.

[0110] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0111] 100 High-bandwidth memory 110 Bump structure 111 Bump pillar 112 Solder ball 113 Underbump Metal Radio 113U diffusion barrier layer 120 base die 121 Die Base 122 Front structure 123 First Through-Silicon Via TSV 124 Conductive Pads 125 Test Pads 126 Protective layer 127 Dummy Structure 130, 130T memory die 131 Memory die base 132 Front structure 133 Second Through-Penetration Silicon Via TSV 140A First interconnection structure 140 Second interconnection structure 141 Back silicone layer 142 Front Silicone Layer 143 Back Bonding Pad 144 Front Bonding Pad 145 Bonding Pad 146 Second Bump Structure 147 Bump Pillar 148 solder balls 149 Insulating material 150 Adhesive Members 160 Dummy Dies 170 Molding material S Memory stack (semiconductor stack) SL Seed Metal Layer

Claims

1. High-bandwidth memory, A base die including a first surface and a second surface facing the first surface, Here, the first surface includes a first region and a second region surrounding the first region. One or more dummy structures placed on the first region, Multiple bump structures are arranged on the second region and next to one or more dummy structures, A high-bandwidth memory characterized by having a semiconductor stack including a plurality of core dies arranged on the second surface of the base die.

2. The high-bandwidth memory according to claim 1, characterized in that the one or more dummy structures are electrically isolated from the base die.

3. Each of the aforementioned bump structures is Bump pillar and, The set includes a solder ball positioned on the bump pillar, The base die includes a plurality of test pads within the first region, The high-bandwidth memory according to claim 1, characterized in that the plurality of test pads on the plane are spaced apart from the solder balls.

4. The one or more dummy structures have a first thickness in the vertical direction, The aforementioned multiple bump structures have a second thickness in the vertical direction, The high-bandwidth memory according to claim 1, characterized in that the first thickness is smaller than the second thickness.

5. Each of the aforementioned bump structures is Bump pillar and, The set includes a solder ball positioned on the bump pillar, The bump pillar has a third thickness in the vertical direction, The high-bandwidth memory according to claim 4, characterized in that the third thickness is the same as or greater than the first thickness.

6. The high-bandwidth memory according to claim 1, characterized in that the one or more dummy structures are dummy pillars.

7. The high-bandwidth memory according to claim 6, characterized in that the dummy pillar is electrically isolated from external devices of the high-bandwidth memory.

8. Buffer die and Here, the buffer die is A die base including a front surface and a rear surface facing the front surface, An element layer disposed on the front surface of the die base, The element layer includes a wiring layer disposed on the element layer, The wiring layer includes a first region and a second region surrounding the first region, and the wiring layer includes a plurality of test pads in the first region and a plurality of conductive pads in the second region. One or more dummy structures on the first region, Multiple bump structures on the second region, Here, each of the plurality of bump structures is placed on the corresponding conductive pad of the plurality of conductive pads, A high-bandwidth memory characterized by having a memory stack, which includes a plurality of memory dies, and which is disposed on the back surface of the die base.

9. The buffer die includes a plurality of signal-through silicon vias and a plurality of power-through silicon vias, The high-bandwidth memory according to claim 8, characterized in that each of the plurality of test pads is directly electrically connected to a corresponding signal-through silicon via among the plurality of signal-through silicon vias or a corresponding power-through silicon via among the plurality of power-through silicon vias.

10. The high-bandwidth memory according to claim 8, characterized in that the one or more dummy structures are electrically isolated from the plurality of test pads.

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