Memory controller, memory device, and memory system

Abstract

The present invention provides a memory controller, memory device, and memory system that reduce the delay in general operation. [Solution] Embodiments of the present disclosure provide a memory system including a memory device that provides data processing functions such as arithmetic functions, wherein at least one of the remaining ranks performs general operations such as write or read operations during at least a portion of the period in which some of the N ranks sharing a data channel perform arithmetic operations, thereby providing arithmetic functions and reducing the delay of general operations.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory controller, a memory device, and a memory system.

Background Art

[0002] A memory device can include a plurality of memory cells that store data. The memory device can, for example, store data according to a command from a host device or provide stored data to the host device.

[0003] The host device can perform calculations using the data stored in the memory device and provide a data processing result corresponding to the calculations. As the amount of calculations executed by the host device increases, the amount of data transferred between the host device and the memory device for the calculations may increase.

[0004] As the amount of data transferred between the host device and the memory device increases, the operating performance of the memory device and the computing system including the memory device and the host device may decrease.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problems of the embodiments of the present disclosure are not limited to the problems mentioned in this specification, and further problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Embodiments of the present disclosure can provide a solution that provides a computing function by a memory device and improves the operating efficiency of the memory device during the period in which the computing function by the memory device is executed.

Means for Solving the Problems

[0007] Embodiments of the present disclosure can provide a memory system including a memory controller that controls the operation of the multiple ranks based on commands waiting for each of the multiple ranks, and controls that for at least a portion of a first period in which P (integer N>P≧1) racks of N (integer N≧2) ranks sharing a data channel operate according to a first command, at least one of the (NP) ranks operates according to a second command, and the operation according to the second command is performed without the operation of the arithmetic logic.

[0008] Embodiments of the present disclosure can provide a memory controller that includes at least one command queue for storing a first command and a second command for each of a plurality of ranks, and a scheduler that, based on the number of first commands and the number of second commands, sets commands to be executed by each of the plurality of ranks during a preset operating period, and, if the number of second commands is greater than zero, sets so that while some of the plurality of ranks are performing operations according to the first commands, at least one of the remaining ranks is performing operations according to the second commands.

[0009] Embodiments of the present disclosure provide a memory device comprising a first rank having a plurality of first banks, each including a first memory cell array and a first arithmetic logic that performs operations using the first memory cell array, and a second rank having a plurality of second banks, each including a second memory cell array and a second arithmetic logic that performs operations using the second memory cell array, wherein the first and second ranks share a data channel, and a program operation or read operation is performed on the second memory cell array during a first period in which the first arithmetic logic in the first rank is operating, without the operation of the second arithmetic logic in the second rank.

[0010] Embodiments of the present disclosure provide a memory device comprising a first memory chip having a plurality of first banks, each including a first memory cell array and a first arithmetic logic that performs calculations using the first memory cell array, and a second memory chip having a plurality of second banks, each including a second memory cell array and a second arithmetic logic that performs calculations using the second memory cell array, wherein during a first period, the first arithmetic logic included in a first group of the plurality of first banks and the second arithmetic logic included in a first group of the plurality of second banks operate, while the first arithmetic logic included in a second group of the plurality of first banks and the second arithmetic logic included in a second group of the plurality of second banks do not operate.

[0011] Embodiments of the present disclosure provide a memory device comprising a first memory chip having a first memory cell array and a plurality of first banks including a first arithmetic logic that performs operations using the first memory cell array, and a second memory chip having a plurality of second banks including a second memory cell array, wherein a program operation or read operation is performed on the first group of the plurality of second banks for at least a portion of a first period in which the first arithmetic logic included in the first group of the plurality of first banks is in operation. [Effects of the Invention]

[0012] According to embodiments of this disclosure, the arithmetic function of the memory device can improve data processing performance using the memory device, and the operational performance of the memory device can be improved through the operation scheduling of the memory device during the period in which the arithmetic function of the memory device is executed.

[0013] The effects of the embodiments of this disclosure are not limited to those mentioned above, and any further effects not mentioned will be clearly understood by those skilled in the art from the claims. [Brief explanation of the drawing]

[0014] The content of the present disclosure will be more fully understood from the following detailed description and the accompanying drawings. The detailed description and the accompanying drawings are provided for illustrative purposes only and do not limit the content of the present disclosure.

[0015] [Figure 1] FIG. is a diagram showing an example of a schematic configuration of a memory system according to an embodiment of the present disclosure.

[0016] [Figure 2] FIG. is a diagram showing an example of a memory device included in a memory system according to an embodiment of the present disclosure.

[0017] [Figure 3] FIG. is a diagram showing another example of a memory device included in a memory system according to an embodiment of the present disclosure.

[0018] [Figure 4] FIG. is a diagram showing an example of an operation mode of the memory system shown in FIG. 3. [Figure 5] FIG. is a diagram showing an example of an operation mode of the memory system shown in FIG. 3.

[0019] [Figure 6] FIG. is a diagram showing an example of an operation timing of the memory system shown in FIG. 3. [Figure 7] FIG. is a diagram showing an example of an operation timing of the memory system shown in FIG. 3.

[0020] [Figure 8] FIG. is a diagram showing another example of an operation mode of the memory system according to an embodiment of the present disclosure.

[0021] [Figure 9a] FIG. is a diagram showing an exemplification of operation modes of various types of memory systems according to an embodiment of the present disclosure. [Figure 9b] FIG. is a diagram showing an exemplification of operation modes of various types of memory systems according to an embodiment of the present disclosure. [Figure 10]This figure shows examples of the operating modes of various types of memory systems according to embodiments of the present disclosure. [Modes for carrying out the invention]

[0022] Hereinafter, some embodiments of this disclosure will be described in detail with reference to illustrative drawings. In assigning reference numerals to components in each drawing, the same reference numeral may be used for the same component whenever possible, even if it is shown in other drawings. In describing this disclosure, if it is determined that a specific description of a relevant known configuration or function would obscure the gist of this disclosure, such detailed description will be omitted. Where the terms “includes,” “has,” “consists of,” etc., used herein, other parts may be added unless “only” is used. When a component is expressed singularly, it may include multiple components unless otherwise explicitly stated.

[0023] Furthermore, in describing the components of this disclosure, terms such as 1, 2, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of such components.

[0024] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0025] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0026] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0027] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0028] Figure 1 shows an example of a schematic configuration of the memory system 100 according to an embodiment of the present disclosure.

[0029] Referring to Figure 1, the memory system 100 according to an embodiment of the present disclosure may include at least one memory device 110. The memory system 100 may include a memory controller 120 that controls the operation of the memory device 110.

[0030] The memory device 110 may be a volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, but the embodiments of this disclosure are not limited thereto. The memory device 110 may also be a non-volatile memory such as NAND flash memory, 3D NAND flash memory, or NOA flash memory. In some cases, a portion of the memory device 110 included in the memory system 100 may be a volatile memory and another portion may be a non-volatile memory.

[0031] Furthermore, the memory device 110 may be one of various types of memory, such as a resistive RAM, a phase-change memory, a self-resistive memory, a ferroelectric memory, or a spin-transfer magnetization reversal memory.

[0032] Furthermore, the memory device 110 may, in some cases, be a processing-in-memory including arithmetic functions or data processing functions. The configuration for performing arithmetic functions in the memory device 110 may be located inside or outside the bank of the memory device 110. If located outside the bank, the configuration for performing arithmetic functions may be located adjacent to the bank or in an area separated from the bank. In this specification, the memory device 110 may be referred to as a memory chip or memory.

[0033] The memory controller 120 can control the operation of the memory device 110 based on commands received from an external source. The memory controller 120 can also control the operation of the memory device 110 based on its own commands.

[0034] The memory controller 120 can send commands, addresses, data, etc., to the memory device 110 to control its operation. A physical layer for sending and receiving signals may be located outside or inside the memory controller 120. The memory controller 120 may include multiple logics that perform various functions and may be implemented as a single chip, or in some cases, at least some of the multiple logics may be implemented as chiplets. For example, the memory controller 120 can control data writing operations to the memory device 110. The memory controller 120 can control operations to read data written to the memory device 110.

[0035] The memory controller 120 can control refresh or erase operations on the data written to the memory device 110, depending on the type of memory device 110.

[0036] The memory controller 120 can perform operations to detect and correct errors in the data read from the memory device 110. In some cases, the error correction operation may be performed inside the memory device 110.

[0037] The memory controller 120 can control the operation of the memory device 110 based on commands received from the external host device 200.

[0038] The host device 200 may, for example, be a computer, UMPC (Ultra Mobile PC), workstation, PDA (Personal Digital Assistant), tablet, mobile phone, smartphone, e-book, PMP (Portable Multimedia Player), portable game console, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, smart television, digital audio recorder, digital audio player, digital video recorder, digital video player, digital video recorder, digital video player, storage constituting a data center, one of various electronic devices constituting a home network, one of various electronic devices constituting a telematics network, RFID (Radio Frequency Identification) device, or a mobile device that operates in response to human control or autonomously (e.g., vehicle, robot, drone). Alternatively, the host device 200 may be a virtual / augmented reality device that provides two-dimensional or three-dimensional virtual reality images or augmented reality images. Furthermore, in addition to the examples above, the host device 200 may be any of various electronic devices that require a memory system 100 capable of storing data for data processing. Furthermore, the host device 200 may be, but is not limited to, a processor such as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), NPU (Neural Processing Unit), or TPU (Tensor Processing Unit). The host device 200 and the memory system 100 together may be referred to as a computing system. The computing system may include at least one memory system 100 arranged around the host device 200, and may further include at least one data storage device other than the memory system 100.

[0039] The host device 200 may include at least one operating system. The operating system can manage and control the overall functions and operations of the host device 200 and can control the interaction between the host device 200 and the memory system 100. Depending on the mobility of the host device 200, the operating system can be classified into a general operating system and a mobile operating system.

[0040] The memory controller 120 and the host device 200 may be separate devices. In some cases, the memory controller 120 and the host device 200 may be integrated into a single device. All functions of the memory controller 120 may be integrated into the host device 200, or some functions of the memory controller 120 may be integrated into the host device 200. For the sake of explanation, the following description will illustrate the case where the memory controller 120 is located inside the memory system 100 as a separate device from the host device 200, but the embodiments of this disclosure are not limited thereto.

[0041] The memory system 100 according to an embodiment of the present disclosure can perform a portion of the arithmetic functions of a host device 200 and provide the arithmetic results to the host device 200. The memory system 100 may include at least one memory device 110 that provides the arithmetic functions. The memory controller 120 can control whether or not the arithmetic functions of the memory device 110 are executed, the timing of the execution of the arithmetic functions, and so on. By providing the arithmetic functions through the memory system 100, the operational performance of a computing system that performs data processing using the memory system 100 may be improved.

[0042] Figure 2 shows an example of a memory device 110 included in the memory system 100 according to an embodiment of the present disclosure.

[0043] Referring to Figure 2, the memory system 100 may include a memory device 110 and a memory controller 120.

[0044] The memory system 100 may, for example, include a first memory device 111 and a second memory device 112.

[0045] The first memory device 111 may include a plurality of first banks 310. Each of the plurality of first banks 310 may include a first memory cell array 311 and a first arithmetic logic 312. While the description illustrates the case where the first arithmetic logic 312 is located inside the first bank 310, embodiments of this disclosure may also apply when the first arithmetic logic 312 is located outside the first bank 310.

[0046] The second memory device 112 may include a plurality of second banks 320. Each of the plurality of second banks 320 may include a second memory cell array 321. Each of the plurality of second banks 320 may include circuitry for the operation of the second memory cell array 321.

[0047] The memory system 100 may include memory devices 110 that provide arithmetic functions, such as the first memory device 111, and memory devices 110 that do not provide arithmetic functions, such as the second memory device 112. The memory system 100 may include at least one first memory device 111 and at least one second memory device 112. In some cases, the memory system 100 may also include only memory devices 110 that provide arithmetic functions, such as the first memory device 111.

[0048] The memory system 100 can schedule commands to be processed by the first memory device 111 and the second memory device 112, and control the operation of the first memory device 111 and the second memory device 112, in order to ensure efficient operation of the first memory device 111 and the second memory device 112.

[0049] For example, the memory controller 120 of the memory system 100 may include a command queue 121 and a scheduler 122. The command queue 121 may, for example, store commands received from the host device 200. The command queue 121 may store the entire command in order, or it may store the commands waiting for each memory device 110 in order.

[0050] The scheduler 122 can control the types and order of commands processed by the first memory device 111 and the second memory device 112 based on the commands stored in the command queue 121.

[0051] For example, the first memory device 111 can share a data channel with the second memory device 112. The scheduler 122 can control the command processing operations of the first memory device 111 and the second memory device 112 that share a data channel. The scheduler 122 can control the operations of the first memory device 111 and the second memory device 112 according to the commands stored in the command queue 121.

[0052] The scheduler 122 can control the first memory device 111 to perform operations using the first arithmetic logic 312 according to commands stored in the command queue 121. The scheduler 122 can control operations to write data to the second memory device 112 or read data written to the second memory device 112 during at least a portion of the period in which the operations of the first arithmetic logic 312 of the first memory device 111 are performed.

[0053] The scheduler 122 can perform operations to write data to the first memory device 111 or read data written to the first memory device 111, depending on the waiting order of commands stored in the command queue 121. The scheduler 122 can control the execution of write or read operations to the first memory device 111 depending on the waiting order of commands for the first memory device 111 and commands for the second memory device 112.

[0054] The scheduler 122 can improve the command processing performance of the first memory device 111 and the second memory device 112 by controlling the operation order of the first memory device 111 and the second memory device 112 based on the type, order, and number of commands waiting in the first memory device 111 and the second memory device 112, which share a data channel.

[0055] Alternatively, as in the example above, the memory system 100 may include a memory device 110 that provides arithmetic functions and a memory device 110 that does not provide arithmetic functions, or the memory system 100 may be composed of a memory device 110 that provides arithmetic functions. Even in such cases, the scheduler 122 of the memory controller 120 can control the operation of the memory devices 110 that share data channels, thereby improving the operational efficiency of the memory system 100.

[0056] Figure 3 shows another example of a memory device 110 included in the memory system 100 according to an embodiment of the present disclosure.

[0057] Referring to Figure 3, the memory system 100 may include at least one memory device 110. The memory system 100 may also include a memory controller 120 that controls the operation of the at least one memory device 110.

[0058] At least one memory device 110 can be divided into at least one rank 400. A rank 400 can mean a unit that operates according to the control of the memory controller 120. A rank 400 may, for example, be a part of a memory device 110. Alternatively, a rank 400 may include parts of each of multiple memory devices 110. For example, parts corresponding to a first group of each of multiple memory devices 110 may constitute one rank 400.

[0059] The memory system 100 may include a first rank 410 and a second rank 420. The first rank 410 may share a data channel with the second rank 420. The two ranks 400 included in the memory system 100 are just an example, and the number of ranks 400 included in the memory system 100 can vary.

[0060] The first rank 410 may include multiple first banks (310a, 310b, ..., 310k). These multiple first banks (310a, 310b, ..., 310k) may be contained in the same memory device 110. Alternatively, each of the multiple first banks (310a, 310b, ..., 310k) may be contained in a different memory device 110.

[0061] Each of the multiple first banks (310a, 310b, ..., 310k) may contain a first memory cell array (311a, 311b, ..., 311k) and a first arithmetic logic (312a, 312b, ..., 312k). The first arithmetic logic (312a, 312b, ..., 312k) may be located inside the multiple first banks (310a, 310b, ..., 310k), or, in some cases, outside the multiple first banks (310a, 310b, ..., 310k).

[0062] The second rank 420 may include multiple second banks (320a, 320b, ..., 320k). These multiple second banks (320a, 320b, ..., 320k) may be contained in the same memory device 110 or in different memory devices 110. At least some of the multiple second banks (320a, 320b, ..., 320k) may be contained in the same memory device 110 as at least some of the multiple first banks (310a, 310b, ..., 310k). For example, the first bank 310a and the second bank 320a may be contained in the same memory device 110.

[0063] Each of the multiple second banks (320a, 320b, ..., 320k) may contain a second memory cell array (321a, 321b, ..., 321k) and a second arithmetic logic (322a, 322b, ..., 322k). The second arithmetic logic (322a, 322b, ..., 322k) may be located inside the multiple second banks (320a, 320b, ..., 320k), or, in some cases, outside the multiple second banks (320a, 320b, ..., 320k).

[0064] The memory controller 122 may include a command queue 121 and a scheduler 122. The command queue 121 can store commands for each rank 400.

[0065] For example, command queue 121 can store a first command CMDa and a second command CMDb waiting for a first rank 410. Command queue 121 can also store a first command CMDa and a second command CMDb waiting for a second rank 420. The number and types of commands stored in command queue 121 can vary.

[0066] The first command CMDa may, for example, be a command that requires the operation of arithmetic logic included in each rank 400. When the first command CMDa is executed, either the first arithmetic logic 312 included in the first rank 410 will be executed, or the second arithmetic logic 322 included in the second rank 420 will be executed. The first command CMDa can be called an arithmetic command, and the operation performed in accordance with the first command CMDa can be called an arithmetic operation.

[0067] The arithmetic logic can perform calculations using data stored in the memory cell array in response to commands. For example, the arithmetic logic can read data stored in at least a portion of the memory cell array and perform calculations on the read data. The arithmetic logic can then store data corresponding to the calculation results in the memory cell array.

[0068] The second command CMDb may, for example, be a command that does not require the operation of arithmetic logic included in each rank 400. The second command CMDb may be a command that instructs an operation to write data to the memory cell array included in each rank 400, or to read data written to the memory cell array. The second command CMDb may include commands other than those that require the operation of arithmetic logic. The second command CMDb may be called a general command, and the operation performed in accordance with the second command CMDb may be called a general operation.

[0069] The first rank 410 or the second rank 420 can perform operations to write data to or read data written to the memory cell arrays included in each rank 400 when operating according to the second command CMDb. The arithmetic logic included in each rank 400 does not need to operate while operations according to the second command CMDb are being performed.

[0070] The scheduler 122 of the memory controller 120 can set the commands to be processed by each rank 400 based on the type, order, and number of commands waiting for each rank 400 in the command queue 121. The scheduler 122 can set the commands to be processed by the first rank 410 and the commands to be processed by the second rank 420 at pre-set intervals.

[0071] For example, if the number of second command CMDb stored in the command queue 121 is greater than 0, the scheduler 122 can control at least one of the multiple ranks 400 to operate according to the second command CMDb.

[0072] The scheduler 122 can control that, of the N (integer N≧2) rank 400s sharing a data channel, at least one of the (NP) rank 400s operates according to the second command CMDb for at least a portion of the period during which P (integer N>P≧1) rank 400s operate according to the first command CMDa.

[0073] As an example, in the example shown in Figure 3, the scheduler 122 can control the second rank 420 to operate according to the second command CMDb for at least a portion of the period during which the first rank 410 operates according to the first command CMDa. During the same period of time for ranks sharing a data channel, the first rank 410 can operate according to the first command CMDa, and the second rank 420 can operate according to the second command CMDb.

[0074] The scheduler 122 can control all of the ranks 400 to operate according to the first command CMDa if the number of second commands CMDb stored in the command queue 121 is 0.

[0075] The scheduler 122 can also control multiple ranks 400 to perform actions according to the first command CMDa if the waiting time for the first command CMDa stored in the command queue 121 is greater than or equal to a preset threshold time, even if the number of second commands CMDb stored in the command queue 121 is greater than 0.

[0076] The scheduler 122 controls the operation of the first rank 410 and the second rank 420, which share a data channel, based on commands stored in the command queue 121, so that the arithmetic operations of the memory device 110, which includes arithmetic logic, can be executed efficiently. In addition, since write or read operations are performed on other ranks 400 simultaneously while some ranks 400 sharing a data channel are performing arithmetic operations, delays in write or read operations caused by the provision of arithmetic functions can be prevented or reduced.

[0077] Figures 4 and 5 show an example of the operation method of the memory system 100 shown in Figure 3.

[0078] Referring to Figure 4, the memory controller 120 can check the type, order, number, etc., of commands stored in the command queue 121. The command queue for the first rank 410 may store the first command queue CMDa and the second command queue CMDb. The command queue for the second rank 420 may store the first command queue CMDa and the second command queue CMDb.

[0079] Commands waiting for each rank 400 may be divided into a first command CMDa that requires the operation of arithmetic logic and a second command CMDb that does not require the operation of arithmetic logic, and the number of commands waiting for each rank 400 may be three or more.

[0080] Since the number of second command CMDb stored in the command queue 121 is greater than 0, the memory controller 120 can set at least one rank 400 out of several ranks 400 that share the data channel to perform an action according to the second command CMDb.

[0081] For example, the memory controller 120 can be configured to operate according to the second command CMDb during a preset operating period. The memory controller 120 can also be configured to operate according to the first command CMDa during a preset operating period, where the first rank 410, which shares a data channel with the second rank 420, operates according to the first command CMDa.

[0082] During a pre-set operating period, the second rank 420 may operate according to the second command CMDb for at least a portion of the period during which the first rank 410 operates according to the first command CMDa.

[0083] Since the first rank 410 operates according to the first command CMDa, the first arithmetic logic (312a, 312b, ..., 312k) contained in the first bank (310a, 310b, ..., 310k) of the first rank 410 can operate. Since the second rank 420 operates according to the second command CMDb, the second arithmetic logic (322a, 322b, ..., 322k) contained in the second bank (320a, 320b, ..., 320k) of the second rank 420 does not need to operate. Data may be written to at least a portion of the second memory cell array (321a, 321b, ..., 321k) contained in the second bank (320a, 320b, ..., 320k), or a read operation may be performed on the written data.

[0084] During the period in which the calculation function of rank 400 is executed, write or read operations are performed on rank 400s that share a data channel with that rank 400. Therefore, it is possible to prevent a decrease in the performance of data write or read operations due to the execution of the calculation function.

[0085] The memory controller 120 can set the operating state of each rank 400 at intervals corresponding to a preset operating period.

[0086] As an example, referring to Figure 5, the memory controller 120 can set the operation of the first rank 410 and the second rank 420 for the next operation period after the operation period shown in Figure 4 has ended.

[0087] Once the arithmetic operations for the first rank 410 and the general operations for the second rank 420 are completed, the memory controller 120 can configure the operations for the first rank 410 and the second rank 420 based on the commands stored in the command queue 121.

[0088] The memory controller 120 can control at least some of the multiple first banks (310a, 310b, ..., 310k) included in the first rank 410 to operate according to a second command CMDb. The first arithmetic logic (312a, 312b, ..., 312k) included in the first banks (310a, 310b, ..., 310k) does not have to operate. Data may be written to the first memory cell arrays (311a, 311b, ..., 311k) included in the first banks (310a, 310b, ..., 310k), or read operations may be performed on the written data.

[0089] The memory controller 120 can control at least some of the multiple second banks (320a, 320b, ..., 320k) included in the second rank 420 to operate according to the first command CMDa. The second arithmetic logic (322a, 322b, ..., 322k) included in the second banks (320a, 320b, ..., 320k) can operate.

[0090] The second arithmetic logic (322a, 322b, ..., 322k) can read data written to the second memory cell array (321a, 321b, ..., 321k), perform calculations, and write the result data of the calculation performed by the second arithmetic logic (322a, 322b, ..., 322k) to the second memory cell array (321a, 321b, ..., 321k).

[0091] Of the first rank 410 and the second rank 420, which share a data channel, the first rank 410 can perform general operations for at least a portion of the period during which the second rank 420 performs computational operations.

[0092] A calculation function may be provided by rank 400, which includes calculation logic. At the same time, general operations are performed by rank 400 that do not perform calculation operations, thus preventing delays in general operations due to the execution of calculation operations. The extent to which rank 400 that perform calculation operations use data channels may be very low, and the data channels may be used by rank 400 that perform general operations, potentially improving the efficiency of data channel utilization.

[0093] Figures 6 and 7 show an example of the operating timing of the memory system 100 shown in Figure 3.

[0094] Referring to Figure 6, the banks included in the multiple memory devices 110 of the memory system 100 can constitute multiple ranks 400. Of the multiple ranks 400 included in the memory system 100, N ranks 400 can share a data channel.

[0095] The memory controller 120 can schedule the operating modes of N ranks 400 that share a data channel based on the commands waiting in each rank 400.

[0096] As an example, the memory controller 120 can set one of the N ranks 400 to perform arithmetic operations. The rank 400 that performs arithmetic operations can be referred to as the rank 400 that operates in the first operating mode. The memory controller 120 can also set one of the N ranks 400 to perform general operations. The rank 400 that performs general operations can be referred to as the rank 400 that operates in the second operating mode.

[0097] Figure 6 <ex1>Referring to the above, the memory controller 120 can be configured so that, during the first period P1, ranks #1 to #(N-1) of the N ranks 400 operate according to the first operating mode. The arithmetic logic included in ranks #1 to #(N-1) of rank 400 can operate. Arithmetic functions can be performed by ranks #1 to #(N-1) of rank 400.

[0098] The memory controller 120 can be configured so that, during the first period P1, #N of the N ranks 400 operate according to the second operating mode. The arithmetic logic included in #N ranks 400 does not need to be operated. General operation can be performed by #N ranks 400.

[0099] The memory controller 120 can send and receive a second command CMDb for the second operating mode and data according to the second command CMDb via a data channel shared by N ranks 400, except during periods when a first command CMDa for the first operating mode is sent. For example, in each period, the memory controller 120 can send a first command CMDa to the corresponding rank 400 via the data channel, and then send and receive a second command CMDb and data according to the second command CMDb.

[0100] The memory controller 120 can control rank 400 of #N to perform general operation if the command waiting in rank 400 of #N includes a second command CMDb. Furthermore, the memory controller 120 can control rank 400 of #N to operate according to the second command CMDb if the waiting time for the second command CMDb waiting for rank 400 of #N is the longest among the second command CMDbs waiting in each rank 400.

[0101] The memory controller 120 can set rank 400 to operate according to the first and second operating modes for each cycle.

[0102] The memory controller 120 can set the operating mode for each rank 400 in the second period P2 following the first period P1. The memory controller 120 can set the operating mode for each rank 400 in the second period P2 based on the commands waiting for each rank 400 in the first period P1.

[0103] The memory controller 120 can be configured so that ranks 400 from #1 to #(N-2) and rank 400 of #N operate according to the first operating mode during the second period P2. The arithmetic logic contained in ranks 400 from #1 to #(N-2) and rank 400 of #N operates, and arithmetic functions can be executed.

[0104] The memory controller 120 can be configured so that rank 400 of #(N-1) operates according to the second operating mode during the second period P2. The arithmetic logic included in rank 400 of #(N-1) does not have to operate. General operation may be performed by rank 400 of #(N-1).

[0105] At least one rank 400 that operated in accordance with the first command CMDa during the first period P1 may operate in accordance with the second command CMDb during the second period P2. A rank 400 that operates in accordance with the second command CMDb during the second period P2 may be different from a rank 400 that operated in accordance with the second command CMDb during the first period P1.

[0106] The memory controller 120 can set the operating mode of each rank 400 in the third period P3, according to the commands to wait for each rank 400 during the second period P2.

[0107] If the number of second command CMDb pending for each rank 400 in the second period P2 is 0, the memory controller 120 can control all N ranks 400 sharing a data channel to operate according to the first operating mode in the third period P3. In the third period P3, arithmetic operations can be performed by the N ranks 400. The memory controller 120 can set the operating mode of each rank 400 for the next cycle according to the commands pending for each rank 400.

[0108] The memory controller 120 can, in some cases, control multiple ranks 400 to operate in a second operating mode during each period.

[0109] As an example, Figure 6 <ex2>Referring to the above, during the first period P1, rank 400s #1 through #(N-1) can operate according to the first operating mode. During the first period P1, rank 400 #N can operate according to the second operating mode.

[0110] During the second period P2 following the first period P1, rank 400 #N can operate according to the first operating mode. During the second period P2, rank 400s #1 through #(N-1) can operate according to the second operating mode.

[0111] The memory controller 120 can control two or more ranks 400 to operate according to a second operating mode if the number of first commands CMDa waiting for each rank 400 is small or the number of second commands CMDb is large. The memory controller 120 can control the rank 400 from #1 to #(N-1) that has the longest waiting time for the second command CMDb to perform operations according to the second command CMDb. Alternatively, the memory controller 120 may control two or more ranks 400 from #1 to #(N-1) to perform general operations in a time-divided period during the second period P2.

[0112] The memory controller 120 can schedule the operating mode of rank 400 according to the data channel sharing status and the commands to wait for, and can set the operating mode of each rank 400 based on the type and status of the commands to wait for, the waiting time, etc. For example, if the waiting time of the first command CMDa, which requires the operation of the arithmetic logic, exceeds a preset threshold time (for example, a time equivalent to two cycles), the memory controller 120 can also control all rank 400s to process the first command CMDa, even if a second command CMDb exists in the command queue 121.

[0113] In this way, the memory controller 120 can efficiently control the operation of ranks, including arithmetic logic, according to commands waiting for each rank 400, and can control the refresh operation for each rank 400 depending on the operating mode.

[0114] As an example, Figure 7 <ex1>Referring to the above, the memory controller 120 can configure N ranks 400 that share a data channel to operate in a first operating mode and ranks 400 that operate in a second operating mode.

[0115] The memory controller 120 can control the system so that a refresh operation is performed on rank 400 operating in the second operating mode during each cycle. For example, during the first period P1, rank 400 #N may operate according to the second operating mode, and a refresh operation may be performed on the banks included in rank 400 #N during a portion of the first period P1. Even if the memory system 100 includes banks on which arithmetic operations are performed by arithmetic logic, the refresh operation may be performed during periods on which general operations such as write and read operations are performed.

[0116] As another example, Figure 7 <ex2>Referring to the above, the memory controller 120 can be controlled so that a refresh operation is performed on rank 400 operating in the first operating mode during each cycle. When the arithmetic operation by rank 400 operating in the first operating mode is completed, the memory controller 120 can be controlled so that a refresh operation is performed on all banks included in rank 400. The arithmetic operation and the refresh operation can be performed consecutively.

[0117] In addition, depending on the circumstances, a refresh operation may be performed simultaneously on rank 400 operating in the first operating mode and rank 400 operating in the second operating mode.

[0118] In addition, the length of the period during which the refresh operation is performed may be variably adjusted in some cases.

[0119] As an example, Figure 7 <ex3>Referring to the above, during the first period P1, (N-1) ranks 400 can operate according to a first operating mode, and one rank 400 can operate according to a second operating mode. The memory controller 120 can set the operating mode of each rank 400 during the second period P2 based on the commands waiting for each rank 400 during the first period P1.

[0120] The memory controller 120 can control the system so that a refresh operation is performed for each rank 400 during the second period P2. The memory controller 120 can be set so that the refresh operation is performed after the arithmetic operation or general operation for each rank 400 is completed. The memory controller 120 can set the length of the second period P2 in which the refresh operation is performed to be different from the length of the first period P1. The length of the second period P2 may be greater than the length of the first period P1. The memory controller 120 can lengthen the period in which the refresh operation is performed so that the refresh operation is performed after the arithmetic operation or general operation for each rank 400 is completed.

[0121] The memory controller 120 can control the operating mode and refresh operation method of each rank 400 based on commands waiting for rank 400s that share a data channel, and can control the operation of rank 400 independently for each data channel.

[0122] Figure 8 shows another example of the operation method of the memory system 100 according to an embodiment of the present disclosure.

[0123] Referring to Figure 8, the memory system 100 may include a first rank 410 and a second rank 420 that share a first data channel. The memory system 100 may also include a third rank 430 and a fourth rank 440 that share a second data channel.

[0124] The memory controller 120 can control the operating modes of the first rank 410 and the second rank 420, which share the first data channel, according to commands that it has on standby for the first rank 410 and the second rank 420. The memory controller 120 can also control the operating modes of the third rank 430 and the fourth rank 440, which share the second data channel, according to commands that it has on standby for the third rank 430 and the fourth rank 440.

[0125] As an example, the memory controller 120 can control the first rank 410 and the fourth rank 440 to operate according to a first operating mode during the same operating period. The arithmetic logic contained in the first rank 410 and the fourth rank 440 can operate and perform arithmetic operations.

[0126] The memory controller 120 can control the second rank 420 and the third rank 430 to operate according to the second operating mode during the period when the first rank 410 and the fourth rank 440 operate according to the first operating mode. The arithmetic logic included in the second rank 420 and the third rank 430 does not have to be operated. General operation can be performed by the second rank 420 and the third rank 430.

[0127] Alternatively, the memory controller 120 may control the first rank 410, which shares the first data channel, to operate according to the first operating mode, and the second rank 420, which shares the first data channel, to operate according to the second operating mode, during the same operating period. The memory controller 120 may also control both the third rank 430 and the fourth rank 440, which share the second data channel, to operate according to the first operating mode, during the same period.

[0128] The memory controller 120 can improve the efficiency of arithmetic operations and general operations by setting the operating mode of each of the multiple ranks 400 that share each data channel, according to the status of commands waiting for each data channel, every cycle.

[0129] Even when various types and connection structures of the memory devices 110 included in the memory system 100 are implemented, the memory controller 120 can control the operating mode of each rank 400 each cycle based on the commands waiting for each rank 400.

[0130] Figures 9a, 9b, and 10 illustrate examples of the operation of various types of memory systems 100 according to embodiments of the present disclosure.

[0131] Referring to Figure 9a, an example is shown in which the memory system 100 includes rank 400 containing arithmetic logic and rank 400 without arithmetic logic.

[0132] For example, the first rank 410, the second rank 420, the third rank 430, and the fourth rank 440 can share a first data channel. The first rank 410 may include a first memory cell array 311 and a first arithmetic logic 312. The second rank 420 may include a second memory cell array 321 and a second arithmetic logic 322. The third rank 430 may include a third memory cell array 331 and a third arithmetic logic 332. The fourth rank 440 may include a fourth memory cell array 341. The fourth rank 440 may not include arithmetic logic.

[0133] A rank 400 sharing the first data channel may include rank 400s that contain arithmetic logic and rank 400s that do not contain arithmetic logic. The number of rank 400s that contain arithmetic logic and the number of rank 400s that do not contain arithmetic logic may be different.

[0134] For example, among the rank 400s sharing the first data channel, the number of rank 400s that include arithmetic logic may be greater than the number of rank 400s that do not include arithmetic logic. In some cases, the number of rank 400s that include arithmetic logic may be less than the number of rank 400s that do not include arithmetic logic.

[0135] The memory controller 120 can set the operating mode of each rank 400 during each operating period in accordance with a command waiting for the rank 400 that shares the first data channel.

[0136] As an example, as shown in Figure 9a, the first rank 410, the second rank 420, and the third rank 430 can operate according to the first operating mode. The fourth rank 440 can operate according to the second operating mode.

[0137] The memory controller 120 can control at least one of the ranks 400, which include arithmetic logic, to operate according to a second operating mode.

[0138] As an example, referring to Figure 9b, the first rank 410 and the third rank 430 can operate according to the first operating mode. During this period, the second rank 420 can operate according to the second operating mode. Since the second rank 420 operates according to the second operating mode, the fourth rank 440 does not need to operate during this period.

[0139] The fourth rank 440 can operate in the second operating mode during periods when the first rank 410, the second rank 420, and the third rank 430, which share the first data channel, are not operating in the second operating mode. The fourth rank 440 may be idle during periods when at least one of the first rank 410, the second rank 420, and the third rank 430, which share the first data channel, is operating in the second operating mode. In some cases, the fourth rank 440 can perform a refresh operation during periods when at least one of the first rank 410, the second rank 420, and the third rank 430 is operating in the second operating mode.

[0140] The memory system 100 can be configured with a memory device 110 that includes arithmetic logic and a memory device 110 that does not include arithmetic logic, in order to efficiently control arithmetic operations and general operations and improve the operational performance of the memory system 100. Even in such cases, the delay between arithmetic operations and general operations can be reduced and the operational performance of the memory system 100 can be improved through scheduling by the memory controller 120.

[0141] Furthermore, the scheduling control based on commands waiting for each rank 400 can be applied to various types of memory systems 100, and for example, it can be applied when multiple memory devices 100 are stacked to constitute a rank 400.

[0142] As an example, referring to Figure 10, multiple memory devices 111, 112, 113, and 114 may be stacked and arranged on a substrate 600. The substrate 600 may be made of silicon, for example, and the substrate 600 may further have an intermediate substrate to facilitate wiring connections between the memory devices 110. Such an intermediate substrate may be called an interposer.

[0143] A memory controller 120 may be placed on the substrate 600. Multiple memory devices 110 may be stacked on a base die 500. The base die 500 may be called a logic die, and various circuits for the operation of the memory devices 110 may be placed on it. The base die 500 is controlled according to commands from the memory controller 120, and the memory devices 110 on the base die 500 can be operated.

[0144] A first memory device 111, a second memory device 112, a third memory device 113, and a fourth memory device 114 may be stacked and arranged on the base die 500.

[0145] The banks included in the first memory device 111, the second memory device 112, the third memory device 113, and the fourth memory device 114 can constitute rank 400 in various ways.

[0146] As an example, Figure 10 <ex1>As illustrated in the example, the first group of the first memory device 111, the first group of the second memory device 112, the first group of the third memory device 113, and the first group of the fourth memory device 114 can constitute the first rank 410. The second group of the first memory device 111, the second group of the second memory device 112, the second group of the third memory device 113, and the second group of the fourth memory device 114 can constitute the second rank 420.

[0147] During at least a portion of the period in which the first rank 410 operates according to the first operating mode, the second rank 420 may operate according to the second operating mode.

[0148] As another example, Figure 10 <ex2>As illustrated in the diagram, at least a portion of the first memory device 111 and at least a portion of the second memory device 112 can constitute the first rank 410. At least a portion of the third memory device 113 and at least a portion of the fourth memory device 114 can constitute the second rank 420. During the period in which the first rank 410 operates in the first operating mode, the second rank 420 can operate according to the second operating mode.

[0149] The first rank 410 and the second rank 420 can also be configured in various ways depending on the data channel connection structure, and by having the other ranks perform general operations during at least a portion of the period in which some of the ranks sharing the data channel perform arithmetic operations, it is possible to prevent or reduce delays in the general operation of the memory system 100 that provides the arithmetic functions.

[0150] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only and not to limit the technical concept of this disclosure, and the scope of the technical concept of this disclosure is not limited by such embodiments.

Claims

1. A memory device comprising multiple ranks, each of which comprises at least one bank including a memory cell array for storing data and arithmetic logic for performing data processing; and A memory system including a memory controller that controls the operation of a plurality of ranks based on commands waiting for each of the plurality of ranks, and controls that at least one of the (N-P) ranks to operate according to a second command during at least a portion of a first period in which P (N > P ≥ 1) ranks out of N (N ≥ 2) ranks that share a data channel operate according to a first command, wherein the operation according to the second command is performed without the operation of the arithmetic logic.

2. The memory system according to claim 1, wherein, prior to the first period, if the number of second commands waiting for at least one of the N ranks is greater than zero, the memory controller controls for at least a portion of the first period that at least one of the (N-P) ranks operates according to the second command.

3. The memory system according to claim 1, wherein if the number of second commands waiting for the N ranks is zero, the memory controller controls the second period following the first period so that all N ranks operate according to the first command.

4. The memory system according to claim 1, wherein the memory controller controls Q (an integer N > Q ≥ 1) of the N ranks to operate according to the first command during a second period following the first period, and controls at least one of the (N - Q) ranks to operate according to the second command during at least a portion of the second period.

5. The memory system according to claim 4, wherein the rank operating in accordance with the second command during the second period is different from the rank operating in accordance with the second command during the first period.

6. The memory system according to claim 4, wherein at least one of the P ranks that operated in accordance with the first command during the first period operates in accordance with the second command during the second period.

7. The memory system according to claim 1, wherein the memory controller sets, at each cycle corresponding to the length of the first period, a rank from among the N ranks that performs an operation according to the first command and a rank that performs an operation according to the second command.

8. The memory system according to claim 1, wherein the memory controller sets the rank to operate according to the first command based on the waiting time for the first command which is waiting for each of the N ranks.

9. The memory system according to claim 1, wherein the memory controller performs a refresh operation for at least one of the ranks that operate according to the second command during the first period.

10. The memory system according to claim 1, wherein, during the first period, when the operation of a rank operating in accordance with the first command is completed, the memory controller performs a refresh operation for all ranks for which the operation in accordance with the first command has been performed.

11. The memory system according to claim 1, wherein the memory controller performs a refresh operation on at least a portion of the N ranks during a second period following the first period, and the length of the second period is different from the length of the first period.

12. The memory system according to claim 1, wherein the memory controller transmits the first command to the P ranks that operate according to the first command during the first period, and then transmits the second command to at least one of the (N-P) ranks.

13. The memory system according to claim 1, wherein, during the first period, the second command and data according to the second command are transmitted and received through the data channel shared by the N ranks, except during the period in which the first command is transmitted.

14. During the first period, of the first rank and the second rank sharing the first data channel, the first rank operates according to the first command, and the second rank operates according to the second command. The memory system according to claim 1, wherein during the first period, the third and fourth ranks sharing the second data channel operate according to the first command.

15. The memory system according to claim 1, wherein the operation performed in accordance with the first command is the operation in which the operation of the arithmetic logic is performed.

16. A command queue that stores a first command and a second command for each of several ranks; and A memory controller including a scheduler that, based on the number of first commands and the number of second commands, sets commands to be executed by each of the plurality of ranks during a predetermined operating period, and, if the number of second commands is greater than zero, sets that while some of the plurality of ranks are performing operations according to the first commands, at least one of the remaining ranks is performing operations according to the second commands.

17. The memory controller according to claim 16, wherein the scheduler sets, in a first period, a rank to operate according to the first command and a rank to operate according to the second command, based on the number of first commands and the number of second commands stored in the command queue, in a second period following the first period.

18. The memory controller according to claim 16, wherein the scheduler sets a first group of the plurality of ranks to operate in accordance with a first command during a first period, and sets at least one rank included in the first group to operate in accordance with a second command during a second period following the first period.

19. The memory controller according to claim 18, wherein the scheduler configures the second group of the plurality of ranks to operate according to the second command during the first period, and the ranks included in the second group do not share data channels with one another.

20. The memory controller according to claim 16, wherein at least one of the plurality of ranks that perform an operation according to the first command shares a data channel with at least one of the ranks that perform an operation according to the second command.

21. A first rank comprising a plurality of first banks, each including a first memory cell array and a first arithmetic logic that performs operations using the first memory cell array; and A second rank comprising a plurality of second banks, each including a second memory cell array and a second arithmetic logic that performs operations using the second memory cell array, A memory device in which the first rank and the second rank share a data channel, and during a first period in which the first arithmetic logic included in the first rank is operating, a program operation or read operation on the second memory cell array is performed without the operation of the second arithmetic logic included in the second rank.

22. The memory device according to claim 21, wherein at least one of the first arithmetic logic included in the first rank or the second arithmetic logic included in the second rank operates during a second period following the first period.

23. The memory device according to claim 21, wherein during a second period following the first period, a program operation or read operation is performed on the first memory cell array included in the first rank.

24. The memory device according to claim 23, wherein the second arithmetic logic included in the second rank operates during the second period.

25. The memory device according to claim 21, wherein a refresh operation for the first rank is performed after the operation of the first arithmetic logic is completed.

26. The memory device according to claim 21, wherein a refresh operation is performed on the second rank after the program operation or read operation on the second rank has been completed.

27. The memory device according to claim 21, wherein a refresh operation is performed on the first rank and the second rank during a second period following the first period, and the length of the second period is different from the length of the first period.

28. The memory device according to claim 21, wherein after a command instructing the operation of the first arithmetic logic is transmitted via the data channel, a command instructing the program operation or the read operation of the second memory cell array is transmitted.

29. A third rank comprising a plurality of third banks, each including a third memory cell array and a third arithmetic logic that performs operations using the third memory cell array; and A fourth bank comprises a fourth memory cell array and a fourth arithmetic logic that performs operations using the fourth memory cell array, and further includes a fourth rank that shares a data channel with the third rank, The memory device according to claim 21, wherein during the first period, the third arithmetic logic included in the third rank and the fourth arithmetic logic included in the fourth rank operate.

30. The memory device according to claim 29, wherein in a second period following the first period, the first arithmetic logic and the second arithmetic logic operate, and one of the third arithmetic logic and the fourth arithmetic logic operates while the other does not.

31. A first memory chip comprising a plurality of first banks, each including a first memory cell array and a first arithmetic logic that performs calculations using the first memory cell array; and The second memory chip includes a plurality of second banks, each comprising a second memory cell array and a second arithmetic logic that performs operations using the second memory cell array. A memory device in which, during a first period, the first arithmetic logic included in the first group of the plurality of first banks and the second arithmetic logic included in the first group of the plurality of second banks operate, while the first arithmetic logic included in the second group of the plurality of first banks and the second arithmetic logic included in the second group of the plurality of second banks do not operate.

32. The memory device according to claim 31, wherein during the first period, a program operation or a read operation is performed on at least a portion of the second group of the plurality of first banks or the second group of the plurality of second banks.

33. During a second period following the first period, the first arithmetic logic included in the second group of the plurality of first banks and the second arithmetic logic included in the second group of the plurality of second banks operate. The memory device according to claim 32, wherein during the second period, the first arithmetic logic included in the first group of the plurality of first banks and the second arithmetic logic included in the first group of the plurality of second banks are not in operation.

34. The memory device according to claim 33, wherein during the first period, a refresh operation is performed on the first group of the plurality of first banks and the first group of the plurality of second banks.

35. The memory device according to claim 33, wherein a refresh operation is performed on at least a portion of the plurality of first banks or at least a portion of the plurality of second banks during a third period following the second period, and the length of the third period is different from the length of the second period.

36. The memory device according to claim 31, wherein the timing at which commands are transmitted to the first group of the plurality of first banks and the first group of the plurality of second banks is different from the timing at which commands are transmitted to the second group of the plurality of first banks and the second group of the plurality of second banks.

37. The memory device according to claim 31, wherein the first group of the plurality of first banks and the first group of the plurality of second banks are included in a first rank, and the second group of the plurality of first banks and the second group of the plurality of second banks are included in a second rank.

38. The memory device according to claim 37, wherein the first rank and the second rank share a data channel.

39. The memory device according to claim 31, wherein the first memory chip and the second memory chip are stacked and arranged.

40. A first memory chip comprising a plurality of first banks, each including a first memory cell array and a first arithmetic logic that performs calculations using the first memory cell array; and Includes a second memory chip comprising a plurality of second banks, each containing a second memory cell array. A memory device in which, during at least a portion of a first period in which the first arithmetic logic included in the first group of the plurality of first banks is in operation, a program operation or a read operation is performed on the first group of the plurality of second banks.

41. The memory device according to claim 40, wherein during a second period following the first period, a program operation or read operation is performed on the first group of the plurality of first banks, and the first group of the plurality of second banks is in an idle state.

42. The memory device according to claim 40, wherein the first group of the plurality of second banks is idle for at least a portion of the period during which the first arithmetic logic included in the first group of the plurality of first banks is not operating.

43. The memory device according to claim 40, wherein the first group of the plurality of first banks shares a data channel with the first group of the plurality of second banks.

44. The memory device according to claim 40, wherein during the first period, a program operation or a read operation is performed on a second group of the plurality of first banks.

45. The memory device according to claim 44, wherein the second group of the plurality of first banks does not share a data channel with the first group of the plurality of first banks and the first group of the plurality of second banks.

46. The memory device according to claim 40, wherein during the first period, a refresh operation is performed on the first group of the plurality of first banks.

47. The memory device according to claim 40, wherein a refresh operation is performed on the first group of the plurality of first banks or the first group of the plurality of second banks during a second period following the first period, and the length of the second period is different from the length of the first period.

48. The memory device according to claim 40, wherein the period during which commands are received for the first group of the plurality of first banks is different from the period during which commands are received for the first group of the plurality of second banks.

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