Non-volatile memory device and method of operating the non-volatile memory device for minimizing common source line bouncing

Abstract

To provide a non-volatile memory device and a method for operating the non-volatile memory device to minimize common source line bouncing. [Solution] The non-volatile memory device of the present invention comprises a plurality of memory blocks, each having a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines; N planes, each having one of the plurality of memory blocks; N discharge control circuits, each physically adjacent to each of the N planes, for connecting each of the common source lines of the N planes to the ground voltage terminal in response to each of the N discharge control signals; a plane selection circuit for selecting K planes from the N planes as targets for verification / readout operations; and an operation control circuit that adjusts the voltage levels of the K discharge control signals by the physical position difference between each of the K discharge control circuits corresponding to the K planes selected by the plane selection circuit and the ground voltage terminal.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly, to a non-volatile memory device for minimizing common source line bouncing and a method of operating the non-volatile memory device.

Background Art

[0002] Generally, among various semiconductor devices realized using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc., in devices that use a memory system as a storage medium, such as mobile digital electronic devices like digital cameras, smartphones, and tablet PCs, in order to store data, it is possible to include a volatile memory device and a non-volatile memory device. A volatile memory device is a memory device in which the stored data is erased when the power supply is cut off. Examples of volatile memory devices include SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), etc. A non-volatile memory device is a memory device in which the stored data is maintained even when the power supply is cut off. Examples of non-volatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (registered trademark) (Electrically Erasable and Programmable ROM), flash memory device, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (registered trademark) (Resistive RAM), FRAM (registered trademark) (Ferroelectric RAM), etc.

[0003] On the other hand, it is known that during the programming, reading, and verification operations of non-volatile memory devices, a phenomenon called source line bouncing occurs, in which the potential of the source plate rises unnecessarily. Since such source line bouncing can cause underprogramming and read failures, it is necessary to suppress the source line bouncing phenomenon. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a non-volatile memory device and a method for operating the non-volatile memory device to minimize common source line bouncing.

[0005] The technical problems that the present invention aims to solve are not limited to those mentioned above, and any other technical problems not mentioned can be clearly understood by a person with ordinary skill in the art to which the present invention pertains from the following description. [Means for solving the problem]

[0006] An embodiment of the present invention of a non-volatile memory device may include a plurality of memory blocks, each having a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines; N planes, each having one of the plurality of memory blocks; N discharge control circuits, each physically adjacent to each of the N planes, for connecting each of the common source lines of the N planes to a ground voltage terminal in response to each of the N discharge control signals; a plane selection circuit for selecting K planes from the N planes as targets for verification / readout operations; and an operation control circuit for adjusting the voltage levels of the K discharge control signals based on the physical position difference between each of the K discharge control circuits corresponding to the K planes selected by the plane selection circuit and a ground voltage terminal, where N is a natural number of 2 or more and K is a natural number of 1 or more less than or equal to N.

[0007] A method for operating a non-volatile memory device according to yet another embodiment of the present invention comprises N planes, each having a plurality of non-volatile memory cells, and N discharge control circuits for connecting each of the common source lines of the N planes to a ground voltage terminal in response to each of the N discharge control signals, the method for operating a non-volatile memory device comprising: a selection step of selecting K planes from the N planes to be used for verification / read operation; and an adjustment step of adjusting the voltage levels of the K discharge control signals by the physical position difference between each of the K discharge control circuits corresponding to the K planes selected in the selection step and the ground voltage terminal. [Effects of the Invention]

[0008] This technology can adjust the voltage level of the signal that controls the connection between the common source line and the ground voltage terminal of each of the multiple planes by the physical positional difference between the common source line and the ground voltage terminal of each of the multiple planes.

[0009] This minimizes the occurrence of common source line bouncing. [Brief explanation of the drawing]

[0010] [Figure 1] This is a diagram illustrating the configuration of a non-volatile memory device according to an embodiment of the present invention. [Figure 2A] This figure illustrates the physical arrangement of multiple discharge control circuits included in a non-volatile memory device according to an embodiment of the present invention. [Figure 2B] This figure illustrates the physical arrangement of multiple discharge control circuits included in a non-volatile memory device according to an embodiment of the present invention. [Figure 3] This figure illustrates the configuration of each of the multiple planes included in a non-volatile memory device according to an embodiment of the present invention. [Figure 4] This figure illustrates the structure of each of the multiple memory blocks included in a non-volatile memory device according to an embodiment of the present invention. [Figure 5A] This is a circuit diagram illustrating an example of a discharge control circuit of the first group included in a non-volatile memory device according to an embodiment of the present invention. [Figure 5B] This is a circuit diagram illustrating an example of a second group of discharge control circuits included in a non-volatile memory device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0011] Preferred embodiments of the present invention will be described below with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below and can be configured in a variety of different forms, and these embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those in the ordinary skill of the scope of the invention.

[0012] Figure 1 is a diagram illustrating the configuration of a non-volatile memory device according to an embodiment of the present invention.

[0013] Figures 2A and 2B are diagrams illustrating the physical arrangement of a plurality of discharge control circuits included in a non-volatile memory device according to an embodiment of the present invention.

[0014] First, as shown in Figure 1, the non-volatile memory device according to an embodiment of the present invention may include a control circuit 1 and a memory cell array 2.

[0015] Here, the memory cell array 2 may include a plurality of planes PLANE<1:6> and a plurality of discharge control circuits 21, 22, 23, 24, 25, 26.

[0016] Specifically, each of the multiple planes PLANE<1:6> can contain multiple memory blocks BLK1-BLKz (where z is a natural number greater than or equal to 2). Furthermore, each of the multiple memory blocks BLK1-BLKz can contain multiple pages.

[0017] Here, a single memory block can be understood as a group of multiple memory cells whose data is removed together through an erase operation. Similarly, a single page can be understood as a logical grouping of multiple memory cells, such as those that store data together during a program operation or output data together during a read operation.

[0018] Unlike logical perspectives such as program operation or read operation, from a physical perspective, each of the multiple memory blocks may be provided with multiple non-volatile memory cells (not shown) connected between multiple word lines (not shown) and multiple bit lines (not shown). In this case, one word line can correspond to at least one page, depending on the number of bits that can be stored or represented in one memory cell. For example, if one memory cell is a single-level cell (SLC) that stores one data bit, one word line can correspond to one page. If one memory cell is a double-level cell (DLC) that stores two data bits, one word line can correspond to two pages. If one memory cell is a triple-level cell (TLC) that stores three data bits, one word line can correspond to three pages. If one memory cell is a quadruple-level cell (QLC) that stores four data bits, one word line can correspond to four pages. In this configuration, if a single memory cell is a multiple-level cell that stores five or more data bits, then a single word line can correspond to five or more pages.

[0019] Furthermore, each of the multiple discharge control circuits 21, 22, 23, 24, 25, and 26 can be physically adjacent to each of the multiple planes PLANE<1:6>. In addition, each of the multiple discharge control circuits 21, 22, 23, 24, 25, and 26 can connect each of the common source lines CSL<1:6> of the multiple planes PLANE<1:6> to the ground voltage terminal in response to each of the multiple discharge control signals DISP<1:6>.

[0020] According to an embodiment, the first discharge control circuit 21 can control the connection between the common source line CSL1 of the first plane PLANE1 and the ground voltage VSS terminal in response to the first discharge control signal DISP1. Also, the second discharge control circuit 22 can control the connection between the common source line CSL2 of the second plane PLANE2 and the ground voltage VSS terminal in response to the second discharge control signal DISP2. Also, the third discharge control circuit 23 can control the connection between the common source line CSL3 of the third plane PLANE3 and the ground voltage VSS terminal in response to the third discharge control signal DISP3. Also, the fourth discharge control circuit 24 can control the connection between the common source line CSL4 of the fourth plane PLANE4 and the ground voltage VSS terminal in response to the fourth discharge control signal DISP4. Also, the fifth discharge control circuit 25 can control the connection between the common source line CSL5 of the fifth plane PLANE5 and the ground voltage VSS terminal in response to the fifth discharge control signal DISP5. Also, the sixth discharge control circuit 26 can control the connection between the common source line CSL6 of the sixth plane PLANE6 and the ground voltage VSS terminal in response to the sixth discharge control signal DISP6.

[0021] Thus, the number of the plurality of discharge control circuits 21, 22, 23, 24, 25, 26 is the same as the number of the plurality of planes PLANE<1:6> and can correspond to each other one-to-one. That is, if the number of the plurality of planes PLANE<1:6> is N (N is a natural number of 2 or more), the number of the plurality of discharge control circuits 21, 22, 23, 24, 25, 26 can also be N.

[0022] For reference, in the drawings, it is assumed that N is 6, but this is merely one embodiment and actually can be set to any other value. For reference, in the following, it is assumed that N is 6, that is, it is assumed that the memory cell array 2 includes six planes PLANE<1:6> and the description will be made.

[0023] And the control circuit 1 can be configured to perform a program operation, a read operation, or an erase operation on a selected area of the memory cell array 2.

[0024] Here, the program operation may include program pulse application operation and verification operation.

[0025] First, the program pulse application operation can be an operation that changes the threshold voltage of the memory cell selected as the target of programming by applying a program pulse, in which the voltage increases in steps, to the program word line to which the memory cell selected as the target of programming is connected by an Incremental Step Pulse Program (ISPP) algorithm.

[0026] Furthermore, the verification operation can be an operation that checks whether the threshold voltage level of the memory cell selected as the target for programming has reached the target voltage level by applying a program pulse via the program operation, and then applying a verification pulse set to the target voltage level to the program word line.

[0027] Therefore, in programmed operation, the ISPP algorithm can alternate between programmed pulse application and verification operations.

[0028] Furthermore, the read operation can be an operation in which the data value stored in the memory cell selected for read is verified against the target voltage level by applying a read pulse set to the target voltage level to the read word line to which the memory cell selected for read is connected.

[0029] At this point, it can be seen that the verification operation and the read operation are almost identical in their operating methods and conditions, as they both involve checking the threshold voltage level state of the selected memory cell. Consequently, source line bouncing can occur in both the verification operation and the read operation for almost the same reasons. Therefore, in this invention, the "verification operation" and the "read operation" are combined into a single operation and named "verification / read operation".

[0030] The control circuit 1 may include a plane selection circuit 10, an operation control circuit 12, a first voltage generation circuit 16, and a second voltage generation circuit 18.

[0031] Here, the plane selection circuit 10 can set the values ​​of multiple plane selection signals SEL_P<1:6> in order to select at least one plane from a plurality of planes PLANE<1:6> in response to an externally applied address ADD.

[0032] Depending on the embodiment, the plane selection circuit 10 can set the values ​​of multiple plane selection signals SEL_P<1:6> in order to select at least one of the multiple planes PLANE<1:6> as the target for verification / readout operation.

[0033] In other embodiments, the plane selection circuit 10 can set values ​​for multiple plane selection signals SEL_P<1:6> in order to select at least one of a plurality of planes PLANE<1:6> as the target for program pulse application operation.

[0034] In further embodiments, the plane selection circuit 10 can set values ​​for multiple plane selection signals SEL_P<1:6> to select at least one of the multiple planes PLANE<1:6> in an idle state where no operation is performed.

[0035] For example, the plane selection circuit 10 can select the first plane PLANE1 and the second plane PLANE2 from the six planes PLANE<1:6> included in the memory cell array 2 as targets for read operations, and select the fifth plane PLANE5 as the target for verification operations. That is, in response to address ADD, the plane selection circuit 10 can set the first plane selection signal SEL_P1 and the second plane selection signal SEL_P2 to values ​​for selecting targets for read operations, and set the fifth plane selection signal SEL_P5 to values ​​for selecting targets for verification operations.

[0036] In this case, the selection of the fifth plane, PLANE5, as the target of verification operation means that it is repeatedly selected by the ISPP algorithm as the target of program pulse application operation and verification operation. In such a case, the plane selection circuit 10 can repeatedly select the fifth plane, PLANE5, as the target of verification operation and program pulse application operation while the first plane, PLANE1, and the second plane, PLANE2, out of the six planes PLANE<1:6>, are selected as the targets of read operation operation. That is, the plane selection circuit 10 can repeatedly set the fifth plane selection signal SEL_P5 to a value for selecting it as the target of program pulse application operation and a value for selecting it as the target of verification operation, while the first plane selection signal SEL_P1 and the second plane selection signal SEL_P2 are set to values ​​for selecting them as the targets of read operation operation in response to address ADD.

[0037] Then, after the plane selection circuit 10 has selected at least one plane for verification / read operation, program pulse application operation, or standby state, the operation control circuit 12 can adjust the voltage level of the discharge control signal DISP<1:6> by the physical position between each of the discharge control circuits 21, 22, 23, 24, 25, 26 corresponding to the selected plane and the ground voltage VSS terminal.

[0038] For example, the plane selection circuit 10 can select the first plane PLANE1 as the target for read operation and the fifth plane PLANE5 as the target for verification operation from among the six planes PLANE<1:6> included in the memory cell array 2. In such a case, the operation control circuit 12 can confirm the physical position between the first discharge control circuit 21 corresponding to the first plane PLANE1 and the ground voltage VSS terminal, and the physical position of the fifth discharge control circuit 25 corresponding to the fifth plane PLANE5, and adjust the level of the first discharge control signal DISP1 applied to the first discharge control circuit 21 and the level of the fifth discharge control signal DISP5 applied to the fifth discharge control circuit 25 according to the confirmation result.

[0039] The first voltage generation circuit 16 can generate a first internal voltage VIN1 having a first voltage level during the program pulse application operation section and the verification / readout operation section.

[0040] Furthermore, the second voltage generation circuit 18 can generate a second internal voltage VIN2 having a voltage level equal to or greater than the second voltage level during the program pulse application operation section. Also, the second voltage generation circuit 18 can generate a second internal voltage VIN2 having a second or third voltage level during the verification / readout operation section. In this case, the second voltage level can be higher than the first voltage level. The third voltage level can be higher than the first voltage level and lower than the second voltage level.

[0041] In this case, the second internal voltage VIN2 can be the voltage supplied to generate the program pulse applied to the programmed word line during the program pulse application operation section. Therefore, the second internal voltage VIN2 cannot be used for other purposes during the program pulse application operation section. However, the second internal voltage VIN2 does not need to be supplied to generate the program pulse during the verification / readout operation section. Therefore, during the verification / readout operation section, the second internal voltage VIN2 can be applied to multiple discharge control circuits 21, 22, 23, 24, 25, and 26.

[0042] More specifically, the operation control circuit 12 can set the discharge control signals of the first group applied to the discharge control circuits of the first group of discharge control circuits that are physically adjacent to the ground voltage VSS terminal, among the six discharge control circuits 21, 22, 23, 24, 25, 26 included in the memory cell array 2, to a first voltage level or a disabled level.

[0043] Furthermore, the operation control circuit 12 can set the discharge control signals of the second group of discharge control circuits, which are applied to the second group of discharge control circuits that are physically farther from the ground voltage VSS terminal than the first group of discharge control circuits, to a voltage level between the first voltage level and the second voltage level, or to a disabled level, among the six discharge control circuits 21, 22, 23, 24, 25, and 26 included in the memory cell array 2. In this case, the second voltage level can be a voltage level higher than the first voltage level. That is, the operation control circuit 12 can set the discharge control signals of the second group to the first voltage level, to the second voltage level, or to a third voltage level or disabled level that exceeds the first voltage level and is less than the second voltage level.

[0044] At this time, setting the discharge control signal for the first group or the second group to a disabled level in the operation control circuit 12 means disconnecting the common source line of the plane of the first group or the second group from the ground voltage VSS terminal, that is, controlling the system so that no current flows from the common source line of the plane of the first group or the second group to the ground voltage VSS terminal. For example, the disabled level can be a ground voltage VSS level lower than the first voltage level.

[0045] In one embodiment, it can be assumed that the plane selection circuit 10 selects all planes of the first group and all planes of the second group as targets for verification / readout operations.

[0046] Thus, when the plane selection circuit 10 selects all planes of the first group and the planes of the second group as targets for verification / readout operation, current is being discharged from the common source line of the planes of the first group to the ground voltage VSS terminal in response to the discharge control signal of the first group set to the first voltage level. Therefore, in order to stably discharge current from the common source line of the planes of the second group to the ground voltage VSS terminal, the operation control circuit 12 must control the discharge control signal of the second group to have a voltage level that is sufficiently higher than the discharge control signal of the first group.

[0047] Therefore, the operation control circuit 12 can set the discharge control signal for the first group to a first voltage level and the discharge control signal for the second group to a second voltage level. That is, the operation control circuit 12 can set the discharge control signal for the first group to a first voltage level by being supplied with a first internal voltage VIN1 set to a first voltage level from the first voltage generation circuit 16. Also, the operation control circuit 12 can set the discharge control signal for the second group to a second voltage level by being supplied with a second internal voltage VIN2 set to a second voltage level from the second voltage generation circuit 18.

[0048] In this way, by setting the discharge control signal for the second group to the second voltage level in the operation control circuit 12, source line bouncing in the common source line of the plane of the second group can be minimized.

[0049] In another embodiment, it is possible to assume that the plane selection circuit 10 selects the planes of the first group as targets for verification / readout operations, and selects the planes of the second group in a standby state.

[0050] Thus, when the plane selection circuit 10 selects the planes of the first group as the target for verification / readout operation and the planes of the second group are selected in a standby state, the operation control circuit 12 can set the discharge control signal for the first group to a first voltage level and the discharge control signal for the second group to a disabled level. In other words, the operation control circuit 12 can set the discharge control signal for the first group to a first voltage level by being supplied with a first internal voltage VIN1 set to a first voltage level from the first voltage generation circuit 16.

[0051] In this case, setting the discharge control signal for the second group to the disabled level means disconnecting the common source line of the second group's plane from the ground voltage VSS terminal, that is, controlling the system so that no current flows from the common source line of the second group's plane to the ground voltage VSS terminal.

[0052] In this way, by setting the discharge control signal for the second group to a disabled level in the operation control circuit 12 and setting the discharge control signal for the first group to a first voltage level, source line bouncing in the common source line of the plane of the first group can be minimized.

[0053] Furthermore, in another embodiment, it is possible to assume a case where the plane selection circuit 10 selects the planes of the second group as the target for verification / readout operation, and selects the planes of the first group in a standby state.

[0054] Thus, when the plane selection circuit 10 selects the planes of the second group as the target for verification / readout operation and the planes of the first group are selected in a standby state, the operation control circuit 12 can set the discharge control signal for the second group to the third voltage level and the discharge control signal for the first group to the disabled level. That is, the operation control circuit 12 can set the discharge control signal for the second group to the second voltage level by being supplied with a second internal voltage VIN2 set to the third voltage level from the second voltage generation circuit 18.

[0055] In this case, setting the discharge control signal for the first group to the disabled level means disconnecting the common source line of the first group's plane from the ground voltage VSS terminal, that is, controlling the circuit so that no current flows from the common source line of the first group's plane to the ground voltage VSS terminal. In other words, when the plane of the first group is in standby mode in the plane selection circuit 10 and the plane of the second group is selected as the target for verification / readout operation, no current is being discharged from the common source line of the first group's plane to the ground voltage VSS terminal. Therefore, even if the operation control circuit 12 of the second group sets the discharge control signal for the second group to a third voltage level that is higher than the first voltage level but lower than the second voltage level, the discharge control circuit of the second group can stably discharge current to the ground voltage VSS terminal.

[0056] In this way, by setting the discharge control signal for the second group to the third voltage level in the operation control circuit 12, source line bouncing in the common source line of the plane of the second group can be minimized.

[0057] Furthermore, in another embodiment, it can be assumed that the plane selection circuit 10 selects one of the planes from the first group and the second group as the target for program pulse application operation, and selects the plane of the remaining group as the target for verification / readout operation.

[0058] Thus, when the plane selection circuit 10 selects one of the planes from the first group and the second group as the target for program pulse application, the second internal voltage VIN2 must be supplied to generate the program pulse, so only the first internal voltage VIN1 can be used. In addition, the common source line of the plane of the one group selected as the target for program pulse application must also be connected to the ground voltage VSS terminal.

[0059] Therefore, the operation control circuit 12 can set the discharge control signal for the first group to a first voltage level and the discharge control signal for the second group to a first voltage level. That is, the operation control circuit 12 is supplied with a first internal voltage VIN1 set to a first voltage level from the first voltage generation circuit 16, and can set the discharge control signals for the first group and the second group to a first voltage level.

[0060] On the other hand, as shown in Figures 2A and 2B, along with Figure 1, it is possible to see in what form the physical positions of the six discharge control circuits 21, 22, 23, 24, 25, and 26, which correspond to each of the six planes PLANE<1:6>, change.

[0061] First, as shown in Figure 2A along with Figure 1, it can be seen that of the six planes PLANE<1:6>, the first plane PLANE1, the second plane PLANE2, and the fifth plane PLANE5 are located on the left side, while the third plane PLANE3, the fourth plane PLANE4, and the sixth plane PLANE6 are located on the right side. Furthermore, of the six planes PLANE<1:6>, the first plane PLANE1 and the third plane PLANE3 are located at the top, the fifth plane PLANE5 and the sixth plane PLANE6 are located at the bottom, and the second plane PLANE2 and the fourth plane PLANE4 are located in the middle between the top and bottom. Additionally, the ground voltage VSS terminal is located adjacent to the top.

[0062] Furthermore, it can be seen that the first discharge control circuit 21, the second discharge control circuit 22, the third discharge control circuit 23, and the fourth discharge control circuit 24 are each physically adjacent to the lower part of the first plane PLANE1, the second plane PLANE2, the third plane PLANE3, and the fourth plane PLANE4, respectively. Also, it can be seen that the fifth discharge control circuit 25 and the sixth discharge control circuit 26 are each physically adjacent to the upper part of the fifth plane PLANE5 and the sixth plane PLANE6, respectively.

[0063] As a result, the second discharge control circuit 22 and the fifth discharge control circuit 25 can be considered to be physically adjacent to each other, while the first discharge control circuit 21 and the second discharge control circuit 22 can be considered not to be physically adjacent to each other. Furthermore, the first discharge control circuit 21 can be considered to be adjacent to the ground voltage VSS terminal, while the second discharge control circuit 22 and the fifth discharge control circuit 25 can be considered not to be adjacent to the ground voltage VSS terminal. In other words, with respect to the ground voltage VSS terminal, the second discharge control circuit 22 and the fifth discharge control circuit 25 can be considered to be physically further away from the first discharge control circuit 21.

[0064] Similarly, the fourth discharge control circuit 24 and the sixth discharge control circuit 26 can be considered to be physically adjacent to each other, while the third discharge control circuit 23 and the fourth discharge control circuit 24 can be considered not to be physically adjacent to each other. Furthermore, the third discharge control circuit 23 can be considered to be adjacent to the ground voltage VSS terminal, while the fourth discharge control circuit 24 and the sixth discharge control circuit 25 can be considered not to be adjacent to the ground voltage VSS terminal. In other words, with respect to the ground voltage VSS terminal, the fourth discharge control circuit 24 and the sixth discharge control circuit 26 can be considered to be physically further away from the third discharge control circuit 23.

[0065] In summary, the operation control circuit 12 can classify the first discharge control circuit 21 and the third discharge control circuit 23, which can be considered adjacent to the ground voltage VSS terminal, as a first group of discharge control circuits. Therefore, the operation control circuit 12 can set the first discharge control signal DISP1 applied to the first discharge control circuit 21 and the third discharge control signal DISP3 applied to the third discharge control circuit 23 to a first voltage level. At this time, the operation control circuit 12 can be supplied with a first internal voltage VIN1 generated by the first voltage generation circuit 16 in order to set the first discharge control signal DISP1 and the third discharge control signal DISP3 to a first voltage level.

[0066] Furthermore, the operation control circuit 12 can classify the second discharge control circuit 22, the fourth discharge control circuit 24, the fifth discharge control circuit 25, and the sixth discharge control circuit 26, which can be considered not to be adjacent to the ground voltage VSS terminal, as a second group of discharge control circuits. Accordingly, the operation control circuit 12 can set the second discharge control signal DISP2 applied to the second discharge control circuit 22, the fourth discharge control signal DISP4 applied to the fourth discharge control circuit 24, the fifth discharge control signal DISP5 applied to the fifth discharge control circuit 25, and the sixth discharge control signal DISP6 applied to the sixth discharge control circuit 26 to voltage levels between the first voltage level and the second voltage level. In this case, the second voltage level can be a voltage level higher than the first voltage level. In other words, the operation control circuit 12 can set the second discharge control signal DISP2, the fourth discharge control signal DISP4, the fifth discharge control signal DISP5, and the sixth discharge control signal DISP6 to a first voltage level, a second voltage level, or a third voltage level. In this case, the third voltage level can be a voltage level that exceeds the first voltage level and is less than the second voltage level.

[0067] At this time, the first internal voltage VIN1 generated by the first voltage generation circuit 16 can be supplied to the operation control circuit 12 in order to set the second discharge control signal DISP2, the fourth discharge control signal DISP4, the fifth discharge control signal DISP5, and the sixth discharge control signal DISP6 to the first voltage level. In addition, the second internal voltage VIN2 generated by the second voltage generation circuit 18 can be supplied to the operation control circuit 12 in order to set the second discharge control signal DISP2, the fourth discharge control signal DISP4, the fifth discharge control signal DISP5, and the sixth discharge control signal DISP6 to the second or third voltage level.

[0068] In this way, the operation control circuit 12 can minimize source line bouncing even in common source lines of planes that are not adjacent to the ground voltage VSS terminal by adjusting the level of the discharge control signal DISP<1:6> based on the physical distance to the ground voltage VSS terminal.

[0069] As shown in Figure 2B, along with Figure 1, it can be seen that of the six planes PLANE<1:6>, the first plane PLANE1, the second plane PLANE2, and the fifth plane PLANE5 are located on the left side, while the third plane PLANE3, the fourth plane PLANE4, and the sixth plane PLANE6 are located on the right side. It can also be seen that of the six planes PLANE<1:6>, the first plane PLANE1 and the third plane PLANE3 are located at the top, the fifth plane PLANE5 and the sixth plane PLANE6 are located at the bottom, and the second plane PLANE2 and the fourth plane PLANE4 are located in the middle between the top and bottom. Furthermore, it can be seen that the ground voltage VSS terminal is located adjacent to the top.

[0070] Furthermore, it can be seen that the first discharge control circuit 21 and the third discharge control circuit 23 are physically adjacent to the lower part of the first plane PLANE1 and the third plane PLANE3, respectively. Also, it can be seen that the second discharge control circuit 22, the fourth discharge control circuit 24, the fifth discharge control circuit 25, and the sixth discharge control circuit 26 are physically adjacent to the upper part of the second plane PLANE2, the fourth plane PLANE4, the fifth plane PLANE5, and the sixth plane PLANE6, respectively.

[0071] As a result, the first discharge control circuit 21 and the second discharge control circuit 22 can be considered to be physically adjacent to each other, while the second discharge control circuit 22 and the fifth discharge control circuit 25 can be considered not to be physically adjacent to each other. Furthermore, the first discharge control circuit 21 and the second discharge control circuit 22 can be considered to be adjacent to the ground voltage VSS terminal, while the fifth discharge control circuit 25 can be considered not to be adjacent to the ground voltage VSS terminal. In other words, with respect to the ground voltage VSS terminal, the fifth discharge control circuit 25 can be considered to be physically located further away than the first discharge control circuit 21 and the second discharge control circuit 22.

[0072] Similarly, the third discharge control circuit 23 and the fourth discharge control circuit 24 can be considered to be physically adjacent to each other, while the fourth discharge control circuit 24 and the sixth discharge control circuit 26 can be considered not to be physically adjacent to each other. Furthermore, the third discharge control circuit 23 and the fourth discharge control circuit 24 can be considered to be adjacent to the ground voltage VSS terminal, while the sixth discharge control circuit 25 can be considered not to be adjacent to the ground voltage VSS terminal. In other words, the sixth discharge control circuit 26 can be considered to be physically further away from the ground voltage VSS terminal than the third discharge control circuit 23 and the fourth discharge control circuit 24.

[0073] In summary, the operation control circuit 12 can be divided into a first group of discharge control circuits: a first discharge control circuit 21, a second discharge control circuit 22, a third discharge control circuit 23, and a fourth discharge control circuit 24, all of which can be considered adjacent to the ground voltage VSS terminal. Therefore, the operation control circuit 12 can set the first discharge control signal DISP1 applied to the first discharge control circuit 21, the second discharge control signal DISP2 applied to the second discharge control circuit 22, the third discharge control signal DISP3 applied to the third discharge control circuit 23, and the fourth discharge control signal DISP4 applied to the fourth discharge control circuit 24 to a first voltage level. At this time, the operation control circuit 12 can be supplied with a first internal voltage VIN1 generated by the first voltage generation circuit 16 in order to set the first discharge control signal DISP1, the second discharge control signal DISP2, the third discharge control signal DISP3, and the fourth discharge control signal DISP4 to a first voltage level.

[0074] Furthermore, the operation control circuit 12 can classify the fifth discharge control circuit 25 and the sixth discharge control circuit 26, which can be considered not to be adjacent to the ground voltage VSS terminal, as a second group of discharge control circuits. Therefore, the operation control circuit 12 can set the fifth discharge control signal DISP5 applied to the fifth discharge control circuit 25 and the sixth discharge control signal DISP6 applied to the sixth discharge control circuit 26 to a voltage level between the first voltage level and the second voltage level. In this case, the second voltage level can be a voltage level higher than the first voltage level. That is, the operation control circuit 12 can set the fifth discharge control signal DISP5 and the sixth discharge control signal DISP6 to the first voltage level, the second voltage level, or the third voltage level. In this case, the third voltage level can be a voltage level that exceeds the first voltage level and is lower than the second voltage level.

[0075] At this time, the first internal voltage VIN1 generated by the first voltage generation circuit 16 can be supplied to the operation control circuit 12 in order to set the fifth discharge control signal DISP5 and the sixth discharge control signal DISP6 to the first voltage level. In addition, the second internal voltage VIN2 generated by the second voltage generation circuit 18 can be supplied to the operation control circuit 12 in order to set the fifth discharge control signal DISP5 and the sixth discharge control signal DISP6 to the second or third voltage level.

[0076] In this way, the operation control circuit 12 can minimize source line bouncing even in common source lines of planes that are not adjacent to the ground voltage VSS terminal by adjusting the level of the discharge control signal DISP<1:6> based on the physical distance to the ground voltage VSS terminal.

[0077] Figure 3 is a diagram illustrating the configuration of each of the multiple planes included in a non-volatile memory device according to an embodiment of the present invention.

[0078] As shown in Figure 3, among the multiple planes PLANE<1:6> included in the non-volatile memory device shown in Figure 1, the first plane PLANE1 may include multiple memory blocks BLK1-BLKz, a raw decoder 303 (X-DEC), and a page buffer circuit 302.

[0079] Specifically, the low decoder 303 can be connected to multiple memory blocks BLK1-BLKz via a low line RL. The low line RL may comprise at least one drain select line, multiple word lines, and at least one source select line.

[0080] Furthermore, the low decoder 303 can select one of the memory blocks BLK1-BLKz included in the multiple memory blocks BLK1-BLKz in response to the low address X_ADD provided by the control circuit 1. The low decoder 303 can transmit the operating voltage X_VOL provided by the control circuit 1 to the low line RL connected to the selected memory block from the multiple memory blocks BLK1-BLKz included in the multiple memory blocks BLK1-BLKz.

[0081] Furthermore, multiple memory blocks BLK1-BLKz can be connected to a page buffer circuit 302 via bit lines BL1-BLm. The page buffer circuit 302 can include multiple page buffers PB1-PBm, each connected to a bit line BL1-BLm. The page buffer circuit 302 can receive a page buffer control signal PB_C from the control circuit 1 and can send and receive a data signal DATA to and from the control circuit 1. The page buffer circuit 302 can control the bit lines arranged in the multiple memory blocks BLK1-BLKz in response to the page buffer control signal PB_C. For example, the page buffer circuit 302 can detect data stored in the memory cells of the multiple memory blocks BLK1-BLKz by sensing the signals of the bit lines BL1-BLm of the multiple memory blocks BLK1-BLKz in response to the page buffer control signal PB_C, and can transmit a data signal DATA to the control circuit 1 based on the detected data. The page buffer circuit 302 can apply signals to bit lines BL1-BLm based on the data signal DATA received from the control circuit 1 in response to the page buffer control signal PB_C, thereby writing data to memory cells of multiple memory blocks BLK1-BLKz. The page buffer circuit 302 can write data to or read data from memory cells connected to word lines activated by the raw decoder 303.

[0082] The first discharge control circuit 21 can be connected to a plurality of memory blocks BLK1-BLKz via a first common source line CSL1. The first discharge control circuit 21 can receive a first discharge control signal DISP1 from control circuit 1. In response to the first discharge control signal DISP1, the discharge control circuit 21 can electrically connect the first common source line CSL1 to the ground voltage VSS terminal.

[0083] Control circuit 1 can receive command signals CMD, address signals ADD, and control signals CTRL from outside the non-volatile memory device, and can send and receive data DATA to and from an external device, such as a memory controller. Based on the command signals CMD, address signals ADD, and control signals CTRL, control circuit 1 can output signals for writing data to multiple memory blocks BLK1-BLKz or reading data from multiple memory blocks BLK1-BLKz, such as a low address X_ADD, a page buffer control signal PB_C, and a first discharge control signal DISP1. Control circuit 1 can generate various voltages required by the non-volatile memory device, including the operating voltage X_VOL.

[0084] For reference, although the drawings only disclose the detailed configuration of the first plane, PLANE1, out of several planes, the remaining planes, PLANE2:6, can also be disclosed in the same form as the detailed configuration of the first plane, PLANE1.

[0085] Figure 4 is a diagram illustrating the structure of each of the multiple memory blocks included in a non-volatile memory device according to an embodiment of the present invention.

[0086] As shown in Figure 4, among the multiple planes PLANE<1:6> included in the non-volatile memory device shown in Figure 1, the first plane PLANE1 may have multiple memory blocks BLK1-BLKz, each of which may include multiple cell strings CSTR connected between multiple bit lines BL1-BLm and a common source line CSL.

[0087] Here, bit lines BL1-BLm can extend in a second direction SD and be arranged along a first direction FD. Multiple cell strings CSTR can be connected in parallel to each of the bit lines BL1-BLm. Cell strings CSTR can be connected in common to a common source line CSL. Multiple cell strings CSTR can be placed between multiple bit lines BL1-BLm and one common source line CSL.

[0088] Furthermore, each cell string CSTR may include a drain-selection transistor DST connected to bit lines BL1-BLm, a source-selection transistor SST connected to a common source line CSL, and multiple memory cells MC connected between the drain-selection transistor DST and the source-selection transistor SST. The drain-selection transistor DST, memory cells MC, and source-selection transistor SST may be connected in series along a third direction TD.

[0089] Furthermore, a drain selection line DSL, multiple word lines WL, and a source selection line SSL can be arranged along a third direction TD between the bit lines BL1-BLm and the common source line CSL. Each drain selection line DSL can be connected to the gate of its corresponding drain selection transistor DST. Each word line WL can be connected to the gate of its corresponding memory cell MC. A source selection line SSL can be connected to the gate of a source selection transistor SST. Memory cells MC commonly connected to one word line WL can constitute at least one page.

[0090] The bit lines BL1-BLm and the common source line CSL can be commonly connected to memory blocks BLK1-BLKz. That is, memory blocks BLK1-BLKz can share the bit lines BL1-BLm and the common source line CSL. The drain selection line DSL, multiple word lines WL, and source selection line SSL can be individually provided to each of the memory blocks BLK1-BLKz. A discharge control circuit 21 can be connected to the common source line CSL.

[0091] For reference, the first direction FD and the second direction SD can mean each of two directions that are parallel to the top surface of the substrate but intersect each other. The third direction TD can mean a direction that protrudes perpendicularly from the top surface of the substrate. In this case, the first direction FD and the second direction SD can intersect substantially perpendicularly to each other. Furthermore, the third direction TD can be a direction perpendicular to the first direction FD and the second direction SD. In the following specification, "perpendicular" or "perpendicular direction" will be used with substantially the same meaning as the third direction TD. In the drawings, the direction indicated by the arrow and its opposite direction represent the same direction.

[0092] Furthermore, although the drawings only disclose the detailed configuration of multiple memory blocks BLK1-BLKz included in the first plane PLANE1 among the multiple planes PLANE<1:6>, the remaining other planes PLANE<2:6> can also be disclosed in the same form as the detailed configuration of the first plane PLANE1.

[0093] Figure 5A is a circuit diagram illustrating an example of a first group of discharge control circuits included in a non-volatile memory device according to an embodiment of the present invention.

[0094] First, as explained in Figures 1 to 2B, the operation control circuit 12 can set the discharge control signals of the first group of discharge control circuits, which are applied to the first group of discharge control circuits that are physically adjacent to the ground voltage VSS terminal (meaning discharge control circuits that are physically closer than the second group of discharge control circuits), among the six discharge control circuits 21, 22, 23, 24, 25, and 26 included in the memory cell array 2, to a first voltage level or a disabled level.

[0095] Furthermore, Figure 5A illustrates the detailed circuit configuration of the first discharge control circuit 21, assuming that the first discharge control circuit 21, which is physically adjacent to the first plane PLANE<1:6> among the multiple planes PLANE<1:6>, is the discharge control circuit of the first group, with reference to Figures 2A and 2B. However, this is for the sake of explanation, and each discharge control circuit classified as a discharge control circuit of the first group can have a circuit configuration like the one shown in Figure 5A. For example, if two discharge control circuits, namely the first discharge control circuit 21 and the third discharge control circuit 23, are classified as the discharge control circuits of the first group, as shown in Figure 2A, then two circuits of the form shown in Figure 5A can be included in the non-volatile memory device. To give another example, as shown in Figure 2B, if four discharge control circuits, namely the first discharge control circuit 21, the second discharge control circuit 22, the third discharge control circuit 23, and the fourth discharge control circuit 24, are classified as the first group of discharge control circuits, then four circuits of the form shown in Figure 5A can be included in the non-volatile memory device.

[0096] Furthermore, in Figure 5A, we assume that the first group of discharge control circuits is the first discharge control circuit 21, and therefore the reference numerals shown in the drawing are related to the first discharge control circuit 21. However, this is only one embodiment, and if the first group of discharge control circuits is the third discharge control circuit 23, the reference numerals shown in the drawing can be changed to reference numerals related to the third discharge control circuit 23 and applied accordingly.

[0097] Specifically, the first group of discharge control circuits may include a first discharge transistor 501, a first level setting unit 502, and a first standby setting unit 503.

[0098] Here, the first discharge transistor 501 can control the connection between the common source line of the first group of planes connected to the drain terminal and the ground voltage VSS terminal connected to the source terminal in response to a discharge control signal of the first group applied to the gate terminal.

[0099] In other words, the first discharge transistor 501 included in the first discharge control circuit 21, which is classified as a first group of discharge control circuits, can control the connection between the common source line CSL1 of the first plane PLANE1 connected to the drain terminal and the ground voltage VSS terminal connected to the source terminal in response to the first discharge control signal DISP1 applied to the gate terminal.

[0100] For example, the first discharge transistor 501 can be an NMOS transistor. Thus, the first discharge transistor 501 can connect the common source line CSL1 of the first plane PLANE1 to the ground voltage VSS terminal in response to the first discharge control signal DISP1 being set to a first voltage level. Conversely, the first discharge transistor 501 can disconnect the common source line CSL1 of the first plane PLANE1 to the ground voltage VSS terminal in response to the first discharge control signal DISP1 being set to the ground voltage VSS level.

[0101] The first level setting unit 502 can set the discharge control signal for the first group to the level of the first internal voltage in response to the plane selection circuit 10 selecting the planes of the first group as targets for verification / readout operation or program pulse application operation.

[0102] In other words, the first level setting unit 502 included in the first discharge control circuit 21, which is classified as a discharge control circuit of the first group, can set the first discharge control signal DISP1 to the level of the first internal voltage VIN1 in response to the first plane PLANE1 being selected by the plane selection circuit 10 as the target of verification / readout operation or program pulse application operation.

[0103] The first standby setting unit 503 can then set the discharge control signal for the first group to a disabled level in response to the plane selection circuit 10 selecting the plane of the first group in a standby state.

[0104] In other words, the first standby setting unit 503 included in the first discharge control circuit 21, which is classified as a discharge control circuit of the first group, can set the first discharge control signal DISP1 to a disabled level in response to the first plane PLANE1 being selected in a standby state by the plane selection circuit 10.

[0105] More specifically, the first level setting unit 502 may include an AND gate AND1 that performs a logical AND operation on DIS_EN and SEL_EN1 to set the logic level of SEL_L, a switch EN_SWITCH1 for transmitting SEL_L when ENVOL is logic high, two inverters IV1 and IV2 supplied with a first internal voltage VIN1 as a power source for buffering and driving SEL_L, and an NMOS transistor N1 that outputs the buffered SEL_L signal via the two inverters IV1 and IV2 as a first discharge control signal DISP1 in response to the output signal of the switch EN_SWITCH1 input to the gate.

[0106] Furthermore, the first standby setting unit 503 may include an inverter IV3 that inverts and outputs DIS_EN, and an NMOS transistor N2 for selectively connecting the node of the first discharge control signal DISP1 to the ground voltage VSS terminal in response to the output signal of the inverter IV3.

[0107] In one embodiment, when the plane selection circuit 10 selects the first plane PLANE1, which is classified as a plane of the first group, as the target for verification / read operation or program pulse application operation, it can set SEL_EN1, DIS_EN, and ENVOL to logic high and output them to the first discharge control circuit 21.

[0108] In such a case, the first level setting unit 502 sets SEL_L to logic high, and the switch EN_SWITCH1 sets the NMOS transistor N1 to the turn-on state, so that SEL_L set to the level of the first internal voltage VIN1 can be output as the first discharge control signal DISP1. Since the first internal voltage VIN1 is in a state having a first voltage level, the first discharge control signal DISP1 can have a first voltage level.

[0109] Furthermore, the first standby setting unit 503 can set the NMOS transistor N2 to a turn-off state, thereby preventing the node of the first discharge control signal DISP1 from being connected to the ground voltage VSS terminal.

[0110] Furthermore, the first discharge transistor 501 can turn on the NMOS transistor N3 in response to the first discharge control signal DISP1 set to a first voltage level, thereby connecting the common source line CSL1 of the first plane PLANE1 to the ground voltage VSS terminal.

[0111] In another embodiment, when the plane selection circuit 10 selects the first plane PLANE1, which is to be classified as a plane of the first group, in a standby state, it can set SEL_EN1, DIS_EN, and ENVOL to logic low and output them to the first discharge control circuit 21.

[0112] In such a case, the first level setting unit 502 can set SEL_L to logic low, and the switch EN_SWITCH1 can set the NMOS transistor N1 to the turn-off state, thereby preventing the output of SEL_L, which is set to the level of the ground voltage VSS, as the first discharge control signal DISP1.

[0113] Furthermore, the first standby setting unit 503 can set the NMOS transistor N2 to the turn-on state and connect the node of the first discharge control signal DISP1 to the ground voltage VSS terminal. That is, the first discharge control signal DISP1 can be set to the ground voltage VSS level, which is the disabled level.

[0114] Furthermore, the first discharge transistor 501 can set the NMOS transistor N3 to a turn-off state in response to the first discharge control signal DISP1, which is set to the ground voltage VSS level, thereby preventing the common source line CSL1 of the first plane PLANE1 from being connected to the ground voltage VSS terminal.

[0115] For reference, SEL_EN1, DIS_EN, and ENVOL, output from the plane selection circuit 10 to the first discharge control circuit 21, can be signals whose logic level is determined according to the value of the first plane selection signal SEL_P1, as explained in Figures 1 to 2B above. Furthermore, ENVOL, output from the plane selection circuit 10 to the first discharge control circuit 21, can be set to a voltage level higher than the threshold voltage level or more than the first internal voltage VIN1 in the activated state. In other words, ENVOL can turn on the NMOS transistor N1 so that SEL_L, set to the first voltage level in the activated state, is transmitted as the first discharge control signal DISP1 without loss.

[0116] Figure 5B is a circuit diagram illustrating an example of a second group of discharge control circuits included in a non-volatile memory device according to an embodiment of the present invention.

[0117] First, as explained in Figures 1 to 2B, the operation control circuit 12 can set the discharge control signals of the second group of discharge control circuits, which are applied to the second group of discharge control circuits that are physically farther from the ground voltage VSS terminal than the first group of discharge control circuits, to a voltage level between the first voltage level and the second voltage level, or to a disabled level, among the six discharge control circuits 21, 22, 23, 24, 25, and 26 included in the memory cell array 2. In this case, the second voltage level can be a voltage level higher than the first voltage level. That is, the operation control circuit 12 can set the discharge control signals of the second group to the first voltage level, to the second voltage level, or to a third voltage level or disabled level that exceeds the first voltage level and is less than the second voltage level.

[0118] Furthermore, Figure 5B illustrates the detailed circuit configuration of the fifth discharge control circuit 25, assuming that the fifth discharge control circuit 25, which is physically adjacent to the fifth plane PLANE<1:6> among the multiple planes PLANE<1:6>, belongs to the second group of discharge control circuits, with reference to Figures 2A and 2B. However, this is for the sake of explanation, and each discharge control circuit classified as a second group of discharge control circuits can have a circuit configuration like the one shown in Figure 5B. For example, if four discharge control circuits, namely the second discharge control circuit 22, the fourth discharge control circuit 24, the fifth discharge control circuit 25, and the sixth discharge control circuit 26, are classified as the second group of discharge control circuits, as shown in Figure 2A, then four circuits of the form shown in Figure 5B can be included in the non-volatile memory device. To give another example, as shown in Figure 2B, if two discharge control circuits, namely the fifth discharge control circuit 25 and the sixth discharge control circuit 26, are classified as the first group of discharge control circuits, then two circuits of the form shown in Figure 5B may be included in the non-volatile memory device.

[0119] Furthermore, in Figure 5B, we assume that the second group of discharge control circuits is the fifth discharge control circuit 25, and therefore the reference numerals shown in the drawing are related to the fifth discharge control circuit 25. However, this is only one embodiment, and if the second group of discharge control circuits is the sixth discharge control circuit 26, the reference numerals shown in the drawing can be changed to reference numerals related to the sixth discharge control circuit 26 and applied accordingly.

[0120] Specifically, the second group of discharge control circuits may include a second discharge transistor 504, a second level setting unit 505, a third level setting unit 506, and a second standby setting unit 507.

[0121] Here, the second discharge transistor 504 can control the connection between the common source line of the second group of planes connected to the drain terminal and the ground voltage VSS terminal connected to the source terminal in response to a second group discharge control signal applied to the gate terminal.

[0122] In other words, the second discharge transistor 504, included in the fifth discharge control circuit 25 which is classified as a second group of discharge control circuits, can control the connection between the common source line CSL5 of the fifth plane PLANE5 connected to the drain terminal and the ground voltage VSS terminal connected to the source terminal in response to the fifth discharge control signal DISP5 applied to the gate terminal.

[0123] For example, the second discharge transistor 504 can be an NMOS transistor. Thus, the second discharge transistor 504 can connect the common source line CSL5 of the fifth plane PLANE5 to the ground voltage VSS terminal in response to the fifth discharge control signal DISP5 being set to a first voltage level, a second voltage level, or a third voltage level. Conversely, the second discharge transistor 504 can disconnect the common source line CSL5 of the fifth plane PLANE5 to the ground voltage VSS terminal in response to the fifth discharge control signal DISP5 being set to the ground voltage VSS level.

[0124] The second level setting unit 505 can set the discharge control signal for the second group to the level of the second internal voltage VIN2 in response to the plane selection circuit 10 selecting the planes of the second group as the target for verification / readout operation.

[0125] In other words, the second level setting unit 505 included in the fifth discharge control circuit 25, which is classified as a second group of discharge control circuits, can set the fifth discharge control signal DISP5 to the level of the second internal voltage VIN2 in response to the fifth plane PLANE5 being selected as the target for verification / readout operation by the plane selection circuit 10.

[0126] Then, the third level setting unit 506 can set the discharge control signal for the second group to the level of the first internal voltage VIN1 in response to the plane selection circuit 10 selecting the planes of the second group as the target of programmed operation.

[0127] In other words, the third level setting unit 506 included in the fifth discharge control circuit 25, which is classified as a discharge control circuit of the second group, can set the fifth discharge control signal DISP5 to the level of the first internal voltage VIN1 in response to the fifth plane PLANE5 being selected as the target of program operation by the plane selection circuit 10.

[0128] The second standby setting unit 507 can then set the discharge control signal for the second group to a disabled level in response to the plane selection circuit 10 selecting the plane of the second group in a standby state.

[0129] In other words, the second standby setting unit 507 included in the fifth discharge control circuit 25, which is classified as a second group of discharge control circuits, can set the fifth discharge control signal DISP5 to a disabled level in response to the fifth plane PLANE5 being selected in a standby state by the plane selection circuit 10.

[0130] More specifically, the second level setting unit 502 may include an AND gate AND2 that performs a logical AND operation on DIS_EN and SEL_EN5B to set the logic level of SEL_L, a switch EN_SWITCH3 for transmitting SEL_L when ENVOL is logic high, two inverters IV4 and IV5 supplied with the first internal voltage VIN1 as a power source for buffering and driving SEL_L, and an NMOS transistor N4 for outputting the buffered SEL_L signal via the two inverters IV4 and IV5 as a fifth discharge control signal DISP5 in response to the output signal of the switch EN_SWITCH3 input to the gate.

[0131] Furthermore, the third level setting unit 506 may include an AND gate AND3 that performs a logical AND operation on DIS_EN and SEL_EN5 to set the logic level of SEL_H, a switch EN_SWITCH4 for transmitting SEL_H when ENVOL is logic high, and an NMOS transistor N5 for outputting a second internal voltage VIN2 as a fifth discharge control signal DISP5 in response to the output signal of the switch EN_SWITCH4 input to the gate.

[0132] Furthermore, the second standby setting unit 507 may include an inverter IV6 that inverts and outputs DIS_EN, and an NMOS transistor N6 for selectively connecting the node of the fifth discharge control signal DISP5 to the ground voltage VSS terminal in response to the output signal of the inverter IV6.

[0133] In one embodiment, when the plane selection circuit 10 selects the fifth plane PLANE5, which is classified as a plane of the second group, as the target for verification / readout operation, it can set SEL_EN5, DIS_EN, and ENVOL to logic high and output them to the fifth discharge control circuit 25.

[0134] In such a case, the second level setting unit 505 can set SEL_L to logic low, and the switch EN_SWITCH3 can set the NMOS transistor N4 to the turn-off state, thereby preventing the output of SEL_L, which is set to the level of the ground voltage VSS, as the fifth discharge control signal DISP5.

[0135] Furthermore, the third level setting unit 506 can set SEL_H to logic high, and the switch EN_SWITCH4 can set the NMOS transistor N5 to the turn-on state, thereby setting the fifth discharge control signal DISP5 to the level of the second internal voltage VIN2. Since the second internal voltage VIN2 is in a state having either a second voltage level or a third voltage level, the fifth discharge control signal DISP5 can have either a second voltage level or a third voltage level.

[0136] Furthermore, the second standby setting unit 507 can set the NMOS transistor N6 to a turn-off state, thereby preventing the node of the fifth discharge control signal DISP5 from being connected to the ground voltage VSS terminal.

[0137] Furthermore, the second discharge transistor 504 can turn on the NMOS transistor N7 in response to a fifth discharge control signal DISP5 set to a second or third voltage level, thereby connecting the common source line CSL5 of the fifth plane PLANE5 to the ground voltage VSS terminal.

[0138] In another embodiment, when the plane selection circuit 10 selects the fifth plane PLANE5, which is classified as a plane of the second group, as the target of program operation, it can set SEL_EN5 to logic low and set DIS_EN and ENVOL to logic high and output to the fifth discharge control circuit 25.

[0139] In such a case, the second level setting unit 505 sets SEL_L to logic high, and the switch EN_SWITCH3 sets the NMOS transistor N4 to the turn-on state, so that SEL_L, which is set to the level of the first internal voltage VIN1, can be output as the fifth discharge control signal DISP5. Since the first internal voltage VIN1 is in a state having a first voltage level, the fifth discharge control signal DISP5 can have a first voltage level.

[0140] Furthermore, the third level setting unit 506 can set SEL_H to logic low, and the switch EN_SWITCH4 can set the NMOS transistor N5 to the turn-off state, thereby preventing the fifth discharge control signal DISP5 from being set to the level of the second internal voltage VIN2.

[0141] Furthermore, the second standby setting unit 507 can set the NMOS transistor N6 to a turn-off state, thereby preventing the node of the fifth discharge control signal DISP5 from being connected to the ground voltage VSS terminal.

[0142] Furthermore, the second discharge transistor 504 can turn on the NMOS transistor N7 in response to the fifth discharge control signal DISP5, which is set to the first voltage level, thereby connecting the common source line CSL5 of the fifth plane PLANE5 to the ground voltage VSS terminal.

[0143] In another embodiment, when the plane selection circuit 10 selects the fifth plane PLANE5, which is classified as a plane of the second group, in a standby state, it can set SEL_EN5, DIS_EN, and ENVOL to logic low and output them to the fifth discharge control circuit 25.

[0144] In such a case, the second level setting unit 505 can set SEL_L to logic low, and the switch EN_SWITCH3 can set the NMOS transistor N4 to the turn-off state, thereby preventing the output of SEL_L, which is set to the level of the ground voltage VSS, as the fifth discharge control signal DISP5.

[0145] Furthermore, the third level setting unit 506 can set SEL_H to logic low, and the switch EN_SWITCH4 can set the NMOS transistor N5 to the turn-off state, thereby preventing the fifth discharge control signal DISP5 from being set to the level of the second internal voltage VIN2.

[0146] Furthermore, the second standby setting unit 507 can set the NMOS transistor N6 to the turn-on state and connect the node of the fifth discharge control signal DISP5 to the ground voltage VSS terminal. That is, the fifth discharge control signal DISP5 can be set to the ground voltage VSS level, which is the disabled level.

[0147] Furthermore, the second discharge transistor 504 can turn off the NMOS transistor N7 in response to the fifth discharge control signal DISP5, which is set to the ground voltage VSS level, thereby preventing the common source line CSL5 of the fifth plane PLANE5 from being connected to the ground voltage VSS terminal.

[0148] For reference, SEL_EN5, DIS_EN, and ENVOL, output from the plane selection circuit 10 to the fifth discharge control circuit 25, can be signals whose logic level is determined according to the value of the fifth plane selection signal SEL_P5, as described in Figures 1 to 2B above. Furthermore, ENVOL, output from the plane selection circuit 10 to the fifth discharge control circuit 25, can be set to a voltage level higher than the threshold voltage level above the second internal voltage VIN2 in the activated state. In other words, ENVOL can turn on the NMOS transistor N5 so that the second internal voltage VIN2, set to the second voltage level in the activated state, is transmitted as the fifth discharge control signal DISP5 without loss.

[0149] On the other hand, as shown in both Figures 5A and 5B, the first group of discharge control signals used to control the first discharge transistor 501 included in the first group of discharge control circuits is a first voltage level or ground voltage VSS level. That is, the first discharge control signal DISP1 applied to the gate of the NMOS transistor N3 included in the first discharge transistor 501 is a first voltage level or ground voltage VSS level.

[0150] Furthermore, it can be seen that the second group of discharge control signals used to control the second discharge transistor 504 included in the second group of discharge control circuits is the second voltage level, the third voltage level, or the ground voltage VSS level. In other words, it can be seen that the fifth discharge control signal DISP5 applied to the gate of the NMOS transistor N7 included in the second discharge transistor 504 is the second voltage level, the third voltage level, or the ground voltage VSS level.

[0151] In this case, the second voltage level and the third voltage level can each be higher than the first voltage level.

[0152] Therefore, the second discharge transistor 504 included in the second group of discharge control circuits can be a high-voltage transistor having a thicker oxide film than the first discharge transistor 501 included in the first group of discharge control circuits. That is, the NMOS transistor N7 included in the second discharge transistor 504 can be a high-voltage NMOS transistor having a thicker oxide film than the NMOS transistor N3 included in the first discharge transistor 501.

[0153] The present invention described above is not limited to the embodiments and accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention.

[0154] For example, the logic gates and transistors exemplified in the embodiments described above should be implemented such that their position and type differ depending on the polarity of the input signal.

Claims

1. Multiple memory blocks, each having multiple non-volatile memory cells connected between multiple word lines and multiple bit lines, and N planes, each having the multiple memory blocks, N discharge control circuits, each physically adjacent to each of the N planes, for connecting each of the common source lines of the N planes to the ground voltage terminal in response to each of the N discharge control signals, A plane selection circuit that selects K planes out of N planes to be used for verification / readout operations, An operation control circuit that adjusts the voltage levels of K discharge control signals based on the physical position difference between each of the K discharge control circuits corresponding to the K planes selected by the plane selection circuit and the ground voltage terminal, Equipped with, A non-volatile memory device in which N is a natural number greater than or equal to 2, and K is a natural number less than or equal to N that is greater than or equal to 1.

2. The aforementioned control circuit is Among the N discharge control circuits, the discharge control signal of the first group applied to the discharge control circuit of the first group that is physically adjacent to the ground voltage terminal is set to a first voltage level. The non-volatile memory device according to claim 1, wherein, among the N discharge control circuits, the discharge control signal of the second group applied to the discharge control circuit of the second group which is physically farther away from the ground voltage terminal than the discharge control circuit of the first group is set to a voltage level between the first voltage level and the second voltage level which is higher than the first voltage level.

3. The aforementioned control circuit is The non-volatile memory device according to claim 2, wherein when the plane selection circuit selects each of the planes of the first group and the second group corresponding to the discharge control circuits of the first group and the second group as targets for verification / readout operation, the discharge control signal of the first group is set to the first voltage level and the discharge control signal of the second group is set to the second voltage level.

4. The aforementioned control circuit is The non-volatile memory device according to claim 3, wherein when the plane selection circuit selects the planes of the first group in an idle state and selects the planes of the second group as the target of verification / read operation, the discharge control signal for the first group is set to a disabled level, and the discharge control signal for the second group is set to a third voltage level that exceeds the first voltage level and is less than the second voltage level.

5. The aforementioned control circuit is The non-volatile memory device according to claim 4, wherein when the plane selection circuit selects the first group of planes as the target for plane verification / readout operation and selects the planes of the second group in a standby state, the discharge control signal for the first group is set to the first voltage level and the discharge control signal for the second group is set to the disabled level.

6. The aforementioned control circuit is The non-volatile memory device according to claim 3, wherein, when the plane selection circuit selects one of the planes of the first group and the second group as the target for program pulse application operation and the remaining one as the target for verification / read operation, the discharge control signals of the first group and the second group are set to the first voltage level.

7. A first voltage generation circuit for generating a first internal voltage having the first voltage level during the program pulse application operation section and the verification / readout operation section, A second voltage generation circuit that generates a second internal voltage having a voltage level equal to or greater than the second voltage level during the program pulse application operation section, and generates the second internal voltage having the third voltage level or the second voltage level during the verification / readout operation section, The non-volatile memory device according to claim 4, further comprising:

8. The discharge control circuit of the first group described above is A first discharge transistor controls the connection between a common source line of the first group plane connected to the drain terminal and a ground voltage terminal connected to the source terminal in response to a discharge control signal of the first group applied to the gate terminal, A first level setting unit sets the discharge control signal for the first group to the level of the first internal voltage in response to the plane selection circuit selecting the planes of the first group as targets for verification / readout operation or program pulse application operation. A first standby setting unit sets the discharge control signal for the first group to the disable level in response to the plane selection circuit selecting the plane of the first group in a standby state, The non-volatile memory device according to claim 7, comprising:

9. The discharge control circuit of the second group described above is: A second discharge transistor controls the connection between a common source line of the second group's plane connected to the drain terminal and a ground voltage terminal connected to the source terminal in response to a discharge control signal of the second group applied to the gate terminal, A second level setting unit sets the discharge control signal for the second group to the level of the second internal voltage in response to the plane selection circuit selecting the plane of the second group as the target of verification / readout operation, A third level setting unit sets the discharge control signal for the second group to the level of the first internal voltage in response to the plane selection circuit selecting the plane of the second group as the target of program pulse application operation, A second standby setting unit sets the discharge control signal for the second group to the disable level in response to the plane selection circuit selecting the plane of the second group in a standby state, The non-volatile memory device according to claim 8, comprising:

10. The non-volatile memory device according to claim 9, wherein the second discharge transistor is a high-voltage transistor having a thicker oxide film thickness than the first discharge transistor.

11. In a method for operating a non-volatile memory device comprising N planes, each having a plurality of non-volatile memory cells, and N discharge control circuits for connecting each of the common source lines of the N planes to the ground voltage terminal in response to each of the N discharge control signals, A selection step in which K planes out of N planes are selected as targets for verification / readout operations, An adjustment step which adjusts the voltage levels of K discharge control signals by the physical position difference between each of the K discharge control circuits corresponding to the K planes selected in the selection step and the ground voltage terminal, A method for operating a non-volatile memory device, including the device itself.

12. A step of generating a first internal voltage having the first voltage level during the program pulse application operation section and the verification / readout operation section, The steps include generating a second internal voltage having a voltage level higher than or equal to a second voltage level that is higher than the first voltage level during the program pulse application operation section, and generating the second internal voltage having the second voltage level or a third voltage level during the verification / readout operation section, It further includes, The adjustment step described above is: Among the N discharge control circuits, a first internal voltage is supplied to the discharge control signal of the first group applied to the discharge control circuit of the first group that is physically adjacent to the ground voltage terminal, setting it to the first voltage level; among the N discharge control circuits, the first internal voltage is supplied to the discharge control signal of the second group corresponding to the discharge control circuit of the second group that is physically farther away from the ground voltage terminal than the discharge control circuit of the first group, setting it to the first voltage level, or the second internal voltage is supplied to set it to the second voltage level or the third voltage level. The method for operating a non-volatile memory device according to claim 11, wherein the third voltage level exceeds the first voltage level and is less than the second voltage level.

13. The adjustment step described above is: The method for operating a non-volatile memory device according to claim 12, wherein in the selection step, when each of the planes of the first group and the second group corresponding to the discharge control signals of the first group and the second group is selected as the target for verification / read operation, the first internal voltage is supplied to the discharge control signal of the first group to set it to the first voltage level, and the second internal voltage is supplied to the discharge control signal of the second group to set it to the second voltage level.

14. The adjustment step described above is: The method for operating a non-volatile memory device according to claim 13, wherein, in the selection step, the plane of the first group is selected in an idle state, and the plane of the second group is selected as the target of verification / read operation, the discharge control signal of the first group is set to a disabled level, and the second internal voltage is supplied to the discharge control signal of the second group to set it to the third voltage level.

15. The adjustment step described above is: The method for operating a non-volatile memory device according to claim 14, wherein in the selection step, the plane of the first group is selected as the target for verification / read operation, and the plane of the second group is selected in a standby state, the first internal voltage is supplied to the discharge control signal of the first group to set it to the first voltage level, and the discharge control signal of the second group is set to the disabled level.

16. The adjustment step described above is: The method for operating a non-volatile memory device according to claim 13, wherein in the selection step, one of the planes of the first group and the second group is selected as the target for program pulse application operation, and the remaining one is selected as the target for verification / read operation, and the first internal voltage is supplied to each of the discharge control signals of the first group and the second group to set the voltage to the first voltage level.

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