Processing using compact arithmetic elements

Abstract

To efficiently provide computing power in programmable and / or large-scale parallel processors or other devices. [Solution] The processing element 400 comprises processing elements designed to perform arithmetic operations (for example, operations that include one or more of addition, multiplication, subtraction, and division, although these operations are not mandatory) on low-precision high-dynamic-range (LPHDR) numerical values. The number of LPHDR computation elements in the Sur or other device is the same as the conventional precision (32 High dynamic range (with precision such as 64-bit or 64-bit floating-point arithmetic) It far exceeds the number of computational elements designed to perform the operation.

Description

Technical Field

[0001] The ability to compute quickly has become extremely important to humans. It is also increasingly relied upon in weather and climate prediction, the medical field (such as drug design and tomography), national defense, geological surveys, financial modeling, Internet searches, network communications, scientific research in various fields, and the design of new computer hardware. In order to make further progress in fields such as computer-aided design of complex nano-scale systems and the development of consumer products for seeing, hearing, and understanding, it is thought that there is a need to economically deploy even more advanced computing capabilities.

[0002] Gordon Moore's prediction that the computing performance per dollar would double every two years has been proven valid over 30 years and is thought to continue in some form. However, despite such rapid exponential progress, in reality, the inherent computing power available by silicon has grown to have a much faster capacity than the speed at which software can be made available. In other words, although the theoretical computing power of computer hardware has grown exponentially, due to the interfaces required for software to access the hardware, the ability of software to use the hardware to perform calculations is limited when approaching the theoretical maximum computing power of the hardware.

[0003] Consider a modern silicon microprocessor chip with approximately one billion transistors and a clock frequency of nearly 1 GHz. In one cycle, the chip delivers approximately one effective arithmetic operation to the running software. For example, one value is in the register

[0004] ​The values ​​are transferred between stars, another value is added, and then the multiplication is completed. Although clock speeds are about 1000 times faster today, this is not so different from what microprocessor chips were doing 30 years ago.

[0004] Actual computers are built as physical devices, and the physics on which computer machines are built often offers complex and interesting dynamics. For example, silicon metal-oxide-semiconductor field-effect transistors (silicon MOSFETs) G-STAR is a device capable of performing interesting nonlinear processing, such as exponential processing. The current is added at the contact point of the two wires. If set to the appropriate configuration, 10 Billions of transistors and wires, during the propagation delay of two or three basic components (set If the entire system is a conventional digital design, then it is called a "cycle". And today's CPU chips can perform a significant portion of the billion operations involved in the calculation. Rather, it simply uses a billion transistors to enable it to perform two or three of the aforementioned processes in each cycle. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Embodiments of the present invention relate to processors or other devices, and relate to programmable and / or large-scale parallel processing processors and other devices. This processor or other device then performs arithmetic operations that handle numbers in low-precision high dynamic range (LPHDR) calculations (for example, operations that do not necessarily include, but may include, addition, multiplication, subtraction, or division of 1 or more). It includes processing elements designed for this purpose. Such a processor or other device is, for example, implemented on a single chip. Whether or not it is implemented on a single chip, the number of LPHDR computation elements used in the processor or other device in a certain embodiment of the present invention is different from conventional precision. High dynamic range arithmetic (32-bit or 64-bit floating-point arithmetic) The processor or other device designed to perform operations such as The number of calculation elements used far exceeds that of the original.

[0006] In one embodiment, the “low-precision” calculation element occurs at a frequency of at least 0.1% (one-tenth of 1%). This involves performing calculations that produce results different from the correct result. The precision is considerably worse compared to the IEEE 754 single-precision floating-point standard used. In the embodiment of the programmable processor according to the present invention, programming is performed using an algorithm that functions properly even when such an unusually large number of calculation errors occur. Furthermore, in one embodiment, the processing element processes the input and / or less Both have the ability to output an output with a range that extends from 1 in 1,000,000 to 1,000,000. In the sense of possessing something, the processing element has a "high dynamic range". [Brief explanation of the drawing]

[0007] [Figure 1] This illustrates the overall design of a SIMD processor, which is one embodiment of the present invention. [Figure 2] This illustrates an example of a processing element array for a SIMD processor, which is one embodiment of the present invention. [Figure 3]This is one embodiment of the present invention, illustrating how processing elements in a processor's processing element array communicate data with other parts of the processor. [Figure 4] This illustrates the design of a processing element, which is one embodiment of the present invention. [Figure 5] This illustrates a word format for LPHDR data, which is one embodiment of the present invention. [Figure 6] This is one embodiment of the present invention, illustrating the design of an LPHDR calculation unit. [Best Mode for Carrying Out the Invention]

[0008] As mentioned above, today's CPU chips do not use the built-in transistors efficiently. For example, in a conventional CPU chip containing 1 billion transistors, each clock speed... Each cycle, the software is only able to perform a few operations. This is extremely inefficient, but for reasons that have been widely accepted as valid by those with ordinary knowledge of the field of technology, this method of CPU The design methodology described here, for example, satisfies the requirements for software compatibility in the initial design (which are often essential requirements). Furthermore, this design methodology achieves extremely high precision, typically using 32-bit or 64-bit integers for accurate calculations, and also using fairly accurate, widely standardized calculations with 32-bit and 64-bit floating-point numbers. In many applications, this kind of precision is essential. As a result, conventional CPUs use on the order of a million transistors to perform typical calculations. It is designed to provide the aforementioned level of precision.

[0009] However, in terms of precision, the sensitivity is not high, and there are many economically important applications where extremely large gains can be obtained in the form of application performance per transistor. And, if a million transistors inherently possess... This enormous gain is based on the ability to extract a significant portion of the available computing power. Current architectures used in general-purpose computers are unable to achieve this capability.

[0010] Due to the weaknesses of conventional computers, such as typical microprocessors, other types of computers have been developed to achieve higher performance. These machines utilize design methods such as Single Instruction Stream / Multiple Data Stream (SIMD) and Multiple Instruction Stream / Multiple Data Stream Design methodology for MIMD (Multiple Instruction Stream / Multiple Data Stream), Reconfigurable architectures such as Field Programmable Gate Arrays (FPGAs), and when applied to general-purpose computers, graphics processing units (GPUs) can be seen as a Single Instruction Stream / Multiple Thread (SIMT) design technique. This includes design methodologies for Graphics Processing Units.

[0011] SIMD machines are designed to operate by sequential programs with instructions for processing aggregates of data. There are two main types of SIMD machines, namely vector processors and array processors. Vector processors stream data through processing elements (or small aggregates of processing elements). Each component of the data stream is processed similarly. In vector machines, speed is achieved by omitting many instruction fetch / decode operations (fetching instructions from memory / decoding instructions) and continuously sending them to the processor to increase the processing clock speed (pipelining).

[0012] Array processors distribute data to a grid of processing elements (PEs). Each processing element has its own memory. Instructions are sent sequentially from a central control unit to the processing elements. Each processing element (PE) executes the instructions sent for the local data it has (often, in certain cycles, it can take the option of "idling"). In array processors, speed is achieved by efficiently using silicon. That is, in array processors, only one instruction fetch / decode unit is used to operate many small and simple execution units in parallel.

[0013] Array processors support a wide range of bit widths, such as 1, 4, 8 bits wide or more ​​Fixed-point operations with the above bit widths and floating-point operations have been used to construct. If the bit width is small, the processing elements can be made small, and most of the processing elements can be accommodated within a computer. However, in order to perform conventional operations, many processes need to be executed sequentially. If the bit width is widened, conventional operation processing can be completed in a single cycle. In fact, it is desirable to widen the bit width. In machines originally designed with a small bit width, such as the Connection Machine-1 and the Goodyear superparallel processor using 1-bit-width processing elements, in order to support high-speed operations well, development has been directed towards a wider data path, and machines such as the Connection Machine-2 equipped with hardware for 32-bit floating-point operations and the MasPar superparallel computer that succeeded the Goodyear machine, where the MasPar-1 uses 4-bit processing elements and the MasPar-2 uses 32-bit processing elements, have been created.

[0014] Also, array processors are designed to perform an analog representation of numerical values and use analog circuits when performing calculations. SCAMP corresponds to such a machine. These machines perform low-precision operations, and errors of about a few percent occur in the results of each process performed by these machines. Also, these machines generate noise during the calculation process, so calculations cannot be repeated. Furthermore, these machines handle only a narrow range of values. For example, rather than providing the high dynamic range of 32 or 64-bit floating-point operations, they are more suitable for 8-bit fixed-point numerical values. Due to such constraints, SCAMP is not aimed at general-purpose computers, but is designed and used for modeling in image processing and initial biological vision processes. In such application fields, the full range of arithmetic processing in hardware is not required. For example, SCAMP is not, but is designed and used for modeling in image processing and initial biological vision processes. In such application fields, the full range of arithmetic processing in hardware is not required. For example, SCAMP is designed and used for modeling in image processing and initial biological vision processes. In such application fields, the full range of arithmetic processing in hardware is not required. For example, SCAMP The design omits common division and multiplication operations.

[0015] In the 1980s, SIMD machines were popular, but as the price / performance of microprocessors improved, designers began to consider large collections of communication microprocessors. We started building a machine called MIMD. MIMD machines are fast and have a price / performance ratio that is comparable to the microprocessors that are their components, but MIMD machines are used in This software can only achieve relatively low computational performance per transistor. In that respect, it exhibits a similar level of inefficiency as that component.

[0016] Field-programmable gate arrays (FPGAs) are large general-purpose digital elements. It is an integrated circuit with a grid, and the wiring between digital elements is reconfigurable. These digital elements are originally single digital gates such as "AND" and "OR" gates. Le Gate was developed as a large element that can be programmed using Boolean functions, for example, into a 6-input, 1-output map. This architecture is configured so that FPGAs can perform a wide range of digital calculations from external sources. These digital calculations then allow the device to act as a coprocessor (secondary processing unit) to facilitate CPU calculations. This is intended to allow it to be used. However, operations such as multiplication and division of integers, and especially floating-point numbers, require many gates, consuming a large portion of the FPGA's general-purpose resources. For this reason, modern FPGAs allocate a significant portion of their memory to provide dozens or even hundreds of multiplication blocks. These blocks can then be used instead of general-purpose resources for calculations requiring multiplication. These multiplication blocks typically perform multiplication of integers with a width of 18 bits or more and utilize many transistors. These multiplication blocks are essentially the same as multiplication circuits that function as part of a general-purpose CPU. It seems so.

[0017] Existing field-programmable analog arrays (FPAAs) are similar to FPGAs, but the configurable elements of FPAAs are designed for analog processing. Generally speaking, this Such devices are intended for signal processing, such as those that help model neural circuits. FPAAs have relatively low precision and a relatively low dynamic range. It generates noise during the calculation process. FPAAs are general-purpose computers, or It is not designed for use in general-purpose computers. For example, to someone with ordinary knowledge of the art, FPAAs are high-performance digital... It had not been seen as a machine capable of executing the complex and diverse algorithms used on computers that employ floating-point arithmetic.

[0018] Finally, graphics processing units (GPUs) are a variety of parallel processors developed to provide high-speed graphics capabilities for personal computers. GPUs offer standard floating-point computing capabilities that deliver extremely high performance for specific tasks. The computing model of GPUs is often based on thousands of nearly identical computing threads (SIMT). In that respect, it is executed by a collection of internal computing engines similar to SIMD, where each engine is a slow external DR. AM memory determines or changes the output destination of the results in order to perform the task of providing data. Like other machines that perform standard floating-point arithmetic, GPUs use many transistors for that calculation. In the sense described above, GPUs, like general-purpose CPUs, waste these transistors.

[0019] Some GPUs support 16-bit floating-point numbers (often "half" floating-point numbers). (called a matte). Current GPU manufacturers like NVIDIA and AMD / ATI use the usual 32-bit This capability is useful for rendering images with a higher dynamic range than the RGBA format. The 32-bit RGBA format uses 8 bits of fixed-point data per color, while the 32-bit format uses 32 bits of floating-point data per color component. By using several points, it saves space. Industrial Light & Magic (ILM), a special effects film firm, has independently defined the same image in its OpenEXR standard. ILM states that the High Dynamic Range (HDR) image file format was developed by Industrial Light & Magic (ILM) for use in the field of computer image applications. It states the following about 16-bit floating-point images. It states that "this format includes OpenEXR, OpenGL, and D3DX." It is used in several computer graphics environments. The advantage over 8-bit or 16-bit binary integers is that the expanded dynamic range allows for more detail to be preserved in both highlights and shadows. 32-bit single-precision binary The advantages of this format are that it halves the storage capacity and bandwidth.

[0020] When a graphics processor supports 16-bit floating-point numbers, that support also includes support for 32-bit floating-point numbers, and even 64-bit floating-point numbers. In other words, the 16-bit floating-point format is supported by applications that require it, and is considered necessary for traditional graphics applications and so-called general-purpose GPU applications. Therefore, even higher-precision formats are supported. Consequently, existing GPUs are essentially allocating resources to 32-bit (and even 64-bit) operations, resulting in the waste of transistors described above.

[0021] All of the various architectures described above are attempts to extract even higher performance from silicon than what is possible with conventional processor designs. However, conventional processor designers have struggled with the fact that improving machine performance requires the use of a massive number of transistors. Such machines have historically and economically had to support existing large instruction sets such as the Intel x86 instruction set. Therefore, it is often necessary. Doubling the number of transistors does not improve performance. This is a difficult question, based on the law of diminishing returns, which states that it is not possible to double something. The problem is this: one aspect of the designer's struggle was improving the precision of the calculation process. This was because, if there were enough transistors and the processor originally supported long numbers (for example, 64-bit numbers), a significant speedup could be achieved in certain applications. The improvement in the precision of constant-point numbers, and the transition from 32 bits to 64 bits, and sometimes to 128 bits, has been achieved. The improvements in floating-point precision have led programmers to consider high precision, and they now develop algorithms based on the premise that computer processors provide such precision. This is because precision is everything in a new generation of silicon chips and is not a constraint in any way.

[0022] The embodiments of the present invention efficiently measure by an approach that is fundamentally different from the method described above. The present invention provides computational capabilities. In particular, embodiments of the present invention relate to a computer processor or other device that uses low-precision high dynamic range (LPHDR) processing elements to perform calculations (e.g., arithmetic operations). .

[0023] In a type of LPHDR calculation, the precision is approximately 0.1%, representing values ​​ranging from one part in a million to one million. If these values ​​were represented and handled using floating-point arithmetic, these numbers would have a binary mantissa not exceeding 10 bits plus a sign bit, and a binary exponent of at least 5 bits plus a sign bit. However, multiplication and division of such floating-point numbers The circuitry required for this operation tends to be relatively large. Another example of this approach uses the logarithmic representation of floating-point numbers. In this approach, the number of bits required to represent floating-point numbers is the same, but multiplication and division are performed as logarithmic addition and subtraction, respectively. Addition and subtraction can be performed efficiently, as described below. As a result, the area of ​​the arithmetic circuitry can be made relatively small, and many computational elements can be placed within a given area on the silicon. This means that the machine can perform more operations per unit time or per unit power. And this means that the machine can perform more operations within the LPHDR framework. This means that we can enjoy the advantages of expressible computation.

[0024] Another embodiment utilizes analog representation and processing mechanisms. The analog execution of LPHDR calculations is said to be superior to the digital execution. It has potential. This is because analog computation does not only utilize the digital aspects of a device's behavior, but also attempts to utilize the inherent analog physical behavior of transistors or other physical devices. In this way, utilizing the full capabilities inherent in the device allows for the execution of LPHDR computation. This allows for the reduction of the necessary mechanisms to a smaller scale. In recent years, in the field of silicon circuit technology, analog methods have been replaced by digital methods. This is because digital design is easier than analog design. Furthermore, compared to analog technology, digital technology has undergone continuous and rapid expansion (Moore's There is also the reason of the law. In particular, in the deep submicron region, large dimensions Like the previous generation of transistors, analog transistors no longer function. Such recent changes in well-known behaviors make analog design even more challenging. However, digital transistors are, in reality, analog transistors used in a digital way, and digital circuits are, in fact, designed to switch transistors between a completely "ON" state and a completely "OFF" state. Therefore, while the expansion of digital technology continues, using transistors in this way will begin to confront the realities of analog behavior. The expansion of transistors in digital applications is thought to be either reaching a dead end, or digital designers will need to recognize and deal with analog problems. For these reasons, digital implementations in LPHDR calculations are no longer easy, reliable, and It cannot be said to be scalable. And the analog implementation in LPHDR calculation is commercial This could potentially give it a competitive advantage as an industrial architecture.

[0025] Since the LPHDR processing element is relatively small, it can be handled by a single processor or other device. It can accommodate a very large number of LPHDR processing elements, and they can be processed in parallel with each other, and As a result, it is possible to configure a large-scale parallel processing LPHDR processor or other device. This is possible. Such processors and other devices have never been described or actually used as means of performing general-purpose calculations by anyone with common technical knowledge in the art. There are at least two reasons for this. One is, It was widely believed among those skilled in the art that, firstly, LPHDR calculations, especially large-scale LPHDR calculations, are impractical for circuit boards used for medium-scale general-purpose computing, regardless of whether large-scale parallel processing is performed or not. Secondly, it was widely believed among those skilled in the art that large-scale, high-precision calculations can be handled by compact computing units, and therefore it is not useful to perform large-scale, high-precision calculations on a single chip or a single machine without increasing the bandwidth between processing elements within the machine, the input to the machine, and the bandwidth outside the machine. This is because calculations are limited by wiring, and calculations can be considered to be performed without cost.

[0026] Despite the idea that performing large amounts of computation on a single chip or a large-scale parallel processing machine is not useful, and that large amounts of LPHDR calculations can actually produce worse results, In the embodiments of the present invention disclosed herein, large-scale parallel LPHDR design is actually useful, and less It has been demonstrated that it can provide significant practical advantages in several types of applications.

[0027] In conclusion, while modern digital computing systems can provide high-precision calculations, this high precision comes at a high cost. Although low-precision multiplication requires only a small number of transistors, modern double-precision floating-point multipliers require on the order of millions of transistors. Modern applications require high-precision processing... Although it is widely believed among those skilled in the art that logic is necessary, in reality, certain useful algorithms function properly even with lower precision. As a result, such algorithms can be executed by processors or other devices to which embodiments of the present invention are applied. This brings us closer to achieving the ultimate goal of using only a few transistors for multiplication and wire contacts for addition. Furthermore, this requires relatively few physical resources (a single silicon It enables large-scale parallel computing through a chip-like mechanism. While domain-specific tasks can function with low precision, the idea that relatively general-purpose calculations, such as those typically performed on general-purpose computers today, can also be performed with low precision is not self-evident and has actually been seen as a clear misconception by those skilled in the art. However, in reality, certain useful and important algorithms can function properly even with 32-bit precision or less within a large-scale parallel computing framework. Furthermore, in one embodiment of the present invention, such an algorithm is supported, and therefore transistors are used efficiently. As a result, the conventional Compared to computers, it offers improvements in speed, power consumption, and / or cost.

[0028] The following describes various computing devices to which embodiments of the present invention are applied. Some of the embodiments described here exemplify SIMD computer architectures. MIMD architecture, programmable array architectures (FPGAs and FPAAs) (etc.), or using other architectures such as GPU / SIMT architecture. It is also possible. The technology disclosed herein uses, for example, a processor or other device having an existing architecture as described above, and includes an LPHDR computing unit used in any of the methods disclosed herein, which is housed in the processor or other device. This can be done by replacing or augmenting specific or all existing arithmetic units. However, devices implemented according to embodiments of the present invention do not necessarily need to start by using existing processor designs as they are, and it is precisely in order to include the LPHDR computing unit in the architecture described herein or other architectures that this invention provides. The device to be implemented according to the embodiment of the invention may be designed from the outset.

[0029] For example, embodiments of the present invention can also be implemented using an array processor architecture, which is a special type of SIMD computer. There are many types of array processors disclosed in scientific and commercial literature, some of which are specialized. Examples include computers such as the Illiac 4, Connection Machine 1 and 2, Goodyear MPP, and MasPar.

[0030] However, embodiments of the present invention do not necessarily have to be implemented as SIMD computers. For example, embodiments of the present invention may be implemented as FPGAs, FPAAs, or related architectures that provide flexible connectivity to a group of processing elements. For example, embodiments of the present invention may be implemented as GPU / SIMTs, MIMDs, or other architectures. For example, embodiments of the present invention require fewer resources (number of transistors) compared to conventional architectures. To perform calculations using (or volume), it can be implemented as any type of machine using an LPHDR arithmetic processing element. Furthermore, the "processing element" referred to in the embodiments of the present invention can be any type of arithmetic execution unit, regardless of whether or not it performs LPHDR processing. It should be interpreted in general terms.

[0031] An example of a SIMD computing system 100 is shown in Figure 1. This computing system includes a collection of numerous processing elements (PEs) 104. This computing system often comprises a control unit (CU) 106, an I / O unit (IOU) 108, various peripheral devices 110, and a host computer 102. The set of processing elements (PEs) 104 is a two-dimensional array, grid, or other specific While a layout is not strictly necessary, we will refer to it here as the "Processing Element Array" (PEA) 104. Some machines have additional components, such as an additional memory system called "staging memory" in the Goodyear MPP. However, such additional components are not essential to the computer and are not necessary to understand the embodiments of the present invention. Therefore, for the sake of clarity, we will omit such additional components here. One embodiment of the present invention is a SIMD computing system as shown in Figure 1. Using the terminology of this specification, one or more (e.g., all) PEs in the processing element array (PEA) 104 become LPHDR processing elements.

[0032] The host computer 102 is responsible for the overall control of the computing system 100. The host computer 102 is a conventional uniprocessor, This involves performing real (or nearly serial) calculations. Of course, the host computer 102 will have a more complex structure that includes various types of parallel processing. This is also possible. In fact, employing a heterogeneous computing system that combines multiple computing architectures on a single machine is a preferred method of use for embodiments of the present invention.

[0033] The purpose of the host computer 102 is to provide the processing element array (PEA) 104 in a useful manner. The task is to perform calculations on a large quantity of data. The host computer 102 causes the PEs to perform calculations on data typically stored locally in each PE, in parallel with each other. For example, when there are many PEs, per unit time Then, a large number of calculations are performed.

[0034] The PEs in the Processing Element Array (PEA) 104 are capable of performing individual calculations roughly at a speed similar to that of the host computer 102. This means that the minimum time step of the host computer 102 or the Processing Element Array (PEA) 104 is the same fineness. Over a timescale, the host computer 102 controls the processing element array (PEA) 104. Attempting to do so would mean it is inefficient. (This minimum time step The 'p' corresponds to the clock period in conventional digital designs. ) For this reason... Therefore, a specialized control unit (CU) 106 is included in the architecture. That's fine too. The primary task of the control unit (CU) 106 is to retrieve instructions from the instruction memory. This involves retrieving and decoding instructions, which conceptually involves a control unit (CU). The role of 106 is to transmit the partially decoded instruction to all PEs of the Processing Element Array (PEA) 104. (This may be observed by the software of the control unit (CU) 106 as an event occurring almost simultaneously for all PEs. And, It doesn't need to be literally synchronized. In fact, it is efficient to design it in a synchronized way, where multiple instructions propagate simultaneously to different execution stages, like wavefronts propagating across the entire Processing Element Array (PEA) 104.

[0035] In a design that includes a control unit (CU) 106, the host computer 102 typically loads instructions (programs) for the processing element array (PEA) 104 into the control unit instruction memory (not shown in Figure 1). The control unit (CU) 106 then decodes the program and instructs the processing element array (PEA) 104 to perform calculations according to the instructions. For example, this program handles data movement within and between PEs, logical processing, arithmetic processing, and control flow processing within the control unit (CU) 106. It may also be similar to a general machine language program, with other instructions for performing similar processing. Therefore, the control unit (CU) 106 is a typical... It can execute the Ip program, but it also has the ability to generate large-scale parallel processing instructions for the Processing Element Array (PEA) 104.

[0036] Send data to the control unit (CU) 106 and the processing element array (PEA) 104. And in order to extract data from these, the I / O unit (IOU) 108 controls • Unit (CU) 106 and Processing Element Array (PEA) 104 and host computer 102, host computer memory (not shown in Figure 1), external storage device (e.g., disk drive), and display device for visualizing calculation results and special wide-bandwidth input device Peripheral devices of computer systems such as (for example, vision sensors) 110 It may also be possible to use an interface between them. The ability of the Processing Element Array (PEA) 104 to process data much faster is useful for the I / O Unit (IOU) 108 to allow some parts of data transfer to be performed by bypassing the host computer 102. Furthermore, the host computer 102 may have its own path for communicating with the peripheral devices 110.

[0037] The specific embodiment shown in Figure 1 is for illustrative purposes only and does not limit the present invention. It is not suitable. For example, as an alternative, there is the control unit (CU) 106 The functions performed by the host control omit the control unit (CU) 106. This can also be delegated to computer 102. The control unit (CU) 106 is hardware located away from the processing element array (PEA) 104 (for example, hardware removed from the chip). The control unit (CU) 106 can be installed as a wearable component, or it can be located near the processing element array (PEA) 104 (for example, within the same chip). I / O bypasses the I / O unit (IOU) 108 and goes via the control unit (CU) 106. It can also be routed through a separately provided I / O unit (IOU) 108, as shown in the diagram. It can also be made to allow this. Furthermore, the host computer 102 is optional. For example, the control unit (CU) 106 could be equipped with a CPU, or it could have functions that can replace functions that can be performed by the host computer 102. It may also include components. The peripheral device 110 shown in Figure 1 is optional. In the design shown in Figure 1, Goodyear MPP's " It can be equipped with special memory, such as "staging memory." For example, such memory is created by processing element arrays (PEs) 104 from the processing element array (PEA) to the memory. To access it in parallel at relatively high speed, it connects to an LPHDR chip using 3D assembly technology. It is possible.

[0038] The Processing Element Array (PEA) 104 is connected to the Control Unit (CU) 106 and the I / O Unit (IOU). In addition to being able to communicate with 108 or other possible mechanisms, the Processing Element Array (PEA) 104 itself has means for moving data within the array. For example, the Processing Element Array (PEA) 104 can be driven to move data only from one Processing Element (PE) to the nearest adjacent Processing Element (PE). That is, there is no longer any distance for data transfer. Figures 2 and 3 illustrate embodiments of the present invention, which employ the approach described above. Here, the nearest adjacent Processing Element (PE) consists of four adjacent Processing Element (PEs), located in the north, east, west, and south directions. It consists of processing elements (PEs) and is called NEWS design. For example, Figure 2 shows a processing element array (PEA). A subset of processing elements (PEs) in 104, namely PE 202, PE 204, PE 206, PE 208, And PE 210 is shown. The control unit (CU) 106 is the data transfer command. When an order is issued, all processing elements (PEs) are instructed to either access data from the nearest adjacent processing element (PE) or to send data to the nearest adjacent processing element (PE). For example, Each processing element (PE) accesses a specific data value in the processing element (PE) adjacent to it to the west and copies it into its own local memory. In some embodiments, such as the analog processing embodiment, this type of data transfer results in degradation of the copied value.

[0039] Figure 3 shows a processing element (PE) 302 with data connectivity to an I / O unit (IOU) 108. Therefore, processing element (PE) 302 is connected to processing element (PE) 304 on the north side, processing element (PE) 306 on the east side, processing element (PE) 308 on the south side, and processing element (PE) 310 on the west side. However, The drive signals that go from inside the processing element array (PEA) 104 to the I / O unit (IOU) 108 are Typically, this requires a relatively large drive circuit or analog mechanism. Providing such features in all processing elements (PEs) would exhaust a significant portion of the available hardware execution technology resources (such as the VLSI area). Furthermore, providing independent connections from all processing elements (PEs) to the I / O unit (IOU) 108 would be insufficient. Providing such connections would mean having many and long connections, which would also consume a large portion of the available resources. For this reason, connections between processing elements (PEs) and I / O units (IOUs) 108 may be limited to processing elements (PEs) at the ends of the processing element array (PEA) 104. In this case, to retrieve data from the processing element array (PEA) 104 and to send data back to the processing element array (PEA) 104... The data is read and written to the processing elements (PEs) at the ends of the processing element array (PEA) 104. , and the processing elements (PEs) at the end of the processing element array (PEA) 104 and the processing element array (PEA) 104 To move data between the internal processing elements (PEs), the control unit The instruction of the CU 106 is executed. In this design, data is sent from the I / O unit (IOU) 108 to one of the processing elements (PE) inside the processing element array (PEA) 104 using a direct connection, but the I / O unit (IOU) 108 Data can be read into the processing elements (PEs) at the end of the processing element array (PEA) 104. To send the data, use the control unit (CU) 106 to read the data. That's fine.

[0040] The connection between the control unit (CU) 106 and the processing element array (PEA) 104 is similar. There are variations of this. In one design, instructions are transmitted to all processing elements (PEs) almost simultaneously. One approach would be to give it the ability to do so, but another approach would be for the command to propagate gradually (for example) The processing element array (PEA) 104 is performed horizontally by a shift based on discrete time steps. This is done to allow instructions to reach the processing elements (PEs). This is performed as an embodiment of the present invention. In certain SIMD designs, the OR connections of each processing element (PE) in the processing element array (PE) 104 The state or AND connection state is controlled by the control unit (CU) 106 with a delay of approximately 1 instruction time. Therefore, it is equipped with a device that can read it.

[0041] Numerous well-studied papers exist on this subject, some of which are incorporated into embodiments of the present invention. For example, interconnects such as an 8-way local interconnect can be used. Local interconnects have a mix of distance hop counts, such as distance 1, 4, or 16. The outer ends can be connected using topologies such as torus or twisted torus. In place of, or in addition to, local interconnects, more complex global interconnects, such as hypercube designs, can be used. Furthermore, to create even larger processing element arrays (PEAs) 104, the processing element arrays (PEAs) 104 (e.g., chips) can be duplicated (e.g., circuit boards) It can be physically implemented by laying it on a board. PEAs components The elements do not necessarily have to be arranged in a grid, but by duplicating them, a simple grid-like arrangement or other arrangements can be formed.

[0042] Figure 4 shows an example design of a processing element (PE) 400 (which performs one or more functions of the processing elements (PEs) in the processing element array (PEA) 104). 400 stores local data. The storage capacity for this local data is designed It changes significantly each time. It is used to manufacture the processing element (PE) 400. It heavily depends on the implementation technology that can be used. (Constant values) Constants require fewer locations to be used than frequently changing numerical values ​​(registers). And in some designs, more constants are provided than registers. For example, a single group of transistor cells is used for a constant (e.g., f Using a loading gate flash memory cell, multiple registers are used. There are examples of digital circuits using a group of transistor cells (e.g., a 6-transistor SRAM cell). In analog circuit examples, this situation is often reversed. In this case, sufficient capacitance is required to ensure the long-term stability of the constants. And in such examples, there are more registers than constants. Typically, the storage capacity stored in the registers and constants of each processing element (PE) is in the tens or hundreds of arithmetic values, but these storage capacity The quantity can be adjusted by the designer. For example, one design may have a register memory but not a constant memory. And in another design, the number of values ​​stored in each processing element (PE) may be thousands or more. All such variations are reflected in the embodiments of the present invention.

[0043] Each processing element (PE) needs to process its own local data. Therefore, within the processing element (PE) 400, there are data paths 402a-i, a routing mechanism (such as the multiplexer MUX 404), and a mechanism for collecting the results of logical and arithmetic processing. The components (such as the logical unit 406 and the LPHDR arithmetic unit 408) exist. The LPHDR calculation unit 408 performs LPHDR calculations, which are terms used herein. The inputs, outputs, and intermediate numerical values ​​received by the processing element (PE) 400, output by the processing element (PE) 400, and processed by the processing element (PE) 400 are, for example, represented as numerical values. It takes the form of an electrical signal.

[0044] Furthermore, the processing element (PE) 400 is one or more masks 410 shown in Figure 4. It may also be provided with a flag bit. The purpose of the mask 410 is to provide several processing options. Enables PEs and ignores instructions issued by Control Unit (CU) 106. Therefore, a specific mask bit is set in that processing element (PEs). By doing so, the normal locking of all processing elements (PEs) in the processing element array (PEA) 104 is performed. • Variations in step operations can be created. For example, the control unit (CU) 106 can issue instructions that reset or set the mask 410 of each processing element (PE) depending on whether a specific register within the processing element (PE) is positive or negative. For example, subsequent instructions, such as arithmetic instructions, can include a bit that indicates that the instruction should only be executed by processing elements (PEs) whose mask 410 has been reset. Depending on whether a specific register within that processing element (PE) is negative, the combination will have the effect of conditionally executing the arithmetic instruction at each processing element (PE). Similar to comparison instructions in conventional computers, there are many design options for the mechanism to set and clear the mask.

[0045] Processing in the processing elements (PEs) is controlled by control signals 412a-d received from the control unit (CU) 106. These four control signals are shown in Figure 4, but these are merely examples and do not mean that the system is limited to these. Although the details of this mechanism are not shown, the control signals 412a-d send numerical values ​​from register memory or constant memory within the processing element (PE) 400 to the data path, or Identify adjacent processing elements (PEs). Such processing is performed by logical unit 406 and arithmetic. This is executed by Unit 408 and other processing mechanisms, and the results are stored in registers. The control signals 412a-d then use the set and reset methods and the mask 410. Identify the specific actions to be taken. These are described in detail in the SIMD processor documentation.

[0046] There are many variations in the design of the processing element (PE) 400 and the processing element array (PEA) 104. Many possibilities exist, and all of them are included within the scope of the present invention. Digital processing elements (PEs) include shifters, reference tables, and others as described in the above-mentioned literature. Many other mechanisms can be incorporated. In analog processing elements (PEs), time It can be equipped with inter-base operators, filters, comparators with global bloatcast signals, and many other mechanisms as described in the above literature. The processing element array (PEA) 104 is used for digital processing elements (PEs) with OR connections. It features a global mechanism such as a line or AND connection, and for analog processing elements (PEs), it can have a SUM connection. Again, digital and analog connections Many variations are described in detail in literature on computer architecture.

[0047] For example, it is also possible to support LPHDR operations other than addition and / or, in addition to addition and multiplication. A machine that can only perform multiplication and the function (1-X) cannot perform approximate addition and other operations. It can be used for calculations. The LPHDR processing set is a normal in the art. Using techniques known to those with knowledge, LPHDR operations such as addition, multiplication, subtraction, and division. It is used to estimate the processing time.

[0048] One aspect of the unique embodiment of the present invention is the inclusion of an LPHDR calculation mechanism within the processing elements (PEs). An embodiment of this mechanism is described below.

[0049] In one digital embodiment relating to the LPHDR arithmetic unit 408, the digital (binary) representation is The resulting numerical values ​​are processed. In one digital embodiment, these values ​​are represented logarithmically. This method of representation is called a logarithmic system (LNS) and is a well-known system to those skilled in the art. .

[0050] In a logarithmic system (LNS), numbers are represented by their sign and exponent. In a logarithmic system (LNS), there is an implicit low for the logarithm, which is typically 2 when functioning with digital hardware. In this embodiment, a low of 2 is used as an example. Consequently, the number B is represented by its sign and the logarithm of the low 2, and the number b is represented by its absolute value. For numbers with a maximum display error of 1%, the variable decimal part is in numerical B. It is displayed with sufficient precision to correspond to a change of approximately 1%. If fractions are represented using 6 bits... If so, increasing or decreasing the decimal part by 1 will result in the value B being the 64th root of 2 (approximately 1.011). This corresponds to multiplying or dividing by (to). In this embodiment, the numerical value is This means that the displayed value may have a multiplicative error of approximately 1%. Therefore, in this embodiment, 6 bits are allocated to display the fractional part.

[0051] Furthermore, the range of values ​​processed in this embodiment has a high dynamic range. To represent the absolute value from the billionth to the billionth, the integer part of the logarithm is the lower of the billionth. It must be long enough to represent both positive and negative numbers. Its logarithm is approximately 29.9. In this embodiment, the integer part of the logarithmic representation is 5 bits long to represent numbers from 0 to 31, which is sufficient. In addition, a sign bit is needed for the exponent. Negative logarithms are represented using two's complement representation.

[0052] In a logarithmic system (LNS), the value of 0 is negative infinity. To accurately represent this special value, a display method can be selected. However, in order to minimize the resources used by the arithmetic circuit (for example, to minimize the memory area), in this embodiment, 0 is represented as negative infinity. The largest number, -32, is displayed, which corresponds to the two's complement bit representation "100000 000000", and represents a value of approximately 2.33E-10.

[0053] When performing calculations, situations may arise where the process cannot produce a reasonable value. For example, this can occur when multiplying or adding two very large numbers, or when performing division by zero (or a number close to zero), where the numbers are too large to be represented in the selected word format. A common approach to resolving such problems is to mark the resulting value as "Not A Number (NAN)" and to verify whether a "NAN" occurred during processing, or whether any of the inputs are "NAN". In this embodiment, the approach described below is employed.

[0054] Figure 5 shows the word format 500 used to represent the numerical values ​​in this embodiment. This word format 500 consists of one NAN bit 502a and the sign of the value. It has one bit 502b that gives the value and 12 bits 502c-e that display the logarithm. The bit representing the logarithm has a 5-bit integer part 502d and a 6-bit fractional part 502e. To enable the representation of negative logarithms, the bit representing the logarithm has a logarithmic sign bit 502c, which is expressed in two's complement form. The NAN bit 502a is set if there is a problem with the calculated value. The word format 500 shown in Figure 5 is merely an example and does not limit the scope of the present invention. Other variations can be used as long as they are low precision and have a high dynamic range.

[0055] Figure 6 shows an example of a digital LPHDR calculation unit 408 corresponding to the display format shown in Figure 5. The LPHDR calculation unit 408 receives two inputs A602a and B602b and outputs one output 602c. The inputs 602a-b and output 602c can take the form of electrical signals representing numerical values, for example, according to the display format shown in Figure 5. Yes, it is possible. And inputs 602a-b and output 602c are true signals transmitted within the LPHDR arithmetic unit 408 by the components of the LPHDR arithmetic unit 408. Each of the inputs 602a-b and output 602c consists of a numerical bit and a NAN bit. The LPHDR arithmetic unit 408 is controlled by control signals 412a-d sent from the control unit (CU) 106. These control signals 412a-d then apply to the inputs 602a-b. This determines which arithmetic operations should be performed. In this embodiment, inputs 602a-b All applicable arithmetic operations are performed in parallel by the adder / subtractor 604, the multiplier 606, and the divider 608. The adder / subtractor 604 performs LPHDR addition and subtraction, and the multiplier 606 performs L Perform a PHDR multiplication, and divider 608 performs an LPHDR division.

[0056] The desired result is obtained (from the outputs of adder / subtractor 604, multiplier 606, and divider 608) multiplexed Selected by MUXes 610a and 610b. The right-hand multiplexer (MUX) 610b sends the desired value to output 602c. The left-hand multiplexer (MUX) 610a sends the desired value The NAN bit information obtained from the calculation is sent to the OR gate 612, and this OR gate checks if any of the inputs are NAN, or if a NAN occurs in a particular operation. It is configured to output after being set. Literature discussing computer architectures describes many variations that can be incorporated into the embodiment shown in Figure 6.

[0057] In logarithmic systems (LNS), multiplication (MUL) and division (DIV) are extremely easy. It has the significant advantage of using very few physical resources (less implementation area on silicon). The sign of the operation result is the exclusive OR of the signs of the numbers being operated on. The logarithmic part of the output is the sum of the logarithmic parts of the numbers being operated on in the case of multiplication (MUL), and the difference of the logarithmic parts of the numbers being operated on in the case of division (DIV). The sum and difference of logarithms can overflow, resulting in NANs. Other operations are also easier in logarithmic systems (LNS). For example, the square root is equivalent to dividing the logarithm by 1 / 2, which in the above representation method only requires shifting the bit one bit to the right.

[0058] Therefore, the multiplier 606 and divider 608 shown in Figure 6 are implemented as circuits that simply add and subtract binary complement inputs (binary complement happens to be logarithmic). If the value overflows, it outputs 1 as NAN. Yes, they are.

[0059] The addition and subtraction in a logarithmic system (LNS), i.e., the adder / subtractor 604 in Figure 6, This will be done following a common approach used in the literature on logarithmic systems (LNS). Let us consider addition. Given two positive numbers B and C, expressed by logarithms b and c, the sum of B and C is given by log(B+C). The approach to calculating this result is well known to those skilled in the art and is based on the following notation. Log(B+C)=log(B*(1+C / B))=log(B)+log(1+C / B)=b+F(cb) Here, F(x) = log(1+2^x) Therefore, in this embodiment, cb is calculated using standard digital techniques well known to those skilled in the art, substituted into F, and the result is added to b.

[0060] Much of the published literature on logarithmic systems (LNS) concerns how to compute F(x), a special function for addition (ADD), and a similar function for subtraction (SUB). These two functions often share a circuit. And this is shown in Figure 6. The reason why a single combined adder / subtractor 604 is used in the embodiment shown is Many publications describe methods for calculating or estimating these functions. They also discuss how to handle cases where the precision of the values ​​is low. Such methods, or alternative methods, can be used. Generally speaking, for performing large-scale parallel LPHDR operations, more appropriate methods are available. This approach minimizes the use of resources such as circuit area, as shown in the example in Figure 6. The display used there is of low precision, and the calculations performed there are deterministic. It does not need to be definitive (determinatively determined as one), and is most suitable for low-precision display. The advantages derived from the fact that there is no need to return an exact answer can be enjoyed. Accordingly, in embodiments of the present invention, a circuit that does not calculate the best answer can be selected and used from a limited number of options applicable to low-precision displays.

[0061] In order to enable conditional processing of selected processing elements (PEs), this embodiment uses the calculation results Based on this, the mask flag 410 can be reset or set. This is how it works. The mechanism for doing this is that the control unit (CU) 106 is To perform a basic test on the value that enters the mask 410 through the data path 402f, Along with the command, the flag of mask 410 in each processing element (PE) is reset or set Instructions such as the following are issued to set the flag. Examples of instructions described later include an instruction to copy the sign bit or NAN bit of data that enters the mask bit 410 via the data path 402f. Another example is that the mask bit 410 is set when the 12-bit numeric part of the data on the data path 402f is equal to zero in binary. There are many additional and alternative methods for performing the above-described processing, which is similar to comparison instructions in conventional processors and is well known to those skilled in the art.

[0062] The LPHDR operation is performed using the trivial method described above, which employs the logarithmic system (LNS) processing, but programmers may consider converting the selected numbers to 12-bit binary complement. Multiplication (MUL) and division (DIV) are operations performed on logarithmic systems (LNS), and their accuracy is crucial. For this reason, such numbers can be used for addition and subtraction. The mask set instruction can compare these simple binary numbers. Thus, in addition to performing LPHDR calculations, this digital method using a logarithmic system (LNS) can also perform short signed integer operations. It can perform simple binary arithmetic operations on numbers.

[0063] In one embodiment of the present invention, an analog display and analog processing method may be provided. In such an embodiment, the LPHDR value can be represented, for example, as charge, current, voltage, frequency, pulse width, pulse density, various forms of spikes, or other forms that are not characteristic of conventional digital implementations. A mechanism for processing the values ​​thus represented. Similar to Nism, such display methods have been discussed in numerous publications. These methods, known as analog methods, can be used to perform LPHDR calculations on a wide range of architectures, such as SIMD, which has been discussed here as an example. ru.

[0064] An example of an analog SIMD architecture is Dudek's SCAMP design (and related designs). In this design, the numerical values ​​have a low dynamic range and an accuracy of approximately 1%. The numerical values ​​are represented by the charge of a capacitor. These capacitors are typically the gates of transistors. Each processing element (PE) has several memory cells similar to the registers shown in Figure 4. Addition is performed by turning on the pass transistors from the two arithmetic objects, which transfer their own charge to the analog bus, and the natural charge and wiring The sum is calculated by a scientific process, the circuit is opened to transfer the data to charge the capacitor of another register, and the calculated sum is then displayed. Details disclosed by Dudek Although the mechanism actually produces negative sums, the basic concept remains as described here, and it uses analog displays and simple processing mechanisms to perform addition and subtraction in a simple way.

[0065] Variations of the SCAMP design architecture have been manufactured, and related to image processing. It has been used in the field to perform low-precision, low-dynamic-range processing. This SCAMP design architecture is designed to perform high-dynamic-range calculations. It does not perform such operations, nor does it have a mechanism for multiplying or dividing values ​​stored in registers. However, the Dudek design architecture is analog-based. This suggests the possibility of constructing a SIMD machine. Below is one embodiment of the present invention, which describes a method for constructing an analog SIMD machine that performs LPHDR calculations. I will explain.

[0066] In one embodiment of the present invention, numerical values ​​are displayed as a hybrid method combining analog and digital formats. In this embodiment, numerical values ​​are normalized with low precision, and the lowest value is set to 2 as a floating-point number. The score is expressed as a numerical value, with the mantissa being an analog value and the exponent being a binary digital value. The analog values ​​have an accuracy of approximately 1%, and are based on Dudek's approach, with accuracy derived from the analog processing. It falls well within the reasonable range of scientific and technical standards. Is the exponent 6 bits long? Or, it can be any length necessary to provide the required high dynamic range.

[0067] To multiply numbers, this embodiment is performed by analogy to conventional floating-point arithmetic. The exponent, which is a digital value, is calculated using binary arithmetic, a standard digital technique. The numbers are added together using an adder. The mantissa, which is an analog value, is multiplied. Since these represent normalized numbers between approximately 1 / 2 and 1, their product is a small number, approximately 1 / 4. The value of such a product needs to be normalized to a range of 1 / 2 to 1. In this embodiment, this is done by using a threshold circuit to compare the mantissa, which is an analog value, with an analog representation of 1 / 2. This is done by... If the mantissa, which is an analog value, is less than 1 / 2, the mantissa The mantissa is doubled, and 1 is subtracted from the digital exponent. This subtraction is a simple subtraction of digital values. Doubling the analog mantissa is done by selecting an analog. It is executed in a way that supports log display. For example, it can be used to add two analog values. Any means used can be used to double the mantissa by adding the copied mantissa to the original mantissa. For example, if the mantissa is an analog value When expressed as an electric current, copies can be made using current mirrors or other appropriate mechanisms, and addition can be performed by providing contacts for current addition.

[0068] The method of multiplying by the mantissa, which is the original analog value, depends on the selected representation method. For example, if the mantissa, which is the analog value, is represented by charge based on SCAMP... In such cases, methods known from the literature can be used to convert charge to electric current. For example, since the charge of a capacitor determines the voltage of the capacitor, converting charge to electric current can be performed as a conversion from voltage to electric current. This technique is a fundamental technique well known to those skilled in the art in the field of analog electronics. In any case, if the mantissa, which is an analog value, is expressed as electric current, or if the mantissa has been converted to electric current, then multiplication of the mantissa can be performed using, for example, Gilbert's technique. Gilbert's multiplier produces a current representing the product, and if necessary, this product, the electric current, is multiplied by the charge (or used It can also be converted back to any display format (any format is acceptable). What has been stated here is This is merely an example to show how the process needs to be carried out. Such matters are extensively discussed in the literature, and this type of analog circuit is well known to those skilled in the art.

[0069] In numerical addition and subtraction, it is necessary to normalize the numbers beforehand so that they have the same exponent, as was done in conventional digital floating-point arithmetic. In this embodiment, normalization is performed by comparing the exponents and selecting the one with the smaller exponent. The smaller exponent is subtracted from the larger exponent using a digital method. This difference is calculated by determining how many times the mantissa of the number with the smaller exponent needs to be divided by 1 / 2. This identifies the mantissa. If the mantissa is expressed as an electric current (or converted to an electric current) If (as described above), the ladder is identified by the difference in the exponent calculated as described above. To divide the current by half the number of times required, corresponding to the number of floors, an analog R-2R type is used. A ladder diagram can be used for the expression. To create the mantissa of the output, the current corresponding to the mantissa of the number with the larger exponent is added to the resulting scaled-down current (if this is an LPHDR subtraction, it will be subtracted). The output is The output exponent corresponding to the mantissa will be the larger of the two exponents. At this point, post-normalization processing is required. If the output mantissa is greater than 1, The mantissa needs to be divided by 1 / 2, and the resulting exponent needs to be incremented by 1. If the resulting mantissa is less than 1 / 2, the mantissa needs to be multiplied by 2 the required number of times until it exceeds 1 / 2. Then the resulting exponent is the corresponding The number of operations must be subtracted (decremented) by the number of times. This process is carried out by a series of threshold circuits, multiplier circuits, and decrement circuits. This involves incrementing or decrementing the exponent in binary digital form. Furthermore, doubling or halving the current of the mantissa in the analog form to address these issues is a simple process well known to those skilled in the art.

[0070] In this embodiment, the exponent is represented as a digital binary number. In another embodiment, The exponent can also be represented as an analog value. However, it is particularly important that the exponent is represented in a way that does not introduce noise or errors that would cause fluctuations in the numerical value representing the exponent during storage and calculation. Such fluctuations in the exponent create two changing factors in the value of the stored numerical value. Maintaining the precision of the exponent One possible implementation is to use a relatively small level for the exponent, for example, 16 bits + the sign. It can be quantized to 16 bits. During processing, slight fluctuations in the analog display of the exponent can be eliminated by a circuit that stores the value again in a standardized 16-bit quantization level. In such an embodiment, in order to obtain a sufficient dynamic range, the floating-point number is not as a normal low 2 number, It is also acceptable to treat it as a number with a value of 4. For example, this means that the normalized mantissa is in the range of 1 / 4 to 1. The addition, subtraction, and multiplication mentioned here are only However, this will result in simple fluctuations.

[0071] The examples of using signals mixed in analog format described above are illustrative and not intended to constitute a limitation of the present invention. Publications relating to neuromorphological techniques using signals mixed in analog format describe the actions performed in LPHDR calculations. It provides a great many methods for memory and processing that can do this. In such memory and processing, the operation of the machine performing the LPHDR calculation is similar to assembly error. Noise is also incorporated. Although the results obtained from running software applications using the "fp + noise" calculation, as described later, have a very "non-digital" quality, the machines constructed in this way are surprisingly useful.

[0072] Evidence that LPHDR calculations are effective in several important computational applications. The following is a description of this matter. While there is evidence that the present invention is effective for a wide range of variations of its embodiments, this effectiveness does not depend on the details of the implementation.

[0073] To demonstrate the effectiveness of LPHDR calculations, we select a very common example of an LPHDR machine. The model of such a machine can provide at least the following functions: (1) capable of large-scale parallel processing, (2) capable of providing LPHDR calculations which may be noisy, (3) equipped with a small amount of local memory in each processing unit, and (4) a two-dimensional structure with only local connections (connections that are not powerful, flexible, or have advanced connection mechanisms) between units. (5) The machine is equipped with an arithmetic / memory unit having a rational arrangement, and has only a limited bandwidth between the machine and the host machine. It should be noted that this model is provided solely as an example to demonstrate the effectiveness of variations relating to embodiments of the present invention and is not intended to limit the invention. This model, in particular, operates in digital, analog, or combined forms, is noise-free or noise-inducing, and features architectures that conform to the prerequisites of the model, such as FPGAs, SIMDs, and MIMDs. Furthermore, it includes common designs such as shared memory designs, GPU-like designs, and other sophisticated designs. The architecture incorporates the capabilities of this model. Therefore, LPHDR operations using these architectures are even more useful. Here, we demonstrate that LPHDR operations are effective for a wide range of designs, but SIMD within that wide range of designs is presented as one example for the following discussion, where each unit is referred to as a "processing element" or "PE". Each unit combines memory and operations.

[0074] Several types of applications are described below. For each application, the following points are discussed: (1) When calculations are performed in LPHDR operations where noise generation is possible, the results are valid; and (2) The calculation is constructed in a two-dimensional physical arrangement, with only local data exchange between units, limited to the memory within each unit, and limited to data exchange with the host machine. This results in calculations that efficiently utilize the machine's resources (memory, time, and power). The first requirement concerns "accuracy," and the second requirement concerns "efficiency." Applications that meet these two requirements and operate on this model are expected to function well on many types of LPHDR machines, and therefore, such development Akira's machine can be used effectively in a wide range of applications.

[0075] The application was tested by machine calculations in two embodiments. The first embodiment performs accurate floating-point calculations, but multiplies the result of each calculation by a random number between 0.99 and 1.01, uniformly selected. In the following discussion, this embodiment will be referred to as "fp + noise". This embodiment This represents the results calculated by the machine used in the analog implementation.

[0076] The second embodiment uses logarithmic calculations with numerical values ​​in the display format shown in Figure 5. The calculation is repeatable, meaning it is noise-free, but due to the small size of the fractional part, an error of approximately 1-2% occurs in each process. In the following discussion, this embodiment will be referred to as "lns". This embodiment specifically represents the results calculated by the machine relating to the digital form embodiment.

[0077] To demonstrate the usefulness of the embodiments of the present invention, we will discuss three computational tasks that are executable by the embodiments of the present invention and allow for diversification of practical applications. We will discuss this. Two of the tasks relate to nearest neighbor search, and the remaining one relates to processing visual information. Below, we will describe the tasks, then discuss their practical applications, and then demonstrate that each task can be computed using the general model described above and can be computed by applying embodiments of the present invention. Application 1: Neighbor Search

[0078] A large set of vectors is given, which we will call "Examples". And we will call one of the vectors "Test". The problem is called nearest neighbor search ( The "NN" (referred to as "NN") is to find the "Example" that is closest to "Test," where the metric distance is the square of the Euclidean distance (the sum of the squares of the distances between each component).

[0079] Neural Networks (NNs) are widely used and useful computations. One example of their application is in the field of data compression, known as "vector quantization." In this application, a set of relatively long vectors is prepared in a "codebook" and associated with short "codewords" (these are the Examples). The system moves across the set of vectors to be compressed, and then, for a vector called Test, it finds the closest vector in the codebook and outputs the corresponding codeword. This compresses the set of vectors. The data is reduced to a series of short codewords. Since the codewords do not perfectly identify the original sequence of vectors, this method results in irreversible data compression. Other applications include audio compression and use as an MPEG standard.

[0080] Another application of neural networks (NNs) is to determine whether or not video fragmentation occurs in a large video database. Here, known techniques such as color histograms and scale-invariant feature extraction are used to summarize images from video fragments into feature vectors. Here, Examples are similar feature vectors extracted from the video database. We want to know whether any vector from the video fragments is similar to any vector from the video database, and NNs are effective in making such a determination.

[0081] In many applications of nearest neighbor search, it is preferable to find the true nearest neighbor, but it is also acceptable if the true nearest neighbor is found most of the time, and a slightly more distant neighbor is found occasionally. Therefore, approximate solutions to nearest neighbor search problems are also useful, especially if they can be computed particularly quickly, with low power, or with some other advantage over obtaining the exact solution.

[0082] The following demonstrates a method that satisfies the criteria for "accuracy" and "efficiency," and that, by applying embodiments of the present invention, it is possible to find the nearly nearest neighbor.

[0083] algorithm An algorithm that can be executed by an implemented machine according to an embodiment of the present invention is described below. The algorithm is executed by execution software that includes instructions for executing the algorithm. The input to this algorithm is one set. These are the Examples and Test vectors. And this algorithm is the closest to the Test ( The goal is to find the closest example.

[0084] In the simplest version of the algorithm, the number of Examples is equal to the number of Processing Elements (PEs). Each vector must contain a small amount of information, not exceeding the memory of a single processing element (PE). Examples are placed within the memory of the processing elements (PEs), with one Example placed within each processing element (PE). Given a Test, the Test passes through all the processing elements (PEs) in order. Because the Test passes through the processing elements (PEs), by accompanying the Test, we can determine which processing element (PE) (and therefore which Example) is the closest Example, and the distance from the Test to the closest Example. I understand. Each processing element (PE) interacts with the Example stored in the memory of the processing element (PE). Calculate the distance and transfer the Test along with the distance and the indicator passed into this PE ( If the distance calculated by this PE exceeds the distance passed to this PE, or , along with information indicating that this PE example is the closest, calculated by this PE Transfer the Test along with the calculated distance (the distance calculated by this PE is passed to this PE) (If it is smaller than the distance). Therefore, in this algorithm, Test passes through a set of processing elements (PEs), resulting in a simple, minimized process. When Test and its associated information leave the last PE, the output includes the distance between Example and Test, along with an indication of which PE (and which Example) is closest to Test.

[0085] In a more efficient and improved version of this algorithm, the Test is initially transferred, and the Test and related information are sent downwards, for example, from the top row to all columns, with an efficient search performed in parallel with the other columns. Then, once the information reaches the bottom of a column, the minimum distance of the Example across all columns being processed is calculated, as long as the information is transmitted across the bottom of the column. This means that the time required to process the test is determined by the number of processing elements (PEs) in the rows and columns. It means being proportional to (a large degree of) something.

[0086] The enhancements to this algorithm are carried out as described above, but the enhanced algorithm will show information indicating both the nearest example and the second nearest example found. It calculates and transmits this information. When this information leaves the array of processing elements (PEs), A digital processor managing the processing element (PE) array calculates (with high precision) the distance between Test and the two Examples indicated by the processing element (PE) array, and outputs the closest of the two as being the closest neighbor to Test.

[0087] accuracy Coded in C language and executed by the enhanced algorithm described above. Let's explain the operation. This code calculates the nearest neighbors mentioned above, along with a weighted score, which will be explained later.

[0088] The C code is an example of how the invention is actually performed when it is executed, as if it were run in hardware. It performs the same set of arithmetic operations of the same order, using the same method as the calculation. Therefore, the C code is the same as the result derived by the enhanced algorithm when performing the present invention. It is possible to produce the same result. (When executing in this way, it will function efficiently.) The structure of the algorithm for this purpose will be explained in the section discussing "efficiency."

[0089] In particular, when calculating the distance between Test and each Example, the calculation required to find the sum of the squares of the distances between the vector components of Test and Example may involve summing up long numbers, so the C code uses Kahan's method, as described later.

[0090] As mentioned above, this C code now includes several execution procedures for the calculations. When compiled with "#define fp", calculations are performed using IEEE standard floating-point numbers. If command-line arguments are provided to enable calculations under noise, random noise will be added to each calculation result. This is called "fp + noise". This is an operation of the form ". If compiled without "#define fp", the operation is performed by using low-precision logarithmic arithmetic with a low of 2 and a 6-bit fractional part. This is the "lns" form of operation.

[0091] When this code is executed, it produces output showing the results of the calculations performed by the code. These outputs, as will be explained below, demonstrate that certain command-line arguments cause the enhanced algorithm to produce calculation results for the nearest neighbors of the LPHDR. These results demonstrate the usefulness of this approach. Here, we will briefly explain these results.

[0092] The first result concerns the "fp + noise" format. Ten clearly distinguishable calculations were performed. In each calculation, one million random example vectors were used. Then, an Example vector of length 5 was generated. Each component of each vector was determined based on N(0, 1). Here, N(0, 1) is a Gaussian (normal) distribution. This means the mean is zero and the standard deviation is 1. Furthermore, in each calculation, 100 Test vectors were generated, each with a length of 5. Each component of each vector was determined based on N(0, 1). For each Test, the nearest neighbor was calculated using two methods. One method uses the enhanced algorithm described above, and the other uses the standard "nearest neighbor search method" with high-precision floating-point arithmetic. The results obtained using the enhanced algorithm were the same as those obtained using the standard floating-point method. The results are shown below. % . / a.out 5 10 1000000 100 1 The representation format is floating-point format, and there is noise. Run 1: Performed on 100 tests, 100% (100.0%) suitability, 0.81% mean score error. Run 2: Performed on 100 tests, 100% (100.0%) suitability, 0.84% ​​mean score error. Run 3: Performed on 100 tests, 100% (100.0%) suitability, 0.98% mean score error. Run 4: Performed on 100 tests, 100% (100.0%) suitability, 0.81% mean score error. Run 5: Performed on 100 tests, 100% (100.0%) suitability, 0.94% mean score error. Run 6: Performed on 100 tests, 100% (100.0%) suitability, 0.82% mean score error. Run 7: Performed on 100 tests, 100% (100.0%) suitability, 0.78% mean score error. Run 8: Performed on 100 tests, 100% (100.0%) suitability, 0.86% mean score error. Run 9: Performed on 100 tests, 100% (100.0%) suitability, 0.85% mean score error. Run 10: Performed on 100 tests, 99% (99.0%) suitability, 0.86% mean score error. Here, the average percentage of the number of times the LPHDR operation found the closest example (ultimately DP) (After corrections were made) = 99.90% The average score error when comparing LPHDR calculation with DP is 0.85%.

[0093] Here, the value of "average score error" will be explained later in the section on "weighted scores." The information referred to here as "fit" is relevant ( It means (that which is appropriate).

[0094] The calculation was performed 10 times, targeting only one of the tests each time. The nearest neighbor obtained from the calculations performed on 100 tests was then obtained using a standard high-precision method. The result differed from that of the nearest neighbor. Therefore, the calculation was in the form of "fp + noise". The average percentage of the fit when comparing the performance using the enhanced algorithm with that when using the standard high-precision method was 99.9%.

[0095] Next, a similar calculation was performed using the "lns" form of arithmetic. The results are shown below. vinegar. % . / a.out 5 10 1000000 100 0 The representation format is in lns format, and it is noise-free. Run 1: Performed on 100 tests, 100% (100.0%) suitability, 0.15% mean score error. Run 2: Performed on 100 tests, 100% (100.0%) suitability, 0.07% mean score error. Run 3: Performed on 100 tests, 100% (100.0%) suitability, 0.08% mean score error. Run 4: Performed on 100 tests, 100% (100.0%) suitability, 0.09% mean score error. Run 5: Performed on 100 tests, 100% (100.0%) suitability, 0.11% mean score error. Run 6: Performed on 100 tests, 100% (100.0%) suitability, 0.16% mean score error. Run 7: Performed on 100 tests, 100% (100.0%) suitability, 0.07% mean score error. Run 8: Performed on 100 tests, 100% (100.0%) suitability, 0.13% mean score error. Run 9: Performed on 100 tests, 99% (99.0%) suitability, 0.17% mean score error. Run 10: Performed on 100 tests, 98% (98.0%) suitability, 0.16% mean score error. Here, the average percentage of the number of times the LPHDR operation found the closest example (ultimately DP) (After corrections were made) = 99.70% The average score error when comparing LPHDR calculation with DP is 0.12%.

[0096] In this result, the average percentage of compatibility was 99.7%, which was slightly worse than the "fp + noise" format.

[0097] The accuracy demonstrated by the enhanced nearest neighbor search algorithm using two forms of LPHDR calculation was astonishing. Performing numerous calculations sequentially with an error of 1% and deriving the final result with an error of less than 1% is unprecedented in previous experience. Nevertheless, it demonstrated the efficiency of LPHDR calculation. In applications where the calculation method of finding the closest neighbor is effective, the accuracy obtained was sufficiently high and useful.

[0098] As an extreme case, we evaluated a modified version of the "fp + noise" format. In this case, the noise is designed to smoothly change between +10% and -5%. Therefore, Each calculation yields results ranging from a very large 10% to a very small 5%. The enhanced nearest neighbor search algorithm described above was executed. In each calculation, 100,000 Example vectors were generated. As a result, the following was obtained: Even under extreme conditions such as uncertainty, the presence of noise, and non-zero mean LPHDR calculations, it is useful. We obtained the astonishing result that such results can be achieved. Run 1: Performed on 100 tests, 97% (97.0%) conforming. Run 2: Performed on 100 tests, 100% (100.0%) compliance achieved. Run 3: Performed on 100 tests, 100% (100.0%) compliance achieved. Run 4: Performed on 100 tests, 98% (98.0%) conforming. Run 5: Performed on 100 tests, 98% (98.0%) conforming. Run 6: Performed on 100 tests, 99% (99.0%) conforming. Run 7: Performed on 100 tests, 99% (99.0%) conforming. Run 8: Performed on 100 tests, 99% (99.0%) conforming. Run 9: Performed on 100 tests, 99% (99.0%) conforming. Run 10: Performed on 100 tests, 99% (99.0%) conforming. Here, the average percentage of the number of times the LPHDR operation found the closest example (ultimately DP) (After corrections were made) = 98.80%

[0099] efficiency Given the remarkably accurate results, it is clear to anyone with ordinary knowledge in this field that the computation model presented here efficiently performed calculations using an enhanced nearest neighbor search algorithm. Here, the machine's computation / memory The units are connected in a two-dimensional physical arrangement and use only local communication between processing elements (PEs). However, this is not intended to use a narrow bandwidth on the host machine to perform useful tasks and keep the machine in use.

[0100] When a nearest neighbor search is performed on a single Test, the Test passes through all processing elements (PEs) in the array. As mentioned above, if the array is an MxM grid, at least O(M) steps of computation are performed on the Test for it to pass through the machine and return the result to the host machine. During this time, the machine performs O(MxM) steps of computation to calculate the distance to the nearest neighbor. However, since the machine has the capacity to perform O(MxM) steps of computation at each step, the O(M) step factor is lost.

[0101] Compared to serial-type machines, such machines can be sped up, and the O(M) step factor becomes important and useful. Moreover, efficiency is further increased. If a sufficiently large number of Test vectors, so-called O(M) steps, or even more Test vectors, need to be processed, they flow into the machine, forming a pipeline-like flow. The time it takes to process an O(M) step Test remains O(M) step, the same as the time it takes to process a single Test. However, the machine now performs O(M) x O(MxM) step distance calculations, and as a result, with a constant factor However, this will utilize the entire computing power of the machine.

[0102] The machine becomes particularly efficient if it processes the same number of Test vectors as the square root of the number of processing elements (PEs). There are applications that fit this form well. As such an application, the closest to each Example in the set of Examples is Similar to problems involving finding neighbors, there are also problems involving pattern recognition and compressing a large number of independent tests (e.g., blocks of images, parts of files, independent stock price histories, etc.). As stated above, what is said here is contrary to the viewpoint of those skilled in the art, and machines with a very large number of processing elements on a single chip, or anything similar, are not useful. Application 2: Distance-weighted scoring

[0103] A task related to the nearest neighbor search problem is distance-weighted scoring. In this task, each Example has an associated score, which is a numerical value that characterizes the Example in one way or another. For example, if the Examples are extracted stock price history for a given stock, the score might be a historical indication of whether the stock price is likely to rise or fall. Given a Test vector, the task is to calculate the weighted sum of the scores for all Examples, where the weights are a decreasing function of the distance from Test to each Example. For example, this weighted score might be treated as a prediction of the future stock price of the stock whose history is represented by Test. By applying embodiments of the present invention in this way, it may be possible to support, for example, high-speed stock trading as performed by quantitative hedge funds. This contradicts the view of those skilled in the art that low-precision calculations are not effective for applications in the financial field.

[0104] The C code described above calculates a weighted score along with the nearest neighbor search. In this calculation, the score assigned to Examples is drawn from the range [0, 1]. These are random numbers. The weight for each Example in this calculation is defined as the denormalized weight for the Example divided by the sum of the denormalized weights for all Examples. Furthermore, the denormalized weight for each Example is defined as the reciprocal of the sum of the squared distance plus 1 from the Example to the Test vector. As mentioned above, the C code is multi Perform numerical calculations, derive many examples and tests in those calculations, and then, "fp+ Results calculated using the "noise" and "lns" formats versus conventional floating-point calculations The results were compared with the calculation results.

[0105] Referring again to the output results of the simulation described above, the format is "fp + noise". The average weighted score in the LPHDR calculation was within 0.85% of the corrected value and never exceeded 1%. In calculations using the "lns" format, the error was very small. The average error was exactly 0.12%.

[0106] These results are surprising, and the calculation of the weighted score involves each Example This indicates that the sum of the individual weighted scores involved is included. Since a million examples are processed in each calculation, this means the sum was a small positive value of more than a million. A simplified method of calculating the sum of a million small values ​​with an error of about 1% in each addition will produce a result that contains noise due to approximation. However, this C code is based on Kahan, William (January 1965), "truncating". "Points to note when reducing errors" Invented by ACM8(1) Communication:40), This method calculates the sum using a previously known technique. This technique allows for long sums, which can be used in areas such as calculating distance weighting scores, financial engineering such as calculating the price of derivative securities using the Monte Carlo method, or when performing deconvolution in the image processing algorithm described below.

[0107] The efficiency of this algorithm is similar to that of the neural network algorithm, as mentioned earlier. The machine performs the task particularly efficiently when many test vectors are processed at once. Application 3: Removing blur caused by image motion

[0108] To gather enough light to form an image, cameras are often left with the shutter open for extended periods, which can cause blurring due to camera movement. Aside from mobile cameras mounted on satellites and aircraft, this kind of "blurring" can occur in inexpensive consumer cameras as well as very expensive cameras, as it results from camera shake. If the camera's movement path is known (or can be calculated) If possible, the "blur" can be removed using various "blur" removal algorithms. This can be effectively eliminated. One such algorithm is the Richardson-Lucy method (referred to as the "RL method"). Here, we demonstrate that embodiments of the present invention can implement the algorithm according to the Richardson-Lucy method and derive useful results. Following the description of the algorithm format described above, we will discuss the criteria for accuracy and efficiency.

[0109] algorithm The Richardson-Lucy method is a well-known and widely used algorithm. This method assumes that the image is blurred by a known kernel. In particular, it assumes that this kernel is a straight line and that the image is oriented such that the "blurring" occurs purely horizontally. The Jth pixel in each column of the blurred image A specific kernel for Xel corresponds to pixels J through J+31 of the unblurred image. We consider this to be a uniformly weighted average value.

[0110] accuracy A simple version of the RL method using LPHDR calculations, written in the C programming language. The calculation was performed. This program read a test image, blurred the image using the kernel described above, and then deblurred the image using either the "fp + noise" or "lns" calculation method. The sum was calculated using the RL method algorithm, similar to how the kernel is convolved (integrated) with the current approximate values ​​of the deblurred image. In performing this calculation, as mentioned earlier, Kahan's We used the method to calculate the sum of these values. Figure 7 shows the original test image. This shows the state. This test image is a satellite image of the building used for Barack Obama's inauguration. Figure 8 shows the image that has been extremely blurred by the kernel. Therefore, it is impossible to distinguish any specific object from this image. Figure 9 Figure 10 shows the result of deblurring using standard floating-point arithmetic. Figure 10 shows the result of deblurring using the "fp + noise" type of calculation. Figure 11 shows the result of deblurring using the "lns" format operation. In all these cases, the images were re-saved in a state where buildings, roads, parking lots, and cars could be identified.

[0111] In addition to displaying images for human visual evaluation, numerical characteristic values ​​related to the deblurring performance were calculated. This calculation involved determining the average difference between the original pixel value (a grayscale value from 0 to 255) and the corresponding pixel value in the image reproduced by the RL method algorithm for every pixel in the image. The resulting numerical characteristic values ​​are shown in Table 1 below.

[0112] [Table 1]

[0113] Based on these results and subjective but important human judgment, LHDR calculation This demonstrates that more substantial and useful de-blurring is possible compared to calculations using standard floating-point numbers. Furthermore, this example shows the de-blurring visualization using LPHDR calculations. To better convey its impact and concept, an extremely blurred image was chosen. With a milder, more typical kernel blur, the resulting blurred image would be closer to the original image than the image in this case, and the kernel length would be reduced. The RL method algorithm using LPHDR calculations would then be applied to such an image. By doing so, it becomes possible to view it as something more commonplace.

[0114] efficiency The Richardson-Lucy method, which uses local kernels, performs only local computations. This is self-evident to those skilled in the art. The image to be deblurred can be loaded into an array of processing elements (PEs), with one or more pixels stored in each processing element (PE), and the deconvolution process using the RL method algorithm can be repeated tens or hundreds of times. The deblurred image is then returned to the host processor and loaded. The machine can be used efficiently as long as the iterations are long enough.

[0115] As an extreme form of image blur removal, there is computer tomography (computed tomography). There is an iterative reconstruction method used for shadows, which reconstructs a 3D stereoscopic image from a 2D projected image. This requires an extremely large amount of computational work. The method described above is essentially generalizable to iterative recovery methods and will result in efficient use of the machine.

[0116] The advantages of the embodiments of the present invention include one or more of the following:

[0117] The processing elements (PEs) executed by one embodiment of the present invention are relatively small in terms of the number of processing elements (PEs) that can perform calculations. This is because the unit resources (e.g., transitions) This means that there are many processing elements (PEs) per unit (star, area, volume, etc.), and this means that the computational power required for operations per unit resource is very large. This makes it possible to solve larger problems with a given range of resources compared to conventional computer designs. For example, in a digital embodiment of the present invention, built as a large silicon chip assembled with the latest technology, one cycle Tens of thousands of calculations can be performed per cycle. In contrast, conventional GPUs can only perform a few hundred calculations per cycle, and conventional multi-core CPUs can only perform a very small number of calculations per cycle. This ratio of calculations is reflected in the architectural advantages of the embodiment of the present invention. It will continue to exist as an assembly technology that is being continuously improved, even though we have reached nanotechnology or computation execution technology using both digital and analog methods.

[0118] Generally, performing calculations with fewer resources, and as clearly shown in the embodiments, means that the power used for the calculations is low. As a result, the machines running according to the embodiments of the present invention have reasonable power consumption (e.g., tens of watts). (In a small amount) it exhibits extremely high performance or uses very little power (for example, a fraction of the power) It can be said that it exhibits high performance with (power). This means that such an embodiment is super This means the system is suitable for the full range of computers, from PCs to desktop computers and mobile computers. Similarly, since cost is generally related to the amount of resources available, embodiments of the present invention are able to provide a relatively large amount of computing power per unit cost compared to conventional computer devices.

[0119] The SIMD architecture is quite old and has been abandoned by those skilled in the art as a means of computer design. However, SIMD architectures can be useful if they maintain essential functions such as general computing power, and if the processing elements of a SIMD machine can be made particularly small. The example presented here possesses precisely these qualities.

[0120] Despite the common view that large-scale LPHDR calculations are not useful, The discovery that LPHDR calculations are useful as a very general computational framework is simple This can be effectively utilized not only in SIMD machine implementations but also in any parallel processing machine (whether large or small). Large-scale LPHDR calculations can be performed using FPGAs, FPAAs, GPU / SIMT machines, and with limited resources (such as transistors and volume), to perform massive calculations. It can be used on any type of machine with compact processing elements to perform the operation.

[0121] Another advantage of the embodiments of the present invention is that they are useful not because they can perform calculations efficiently in general, but because they can be used to address various practical problems where high-precision computational elements are generally considered necessary. Embodiments of the present invention may have only low-precision computational elements (or the majority of computational elements may be Even if the accuracy is low, the above can be said. Now, regarding the practical problems While we have described several examples and successfully performed calculations of uncoupled force fields in molecular dynamics simulations and other tasks, these are merely illustrative and do not limit the scope of real-world problems that can be solved by using embodiments of the present invention.

[0122] The embodiments disclosed herein are merely illustrative and do not limit the present invention. Rather, embodiments of the present invention can be carried out in various other ways, as shown below.

[0123] For example, embodiments of the present invention can display values ​​using digital or analog formats, and in any of the following ways: fixed-point, logarithmic, or floating-point representation, voltage, current, charge, pulse width, pulse density, frequency, probability, spike, timing, or a combination thereof. Such inherent display methods can be used individually or in combination to represent the LPHDR value. The LPHDR calculation circuit can use various digital methods (parallel or serial, or pipelined or otherwise) In various methods such as squid, or analog methods, or combinations thereof It can be carried out by one of the following methods. The calculation elements are the four nearest neighbors, and the nearest neighbors. There were eight touching stones of various types, some arranged in a stepping stone pattern, while others were triangular or grid-like. Various connection architectures can be used to connect them, such as in architectures like the one shown. Any method can be used to communicate between computing elements, such as using parallel or serial, digital or analog, or a combination of these modes. Computing elements can process synchronously or asynchronously, and process simultaneously or not simultaneously as a whole. Computing elements can be executed on a single physical device, such as a silicon chip, or on multiple scattered devices. And in embodiments built from multiple devices, the computing elements are connected in various ways, such as grid, truss, hypercube, tree, or other methods. Computing elements can be connected to host machines in various ways, if any, based on cost, bandwidth, and other requirements for a particular embodiment. For example, there are many host machines connected to a collection of computing elements.

[0124] While some embodiments of the present invention are described as being implemented as a SIMD architecture, this is merely illustrative and does not limit the invention to this. For example, embodiments of the present invention can also be implemented as a reconfigurable architecture, such as a programmable logic device, a field-programmable analog array, or a field-programmable gate array architecture (but not limited to these). The field-programmable gate array architecture may be designed such that the existing multiplier blocks of the FPGA are replaced or complemented by any of the LPHDR arithmetic elements disclosed herein. Alternatively, the LPHDR computation element may be included in a new or existing reconfigurable device. There are designs that allow for this. As another example, embodiments of the present invention can be implemented as a GPU or SIMT architecture. And this architecture includes, One of the LPHDR computation elements disclosed here is incorporated. For example, In the design of existing or new graphics processing units, conventional computational elements can be replaced or complemented by LPHDR computational elements. In another example, embodiments of the present invention can also be implemented as a MIMD-type architecture, which incorporates any of the LPHDR computation elements disclosed herein. For example, current or new MIMD composites In the design of computer systems, conventional computational elements are replaced with LPHDR computational elements. They can be replaced or complemented. Furthermore, in another example, embodiments of the present invention can also be run as any type of machine, including a large-scale parallel processing machine. Furthermore, this large-scale parallel processing machine uses compact computing elements to provide a large amount of computing power using fewer resources (such as transistors, area, and volume) compared to conventional architectures.

[0125] Here, we have described certain embodiments of the present invention that execute software, but these are merely illustrative and do not limit the present invention. Furthermore, for example, embodiments of the present invention may control any of the types of LPHDR computation elements disclosed herein. It can be executed using microcode, hardware sequencers, state machines, or other controllers. Furthermore, for example, embodiments of the present invention may use hardwired to control any of the LPHDR computation elements disclosed herein. , can be executed using a pre-programmed or burned-in controller. It is possible.

[0126] While certain embodiments of the present invention have been described as being executed using custom silicon as hardware, this is merely illustrative and does not limit the invention. Furthermore, embodiments of the present invention can be executed using FPGAs or other reconfigurable chips as intrinsic hardware. The reconfigurable chip is configured to perform the LPHDR processing disclosed herein. As another example, embodiments of the present invention are programmable and include conventional digital or analog computing architectures (including those using high-precision computing elements, those using other types of non-LPHDR hardware for LPHDR calculations, and those performing large-scale parallel processing). It can be executed using (which is currently available). And this architecture is here It is programmed with software to perform the LPHDR processing disclosed in [the document]. Embodiments of the present invention can be executed using a software emulator of the functions disclosed herein.

[0127] As yet another example, embodiments of the present invention can be carried out using 3D assembly techniques, whether based on silicon chips or other technologies. In some of the exemplary embodiments, one memory chip is connected to a processor or another device. A dolphin, or several memory chips and / or processor chips, or the Other device chips are stacked and connected to each other. The embodiment employing the 3D technology of the present invention is more densely packed than the embodiment employing 2D technology, and is very useful because it enables 3D information communication between processor units. Furthermore, the embodiment employing this 3D technology can be executed more efficiently than the embodiment employing 2D technology. It is what makes algorithms possible.

[0128] In one embodiment of the present invention, it has been described as being carried out using silicon chip assembly techniques, but this is merely illustrative and does not limit the present invention. Furthermore, embodiments of the present invention can be carried out by techniques using other types of conventional digital and analog computer processors and other devices. Examples of such techniques include various nanomechanical and nanoelectronic technologies, chemical-based technologies such as DNA computing, nanowires and nanotubes. This includes technologies based on transistors, optical technology, mechanical technology, biological technology, and other technologies, whether or not they are transistor-based, which have the potential to perform the types of LPHDR calculations disclosed herein. It possesses this characteristic.

[0129] In some embodiments of the present invention, we have described an embodiment that uses "large-scale parallelism" technology. In some embodiments of the present invention, thousands, millions, or more computing units are included, but embodiments of the present invention can also include only a few (very few) computing units. For example, an embodiment including only a single LPHDR unit can be small and inexpensive. This provides the power to perform large amounts of LPHDR processing on processors and other devices. Therefore, it can be used in serial processing units or other devices.

[0130] In some embodiments of the present invention, even when performed using only digital techniques, the calculations do not necessarily produce a deterministic, repeatable, or most accurate result in a selected low-precision display scheme. For example, for a given input value, the calculations may produce a result that is not the closest to the true calculation result in a selected display scheme.

[0131] The degree of precision of the "low-precision high dynamic range" calculation element varies depending on the individual implementation. For example, in one embodiment, the LPHDR calculation element produces results containing decimals, i.e., numbers greater than 0 and less than 1. For example, in one embodiment, the LPHDR calculation element often (or always) produces results that are more than 0.05% away from the correct result. (That is, the absolute value of the difference between the result produced by the LPHDR calculation element and the correct result is positive.) (It must not exceed 1 / 20th of 1% of the absolute value of the result.) In another example, the LPHDR calculation element often (or always) results in the correct outcome. This produces results that are more than 0.1% different. In another example, the LPHDR calculation element often (or always) results in the correct outcome. This produces results that are more than 0.2% different. Furthermore, in another example, the LPHDR calculation element often (or always) produces the correct result. This produces results that are more than 0.5% different from the target. Furthermore, in another example, the LPHDR calculation element often (or always) produces the correct result. This produces results that are 1%, 2%, 5%, 10%, or 20% or more away from the target.

[0132] The degree of accuracy can take on various values, but in addition to this, LPHDR calculation is required. The execution of the operation changes depending on the dynamic range of the numerical space that the element processes. For example, in one embodiment, the LPHDR operation element processes numbers in a space with a range of approximately 1 / 1,000,000 to 1,000,000. In another example, in one embodiment, the LPHDR operation The elements process numbers in a range space that has a range of approximately 1 in 1 billion to 1 billion. Do so. As yet another example, in one embodiment, the LPHDR arithmetic element processes numerical values in a range space having a range from approximately 1 / 65,000 to 65,000. As yet another example, in one embodiment, the LPHDR arithmetic element processes numerical values in a range space having a range from a specific value between 0 and 1 / 65,000 to a specific value greater than 65,000. As yet another example, in another embodiment, the LPHDR arithmetic element can process numerical values in a dynamic range within or a combination of the ranges shown in the foregoing examples, for example, a range from approximately 1 / 1,000,000,000 to 10,000,000. Similar to another embodiment, in all of these embodiments exemplified as the present invention, the numerical values under discussion are signed, and the above discussion concerns the characteristics of the absolute values of the numerical values to be handled. to a specific value greater than 65,000. As yet another example, in another embodiment, the LPHDR arithmetic element, which is another embodiment, processes numerical values in a range space having a range within or a combination of the ranges shown in the foregoing examples. For example, a dynamic range, for example, a range from approximately 1 / 1,000,000,000 to 10,000,000. In a space with a range. Numerical values can be processed. Another Similar to the embodiment, in all of these embodiments exemplified as the present invention, the numerical values under discussion are signed, and the above discussion concerns the characteristics of the absolute values of the numerical values to be handled.

[0133] The frequency of the LPHDR arithmetic element that can only produce an approximation to the correct result varies depending on the type of operation being performed. For example, in an embodiment where the LPHDR arithmetic element is capable of performing one or more processes (presumably, for example, processes including trigonometric functions), in each process, each of the LPHDR arithmetic elements receives a set of inputs taken from the range of valid numerical values, and for a specific set of input values, the LPHDR arithmetic element produces one or more output values (for example, in a case where both the sine and cosine of the input value are calculated simultaneously), and consider the case where the output values produced for a specific set of input values are deterministic or non-deterministic. In an embodiment of such an example, further consider the ratio F of the magnitude E of the relative error to the valid input. And thereby, the result calculated by the LPHDR arithmetic element is different from the mathematically correct result from the range of valid numerical values, and for a specific set of input values, the LPHDR arithmetic element produces one or more output values (for example, in a case where both the sine and cosine of the input value are calculated simultaneously), and consider the case where the output values produced for a specific set of input values are deterministic or non-deterministic. from the range of valid numerical values, and for a specific set of input values, the LPHDR arithmetic element produces one or more output values (for example, in a case where both the sine and cosine of the input value are calculated simultaneously), and consider the case where the output values produced for a specific set of input values are deterministic or non-deterministic. or more output values (for example, in a case where both the sine and cosine of the input value are calculated simultaneously), and consider the case where the output values produced for a specific set of input values are deterministic or non-deterministic. or more output values (for example, in a case where both the sine and cosine of the input value are calculated simultaneously), and consider the case where the output values produced for a specific set of input values are deterministic or non-deterministic. or more output values (for example, in a case where both the sine and cosine of the input value are calculated simultaneously), and consider the case where the output values produced for a specific set of input values are deterministic or non-deterministic. This is the case. In one embodiment of the present invention, each of the LPHDR calculation elements relates to at least one process that the LPHDR calculation unit can perform, and the permissible process is With respect to at least the ratio F of valid inputs, at least one is produced by the process With respect to the output signal, the statistical average obtained over the entire series of iteratively performed operations, which is obtained by the output signal of the LPHDR arithmetic unit when the processing was performed on each individual input. The statistical mean of the expressed values ​​differs from the correct mathematical calculation result for the same input values ​​by at least E, where F is 1% and E is 0.05%. In some other embodiments, F is not 1% but one of 2%, or 5%, or 10%, or 20%, or 50%. In each of these embodiments, we take some specific value for F, and the value of E is not 0.05% but 0.1%, or 0.2%, or 0.5%, or 1%, or 2%. Other examples exist with E values ​​of %, 5%, 10%, or 20%. These various embodiments are merely illustrative and do not limit the present invention.

[0134] A device (a computer, a processor, or the same) that is embodied by the present invention In other devices (such as computers, processors, or other devices), the number of LPHDR computation elements within the device is different from conventional precision (i.e., 32 bits). (or floating-point operations with word lengths of more bits than that) in high dynamic range The number of computational elements in the device designed to perform the calculation exceeds (which may be zero). Let NL be the total number of LPHDR computational elements in the device, and NH be the number of high precision computational elements in the device. If NL is the total number of computational elements in a device designed to perform dynamic range calculations, then NL exceeds T(NH), where T() represents a function. Any of various functions can be used as the function T(). For example, in one embodiment... So, T(NH) is 20 + 3xNH, and the number of LPHDR computation elements in the device is, if the device performs If there were arithmetic elements, it would exceed 20 + 3 x [number of arithmetic elements in the device]. Here, The device is designed to perform high dynamic range calculations with conventional precision. Also, as another example, in one embodiment, the LPHDR calculation element within the device The number would be 50 + 5 x [number of arithmetic elements in the device], if there were arithmetic elements within the device. This exceeds [value]. Here, this device is designed to perform high dynamic range calculations with conventional precision. Also, as another example, in one embodiment, the number of LPHDR calculation elements in the device exceeds 100 + 5 x [number of calculation elements in the device] if there were calculation elements in the device. Here, this device performs high dynamic range calculations with conventional precision. It is designed to perform dynamic range calculations. Also, as another example, in one embodiment, the number of LPHDR calculation elements in the device is, if there are calculation elements in the device If so, it would exceed 1000 + 5x [number of computational elements in the device]. Here, this device The device is designed to perform high dynamic range calculations with conventional precision. As another example, in one embodiment, the number of LPHDR calculation elements within the device is: If there were computing elements within the device, it would exceed 5000 + 5 x [number of computing elements within the device] Here, the device is designed to perform high dynamic range calculations with conventional precision. Some embodiments of the present invention, but are not limited thereto, are designed to run within a single physical device such as a silicon chip, or stacked chips, or a chip package, or a circuit board. Furthermore, the number NL of LPHDR computation elements in the physical device, and the conventional in the physical device The number NH of computational elements designed to perform high-dynamic-range calculations with precision is equal to the total number of individual computational elements in the physical device. One embodiment of the present invention is It runs within a computer system that includes one or more physical devices. Such physical devices include, but are not limited to, silicon chips, or stacked chips, or chip packages, or assemblies of circuit boards, which are coupled to one another by various means (buses, switches, or any kind of network). These are devices that communicate with each other using a web connection or other means of communication. There is. And in this case, the number NL of LPHDR calculation elements in the computer system, and the calculation of high dynamic range with conventional precision in the computer system The number NH of arithmetic elements designed to perform calculations is equal to the total number of individual arithmetic elements in all these connected physical devices.

[0135] One embodiment of the present invention can constitute a processor or part of a processor. This processor is a device capable of running software for performing calculations. Such a processor includes a mechanism for storing software, a mechanism for using software to determine which operations to perform, a mechanism for performing these operations, a mechanism for storing large amounts of data, a mechanism for modifying data with software that performs specific operations, and a mechanism for communicating with devices connected to the processor. The processor may be a reconfigurable device, such as a field-programmable array, but is not limited thereto. The processor may be a coprocessor to assist a host machine, or it may have the ability to perform calculations independently of an external host machine. The processor may be a CPU, GPU, FPGA, or its It may also be formed as a collection of various types of host processor and coprocessor components, such as other processors and other devices. This is referred to as a processor design for a heterogeneous environment, or a computer system for a heterogeneous environment, and some or all of these components are the same as or variations thereof in the embodiments of the present invention.

[0136] However, embodiments of the present invention can be implemented in devices added to a processor or in devices other than a processor. For example, a computer including a processor and other components (such as memory connected to the processor by a data path) is an example of an embodiment of the present invention. Here, the processor includes components for performing LPHDR processing by any of the methods disclosed herein. More generally, any device or combination of devices that perform the functions disclosed herein, regardless of whether or not they fall within the category of a processor, constitutes an example of an embodiment of the present invention.

[0137] More generally, any of the technologies disclosed herein are performed, for example, by hardware, software or firmware reliably stored on a computer-readable medium, or a combination thereof. The technologies described herein can be performed by one or more computer programs running on a programmable computer having a processor, a processor-readable storage medium (including, for example, volatile or non-volatile memory and / or storage elements), at least one input device, and at least one output device. The program code is input using the input device to perform the functions described above and produce an output. The output is supplied to one or more output devices.

[0138] Each computer program that falls within the scope of the claims described later may be executed in any programming language, such as assembly language, machine language, high-level procedural programming language, or object-oriented language. This is possible. For example, a programming language is compiled and interpreted.

[0139] Each of these computer programs is executed in the form of a computer program product reliably embodied in a machine-readable storage device for execution by a computer processor. The method of this invention is executed by a computer processor that runs a program reliably embodied in a computer-readable storage medium to perform the function of the invention by processing input and producing output. Suitable processors include, for example, both general-purpose and special-purpose microprocessors. Generally, this processor receives instructions and data from read-only memory and / or random-access memory. Suitable memory devices for reliably realizing computer program instructions include, for example, semiconductor memory devices including EPROM and EEPROM, and flash memory devices. Magnetic disks such as internal hard drives and removable disks, optical-magnetic disks There are all types of non-volatile memory, such as disks and CR-ROMs. All of these can be captured and executed by specially designed ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays). Furthermore, computers generally receive programs and data from storage media such as internal hard disks (not shown) or removable disks. These elements are found in conventional desktop and workstation computers, and in other computers suitable for running computer programs that perform the methods described herein. These elements are used in conjunction with digital print engines and marking engines, display monitors, and other raster output devices that have the capability to output color or grayscale pixels onto paper, film, display screens, or other output media.

Claims

[Claim 1] Multiple low-precision high dynamic range (LPHDR) calculation execution units, At least one high-precision calculation execution unit, wherein the precision of the calculation performed by the at least one high-precision calculation execution unit is higher than the precision of the calculation performed by the plurality of LPHDR calculation execution units, The system comprises the plurality of LPHDR calculation execution units and means for controlling the at least one high-precision calculation execution unit to perform the method, The aforementioned method, The system receives multiple example vectors and one test vector as input, The storage of the aforementioned multiple example vectors, Using the aforementioned multiple LPHDR calculation execution units, Among the plurality of example vectors, identify the first example vector that is closest to the one test vector. The identifier of the first example vector is stored, Among the plurality of example vectors, identify the second example vector that is second closest to the first test vector. The identifier of the second example vector is stored, Using the aforementioned at least one high-precision calculation execution unit, The first distance between the test vector and the first example vector is calculated. The second distance between the test vector and the second example vector is calculated. The smaller of the first distance and the second distance is identified. From the first example vector and the second example vector, identify the example vector associated with the smaller of the first distance and the second distance. This includes outputting the example vector associated with the smaller of the first distance and the second distance, device.

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