Semiconductor equipment

Abstract

One of the objectives is to provide a semiconductor device with a novel structure. [Solution] A channel formation region provided on a substrate containing a semiconductor material, and the channel formation region An impurity region is provided so as to sandwich the channel, and a first gate insulating layer is provided on the channel formation region. A first gate electrode on the gate insulating layer of 1, and a first source electrically connected to the impurity region. A first transistor having an electrode and a first drain electrode, and a base containing a semiconductor material A second gate electrode on the board, a second gate insulating layer on the second gate electrode, and a second gate An oxide semiconductor layer on an insulating layer, and a second source electrode electrically connected to the oxide semiconductor layer. A semiconductor device having a second transistor having a second drain electrode.

Description

[Technical Field]

[0001] The technical field of the invention relates to a semiconductor device and a method for manufacturing the same. Here, a semiconductor device is: This term refers to all elements and devices that function by utilizing semiconductor properties. [Background technology]

[0002] Metal oxides exist in diverse forms and are used in a variety of applications. Indium oxide is well known. It is a material that has been developed and is used as a material for transparent electrodes required for liquid crystal display devices and the like. ru.

[0003] Some metal oxides exhibit semiconductor properties. For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, and so on. Thin-film transistors using metal oxides in the channel formation region are already known (for example) , Patent Documents 1 to 4, Non-Patent Document 1, etc.).

[0004] By the way, metal oxides include not only monocrystalline oxides but also multicrystalline oxides. For example... InGaO3(ZnO) has a homologous phase. m (m: natural number) is In, Ga and It is known as a multi-component oxide semiconductor having Zn (for example, Non-Patent Documents 2 to Non-Patent Documents 2 to 2). (See patent document 4, etc.).

[0005] Furthermore, oxide semiconductors composed of In-Ga-Zn oxides as described above are also thin-film transistors. It has been confirmed that it is applicable to the channel formation region of an inverter (for example, patent document). 5. See Non-Patent Documents 5 and 6, etc. [Prior art documents] [Patent Documents]

[0006] [License 1] Special Announcement No. 60-198861 [License 2] Special Announcement No. 8-264794 [License 3] Special Notice No. 11-505377 [License 4] Special Announcement No. 2000-150900 [Patent Document 5] Special Announcement No. 2004-103957 [Non-licensed literature]

[0007] [Non-licensed Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-licensed Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Masaki Nakamura, Noboru Kimizuka, Naohiko Mohri, and Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: natural number) and its Isomorphic Compounds," Solid State Physics, 1993, Vol.28, No.5, pp.317-327. [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] By the way, field-effect transistors, a typical example of semiconductor devices, use materials such as silicon. It is generally configured by. However, a semiconductor device using silicon or the like as a material does not have sufficiently high switching characteristics. For example, in the case of constructing a CMOS inverter circuit and the like, there has been a problem that the semiconductor device is destroyed by a very large through-current. There has also been a problem that the power consumption increases due to the through-current. .

[0009] In addition, in a semiconductor device using silicon or the like as a material, the off-current (also called leakage current or the like) is not small enough to be substantially zero. Therefore, a small current flows regardless of the operation of the semiconductor device, and when constructing a charge-holding type semiconductor device such as a memory device or a liquid crystal display device, it has been difficult to secure a sufficient charge-holding period. There has also been a problem that the power consumption of the semiconductor device increases due to the off-current.

[0010] Therefore, one aspect of the disclosed invention aims to provide a semiconductor device with a new structure that solves the above problems.

Means for Solving the Problems

[0011] One aspect of the present invention relates to a semiconductor device having a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using other materials. For example, the following configuration can be adopted.

[0012] One aspect of the present invention is a channel formation region provided on a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel formation region, and a first gate insulating layer on the channel formation region And, the first gate electrode on the first gate insulating layer and the first which is electrically connected to the impurity region A first transistor having a source electrode and a first drain electrode, and a semiconductor material A second gate electrode on the substrate, a second gate insulating layer on the second gate electrode, and a second An oxide semiconductor layer on the gate insulating layer, and a second source power that is electrically connected to the oxide semiconductor layer. A semiconductor device having a second transistor having a pole and a second drain electrode, be.

[0013] In the above, the first gate electrode and the second gate electrode are electrically connected, and the first A source electrode or a first drain electrode, and a second source electrode or a second drain electrode It is preferable that they are electrically connected. Also, the first transistor is a p-type transistor. The first transistor is a zista (p-channel type transistor), and the second transistor is an n-type transistor. (An n-channel transistor) is preferable.

[0014] Furthermore, in the above, the first gate electrode and the second source electrode or the second drain electrode Preferably, they are electrically connected.

[0015] Furthermore, in the above, the substrate containing the semiconductor material may be a single-crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate. In particular, silicon is preferred as the semiconductor material.

[0016] Furthermore, in the above, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor material. It is preferable that it contains. In particular, the oxide semiconductor layer contains crystals of In2Ga2ZnO7. It is preferable that it contains. Furthermore, the hydrogen concentration of the oxide semiconductor layer is 5 × 10 19 ato ms / cm 3 The following is preferable. Also, the off-current of the second transistor is 1 × 10 -13 It is preferable to set it to A or less.

[0017] In the above, the second transistor is provided in a region that overlaps with the first transistor. It can be configured as follows.

[0018] Furthermore, the first source electrode or the first drain electrode and the second source electrode or the second drain The rain electrode may be formed integrally with the second source electrode. In this configuration, a portion of the second drain electrode functions as either the first source electrode or the first drain electrode. It may also be a part of the first source electrode or the first drain electrode, or the second It may also function as a source electrode or a second drain electrode.

[0019] In this specification, the terms "above" and "below" refer to the relative position of the constituent elements, meaning "directly above". Or it does not limit to being "directly below". For example, "the first on the gate insulating layer If the expression is "gate electrode," then there are other components between the gate insulating layer and the first gate electrode. It does not exclude anything that is included. Also, the terms "upper" and "lower" are used for the sake of explanation. This is merely a generalization, and unless otherwise specified, it also includes variations where the order is reversed.

[0020] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to that. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes." This also includes cases where "or wiring" is formed as a single unit.

[0021] Furthermore, generally speaking, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, etc., a semiconductor layer made of a material other than silicon is provided on the insulating surface. It is used as a concept that also includes the substrate with the specified configuration. In other words, the semiconductor that the "SOI substrate" possesses The layer is not limited to a silicon semiconductor layer. Also, the substrate in "SOI substrate" is silicon This applies not only to semiconductor substrates such as wafers, but also to glass substrates, quartz substrates, sapphire substrates, and metal substrates. This also includes non-semiconductor substrates such as those mentioned above. In other words, semiconductors on conductive substrates or insulating substrates having insulating surfaces. The term "SOI substrate" broadly includes those having layers made of solid material. Furthermore, this specification, etc. In this context, "semiconductor substrate" refers not only to a substrate made solely of semiconductor materials, but also to a substrate made solely of semiconductor materials. This term refers to all substrates including materials. In other words, in this specification, the term "SOI substrate" is also broadly used. It is included in "semiconductor substrates". [Effects of the Invention]

[0022] In one aspect of the present invention, the lower part has a transistor made of a material other than an oxide semiconductor, and the upper A semiconductor device having a transistor made of an oxide semiconductor is provided.

[0023] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating the transistor into a single unit, it differs from transistors using oxide semiconductors. Semiconductors that require different electrical properties (for example, different carriers involved in the operation of the element) The device can be realized.

[0024] Furthermore, transistors using oxide semiconductors have good switching characteristics, so these characteristics can be utilized. Excellent semiconductor devices can be fabricated using this technology. For example, in a CMOS inverter circuit... Furthermore, because the through-current can be sufficiently suppressed, the power consumption of the semiconductor device can be reduced, and also, This can prevent the destruction of semiconductor devices by high currents. Furthermore, transistors using oxide semiconductors... Because the off-current of a zista is extremely low, using it can reduce the power consumption of semiconductor devices. This can be reduced. [Brief explanation of the drawing]

[0025] [Figure 1] Cross-sectional and plan views illustrating a semiconductor device. [Figure 2] Circuit diagram for explaining semiconductor devices [Figure 3] Cross-sectional and plan views illustrating a semiconductor device. [Figure 4] Cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 5] Cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 6] Cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 7] Cross-sectional and plan views illustrating a semiconductor device. [Figure 8] Circuit diagram for explaining semiconductor devices [Figure 9] Cross-sectional and plan views illustrating a semiconductor device. [Figure 10] Circuit diagram for explaining semiconductor devices [Figure 11] A diagram illustrating electronic devices using semiconductor devices. [Modes for carrying out the invention]

[0026] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be interpreted as being limited to the content described therein.

[0027] Furthermore, the location, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The drawings may not always represent the actual location, size, or extent. This is not limited to the location, size, scope, etc. disclosed in the documents.

[0028] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0029] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 1 through 6.

[0030] <Configuration of semiconductor device> Figure 1(A) shows a cross-sectional view of the semiconductor device according to this embodiment, and Figure 1(B) shows the cross-sectional view of the semiconductor device according to this embodiment. The plan views of the semiconductor device relating to its form are shown below. Here, Figure 1(A) is a reference to Figure 1(B). This corresponds to the cross-section along lines A1-A2 and D1-D2. (Figures 1(A) and 1(B)) The semiconductor device shown has a p-type transistor 160 at the bottom and an oxide semiconductor at the top. It has an n-type transistor 162.

[0031] The p-type transistor 160 is formed in a channel formation region provided on a substrate 100 containing semiconductor material. 116, and the impurity region 114 and high concentration provided so as to sandwich the channel-forming region 116. The degree impurity region 120 (these are collectively also simply called the impurity region) and the channel formation region A gate insulating layer 108a provided on 116, and a gate insulating layer 108a provided on the gate insulating layer 108a The electrode 110a and the impurity region 114 provided on one side of the channel formation region 116 A source electrode or drain electrode 130a electrically connected to a channel forming region 116 A source electrode or drain that is electrically connected to the impurity region 114 located on the other side. It has an electrode 130b.

[0032] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Furthermore, the substrate 100 is provided with a sidewall insulating layer 118 sandwiched between them when viewed in plan. It has a high-concentration impurity region 120, and a metal compound region 124 is located on the high-concentration impurity region 120. Furthermore, on the substrate 100, element isolation and insulation are provided so as to surround the p-type transistor 160. A layer 106 is provided, and an interlayer insulating layer 126 is provided so as to cover the p-type transistor 160. An interlayer insulating layer 128 is provided. Through the opening formed, the source electrode or drain electrode 130a enters the channel forming region 1 A metallic compound region 124 provided on one side of 16 is electrically connected to the source electrode or The drain electrode 130b is a metal compound provided on the other side of the channel forming region 116. It is electrically connected to region 124, that is, to the source electrode or drain electrode 130a. The channel is formed through a metal compound region 124 located on one side of the channel-forming region 116. A high-concentration impurity region 120 and channel formation are provided on one side of the channel formation region 116. It is electrically connected to the impurity region 114 located on one side of region 116, and to the source electrode. Alternatively, the drain electrode 130b is a metallized compound provided on the other side of the channel forming region 116. High-concentration impurity region provided on the other side of the channel-forming region 116 via the material region 124 120 and the impurity region 114 provided on the other side of the channel forming region 116 and electrical Connected.

[0033] The n-type transistor 162 has a gate electrode 136c provided on the interlayer insulating layer 128, and A gate insulating layer 138 provided on the gate electrode 136c, and provided on the gate insulating layer 138 A modified oxide semiconductor layer 140, and an oxide semiconductor layer 14 provided on the oxide semiconductor layer 140. Source electrode or drain electrode 142a electrically connected to 0, source electrode or It has a drain electrode 142b.

[0034] Here, the gate electrode 136c of the n-type transistor 162 is formed on the interlayer insulating layer 128. It is provided so as to be embedded in the insulating layer 132. Also, the gate electrode 136c and Similarly, on the source or drain electrodes 130a, 130b of the p-type transistor 160 Electrodes 136a and 136b are formed in contact with the surface.

[0035] Furthermore, on the n-type transistor 162, a portion of the oxide semiconductor layer 140 is in contact with it. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or a dot. An opening is provided that extends to the rain electrode 142a, the source electrode, or the drain electrode 142b. Through this opening, electrodes 150c and 150d are connected to the source electrode or the drain electrode. It is formed in contact with the drain electrode 142a, the source electrode or the drain electrode 142b. Also , similar to the electrode 150c and the electrode 150d, through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, the electrode 150a and the electrode 150b that are in contact with the electrode 136a and the electrode 136b are formed.

[0036] Here, it is desirable that the oxide semiconductor layer 140 is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 atoms / cm 19 atoms / cm 3 or less, desirably 5×10 18 atoms / cm 3 or less, more desirably 5×10 17 atoms / cm 3 or less. Also, by using the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified, the n-type transistor 162 can obtain extremely excellent off-current characteristics. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is in the range of -5V to -20V, the off-current is 1×10 A or less. Thus, by applying the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and reducing the off-current of the n-type transistor 162, a semiconductor device with excellent characteristics can be obtained. The hydrogen concentration in the above-mentioned oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass S pectroscopy). -13 Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and is embedded in the insulating layer 152 The hydrogen concentration is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass S pectroscopy).

[0037] Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and is embedded in the insulating layer 152 ​​​Electrodes 154a, 154b, and 154c are provided so that the electric Electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150b and electrode 150 Electrode 154c is in contact with electrode c, and electrode 154c is in contact with electrode 150d.

[0038] In other words, in the semiconductor device shown in Figure 1, the source electrode or the dot of the p-type transistor 160 Rain electrode 130b and source electrode or drain electrode 142 of n-type transistor 162 a and electrical through electrodes 136b, 150b, 154b and 150c Connected.

[0039] Also, the gate electrode 110a of the p-type transistor 160 and the gate of the n-type transistor 162 Electrode 136c also receives electricity through electrodes formed in the interlayer insulating layer 126 and interlayer insulating layer 128. They are connected electrically.

[0040] Note that the source electrode or drain electrode 130a of the p-type transistor 160 is electrode 154 a, via electrodes 150a and 136a, electrically connected to a power line supplying the first potential. It is done. Also, the source electrode or drain electrode 142b of the n-type transistor 162 is electrically It is electrically connected to the power line supplying the second potential via electrode 154c and electrode 150d. .

[0041] A CMOS transistor consisting of a p-type transistor 160 and an n-type transistor 162 connected in a complementary manner. The equivalent circuit of the circuit is shown in Figure 2. Figure 2 shows the semiconductor device shown in Figures 1(A) and 1(B). In this case, when electrode 154a is set to a positive potential VDD and electrode 154c is set to ground potential GND This is an example. Note that the negative potential VDL may be used instead of the ground potential.

[0042] Next, on the same substrate as the semiconductor device described above, an n-type transistor or a p-type transistor The configuration when using Ta alone will be explained with reference to Figure 3. Figure 3(A) shows the lower part Cross-section of p-type transistor 164 and n-type transistor 166 using an oxide semiconductor on top. Figure 3(A) is a diagram, and Figure 3(B) is its plan view. Note that Figure 3(A) is a diagram of Figure 3(B) with line B1 -This corresponds to the cross-sectional view at line B2 and line C1-C2. Also, in Figure 3, it is the same as in Figure 1. The configuration will be explained using the same reference numerals.

[0043] First, we will explain the configuration and electrical connections of the p-type transistor 164. Source electrode or drain electrode 130c of the lampistor 164, source electrode or drain Electrode 130d has an electrode 136d, which is formed to be embedded in the insulating layer 132, and electrode 1 36e is electrically connected to each other. Also, electrodes 136d and 136e are Formed to be embedded in the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer 146 The electrodes 150e and 150f are electrically connected to each other. Furthermore, electrode 1 50e, electrode 150f has electrode 154d, which is formed to be embedded in the insulating layer 152. The electrodes 154e are electrically connected. This allows the p-type transistor 1 64 source or drain electrode 130c, electrode 136d, electrode 150e, electrode 1 Electrically connected to a predetermined wiring via 54d, and to the source electrode or drain electrode 130d It is electrically connected to predetermined wiring via electrodes 136e, 150f, and 154e. Therefore, the p-type transistor 164 can be used on its own.

[0044] Next, the structure and electrical connection relationship of the n-type transistor 166 will be described. Element separation On the isolation insulating layer 106, a gate insulating layer 108b is provided. Also, on the gate insulating layer 1 08b, a gate wiring 110b is provided. An electrode 130e formed so as to be embedded in the interlayer insulating layer 126 and the interlayer insulating layer 128 is electrically connected to the gate wiring 110b. An electrode 130e is formed so as to be embedded in the insulating layer 132 The gate electrode 136f is electrically connected. Thus, the gate electrode 136f of the n-type transistor 16 6 is electrically connected to the gate wiring 110b via the electrode 130e, so that the n-type transistor 166 can be used alone.

[0045] <Method of manufacturing a semiconductor device> Next, an example of the method of manufacturing the semiconductor device will be described. Hereinafter, first, the method of manufacturing the lower p-type transistor will be described, and then, the method of manufacturing the upper n-type transistor will be described.

[0046] <Method of manufacturing a p-type transistor> First, a substrate 100 including a semiconductor material is prepared (see FIG. 4(A)). As the substrate 100 including a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, an example in the case of using a single crystal silicon substrate as the substrate 100 including a semiconductor material will be shown. In general, the "SOI substrate" refers to a substrate having a structure in which a silicon semiconductor layer is provided on an insulating surface. In this specification, etc., a silicon semiconductor layer is provided on an insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. It shall include those that have been completed.

[0047] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 4(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or similar material can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0048] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 4(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0049] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either method may be used. Note that after the formation of the semiconductor region 104, or after device isolation isolation... After the formation of the margin layer 106, the protective layer 102 is removed.

[0050] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0051] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment may be performed using, for example, He, Ar, Kr, Using noble gases such as Xe and mixed gases such as oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen This can be done. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm or more. It can be reduced to 0 nm or less.

[0052] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0053] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a. Form the gate electrode 110a (see Figure 4(C)). Note that at this time, the gate shown in Figure 3 The 110b wiring can also be formed at the same time.

[0054] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see Figure 4(C)). Then, Boron (B) or aluminum (Al) is added to the semiconductor region 104 to create a shallow junction depth. The impurity region 114 is formed (see Figure 4(C)). The area below the gate insulating layer 108a of the semiconductor region 104 becomes the channel formation region 116 (Figure See 4(C). Here, the concentration of added impurities can be set as appropriate, but for semiconductors... It is desirable to increase the concentration in accordance with the degree of miniaturization of the element. Also, here, The process involves forming an impurity region 114 after forming a marginal layer 112, but the impurity region The process may also involve forming the insulating layer 112 after forming region 114.

[0055] Next, the sidewall insulating layer 118 is formed (see Figure 4(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110a and the impurity region are removed. Expose the top surface of 114.

[0056] Next, cover the gate electrode 110a, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. Then, in the region where the insulating layer is in contact with the impurity region 114, boron (B) and aluminum (Al) are added to form a high-concentration impurity region 120 (Figure) See 4(E). Then, remove the above insulating layer, gate electrode 110a, sidewall insulating A metal layer 122 is formed to cover the marginal layer 118, the high-concentration impurity region 120, etc. (Figure 4(E) (See reference). The metal layer 122 is coated using various methods such as vapor deposition, sputtering, and spin coating. It can be formed using a film deposition method. The metal layer 122 constitutes the semiconductor region 104. It is desirable to form it using a metallic material that reacts with semiconductor materials to form a low-resistance metallic compound. Examples of such metallic materials include titanium, tantalum, tungsten, and nickel. Examples include cobalt and platinum.

[0057] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 4(F)). Furthermore, if polycrystalline silicon or the like is used as the gate electrode 110a, its metal layer 12 A metallic compound region will also be formed in the area that comes into contact with 2.

[0058] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. Because it is such that the conductivity is sufficiently increased, the metal compound region is formed By doing so, electrical resistance can be sufficiently reduced and the characteristics of the element can be improved. After forming the composite region 124, the metal layer 122 is removed.

[0059] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 4(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It may also be formed using organic insulating materials such as acrylic. Note that here, the interlayer insulating layer 126 The structure consists of a two-layer configuration with an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is not limited to this. After the formation of the interlayer insulating layer 128, its surface is smoothed by methods such as CMP or etching. It is desirable to keep it ventilated.

[0060] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening The source electrode or drain electrode 130a, the source electrode or drain electrode 130b ( Both can be called source wiring or drain wiring) forming (Figure 4(H) (See reference). Source electrode or drain electrode 130a, source electrode or drain electrode 130 b is, for example, a conductive layer formed in the region including the opening using PVD or CVD, and then e The conductive layer is formed by removing a portion of it using methods such as chipping or CMP. It is possible.

[0061] Furthermore, a portion of the above conductive layer is removed to form the source electrode or drain electrode 130a, source electrode Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. The necessary tungsten film, titanium film, titanium nitride film, etc., are removed, and the flatness of the surface is improved. This can improve the source electrode or drain electrode 130a, By planarizing the surface of the drain electrode 130b, in a later process, This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and so on.

[0062] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 a. Only the source electrode or drain electrode 130b is shown, but in this process, Wiring and other components that come into contact with the electrode 110a can be formed together. This allows for the formation of a connecting electrode 130e that contacts the gate wiring 110b shown in Figure 3. Used as a source electrode or drain electrode 130a, or a source electrode or drain electrode 130b. There are no particular limitations on the materials that can be used; various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neo Conductive materials such as magnesium and scandium can be used.

[0063] As a result, a p-type transistor is formed using a substrate 100 containing semiconductor material. After the process, wiring and other elements may be formed. The wiring structure may include an interlayer insulating layer and By adopting a multilayer wiring structure having a laminated structure of conductive layers, a highly integrated semiconductor device can be provided.

[0064] <Method for fabricating an n-type transistor> Next, a process for fabricating an n-type transistor on the interlayer insulating layer 128 will be described using FIGS. 5 and 6. In FIGS. 5 and 6, since the manufacturing process of the n-type transistor in the cross section of the line A1 - A2 and the cross section of the line D1 - D2 shown in FIG. 1 is shown, the p-type transistor formed under the n-type transistor is omitted. First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130b (see FIG. 5(A)). The insulating layer 132 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0065] Next, openings reaching the source electrode or drain electrode 130a and openings reaching the source electrode or drain electrode 130b are formed in the insulating layer 132. At this time, openings are also formed in the region where the gate electrode 136c will be formed later. Then, a conductive layer 134 is formed so as to be embedded in the above openings (see FIG. 5(B)). The above openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, dry etching

[0066] is preferably used.​​​​​​​​​​​​​ It is preferable to use a chipping method. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film deposition method. Materials that can be used to form the conductive layer 134 include It is molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as aluminum and scandium, as well as their alloys and compounds (e.g., nitrides). It can be done.

[0067] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is the lower electric Electrode (here, source electrode or drain electrode 130a, or source electrode or drain electrode) It has the function of reducing the oxide film at the interface with 130b) and reducing the contact resistance with the lower electrode. Furthermore, the titanium nitride film that is subsequently formed acts as a barrier function to suppress the diffusion of conductive materials. Prepare.

[0068] After forming the conductive layer 134, the conductive layer 134 is processed using methods such as etching and CMP. By removing a portion of it, the insulating layer 132 is exposed, and the electrodes 136a, 136b, and gate electrode are removed. Form 136c (see Figure 5(C)). Note that a portion of the conductive layer 134 is removed to form the electrode. When forming 136a, electrode 136b, and gate electrode 136c, the surfaces are made flat. It is desirable to process it in this way. Thus, insulating layer 132, electrode 136a, electrode 136b, By planarizing the surface of the gate electrode 136c, a good electrode and distribution can be achieved in subsequent processes. This makes it possible to form wires, insulating layers, semiconductor layers, and so on.

[0069] Next, cover the insulating layer 132, electrode 136a, electrode 136b, and gate electrode 136c, A gate insulating layer 138 is formed (see Figure 5(D)). The gate insulating layer 138 is formed by CVD or It can be formed using sputtering or the like. Furthermore, the gate insulating layer 138 is oxidized. Formed to contain silicon, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, etc. It is preferable to do so. The gate insulating layer 138 may be a single layer or a laminated structure. It is also possible to use silane (SiH4), oxygen, and nitrogen as raw material gases. A gate insulating layer 138 made of silicon oxide nitride can be formed by the Zuma CVD method. The thickness of the gate insulating layer 138 is not particularly limited, but for example, it is between 20 nm and 500 nm. This can be done. In the case of a laminated structure, for example, the layer thickness is 50 nm to 200 nm. A gate insulating layer 1 and a second gate insulating layer on the first gate insulating layer with a film thickness of 5 nm to 300 nm It is preferable to use a laminated structure of insulating layers.

[0070] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0071] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something desirable.

[0072] Of course, if it can form a good insulating layer as a gate insulating layer, then high-purity material Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. In addition, the film quality of the gate insulating layer and acidity can be improved by heat treatment after film formation. An insulating layer may be formed whose interface properties with the ionized semiconductor layer are modified. In any case, The film quality as an insulating layer is good, and the interface state density with the oxide semiconductor layer is reduced. Any material that can form a good interface would be fine.

[0073] Furthermore, 85℃, 2×10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, if impurities are added to the oxide semiconductor, the impurities and the oxide semiconductor... The bond with the main component is broken by a strong electric field (B: bias) and high temperature (T: temperature), and is generated. The uncoupled hands induce a shift in the threshold voltage (Vth).

[0074] In contrast, in one aspect of the disclosed invention, impurities in oxide semiconductors, particularly hydrogen and water, etc. By minimizing the risk and improving the interface characteristics with the gate insulating layer as described above, the BT test This makes it possible to obtain stable transistors even under these conditions.

[0075] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as those described above to form island-shaped oxide semiconductor layers 140. (See Figure 5(E)).

[0076] Examples of oxide semiconductor layers include In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer, particularly an amorphous oxide semiconductor layer. In this embodiment, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor target An amorphous oxide semiconductor layer will be formed using a sputtering method. By adding silicon to a crystalline oxide semiconductor layer, its crystallization can be suppressed. Therefore, for example, using a target containing 2% to 10% by weight of SiO2, A semiconductor layer may be formed.

[0077] For example, an oxide semiconductor layer can be fabricated using the sputtering method. A zinc-based oxide semiconductor film deposition target can be used. A target for oxide semiconductor film deposition containing Ga and Zn (composition ratio: In2O3:G You can also use a ratio such as a2O3:ZnO=1:1:1 (molar ratio). As a target for deposition of oxide semiconductor films containing Ga and Zn, In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1: A target having a composition ratio of 1:4 [molar ratio] may also be used. For oxide semiconductor film deposition. The target filling rate is 90% to 100%, preferably 95% to 99.9%. Yes. By using a target for oxide semiconductor film deposition with a high packing density, a dense oxide semiconductor can be formed. A conductive layer is formed.

[0078] The atmosphere for film deposition is a noble gas atmosphere (typically argon), an oxygen atmosphere, or a noble gas atmosphere. A mixed atmosphere of argon (typically) and oxygen is preferred. Specifically, for example, The concentration of impurities such as hydrogen, water, hydroxyl groups, and hydrides should be around a few ppm (preferably a few ppb). It is preferable to use a high-purity gas that has been removed to a certain degree.

[0079] During the deposition of the oxide semiconductor layer, the substrate is held in a processing chamber under reduced pressure, and the substrate temperature is maintained. The temperature should be between 100°C and 600°C, preferably between 200°C and 400°C. Heat the substrate. By depositing the film while simultaneously reducing the impurity concentration in the deposited oxide semiconductor layer, the impurity concentration in the deposited oxide semiconductor layer is reduced. This is possible. In addition, damage caused by sputtering is reduced. And the residue in the processing chamber While removing moisture, sputtered gas from which hydrogen and moisture have been removed is introduced, and metal oxides are terminate. To form an oxide semiconductor layer, adsorption is used. It is preferable to use a vacuum pump of a certain type. For example, a cryopump, ion pump, or titanium vacuum pump. It is preferable to use an exhaust pump. Also, as an exhaust means, a turbo pump A cold trap may be added to the pump. Exhaust using a cryopump. The deposition chamber is, for example, a compound containing hydrogen atoms such as water (H2O) (more Because compounds containing carbon atoms are also exhausted, the oxide semiconductor layer formed in the deposition chamber The concentration of impurities can be reduced.

[0080] Forming conditions include, for example, a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa, DC power of 0.5 kW, atmosphere is oxygen (oxygen flow rate ratio 100%). These conditions can be applied. Furthermore, when using a pulsed DC power supply, film deposition can be performed. The amount of powdery material (also called particles or dust) that is sometimes generated can be reduced, and the film thickness distribution can be made uniform. This is preferable for the following reasons. The oxide semiconductor layer is 2 nm to 200 nm, preferably 5 nm or less. The thickness should be 30 nm or less. Note that the appropriate thickness will vary depending on the oxide semiconductor material used. Therefore, the thickness should be selected appropriately depending on the material being used.

[0081] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced and plastic Reverse sputtering is performed to generate sputter, and dust adhering to the surface of the gate insulating layer 138 is removed. It is preferable to remove it. Here, reverse sputtering means that in normal sputtering, sputtering Instead of colliding ions with the target, by colliding ions with the treatment surface... This refers to a method of modifying the surface. One method involves colliding ions with the treated surface. A high-frequency voltage is applied to the processing surface in an argon atmosphere to generate plasma near the substrate. There are methods such as using a nitrogen atmosphere, helium atmosphere, or oxygen atmosphere instead of an argon atmosphere. You may also use atmosphere or other similar techniques.

[0082] The above oxide semiconductor layer can be etched using either dry etching or wet etching. You may also use this. Of course, you can also use both in combination. To create the desired shape... To enable etching, etching conditions (etching gas, etching solution, etc.) can be adjusted according to the material. Set the appropriate settings (watching time, temperature, etc.).

[0083] Examples of etching gases used in dry etching include chlorine-containing gases (chlorine-based gases). For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), and carbon tetrachloride. Fluorine (such as CCl4) can be used. In addition, fluorine-containing gases (fluorine-based gases) can be used. For example, carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluic acid. Olomethane (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), and these gases Gases to which noble gases such as lium (He) or argon (Ar) have been added may also be used.

[0084] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0085] Etching solutions used in wet etching include a solution of phosphoric acid, acetic acid, and nitric acid. You can use this. Alternatively, you may use ITO07N (manufactured by Kanto Chemical Co., Ltd.).

[0086] Next, the oxide semiconductor layer is subjected to a first heat treatment. This first heat treatment causes the oxide semiconductor layer The conductive layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 300°C. The temperature should be 750°C or lower, preferably 400°C or higher, and below the strain point of the substrate. For example, resistive heating A substrate is introduced into an electric furnace using a body, and the oxide semiconductor layer 140 is subjected to a nitrogen atmosphere 45 A heat treatment is performed at 0°C for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the atmosphere. To prevent this from happening, and to ensure that water and hydrogen are not re-introduced.

[0087] Furthermore, the heating apparatus is not limited to electric furnaces, but also includes heat conduction from a heated gas or other medium, and This may be a device that heats the object to be processed by thermal radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas contains A Inert gases such as argon or nitrogen, which do not react with the material being treated by heat treatment, are used. A gaseous substance is used.

[0088] For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is moved and placed inside, heated for several minutes, then the substrate is moved and placed in a hot inert gas chamber. GRTA treatment may be performed after the procedure. Using GRTA treatment allows for high-temperature heat treatment in a short time. This becomes possible. Also, because it is a short-duration heating process, the temperature conditions exceed the strain point of the substrate. It can also be applied.

[0089] The first heat treatment mainly uses nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to perform this in an atmosphere that is free from water, hydrogen, etc. The purity of nitrogen, or noble gases such as helium, neon, or argon, introduced into the heat treatment device. The amount is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e.) It is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less.

[0090] Furthermore, depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer It may crystallize, becoming microcrystalline or polycrystalline. For example, if the crystallization rate is 90% or higher, Alternatively, it may become an oxide semiconductor layer with more than 80% microcrystalline properties. Also, the first heat treatment procedure Depending on the material of the oxide semiconductor layer, an amorphous oxide semiconductor that does not contain crystalline components may be used. It can also form layers.

[0091] Furthermore, microcrystals (with a particle size of 1 nm or less) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer will have a mixture of elements smaller than 20 nm (typically between 2 nm and 4 nm). In some cases, this may be the case. For example, using an In-Ga-Zn-O type oxide semiconductor film deposition target. When forming an oxide semiconductor layer, an electrically anisotropic In2Ga2ZnO7 crystal is used. By providing oriented microcrystalline regions, the electrical properties of the oxide semiconductor layer can be altered. Yes, it is possible. In this way, the microcrystalline regions in which the crystal grains of In2Ga2ZnO7 are oriented are formed in an oxide semiconductor. By forming it on the surface of a layer, for example, conductivity in a direction parallel to the surface of an oxide semiconductor layer can be improved. This allows for improved insulation in the direction perpendicular to the surface of the oxide semiconductor layer. These microcrystalline regions have the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. It has the above oxide semiconductor layer, which is surface-treated by GRTA processing. It can be formed by heat. Also, the Zn content is less than the In or Ga content. By using a sputtering target, it is possible to form the material more favorably.

[0092] The first heat treatment of the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into island-shaped layers. It can also be performed on the oxide semiconductor layer before heating. In that case, after the first heat treatment, the heating device The circuit board will be removed from storage and then subjected to the photolithography process.

[0093] Furthermore, the first heat treatment described above has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. Such dehydration treatment The dehydrogenation treatment is performed by forming an oxide semiconductor layer, and then placing a source electrode on the oxide semiconductor layer 140. After stacking the drain electrodes, a protective insulating layer is formed on the source electrode or drain electrode. This can be done at times such as after. The dehydrogenation treatment can be performed multiple times, not just once.

[0094] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 5(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0095] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. It is possible to do so. Furthermore, the conductive layer material can be aluminum, chromium, copper, or tantalum. Elements selected from titanium, molybdenum, and tungsten, or compounds containing the above elements. Gold and other materials can be used. Manganese, magnesium, zirconium, beryllium, triglycerides. One or more materials selected from aluminum may be used. From titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Materials consisting of one or more selected elements may be used. The conductive layer has a single-layer structure. It may be a single layer, or it may be a laminated structure of two or more layers. For example, an aluminum containing silicon A single-layer structure of aluminum film, a two-layer structure in which a titanium film is laminated on an aluminum film, and a titanium film and Examples include a three-layer structure in which a luminium film and a titanium film are stacked.

[0096] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF It is preferable to use laser light. Source electrode or drain on oxide semiconductor layer 140 The lower end of electrode 142a and the source electrode or drain electrode 14 on the oxide semiconductor layer 140 The channel length (L) of the transistor is determined by the distance between the lower end of 2b and the transistor. When exposure is performed with a channel length (L) of less than 25 nm, the range is from a few nanometers to several tens of nanometers. For the first time, using extremely short wavelength ultraviolet light, a mask shape Perform exposure. Ultra-ultraviolet exposure provides high resolution and a large depth of field. Therefore, later The channel length (L) of the formed transistor shall be between 10 nm and 1000 nm. This is also possible, and the operating speed of the circuit can be increased. Furthermore, because the off-current value is extremely small, Miniaturization does not necessarily lead to increased power consumption.

[0097] Furthermore, during etching of the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0098] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The metal layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0099] Furthermore, in order to reduce the number of masks used and the number of processes, exposure is performed in which transmitted light has multiple intensities. The etching process is performed using a resist mask formed by a multi-gradation mask. It is permissible to do so. A resist mask formed using a multi-gradation mask has a shape with multiple film thicknesses. As a result, the shape can be further deformed by ashing, allowing for different patterns. It can be used in multiple etching processes. In other words, a single multi-gradation mask can be used. This means forming a resist mask that corresponds to at least two different patterns. This allows for a reduction in the number of exposure masks, and the corresponding photolithography process. This can reduce the amount of work required, thus simplifying the process.

[0100] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. It is preferable to perform the following: The plasma treatment will cause the surface of the exposed oxide semiconductor layer to Adhering water and other substances are removed. Additionally, plasma treatment is performed using a mixed gas of oxygen and argon. You may go.

[0101] Next, a protective insulating layer 14 that is in contact with a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 5(G)).

[0102] The protective insulating layer 144 has a thickness of 1 nm or more, and water is applied to the protective insulating layer 144 by sputtering or other methods. It can be formed using appropriate methods to prevent the introduction of impurities such as hydrogen. Protective insulating layer 14 Materials that can be used in step 4 include silicon dioxide, silicon nitride, silicon oxide nitride, and silicon oxide nitride. It has elements such as [elements]. Furthermore, its structure can be either a single-layer structure or a layered structure. The substrate temperature when forming the protective insulating layer 144 is preferably between room temperature and 300°C. The atmosphere can be a noble gas atmosphere (typically argon), an oxygen atmosphere, or a noble gas atmosphere (typically A mixed atmosphere of argon and oxygen is preferable.

[0103] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... This can lead to oxygen abstraction in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, protective insulating layer 1 It is important to avoid using hydrogen in the formation process of 44, as it contains as little hydrogen as possible. That is the case.

[0104] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to ensure that the compound semiconductor layer 140 and the protective insulating layer 144 do not contain hydrogen, hydroxyl groups or water. This is the reason.

[0105] To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The film-forming chamber evacuated using a cryopump has, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O), etc. removed, so the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced. Since the film-forming chamber evacuated using a cryopump has, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O), etc. removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced. Since the film-forming chamber evacuated using a cryopump has, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O), etc. removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced.

[0106] As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups or hydrides is removed to about several ppm (preferably about several ppb). As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups or hydrides is removed to about several ppm (preferably about several ppb). As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups or hydrides is removed to about several ppm (preferably about several ppb).

[0107] Next, it is desirable to perform a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 350°C or lower) in an inert gas atmosphere or an oxygen gas atmosphere. For example, perform a second heat treatment at 250°C for 1 hour in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistors. For example, perform a second heat treatment at 250°C for 1 hour in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistors. For example, perform a second heat treatment at 250°C for 1 hour in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistors.

[0108] Also, a heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or it may be heated from room temperature to a heating temperature of 100°C or higher and 200°C or lower, and cooled from the heating temperature to room temperature multiple times. This heat treatment may be performed while maintaining a constant heating temperature, or it may be heated from room temperature to a heating temperature of 100°C or higher and 200°C or lower, and cooled from the heating temperature to room temperature multiple times. It may be carried out again. Further, this heat treatment may be carried out under reduced pressure before forming the protective insulating layer. When the heat treatment is carried out under reduced pressure, the heating time can be shortened. Note that the heat treatment may be carried out instead of the above second heat treatment, or may be carried out after the second heat treatment.

[0109] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 6(A)). The interlayer insulating layer 146 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After forming the interlayer insulating layer 146, it is desirable to flatten its surface by a method such as CMP or etching.

[0110] Next, openings reaching the electrode 136a, electrode 136b, source electrode or drain electrode 142a, and source electrode or drain electrode 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138, and a conductive layer 148 is formed so as to fill the openings (see Fig. 6(B)). The above openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, it is preferable to use dry etching. The formation of the conductive layer 148 can be carried out using a film formation method such as PVD or CVD. Materials that can be used for forming the conductive layer 148 include molybdenum, titanium, chromium, Conductive materials such as tantalum, tungsten, aluminum, copper, neodymium, and scandium Examples include these alloys and compounds (such as nitrides).

[0111] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is the lower electric Poles (here, electrode 136a, electrode 136b, source electrode or drain electrode 142a, The oxide film at the interface with the source electrode or drain electrode 142b) is reduced, and contact with the lower electrode is reduced. It has the function of reducing resistance. Furthermore, the titanium nitride that is formed afterward is a conductive material. It has a barrier function that suppresses diffusion.

[0112] After forming the conductive layer 148, the conductive layer 148 is formed using methods such as etching and CMP. By removing a portion of it and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 1 50c and electrode 150d are formed (see Figure 6(C)). Note that a portion of the conductive layer 148 is When removing and forming electrodes 150a, 150b, 150c, and 150d, It is desirable to process the surface so that it is flat. In this way, the interlayer insulating layer 146 and the electrodes By planarizing the surfaces of electrode 150a, electrode 150b, electrode 150c, and electrode 150d, In subsequent processes, it becomes possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. ru.

[0113] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to 50c and electrode 150d, and a conductive layer is formed so as to be embedded in the opening. After completion, a part of the conductive layer is removed using a method such as etching or CMP to expose the insulating layer 15 2, and electrodes 154a, 154b, and 154c are formed (see FIG. 6(D)). This process is the same as when forming the electrodes 150a, etc., so the details are omitted. When the n-type transistor 162 is fabricated by the method as described above, the hydrogen concentration of the oxide semiconductor layer 140

[0114] becomes 5×10 atoms / cm 19 or less, and also, the off-current of the n-type transistor 162 3 becomes 1×10 A or less, preferably 100 zA / μm or less. By applying an oxide semiconductor layer 140 with such a sufficiently reduced hydrogen concentration and high purity -13 as this, an n-type transistor 162 with excellent characteristics can be obtained. Further, an excellent semiconductor device having a p-type transistor at the bottom and an n-type transistor using an oxide semiconductor at the top can be fabricated. In this way, by adopting a configuration that integrally includes a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor, a semiconductor device that requires different electrical characteristics (for example, different carriers involved in the operation of the device, etc.) from those of the transistor using an oxide semiconductor can be realized.

[0115] <000X971>

[0116] Since the transistor using an oxide semiconductor has good switching characteristics, an excellent semiconductor device can be fabricated by utilizing such characteristics. For example, in a CMOS inverter circuit, the through-current can be sufficiently suppressed, so the power consumption of the semiconductor device can be reduced, and also, a large current

[0116] ​​​This can prevent the destruction of semiconductor devices. Furthermore, it can prevent the destruction of transistors using oxide semiconductors. Because it has an extremely low off-current, using it can reduce the power consumption of semiconductor devices. It is possible.

[0117] In this embodiment, the p-type transistor 160 and the n-type transistor 162 are stacked. I have explained an example of how it can be formed, but it is not limited to this, such as the p-type transistor 160. The n-type transistor 162 may also be formed on the same substrate. In this embodiment, p In an example where the channel lengths of type 160 and type n transistor 162 are orthogonal to each other. As explained above, the positional relationship between the p-type transistor 160 and the n-type transistor 162 is... This is not the only option. Furthermore, p-type transistor 160 and n-type transistor 16 It is also acceptable to superimpose 2 on top of each other.

[0118] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0119] (Embodiment 2) In this embodiment, the configuration of a semiconductor device according to another aspect of the disclosed invention is shown in Figure 7. This will be explained with reference to Figure 8. In this embodiment, the memory element is used The following describes possible configurations for semiconductor devices.

[0120] Figure 7(A) shows a cross-sectional view of the semiconductor device according to this embodiment, and Figure 7(B) shows the cross-sectional view of the semiconductor device according to this embodiment. The plan views of the semiconductor device relating to its form are shown below. Here, Figure 7(A) is a reference to Figure 7(B). This corresponds to the cross-sections along lines E1-E2 and F1-F2. (Figures 7(A) and 7(B)) The semiconductor device shown has a transistor 260 made of a material other than an oxide semiconductor at the bottom. It has a transistor 262 made of oxide semiconductor on its upper part.

[0121] Transistor 260, which uses a material other than an oxide semiconductor, is placed on a substrate 200 containing a semiconductor material. A channel-forming region 216 is provided, and a channel-forming region 216 is provided on either side of it. The impurity region 214 and the high-concentration impurity region 220 (these together are also simply called the impurity region) (referred to as) the gate insulating layer 208a provided on the channel forming region 216, and the gate insulating A gate electrode 210a is provided on layer 208a, and on one side of the channel formation region 216 Source electrode or drain electrode 230a electrically connected to the provided impurity region 214 This then electrically connects to the impurity region 214 located on the other side of the channel formation region 216. It has a source electrode or drain electrode 230b. Pole 230a provides a metal compound region 224 located on one side of the channel-forming region 216. Through this, the impurity region 214 provided on one side of the channel-forming region 216 is electrically connected. The source electrode or drain electrode 230b is connected to the other side of the channel forming region 216. A metal compound region 224 is provided on the other side of the channel forming region 216. It is preferable that the impurity region 214 is electrically connected in this manner. The configuration of the ZISTA 260 is the same as the configuration of the p-type transistor 160 described in the previous embodiment. Since it is similar to the above, other details can be considered in the previous embodiment. Regarding the polarity of transistor 260, it does not need to be limited to p-type; it can also be n-type.

[0122] The oxide semiconductor transistor 262 has a gate electrode 2 provided on the insulating layer 228. 36c, gate insulating layer 238 provided on gate electrode 236c, and gate insulating layer 23 8 provides an oxide semiconductor layer 240, and provides an oxide semiconductor layer 240. Source electrode or drain electrode 242a, electrically connected to semiconductor layer 240, It has a drain electrode or drain electrode 242b. Thus, the configuration of transistor 262 is Since the configuration is the same as that of the n-type transistor 162 described in the previous embodiment, For further details, refer to the previous embodiment. On the other hand, transistor 262 Regarding polarity, it does not need to be limited to n-type; it can also be p-type.

[0123] Next, we will explain the electrical connection between transistor 260 and transistor 262. The source electrode or drain electrode 230a of transistor 260 is electrode 236a, electrode It is electrically connected to the specified wiring via electrodes 250a and 254a, etc. The source electrode or drain electrode 230b of the lampistor 260 is electrode 236b, electrode 25 It is electrically connected to a predetermined wiring via electrodes 0b, 254b, etc.

[0124] The source electrode or drain electrode 242a of transistor 262 is electrode 250d, electrode 2 Through electrodes 54c, 250c, 236b, and 230c, the gate of transistor 260 It is electrically connected to the source electrode 210a. Also, it is connected to the source electrode of transistor 262. Alternatively, the drain electrode 242b is connected to predetermined wiring via electrodes 250e, 254d, etc. They are electrically connected.

[0125] In Figure 7, the element isolation insulating layer 206 is the same as the element isolation insulating layer 106 of Embodiment 1. The sidewall insulating layer 218 is interlayer insulating to the sidewall insulating layer 118 of Embodiment 1. Layer 226 is the interlayer insulating layer 126 of Embodiment 1, and insulating layer 232 is the insulating layer 1 of Embodiment 1 In 32, the protective insulating layer 244 is the protective insulating layer 144 of Embodiment 1, and the interlayer insulating layer 246 is the actual In the interlayer insulating layer 146 of Embodiment 1, the insulating layer 252 corresponds to the insulating layer 152 of Embodiment 1. ru.

[0126] Figure 8 shows an example of a circuit diagram when the above semiconductor device is used as a memory element.

[0127] The source electrode of transistor 260, which uses a material other than an oxide semiconductor, is the first source wiring. It is electrically connected to (Source1). Furthermore, it uses materials other than oxide semiconductors. The drain electrode of transistor 260 is electrically connected to the drain wiring (Drain). Furthermore, the gate electrode of transistor 260, which uses a material other than an oxide semiconductor, is acid It is electrically connected to the drain electrode of transistor 262, which uses a synthetic semiconductor.

[0128] The source electrode of transistor 262, which uses an oxide semiconductor, is connected to the second source wiring (Sour It is electrically connected to ce2). Also, the oxide semiconductor transistor 262 The gate electrode is electrically connected to the gate wiring (Gate).

[0129] Here, transistor 262, which uses an oxide semiconductor, has the special feature of having an extremely small off-current. It has the characteristic. Therefore, by turning off transistor 262, the transistor It is possible to maintain the potential of the 260 gate electrode for an extremely long period of time.

[0130] By taking advantage of the characteristic of maintaining the potential of the gate electrode, for example, the following operation can be performed. It can function as a memory element. First, the potential of the gate wiring (Gate) is The potential at which transistor 262 turns on is set to turn on transistor 262. This causes the potential of the second source wiring (Source2) to be the same as the potential of transistor 260. The potential is applied to the gate electrode (writing operation). Then, the potential of the gate wiring (Gate) is set. The transistor 262 is turned off by setting the potential to the point where the transistor 262 is turned off.

[0131] Since the off-current of transistor 262 is extremely small, the gate electrode of transistor 260 The potential is maintained for a long time. More specifically, for example, the potential of transistor 260 If the potential of the electrode is such that transistor 260 is turned on, then transistor 26 The ON state of 0 will be maintained for a long period of time. Also, the gate of transistor 260 If the potential of the electrode is such that transistor 260 is in the OFF state, then transistor 26 The "off" state (0) is maintained for an extended period.

[0132] Therefore, according to the potential held at the gate electrode of transistor 260, the drain wiring The potential of (Drain) can take on different values. For example, the potential of the gate electrode of transistor 260. If the potential is such that transistor 260 is turned on, then transistor 260 is turned on. As this will be maintained, the potential of the drain wiring will be the same as the potential of the first source wiring. It becomes equal to the potential of (Source1). In this way, the electric potential of the drain wiring (Drain) The position takes on different values ​​depending on the potential held at the gate electrode of transistor 260. Then, by reading this (read operation), it functions as a memory element.

[0133] The semiconductor device according to this embodiment has an extremely long operating time due to the off-current characteristics of the transistor 262. Because it can retain information over time, it can be used as a de facto non-volatile memory element. It is possible to be there.

[0134] For the sake of simplicity, this embodiment only describes the smallest unit of a memory element. However, the configuration of semiconductor devices is not limited to this. Multiple memory elements can be appropriately connected. This allows for the construction of more advanced semiconductor devices. For example, by using multiple of the above memory elements... This makes it possible to construct NAND and NOR type semiconductor devices. The wiring configuration is shown in Figure 8. This is not limited to this, and can be changed as appropriate.

[0135] As described above, in one aspect of the invention, the off-current characteristics of transistor 262 are used, It constitutes a substantially non-volatile memory element. Thus, according to one aspect of the invention, a new A semiconductor device with such a configuration is provided.

[0136] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0137] (Embodiment 3) In this embodiment, the configuration of a semiconductor device according to another aspect of the disclosed invention is shown in Figure 9. This will be explained with reference to Figure 10. In this embodiment, it is used as a memory element. This document describes the configuration of a semiconductor device that can achieve this.

[0138] Figure 9(A) shows a cross-sectional view of the semiconductor device according to this embodiment, and Figure 9(B) shows the cross-sectional view of the semiconductor device according to this embodiment. The plan views of the semiconductor device relating to its form are shown below. Here, Figure 9(A) is a reference to Figure 9(B). This corresponds to the cross-section along lines G1-G2 and H1-H2. Figures 9(A) and 9(B) The semiconductor device shown has a p-type transistor 46 made of a material other than an oxide semiconductor at the bottom. A transistor 464 has 0 and n type transistors, and a transistor 46 with an oxide semiconductor on top. It has 2.

[0139] p-type transistor 460 and n-type transistor 464 using materials other than oxide semiconductors The configuration is similar to that of the p-type transistor 160 and transistor 260 in the previous embodiment. The same applies. Furthermore, the configuration of the transistor 462 using an oxide semiconductor is the same as in the previous embodiment. This is similar to n-type transistors 162 and 262 in the same context. Therefore, the transistor Each component of the transistor is also similar to that of the transistor in the previous embodiment. Yes. For further details, please refer to the previous embodiment.

[0140] In Figure 9, the substrate 400 is the same as the substrate 100 of Embodiment 1, with an element isolation insulating layer 406 The element isolation insulating layer 106 of Embodiment 1 and the gate insulating layer 408a are the gate insulating layer of Embodiment 1 The insulating layer 108a and the gate electrode 410a are connected to the gate electrode 110a of Embodiment 1. The gate wiring 410b corresponds to the gate wiring 110b of Embodiment 1, and the impurity region 414 corresponds to the embodiment In the impurity region 114 of Embodiment 1, the channel formation region 416 is the channel formation region 1 of Embodiment 1 16. The sidewall insulating layer 418 is the same as the sidewall insulating layer 118 of Embodiment 1. The high-concentration impurity region 420 is the same as the high-concentration impurity region 120 of Embodiment 1, and the metal compound region 4 24 is the metal compound region 124 of Embodiment 1, and the interlayer insulating layer 426 is the interlayer of Embodiment 1. The insulating layer 126 and the interlayer insulating layer 428 are connected to the source electrode. Alternatively, the drain electrode 430a is connected to the source electrode or drain electrode 130a of Embodiment 1. The source electrode or drain electrode 430b is the source electrode or drain electrode of Embodiment 1. 130b, the source electrode or drain electrode 430c is the electrode 130e of Embodiment 2, They correspond to each other.

[0141] Furthermore, the insulating layer 432 is the insulating layer 132 of Embodiment 1, and the electrode 436a is the electrode of Embodiment 1. Electrode 136a is electrode 136a, electrode 436b is electrode 136b of Embodiment 1, gate electrode 436c is actual In the gate electrode 136c of Embodiment 1, the gate insulating layer 438 is the gate insulating layer of Embodiment 1. In 138, the oxide semiconductor layer 440 is the oxide semiconductor layer 140 of Embodiment 1, and the source electrode Alternatively, the drain electrode 442a is connected to the source electrode or drain electrode 142a of Embodiment 1. The source electrode or drain electrode 442b is the source electrode or drain electrode of Embodiment 1. On pole 142b, the protective insulating layer 444 is the protective insulating layer 144 of Embodiment 1, and the interlayer insulating layer 44 6 is the interlayer insulating layer 146 of Embodiment 1, and electrode 450a is the electrode 150a of Embodiment 1. Electrode 450b is the electrode 150b of Embodiment 1, and electrode 450c is the electrode 1 of Embodiment 1 Electrode 450d is electrode 150c of Embodiment 1, and electrode 450e is electrode 1 of Embodiment 1 The electrode 150d has an insulating layer 452 which is the insulating layer 152 of Embodiment 1, and the electrode 454a is the embodiment Electrode 154a of Embodiment 1, electrode 454b is electrode 154b of Embodiment 1, electrode 454 c is electrode 154b of Embodiment 1, electrode 454d is electrode 154c of Embodiment 1, and Each will be handled accordingly.

[0142] The semiconductor device according to this embodiment includes a drain electrode of transistor 462 and a p-type transistor The gate electrode of transistor 460 and the gate electrode of n-type transistor 464 are electrically connected to each other. In that it is connected, it differs from the semiconductor device according to the previous embodiment (Figure (See 9). With this configuration, the input signal (INPU) of the CMOS inverter circuit It is possible to temporarily hold T).

[0143] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0144] (Embodiment 4) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment is described below. This will be explained using Figure 11. The semiconductor device obtained in the above embodiment has switching characteristics Because it has transistors using good oxide semiconductors, it reduces the power consumption of each electronic device. It is possible to develop new semiconductor devices that utilize the properties of oxide semiconductors (for example, memo Because elements (such as re-elements) are provided, it becomes possible to provide electronic devices with new configurations. The semiconductor device according to the above embodiment can be mounted on a circuit board or the like, either individually or as an integrated unit. They will then be installed inside each electronic device.

[0145] An integrated circuit incorporating a semiconductor device is a semiconductor device as described in the previous embodiment. In addition, they are often constructed by incorporating various circuit elements such as resistors, capacitors, and coils. Examples of integrated circuits include arithmetic circuits, conversion circuits, amplification circuits, memory circuits, and combinations thereof. Some devices highly integrate circuits and other components related to matching. MPUs and CPUs are prime examples of this. It could be said that this is the case.

[0146] Furthermore, the above-mentioned semiconductor device can also be used as a switching element in a display device. In this case, it is preferable to provide the drive circuit on the same circuit board. Of course, the display device The above semiconductor device can also be used only for the drive circuit of the device.

[0147] Figure 11(A) shows a notebook-type personal computer including a semiconductor device according to the above embodiment. It is a data system consisting of the main unit 301, the casing 302, the display unit 303, the keyboard 304, etc. It has been done.

[0148] Figure 11(B) shows a personal digital assistant (PDA) including a semiconductor device according to the previously described embodiment. The main unit 311 includes a display unit 313, an external interface 315, and operation buttons 314, etc. A stylus 312 is provided as an accessory for operation.

[0149] Figure 11(C) shows an example of an electronic paper including a semiconductor device according to the above embodiment, This shows the e-book 320. The e-book 320 is housed in two enclosures, enclosure 321 and enclosure 323. It is constructed such that the housing 321 and housing 323 are integrated by the shaft portion 337. The shaft portion 337 can be used as a pivot to perform opening and closing operations. With this configuration, paper books It can be used in this way.

[0150] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 11(C)), and on the left-hand display unit (Figure 11 (C) allows an image to be displayed on the display unit 327).

[0151] Furthermore, Figure 11(C) shows an example in which the housing 321 is equipped with an operating section, etc. Body 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. Pages can be advanced using operation key 333. Note that the keyboard is located on the same surface as the display unit. The configuration may also include a dot or pointing device. Furthermore, the back or sides of the enclosure may be... External connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable) The configuration includes terminals that can connect to various cables such as wires, a recording medium insertion section, etc. This is also acceptable. Furthermore, eBook 320 may be configured to function as an electronic dictionary. .

[0152] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0153] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various types of cards, such as TCG cards.

[0154] Figure 11(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The speaker consists of two housings, housing 340 and housing 341. Housing 341 contains, Display panel 342, speaker 343, microphone 344, pointing device It is equipped with 346, a camera lens 347, an external connection terminal 348, etc. Also, housing 34 0 includes a solar cell 349 for charging the mobile phone, an external memory slot 350, and It is equipped with such features. Furthermore, the antenna is built into the 341 casing.

[0155] The display panel 342 is equipped with a touch panel, and Figure 11(D) shows multiple images being displayed. The number operation keys 345 are indicated by dotted lines. Note that this mobile phone uses a solar cell 349. A boost circuit is implemented to increase the output voltage to the voltage required for each circuit. In addition to the above configuration, it is also possible to have a configuration that incorporates a contactless IC chip, a small recording device, etc. Cut.

[0156] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used. Furthermore, housings 340 and 341 slide apart, as shown in Figure 11(D). It can be transformed from an unfolded state to an overlapping state, and miniaturized to be suitable for portability. It is possible.

[0157] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also allows for charging and data communication with personal computers, etc. Furthermore, it has external memory. By inserting a recording medium into slot 350, it is possible to store and transfer larger amounts of data. Furthermore, in addition to the above functions, it may also be equipped with infrared communication functions, television reception functions, etc. stomach.

[0158] Figure 11(E) shows a digital camera including a semiconductor device according to the previous embodiment. The digital camera consists of the main unit 361, the display unit (A) 367, the eyepiece 363, and the operation switch 364. It consists of a display unit (B) 365, a battery 366, and the like.

[0159] Figure 11(F) shows a television apparatus including a semiconductor device according to the above embodiment. The vision device 370 has a display unit 373 incorporated into the housing 371. It is possible to display the video. Also, here, the stand 375 is used for the enclosure 3 This shows the configuration that supported 71.

[0160] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A display unit 377 that displays the information may also be provided.

[0161] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible.

[0162] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. Can be used together [Explanation of Symbols]

[0163] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108a Gate Insulation Layer 108b Gate insulating layer 110a Shuttle bus 110b Gate wiring 110c wiring 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c source electrode or drain electrode 130d Source electrode or drain electrode 130e electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c gate 136d electrode 136e electrode 136f gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 150f electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 154e electrode 160 p-type transistor 162 n-type transistor 164 p-type transistor 166 n-type transistors 200 circuit boards 206 Element Isolation Insulating Layer 208a Gate Insulation Layer 210a Terminal 214 Impurity region 216 Channel formation region 218 Sidewall insulation layer 220 High concentration impurity region 224 Metal compound area 226 Interlayer insulating layer 228 Insulating layer 230a Source electrode or drain electrode 230b Source electrode or drain electrode 230c electrode 232 Insulating layer 236a Electrode 236b Electrode 236c gate electrode 238 Gate Insulation Layer 240 oxide semiconductor layer 242a Source electrode or drain electrode 242b Source electrode or drain electrode 244 Protective insulating layer 246 interlayer insulating layer 250a electrode 250b electrode 250c electrode 250d electrode 250e electrode 252 Insulating layer 254a electrode 254b electrode 254c electrode 254d electrode 260 transistors 262 transistors 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit 400 circuit boards 406 Element Isolation Insulating Layer 408a Gate Insulation Layer 410a Shut-off valve 410b Gate wiring 414 Impurity region 416 Channel formation region 418 Sidewall insulation layer 420 High concentration impurity region 424 Metal compound area 426 Interlayer insulating layer 428 Interlayer insulating layer 430a Source electrode or drain electrode 430b Source electrode or drain electrode 430c source electrode or drain electrode 432 Insulating layer 436a electrode 436b Electrode 436c gate 438 Gate Insulation Layer 440 Oxide semiconductor layer 442a Source electrode or drain electrode 442b Source electrode or drain electrode 444 Protective insulating layer 446 Interlayer insulating layer 450a electrode 450b electrode 450c electrode 450d electrode 450e electrode 452 Insulating layer 454a electrode 454b electrode 454c electrode 454d electrode 460 p-type transistor 462 transistors 464 n-type transistor

Claims

[Claim 1] A first transistor having a channel-forming region provided on a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel-forming region, a first gate insulating layer on the channel-forming region, a first gate electrode on the first gate insulating layer, and a first source electrode and a first drain electrode electrically connected to the impurity region, A semiconductor device having a second transistor, the second gate electrode on a substrate containing the semiconductor material, a second gate insulating layer on the second gate electrode, an oxide semiconductor layer on the second gate insulating layer, and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer.

Images