Manufacturing method for packaging substrates

Abstract

To provide a method for manufacturing a packaging substrate with excellent electrical reliability. [Solution] The method for manufacturing the packaging substrate 200 includes a preparation step of providing a base substrate including a core layer 10, a first redistribution layer 40 disposed on the core layer, and a second seed layer 23 disposed on the first redistribution layer; a resist pattern film formation step of forming a resist pattern film 50 on the second seed layer; and a second electrical conductive layer formation step of forming a second electrical conductive layer from the second seed layer. The first redistribution layer includes a first electrical conductive layer and a first insulating layer 30 surrounding at least a portion of the first electrical conductive layer. The first electrical conductive layer includes a first-1 electrical conductive layer 21 disposed closest to the second seed layer. The ratio of the thickness of the resist pattern film to the thickness of the first-1 electrical conductive layer is 1.8 to 4. This enables highly reliable electrical connections on a redistribution layer where undulations with a wavy surface occur.

Description

[Technical Field]

[0001] The concrete example relates to a method for manufacturing a packaging substrate. [Background technology]

[0002] In the manufacturing of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers into a state where they can be used in actual products is called the back-end process (BE), and the packaging process is included in this back-end process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as line widths in the nanoscale (below the micron), cells exceeding 10 million, high-speed operation, and significant heat dissipation, but relatively speaking, the technology to perfectly package these is not yet supported. Therefore, the electrical performance of a semiconductor is sometimes determined more by the packaging technology and the resulting electrical connections than by the performance of the semiconductor technology itself.

[0004] Ceramics or resins are used as materials for packaging substrates. In the case of ceramic substrates, it is not easy to mount high-performance high-frequency semiconductor elements due to their high resistance or dielectric constant. In the case of resin substrates, it is relatively possible to mount high-performance high-frequency semiconductor elements, but there are limitations to the reduction of the wiring pitch.

[0005] Recently, research has been progressing on applying silicon and glass to high-end packaging substrates. By forming through-holes in silicon or glass substrates and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, resulting in superior electrical characteristics. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Korean Published Patent No. 10-2021-0127188 [Overview of the project] [Problems that the invention aims to solve]

[0007] The objective of this embodiment is to provide a method for manufacturing a packaging substrate with excellent electrical reliability. [Means for solving the problem]

[0008] A method for manufacturing a packaging substrate according to one embodiment of this specification includes a preparation step of providing a base substrate including a core layer, a first redistribution layer disposed on the core layer, and a second seed layer disposed on the first redistribution layer; a resist pattern film formation step of forming a resist pattern film on the second seed layer; and a second electrical conductive layer formation step of forming a second electrical conductive layer from the second seed layer.

[0009] The first redistribution layer includes a first electrical conduction layer and a first insulating layer surrounding at least a portion of the first electrical conduction layer.

[0010] The first electrical conductive layer includes a 1-1 electrical conductive layer located closest to the second seed layer.

[0011] The ratio of the thickness of the resist pattern film to the thickness of the 1-1 electrical conductive layer is 1.8 to 4.

[0012] The thickness of the resist pattern film may be 30 μm to 50 μm.

[0013] The thickness of the first-1 electrical conductive layer may be 20 μm or less.

[0014] The resist pattern film forming step may include a dry film laminating process of laminating a dry film on the second seed layer, and a developing process of patterning the dry film to form the resist pattern film.

[0015] In the dry film laminating process, the dry film may be laminated on the second seed layer by a roll laminator.

[0016] In the dry film laminating process, the roll pressure of the roll laminator may be 0.55 MPa to 1 MPa.

[0017] In the dry film laminating process, the roll temperature of the roll laminator may be 110 °C to 140 °C.

[0018] In the dry film laminating process, the lamination speed of the roll laminator may be 2 m / min or less.

[0019] The Ra value, which is the arithmetic mean roughness of the first rewiring layer, may be 1 μm to 10 μm.

[0020] The method for manufacturing the packaging substrate may further include an insulating layer forming step of forming an insulating layer including a hole pattern on the second electrically conductive layer.

[0021] The insulating layer forming step may include an insulating layer forming process of forming an insulating layer on the second electrically conductive layer, and a resist pattern film forming process for a metal mask of forming a resist pattern film for a metal mask on the insulating layer.

[0022] The resist pattern film forming process for a metal mask may include a laminating process of laminating a resist film for a metal mask on the base substrate, and an exposure process of selectively exposing the resist film for a metal mask.

[0023] The resist pattern film for the metal mask may include a hole pattern with a diameter of 20 μm or less.

[0024] The resist film for the metal mask may also contain a negative resist.

[0025] The exposure dose during the aforementioned exposure process was 170 mJ / cm². 2 ~215 mJ / cm² 2 That's fine.

[0026] A method for manufacturing a packaging substrate according to other embodiments of this specification includes a step of forming a resist pattern film for a metal mask on a base substrate which includes a core layer and a metal base layer formed on the core layer.

[0027] The step of forming a resist pattern film for a metal mask includes a lamination process of laminating a resist film for a metal mask onto the base substrate, and an exposure process of selectively exposing the resist film for a metal mask.

[0028] The resist pattern film for the metal mask includes a hole pattern with a diameter of 20 μm or less.

[0029] The resist film for the metal mask includes a negative resist.

[0030] The exposure dose during the aforementioned exposure process was 170 mJ / cm². 2 ~215 mJ / cm² 2 That is the case.

[0031] The step of forming a resist pattern film for a metal mask may further include a developing step of developing the exposed resist film for the metal mask to form the resist pattern film for the metal mask.

[0032] In the development process, the developing solution may be sprayed onto the resist film for the metal mask to form the resist pattern film for the metal mask.

[0033] The spray pressure of the developer may be 0.13 MPa to 3 MPa.

[0034] The temperature of the developer may be 20°C or higher and less than 30°C.

[0035] In the lamination process, the resist film may be laminated in contact with the metal base layer for the metal mask using a roll laminator.

[0036] The roll pressure of the aforementioned roll laminator may be 0.3 MPa to 1 MPa.

[0037] In the lamination process, the roll temperature of the roll laminator may be 105°C to 130°C.

[0038] In the lamination process, the lamination speed of the roll laminator may be 1 m / min to 2 m / min.

[0039] The method for manufacturing the packaging substrate may further include a metal mask layer formation step in which the metal base layer is selectively wet-etched using the resist pattern film for the metal mask to provide a metal mask layer.

[0040] The base substrate may further include an insulating layer disposed between the metal mask layer and the core layer.

[0041] The method for manufacturing the packaging substrate may further include an insulating pattern layer formation step in which the insulating layer is selectively plasma-etched using the metal mask layer to form an insulating pattern layer.

[0042] In the insulating pattern layer formation step, the insulating layer may be selectively plasma-etched in an atmosphere containing a first etching gas and a second etching gas.

[0043] The first etching gas may be a fluorine-based gas.

[0044] The second etching gas may be oxygen gas. [Effects of the Invention]

[0045] The manufacturing method for the packaging substrate in this example can realize a packaging substrate with excellent reliability. [Brief explanation of the drawing]

[0046] [Figure 1] This is a cross-sectional view illustrating a base substrate provided in the preparation step according to one embodiment of the concrete example. [Figure 2] This is a cross-sectional view illustrating a base substrate on which a resist pattern film is formed through a resist pattern film formation step according to one embodiment of the concrete example. [Figure 3] This is a cross-sectional view illustrating a packaging substrate manufactured by a packaging substrate manufacturing method according to one embodiment of the concrete example. [Figure 4] This is a cross-sectional view illustrating a base substrate according to another embodiment of the concrete example. [Figure 5] This is a cross-sectional view illustrating a resist pattern film according to another embodiment of the concrete example. [Figure 6] This is a cross-sectional view illustrating a metal mask layer according to another embodiment of the concrete example. [Figure 7] This is a cross-sectional view illustrating an insulating pattern layer according to another embodiment of the concrete example. [Figure 8] This is a cross-sectional view illustrating a packaging substrate manufactured by a manufacturing method relating to another embodiment of the concrete example. [Best Mode for Carrying Out the Invention]

[0047] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. However, the present invention can be realized in a variety of different forms and is not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0048] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0049] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0050] In this specification, "~system" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0051] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0052] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0053] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0054] In this specification, the form, relative size, angles, etc., of each component in the drawings are illustrative and may be exaggerated for illustrative purposes, and the rights shall not be construed as being limited to the drawings.

[0055] In this specification, "adjacent to A and B" means that A and B are located touching each other, or that A and B are not touching but are located close to each other. In this specification, the expression "adjacent to A and B" is not construed to mean that A and B are located touching each other unless otherwise specified.

[0056] In this specification, unless otherwise specified, the physical properties of each component within the packaging substrate are assumed to have been measured at room temperature. Room temperature is defined as 20°C to 25°C.

[0057] During the process of creating a redistribution layer on a core layer, undulations, characterized by wavy undulations, may occur on the surface of the redistribution layer. These undulations can hinder the precise creation of conductive layer patterns on the redistribution layer and, in particular, can frequently cause short circuits in the conductive layer. As the structures of the core layer and conductive layer within the packaging substrate become more miniaturized and complex, the frequency of undulations may increase, and the impact of undulations on the yield of the packaging substrate may become even greater.

[0058] The inventors of the embodiment experimentally confirmed that highly reliable electrical connections can be achieved even when an electrical conductive layer is formed on an uneven redistribution layer by introducing the technical features detailed below, and thus completed the embodiment.

[0059] The following provides a detailed explanation of specific examples.

[0060] The manufacturing method for a packaging substrate in the embodiment includes a preparation step of providing a base substrate including a core layer, a first redistribution layer disposed on the core layer, and a second seed layer disposed on the first redistribution layer; a resist pattern film formation step of forming a resist pattern film on the second seed layer; and a second electrical conductive layer formation step of forming a second electrical conductive layer from the second seed layer. Figure 1 is a cross-sectional view illustrating the base substrate provided through the preparation steps of the embodiment. The embodiment will be described below with reference to Figure 1.

[0061] Preparation Steps Figure 1 is a cross-sectional view illustrating the base substrate provided through the preparation steps of the embodiment. The embodiment will be described below with reference to Figure 1.

[0062] The base substrate 100 may include a core layer 10, a first redistribution layer 40 disposed on the core layer 10, and a second seed layer 23 disposed on the first redistribution layer 40.

[0063] The core layer 10 can function as a support layer in the packaging substrate. The core layer 10 can be applied without limitation as long as it can be used as a support layer in the field of packaging substrates. For example, the core layer 10 may be a glass substrate, a ceramic substrate, an organic substrate, etc.

[0064] The core layer 10 may include through vias (not shown) that penetrate in the thickness direction of the core layer 10.

[0065] A through via consists of an internal space (not shown) and an inner diameter surface of the via (not shown) surrounding the internal space. The internal space refers to an empty space, and the inner diameter surface of the via refers to the surface of the core layer 10 formed on the inside of the through via.

[0066] The through vias may have a diameter that varies in the thickness direction of the core layer 10. The through vias may have a substantially uniform diameter in the thickness direction of the core layer 10.

[0067] The surface of the core layer 10 may include an upper surface and a side surface connected to the upper surface and formed in the thickness direction of the core layer 10. The surface of the core layer 10 may also include a lower surface facing the upper surface.

[0068] The statement that the side surface is formed in the thickness direction of the core layer 10 is interpreted to mean not only that the side surface is perpendicular to the upper surface of the core layer 10, but also that at least a portion of the side surface forms an angle (angle of inclination) other than 90° with the upper surface.

[0069] The aforementioned side surface may be flat or curved.

[0070] The thickness of the core layer 10 may be 100 μm or more. The thickness may be 200 μm or more. The thickness may be 300 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. In such cases, the core layer 10 can have mechanical properties suitable for application to a packaging substrate.

[0071] The core layer 10 may include a cavity portion (not shown) formed by recessing the upper surface. The cavity portion may be formed by recessing a part of the upper surface of the core layer 10 in the thickness direction of the core layer 10. The cavity portion may be formed by penetrating through the core layer 10 in the thickness direction.

[0072] The cavity portion may include a mounting space (not shown) on which an element or element package is mounted, and an inner cavity surface (not shown) surrounding the mounting space. An element and / or element package can be placed in the mounting space.

[0073] The elements may include not only semiconductor elements such as CPUs, GPUs, and memory chips, but also capacitor elements, transistor elements, impedance elements, and other modules. In other words, any semiconductor element that is mounted on a semiconductor device can be used as the element without limitation.

[0074] An element package is one or more elements packaged by an element insulating material. The element insulating material can surround at least a portion of the surface of the elements. The element insulating material can fix one or more elements within the element package and provide insulation to the desired area within the element package.

[0075] In the base substrate 100, the first redistribution layer 40 may be placed in contact with the core layer 10. In the base substrate 100, other components may be placed between the first redistribution layer 40 and the core layer 10.

[0076] The first redistribution layer 40 includes a first electrical conductive layer 20 and a first insulating layer 30 surrounding at least a portion of the first electrical conductive layer 20.

[0077] The first electrical conductive layer 20 is a conductor that is placed within the first rewiring layer 40 and transmits electrical signals. The first electrical conductive layer 20 may have a patterned shape.

[0078] The first electrical conductive layer 20 may contain an electrical conductive material. The first electrical conductive layer 20 may be formed by a dry method or a wet method.

[0079] The dry method involves sputtering in the region where the first electrical conductive layer 20 is to be placed to form a seed layer, and then plating the region where the seed layer is formed to form the conductive layer. When forming the seed layer, metals such as titanium, chromium, and nickel may be sputtered, or the aforementioned metals and copper may be applied together for sputtering. Through sputtering, an anchoring effect occurs in which the surface on which the first electrical conductive layer 20 is placed and the deposited metal particles interact, thereby improving the adhesion of the first electrical conductive layer 20.

[0080] The wet method is a method in which a primer is applied to the area where the first electrical conductive layer 20 needs to be formed, and then a seed layer is formed. The primer may include compounds having functional groups such as amines. Depending on the desired degree of adhesion, the primer may contain both a compound having functional groups such as amines and a silane coupling agent. When using a silane coupling agent, the surface to be primed can be pretreated with the silane coupling agent, and then a compound having amine groups can be applied to the pretreated area to form the primer layer.

[0081] After forming the seed layer, the first electrical conductive layer 20 can be formed by plating with a metal. Copper plating may be applied during the formation of the first electrical conductive layer 20, but is not limited to this. Before metal plating, parts of the seed layer or primer layer where the formation of the first electrical conductive layer 20 is unnecessary can be deactivated, or parts where the formation of the first electrical conductive layer 20 is necessary can be activated before plating. The activation or deactivation treatment method may include light irradiation treatment using a laser of a specific wavelength, chemical treatment, etc. However, after metal plating without applying activation or deactivation treatment, the first electrical conductive layer 20 can be etched and patterned according to a pre-designed shape.

[0082] The first electrical conductive layer 20 includes the 1-1 electrical conductive layer 21. The first electrical conductive layer 20 may also include the 1-1 electrical conductive layer 21 and the 1-2 electrical conductive layer 22.

[0083] The first-first conductive layer 21 is the first conductive layer 20 located closest to the second seed layer 23, which is located on the first redistribution layer 40. The first-first conductive layer 21 is the uppermost conductive layer among the first conductive layers 20. The first-first conductive layer 21 is a conductive layer formed in the in-plane direction of the packaging substrate. That is, terminals located on the first-first conductive layer 21 and electrically connected to the first-first conductive layer 21, or via patterns formed in the thickness direction of the base substrate 100, are not included in the first-first conductive layer 21.

[0084] The first-second electrical conductive layer 22 is an electrical conductive layer of the first electrical conductive layer 20 that does not correspond to the first-first electrical conductive layer 21.

[0085] The first insulating layer 30 can surround at least a portion of the first conductive layer 20. The first insulating layer 30 and the first conductive layer 20 can be arranged together within the first redistribution layer 40. The first conductive layer 20 having a patterned shape can be formed in a form embedded within the first insulating layer 30.

[0086] The first insulating layer 30 can be formed by methods for forming insulating layers that are commonly applicable in the field of packaging substrates. For example, the first insulating layer 30 may be made of an epoxy resin containing a filler. The first insulating layer 30 may also, but is not limited to, a build-up layer material such as Ajinomoto's ABF (Ajinomoto Build-up Film), an undercoat material, etc.

[0087] The first insulating layer 30 may be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0088] The manufacturing method for the packaging substrate in the embodiment allows the roughness characteristics of the first redistribution layer 40 to be controlled within a range predetermined in the embodiment. Through this, it is possible to suppress the peeling of the resist pattern film from the area to be formed when forming a resist pattern film to form an electrical conductive layer pattern on the first redistribution layer 40.

[0089] The Ra value, which is the arithmetic mean roughness of the first redistribution layer 40, is measured using a surface roughness measuring instrument in accordance with the ISO 4287:1997 standard.

[0090] The Ra value of the first redistribution layer 40 may be 1 μm to 10 μm. The Ra value may be 3 μm or more. The Ra value may be 8 μm or less. In such cases, even if the first redistribution layer 40 has irregularities, it can help suppress the detachment of part or all of the resist pattern film from the surface to which it is attached.

[0091] The base substrate 100 may include a second seed layer 23 disposed on the first redistribution layer 40. The second seed layer 23 can function as a seed layer for forming a second electrical conductive layer on the first redistribution layer 40.

[0092] The second seed layer 23 may be formed in contact with the first redistribution layer 40. Other components may be placed between the second seed layer 23 and the first redistribution layer 40.

[0093] The second seed layer 23 may include a second lower seed layer (not shown) and a second upper seed layer (not shown) disposed on the second lower seed layer. The second lower seed layer may be made of a different material than the plating layer formed on the second seed layer 23. For example, the second lower seed layer may be made of titanium, chromium, nickel, etc. The second upper seed layer may be made of the same material as the plating layer. For example, the second upper seed layer may be made of copper.

[0094] The second seed layer 23 can be formed using the dry method. The explanation of the dry method is omitted as it overlaps with the previous explanation.

[0095] Resist pattern film formation step Figure 2 is a cross-sectional view illustrating the base substrate 100 on which a resist pattern film is formed through the resist pattern film formation step of the embodiment. The embodiment will be described below with reference to Figure 2.

[0096] The core layer 10 and the first redistribution layer 40, etc., are the same as those described in Figure 1 above. The differences will be explained below.

[0097] In the resist pattern film formation step, a resist pattern film 50 can be formed on the second seed layer 23.

[0098] The resist pattern film 50 can be applied to pattern formation of the second electrical conductive layer formed from the second seed layer 23. The resist pattern film 50 may be placed in contact with the second seed layer 23. Other components may be placed between the resist pattern film 50 and the second seed layer 23.

[0099] The resist pattern film formation step may include a dry film lamination process in which a dry film is laminated on the second seed layer 23, and a development process in which the dry film is patterned to form a resist pattern film 50.

[0100] In this embodiment, the ratio between the thickness of the resist pattern film 50 formed through the resist pattern film formation step and the thickness of the first-1 electrical conductive layer 21 can be controlled. Through this, it is possible to suppress excessive undulation on the upper surface of the first redistribution layer 40, and to laminate the dry film to the upper surface of the first redistribution layer 40, which has a curved shape, so that it adheres well to the entire surface and has stable adhesion.

[0101] The ratio of the thickness of the resist pattern film 50 to the thickness of the first-1 electrical conductive layer 21 can be 1.8 to 4. The ratio may be 2 or more. The ratio may be 2.2 or more. The ratio may be 3.8 or less. The ratio may be 3.6 or less. The ratio may be 3.4 or less. In this case, the dry film can be stably attached to the entire first redistribution layer 40 having a curved surface, and the penetration of the plating solution applied to form the second electrical conductive layer into the bottom side of the resist pattern film 50 can be suppressed.

[0102] The thickness of the resist pattern film 50 may be 30 μm to 50 μm. The thickness may be 32 μm or more. The thickness may be 34 μm or more. The thickness may be 48 μm or less. The thickness may be 46 μm or less. In such cases, it is possible to suppress the peeling of the resist pattern film 50 from the adhesion target area while substantially preventing pattern collapse due to a high aspect ratio.

[0103] The thickness of the first-1 electrical conductive layer 21 may be 20 μm or less. The thickness may be 18 μm or less. The thickness may be 16 μm or less. The thickness may be 14 μm or less. The thickness may be 13 μm or less. The thickness may be 1 μm or more. In such cases, it is possible to suppress the occurrence of excessive undulation of the first redistribution layer 40 caused by the thickness of the first-1 electrical conductive layer 21.

[0104] The resist pattern film formation step may include a dry film lamination process in which a dry film is laminated on the second seed layer 23, and a development process in which the dry film is patterned to form the resist pattern film 50.

[0105] Dry film lamination process In the dry film lamination process, the dry film can be laminated onto the second seed layer 23 using a roll laminator. Specifically, the protective film attached to the dry film is peeled off and simultaneously positioned on the second seed layer 23, and high temperature and pressure are applied to the dry film using the rolls of the roll laminator to laminate the dry film onto the second seed layer 23.

[0106] The dry film used in the dry film lamination process can be any dry film commonly used in the field of packaging substrates, without any limitations. The dry film may be a positive resist film. The dry film may be a negative resist film. When a negative resist film is used as the dry film, it may be advantageous for forming an electrically conductive layer pattern with a fine width.

[0107] The thickness of the dry film may be 30 μm to 50 μm. The thickness may be 32 μm or more. The thickness may be 34 μm or more. The thickness may be 48 μm or less. The thickness may be 46 μm or less. In such cases, it may be helpful to ensure that the resist pattern film 50 has a thickness within the range predetermined in the embodiment.

[0108] The embodiment allows for control of the process conditions of a roll laminator applied to the dry film lamination process. Through this, it is possible to suppress at least a portion of the dry film from falling off the upper surface of the first redistribution layer 40 when laminating the dry film onto the upper surface of the uneven first redistribution layer 40. Furthermore, it is possible to effectively suppress the penetration of the plating solution under the resist pattern film 50 and the occurrence of a short circuit in the second electrical conductive layer during the formation process of the second electrical conductive layer.

[0109] The roll laminator is not limited to those commonly used in the field of packaging substrates. For example, the ATOCHEM Hot Roller model can be used as a roll laminator.

[0110] In the dry film lamination process, the roll pressure of the roll laminator may be 0.55 MPa to 1 MPa. The roll pressure may be 0.58 MPa or higher. The roll pressure may be 0.9 MPa or lower. The roll pressure may be 0.8 MPa or lower. The roll pressure may be 0.7 MPa or lower. In such cases, the dry film can be laminated to the entire upper surface of the first redistribution layer 40 having a curved surface in close contact with substantially no gaps.

[0111] In the dry film lamination process, the roll temperature of the roll laminator may be 110°C to 140°C. The roll temperature may be 115°C or higher. The roll temperature may be 135°C or lower. In such cases, the dry film laminated on the first redistribution layer 40 can have excellent adhesion to the upper surface of the first redistribution layer 40.

[0112] In the dry film lamination process, the lamination speed of the roll laminator may be 2 m / min or less. The lamination speed may be 1.8 m / min or less. The lamination speed may be 1.5 m / min or less. The lamination speed may be 0.5 m / min or more. In such cases, sufficient time can be ensured for the dry film to have excellent adhesion to the upper surface of the first redistribution layer 40, thereby shortening the manufacturing time and improving process efficiency.

[0113] development process During the development process, the dry film laminated on the first redistribution layer 40 can be developed to form a resist pattern film 50. The dry film can be irradiated with exposure light according to a pre-designed pattern shape, and the dry film after light irradiation can be treated with a developer to form the resist pattern film 50.

[0114] Exposure light can be applied using a laser direct imaging (LDI) exposure machine or through a selective exposure process using a photomask.

[0115] In the irradiation of exposure light, exposure light having an adjusted wavelength band may be applied. Specifically, light with a wavelength of 405 nm can be applied as the exposure light.

[0116] The exposure energy when irradiating the exposure light can be adjusted according to the thickness of the dry film to be exposed. The exposure energy may be 30 mJ / cm 2 or more. The exposure energy may be 35 mJ / cm 2 or more. The exposure energy may be 40 mJ / cm 2 or more. The exposure energy may be 45 mJ / cm 2 or more. The exposure energy may be 100 mJ / cm 2 or less. The exposure energy may be 90 mJ / cm 2 or less.

[0117] The dry film after exposure can be heat-treated. When the dry film is a negative resist film, through heat treatment, the exposed area in the dry film can be sufficiently cured down to the lower side. The heat treatment may be performed at a temperature of 80°C to 120°C.

[0118] The exposed dry film can be developed using a developer to form a resist pattern film 50. When the dry film is a negative resist film, the unexposed area in the dry film can be developed through the developer. Any developer that is normally applied in the field of resist can be applied without limitation.

[0119] When developing a dry film, a developer can be sprayed onto the dry film to form a resist pattern film 50. When developing a dry film, the spray pressure of the developer may be 1.5 kPa or higher. The spray pressure may be 1.8 kPa or higher. The spray pressure may be 3 kPa or lower. In such cases, the area to be removed within the dry film is sufficiently removed by the developer, and the shape of the resist pattern film 50 can be precisely controlled.

[0120] The temperature of the developer may be 15°C or higher. The temperature may be 20°C or higher. The temperature may be 25°C or higher. The temperature may be 50°C or lower. The temperature may be 45°C or lower.

[0121] During the development process, the developer can be sprayed onto the dry film by having the base substrate pass through the space in which the developer is sprayed. The movement speed of the base substrate when spraying the developer may be 900 mm / min or less. The movement speed may be 850 mm / min or less. The movement speed may be 800 mm / min or less. The movement speed may be 500 mm / min or more.

[0122] In such cases, the shape of the resist pattern film formed on the second seed layer can be precisely controlled.

[0123] Second electrical conduction layer formation step Figure 3 is a cross-sectional view illustrating a packaging substrate manufactured by the manufacturing method of the example packaging substrate. The example will be described below with reference to Figure 3.

[0124] The core layer 10 and the first redistribution layer 40, etc., are the same as those described in Figures 1 and 2 above. The differences will be explained below.

[0125] In the second electrical conductive layer formation step, the second electrical conductive layer 24 can be formed from the second seed layer. The second electrical conductive layer 24 is an electrical conductive layer formed from the second seed layer.

[0126] A second electrical conductive layer 24 can be formed by plating a metal onto the second seed layer. Copper plating may be applied during the formation of the second electrical conductive layer 24, but is not limited to this. The second electrical conductive layer 24 can be formed in areas of the second seed layer that are exposed and not covered by the resist pattern film.

[0127] After the formation of the second electrical conductive layer 24 is complete, the resist pattern film can be removed. After spraying a stripping solution onto the base substrate 100 on which the second electrical conductive layer 24 is formed, the resist pattern film can be peeled off and removed.

[0128] The spray pressure of the stripping solution applied when stripping the resist pattern film may be 1.2 kPa or higher. The pressure may be 1.4 kPa or higher. The pressure may be 3 kPa or lower.

[0129] The temperature of the stripping solution may be 35°C or higher. The temperature of the stripping solution may be 40°C or higher. The temperature of the stripping solution may be 45°C or higher. The temperature of the stripping solution may be 50°C or higher. The temperature of the stripping solution may be 80°C or lower. The temperature of the stripping solution may be 75°C or lower. The temperature of the stripping solution may be 70°C or lower.

[0130] The base substrate's movement speed during the spraying of the stripping solution may be 1200 mm / min or less. The speed may be 1100 mm / min or less. The movement speed may be 900 mm / min or less. The movement speed may be 550 mm / min or more. The movement speed may be 500 mm / min or more.

[0131] In such cases, damage to the second electrical conductive layer 24 can be suppressed, and the resist pattern film can be smoothly removed.

[0132] After removing the resist pattern film, the upper surface of the base substrate 100 can be etched to remove the unnecessary second seed layer. The upper surface of the base substrate 100 can be dry-etched to remove the second seed layer located in areas where the second electrical conductive layer 24 is not formed.

[0133] Second insulating layer formation step The manufacturing method of the packaging substrate in the embodiment may further include a second insulating layer formation step of forming a second insulating layer 31 including a hole pattern on the second electrical conductive layer 24.

[0134] The second insulating layer formation step may include a second insulating layer formation process for forming a second insulating layer 31 on the second electrical conductive layer 24, a metal base layer formation process for forming a metal base layer (not shown) disposed on the second insulating layer 31, and a metal mask resist pattern film formation process for forming a metal mask resist pattern film (not shown) on the second insulating layer 31.

[0135] The second insulating layer 31 is an insulating layer placed on the second electrical conductive layer 24. The second insulating layer 31 can surround at least a portion of the second electrical conductive layer 24.

[0136] In the process of forming the second insulating layer, the second insulating layer 31 can be formed using the same method as the method used to form the first insulating layer 30. Specific details regarding the second insulating layer 31 are omitted as they overlap with the previously mentioned details.

[0137] The metal base layer is a layer used to form the metal mask layer. The metal base layer may contain metal elements. The metal base layer may be composed of a metal material. By using metal elements as the material for the metal base layer, the metal mask layer can have excellent plasma resistance properties during patterning via plasma etching of the second insulating layer 31, contributing to the accurate transfer of patterns to the second insulating layer 31 and the like.

[0138] The metal base layer may contain any one selected from the group consisting of copper, nickel, manganese, iron, tungsten, titanium, and combinations thereof. The metal base layer may contain copper. The metal base layer may contain 95 at% or more of copper. The metal base layer may contain 99 at% or more of copper. The metal base layer may contain 100 at% or less of copper.

[0139] The thickness of the metal base layer may be 100 nm to 1000 nm. The thickness may be 120 nm or more. The thickness may be 150 nm or more. The thickness may be 180 nm or more. The thickness may be 800 nm or less. The thickness may be 500 nm or less. In such cases, a metal mask layer with etching resistance suitable for plasma etching processes can be provided.

[0140] In the process of forming a metal base layer, the metal base layer can be formed by vapor deposition. The metal base layer may also be formed by a PVD (Physical Vapor Deposition) process. The metal base layer may also be formed by sputtering.

[0141] The metal base layer may be formed by methods commonly used in the field of vapor deposition.

[0142] The metal base layer may be placed in contact with the upper surface of the second insulating layer 31. Other components may be placed between the metal base layer and the second insulating layer 31.

[0143] In the process of forming a resist pattern film for a metal mask, a resist pattern film for a metal mask can be formed on the second insulating layer 31. The resist pattern film for a metal mask can function as an etching mask when etching the metal base layer.

[0144] The step of forming a resist pattern film for a metal mask includes a lamination step of laminating a resist film for a metal mask on a second insulating layer 31, and an exposure step of selectively exposing the resist film for a metal mask.

[0145] During the lamination process, a resist film for a metal mask can be laminated on the metal base layer 41. The resist film for the metal mask may be formed in contact with the upper surface of the metal base layer. Other components may be placed between the resist film for the metal mask and the upper surface of the metal base layer.

[0146] In the lamination process, a dry film for a metal mask can be heated and pressurized on a metal base layer using a roll laminator to form a resist film for a metal mask.

[0147] A dry film for a metal mask may be a negative resist film. A resist film for a metal mask may contain a negative resist. A negative resist may be advantageous in suppressing the reduction in pattern accuracy caused by diffraction when realizing a pattern with a fine pitch in a resist film for a metal mask.

[0148] The negative resist film can be any type commonly used in the field of packaging substrates, without limitation. The negative resist film may contain an acrylic resin. For example, Showa Denko's RY-5107 model can be used.

[0149] The thickness of the dry film for the metal mask may be 3 μm to 30 μm. The thickness may be 5 μm or more. The thickness may be 20 μm or less. The thickness may be 15 μm or less. The thickness may be 9 μm or less. In such cases, by adjusting the aspect ratio of the resist pattern film for the metal mask, it is possible to substantially suppress the collapse of the resist pattern film for the metal mask and contribute to precise etching of the metal base layer.

[0150] In the lamination process, the process conditions of the roll laminator can be controlled within a range predetermined in the example. Through this, the resist film for the metal mask and the resist pattern film for the metal mask formed from the resist film for the metal mask are stably fixed and attached to the metal base layer, which helps to precisely transfer the pattern to the metal base layer for the metal mask.

[0151] The roll laminator is not limited to those commonly used in the field of packaging substrates. For example, the ATOCHEM Hot Roller model can be used as a roll laminator.

[0152] In the dry film lamination process for metal masks, the roll pressure of the roll laminator may be 0.3 MPa to 1 MPa. The roll pressure may be 0.4 MPa or higher. The roll pressure may be 0.9 MPa or lower. The roll pressure may be 0.8 MPa or lower. The roll pressure may be 0.7 MPa or lower. In such cases, the dry film can be laminated to the entire upper surface of the metal base layer in close contact with substantially no gaps.

[0153] In the lamination process, the roll temperature of the roll laminator may be 105°C to 130°C. The roll temperature may also be 110°C or higher. The roll temperature may also be 125°C or lower. In such cases, the dry film for the metal mask can have excellent adhesion to the upper surface of the metal base layer.

[0154] In the lamination process, the lamination speed of the roll laminator may be 2 m / min or less. The lamination speed may be 1.9 m / min or less. The lamination speed may be 1.8 m / min or less. The lamination speed may be 1 m / min or more. In such cases, a stable bonding force can be formed between the dry film for the metal mask and the upper surface of the metal base layer. Furthermore, the manufacturing time can be shortened and the process can be made more efficient.

[0155] In the exposure process, the resist film for the metal mask can be selectively exposed. In the exposure process, exposure light can be irradiated onto the resist film for the metal mask according to a pre-designed pattern shape. The exposure light may be irradiated through a selective exposure process using DLT (Digital Lithography Technology), Laser Direct Imaging (LDI) exposure equipment, or a photomask.

[0156] The exposure light can have a tuned wavelength range. Specifically, light with a wavelength of 405 nm can be applied as the exposure light.

[0157] One concrete example is that by applying a controlled exposure amount in the exposure process, a hole pattern can be precisely formed on the resist film for the metal mask to have a pre-designed shape and position.

[0158] The exposure dose for the exposure process was 170 mJ / cm². 2 ~215 mJ / cm² 2 This is possible. The exposure dose is 175 mJ / cm². 2 The above exposure amount may also be 210 mJ / cm². 2 The following may also apply: The exposure dose is 200 mJ / cm². 2 The following may also be the case. In such cases, when forming a fine pattern on a resist film for a metal mask, errors such as the diameter or width of the pattern can be effectively reduced.

[0159] The resist film for the metal mask can be heat-treated after exposure. Through this process, the exposed areas within the resist film for the metal mask can be thoroughly cured overall. This heat treatment can be performed at a temperature of 80°C to 120°C.

[0160] The process for forming a resist pattern film for a metal mask may further include a developing step in which the exposed resist film for the metal mask is developed to form a resist pattern film for the metal mask.

[0161] In the development process, a developer can be used to develop the exposed resist film for the metal mask to form a resist pattern film for the metal mask. In the case of a resist film for a metal mask containing a negative resist as an example, the unexposed areas within the resist film can be developed via the developer. The developer can be any developer commonly used in the field of resists, without any limitations.

[0162] In the development process, a developer can be sprayed onto a resist film for a metal mask to form a resist pattern film for the metal mask. In one example, controlling the spray pressure of the developer can contribute to precisely controlling the overall shape of the resist pattern film for the metal mask.

[0163] In the developing process, the spray pressure of the developer solution may be 0.13 MPa or higher. The spray pressure may be 0.14 MPa or higher. The spray pressure may be 0.3 MPa or lower. In such cases, the areas to be removed by the developer solution within the resist film for the metal mask can be sufficiently removed, and the shape of the resist pattern film for the metal mask can be precisely controlled.

[0164] The developer temperature may be 20°C or higher. The temperature may also be 25°C or higher. The temperature may also be less than 30°C. In such cases, it may be helpful to ensure that the unexposed areas within the resist film for the metal mask are effectively dissolved by the developer.

[0165] In the developing process, the developer can be sprayed from a fixed position, and the base substrate 100 can move continuously in a direction passing through the position. Through this, the developer can be sprayed onto the resist film for the metal mask. When spraying the developer, the moving speed of the base substrate 100 may be 2000 mm / min or less. The moving speed may be 1900 mm / min or less. The moving speed may be 1800 mm / min or less. The moving speed may be 500 mm / min or more.

[0166] In such cases, the unexposed areas within the resist film for the metal mask can be sufficiently dissolved in the developer solution during the development process.

[0167] A resist pattern film for a metal mask can be formed through the development process. The resist pattern film for the metal mask may be placed in contact with the upper surface of the metal base layer. Other components may be placed between the resist pattern film for the metal mask and the upper surface of the metal base layer.

[0168] The resist pattern film for the metal mask may include a hole pattern with a diameter of 20 μm or less. The diameter of the hole pattern may be 15 μm or less. The diameter of the hole pattern may be 12 μm or less. The diameter of the hole pattern may be 10 μm or less. The diameter of the hole pattern may be 0.5 μm or more. Through this, the metal mask layer for the metal mask has a hole pattern with a fine diameter, enabling high-density electrical connection to the second insulating layer 31.

[0169] The hole pattern may be such that the height relative to the diameter is adjusted to a range predetermined in the embodiment. When a hole pattern with a controlled aspect ratio is formed on a resist pattern film for a metal mask in this way, the diameter distribution of the hole pattern within the resist pattern film for the metal mask can be made even more uniform.

[0170] The resist pattern film for metal masks may include hole patterns where the height relative to the diameter is 1.3 or less. The resist pattern film for metal masks may include hole patterns where the height relative to the diameter is 1.2 or less. The resist pattern film for metal masks may include hole patterns where the height relative to the diameter is 1.1 or less. The resist pattern film for metal masks may include hole patterns where the height relative to the diameter is 0.5 or more. In such cases, a hole pattern with an even more uniform diameter distribution can be formed on the resist pattern film for metal masks.

[0171] The second insulating layer formation step may further include a metal mask layer formation process in which a metal base layer is selectively wet-etched using a resist pattern film for a metal mask to provide a metal mask layer. In the metal mask layer formation process, the resist pattern film for a metal mask can be used as an etching mask to form the metal mask layer from the metal base layer. Through this, the pattern of the resist pattern film for a metal mask can be transferred to the metal mask layer.

[0172] In the metal mask layer formation process, the metal base layer can be selectively etched with a liquid etchant to form the metal mask layer. Any liquid etchant commonly used in the field of wet etching can be applied without limitation.

[0173] During the metal mask layer formation process, a liquid etchant is sprayed onto the upper surface of the base substrate 100 on which the resist pattern film for the metal mask is formed, allowing for selective etching of areas within the metal base layer that are not covered by the resist pattern film. The time required for the wet etching process can be adjusted according to the thickness of the metal base layer.

[0174] After the formation of the metal mask layer is complete, the resist pattern film for the metal mask placed on the metal mask layer can be peeled off and removed.

[0175] The second insulating layer formation step may further include a hole pattern formation process in which the second insulating layer 31 is selectively plasma-etched using a metal mask layer to form a hole pattern (not shown) on the second insulating layer 31.

[0176] During the hole pattern formation process, the hole pattern of the metal mask layer is transferred to the second insulating layer 31, thereby forming a hole pattern on the second insulating layer 31.

[0177] During the hole pattern formation process, the metal mask layer can be used as an etching mask, allowing plasma etching to be performed on the portions of the second insulating layer 31 that are not covered by the metal mask layer.

[0178] The hole pattern formation process can be carried out in an atmosphere containing a first etching gas and a second etching gas. The first etching gas may be a fluorine-based gas. The first etching gas may be any one of carbon fluoride, nitrogen fluoride, sulfur fluoride, or a combination thereof. Exemplary examples of carbon fluoride may be any one of CF4, CHF3, CH2F2, CH3F, or a combination thereof. Nitrogen fluoride may be NF3. Sulfur fluoride may be SF6. The first etching gas may be nitrogen fluoride.

[0179] The second etching gas may be oxygen gas.

[0180] During the hole pattern formation process, the etching rate for the second insulating layer 31 can be further increased by applying both the first etching gas and the second etching gas as the ambient gas.

[0181] In the hole pattern formation process, the plasma power may be 1.5 kW or more and 3 kW or less. The plasma power may be 1.7 kW or more. The plasma power may be 2 kW or more. The plasma power may be 2.7 kW or less. The plasma power may be 2.5 kW or less. In such cases, an etching rate of a certain level or higher can be ensured for the second insulating layer 31, and excessive damage to the second insulating layer 31 by plasma etching can be prevented.

[0182] The second insulating layer 31, which includes a hole pattern formed through a hole pattern formation process, may include a hole pattern formed in the thickness direction of the second insulating layer 31. The hole pattern can spatially connect the upper and lower surfaces of the second insulating layer 31. An electrically conductive layer (not shown) may be placed within the hole pattern. The electrically conductive layer placed within the hole pattern can electrically connect an electrically conductive layer placed on the second insulating layer 31 with an electrically conductive layer (not shown) placed below the second insulating layer 31.

[0183] The diameter of the hole pattern may be 20 μm or less. The diameter may be 15 μm or less. The diameter may be 12 μm or less. The diameter may be 10 μm or less. The diameter may be 0.5 μm or more.

[0184] In the hole pattern formation process, the metal mask layer can be removed after the formation of the hole pattern is complete. The metal mask layer can be removed by wet etching.

[0185] An electrically conductive layer can be formed within the hole pattern. The electrically conductive layer may be formed using either the dry or wet method described above. The explanations of the dry and wet methods are omitted here as they overlap with the previously mentioned content.

[0186] Other steps If necessary, a redistribution layer may be further formed below the core layer 10. The redistribution layer formed below the core layer 10 can be formed in the same manner as the first redistribution layer 40, except for the thickness of each layer constituting the redistribution layer.

[0187] If necessary, upper terminals or the like may be further formed on the upper side of the packaging substrate 200, and bumps may be further formed on the lower side of the packaging substrate 200. The bumps can be positioned in a predetermined manner below the redistribution layer located below the core layer 10. For example, the bumps may be positioned on a part of the lower surface of the packaging substrate 200 so as to be in contact with the main board or the like.

[0188] Manufacturing method of a packaging substrate according to other examples Figure 4 is a cross-sectional view illustrating a base substrate according to another embodiment of the embodiment; Figure 5 is a cross-sectional view illustrating a resist pattern film according to another embodiment of the embodiment; Figure 6 is a cross-sectional view illustrating a metal mask layer according to another embodiment of the embodiment; Figure 7 is a cross-sectional view illustrating an insulating pattern layer according to another embodiment of the embodiment; and Figure 8 is a cross-sectional view illustrating a packaging substrate manufactured by the manufacturing method according to another embodiment of the embodiment. The embodiment will be described below with reference to Figures 4 to 8.

[0189] The base substrate 100, core layer, etc., are the same as those described in Figures 1 to 3 above. The differences will be explained below.

[0190] A method for manufacturing a packaging substrate according to another embodiment of the embodiment includes a step of forming a resist pattern film for a metal mask on a base substrate 100 which includes a core layer 10 and a metal base layer 41 formed on the core layer 10.

[0191] In the resist pattern film formation step for a metal mask, a base substrate 100 can be provided, which includes a core layer 10 and a metal base layer 41 formed on the core layer 10. The base substrate 100 may further include a third insulating layer 32 disposed between the core layer 10 and the metal base layer 41.

[0192] The explanation of the base substrate 100 and the core layer 10 will be omitted as it will be redundant with the previous explanation.

[0193] The base substrate 100 may further include a third insulating layer 32 disposed between the core layer 10 and the metal base layer 41. The third insulating layer 32 may be formed in contact with the upper surface of the core layer 10. The base substrate 100 may further include an electrical conductive layer (not shown) disposed between the core layer 10 and the third insulating layer 32. The third insulating layer 32 may be disposed on the electrical conductive layer and surround it.

[0194] The third insulating layer 32 may be an insulating layer having the same composition as the first insulating layer 30 and / or the second insulating layer 31 described above.

[0195] In the resist pattern film formation step for the metal mask, a base substrate 100 may be prepared in which a third insulating layer 32 has already been formed between the core layer 10 and the metal base layer 41. Alternatively, in the resist pattern film formation step for the metal mask, the third insulating layer 32 may be formed on the core layer 10, and the metal base layer 41 may be formed on the third insulating layer 32 to provide the base substrate 100.

[0196] The base substrate 100 may further include a metal base layer 41 formed on the core layer 10. The description of the metal base layer is omitted as it will be redundant with the previous description.

[0197] In the step of forming a resist pattern film for a metal mask, a resist pattern film 43 for a metal mask can be formed on the base substrate 100.

[0198] The resist pattern film formation step includes a lamination process of laminating a resist film for a metal mask onto a base substrate 100, and an exposure process of selectively exposing the resist film for a metal mask. The lamination process described above may be applied during the lamination process. The exposure process described above may be applied during the exposure process. The explanation of the lamination process and the exposure process will be omitted as it will be redundant with the above.

[0199] The resist pattern film formation step may further include a development step in which the exposed resist film for the metal mask is developed to form a resist pattern film 43 for the metal mask. The development steps described above may be applied in the development step. A description of the development step will be omitted as it will be redundant with the above.

[0200] A resist pattern film 43 for a metal mask can be formed through the development process. The resist pattern film 43 for a metal mask may be the resist pattern film for a metal mask described above. The explanation of the resist pattern film 43 for a metal mask will be omitted as it will be redundant with the above.

[0201] The manufacturing method for the packaging substrate in the embodiment may further include a metal mask layer formation step in which a metal base layer is selectively wet-etched using a resist pattern film 43 for a metal mask to provide a metal mask layer 42. In the metal mask layer formation step, the resist pattern film 43 for a metal mask can be used as an etching mask to form the metal mask layer 42 from the metal base layer. Through this, the pattern of the resist pattern film 43 for a metal mask can be transferred to the metal mask layer 42.

[0202] In the metal mask layer formation step, the metal mask layer formation process described above may be applied. The explanation of the metal mask layer formation step will be omitted as it will overlap with the content described above.

[0203] After the formation of the metal mask layer 42 is complete, the resist pattern film 43 for the metal mask placed on the metal mask layer 42 can be peeled off and removed.

[0204] The manufacturing method for the packaging substrate in the embodiment may further include an insulating pattern layer formation step in which an insulating layer is selectively plasma-etched using a metal mask layer 42 to form a third insulating pattern layer 33.

[0205] In the insulating pattern layer formation step, the pattern of the metal mask layer 42 is transferred to the insulating layer to form the third insulating pattern layer 33.

[0206] In the insulating pattern layer formation step, the hole pattern formation process described above may be applied. The explanation of the insulating pattern layer formation step will be omitted as it will overlap with the content described above.

[0207] The method for manufacturing a packaging substrate may further include a manufacturing step of manufacturing a packaging substrate 200 from a base substrate 100 on which a third insulating pattern layer 33 is formed.

[0208] In the manufacturing step, a third electrical conductive layer 60 can be formed on the pattern formed on the third insulating pattern layer 33, particularly on the hole pattern.

[0209] The third electrical conductive layer 60 may be formed using a dry method or a wet method. A description of the dry method and the wet method will be omitted as it will overlap with the above.

[0210] After forming the seed layer, a metal can be plated to form the third electrical conductive layer 60. The third electrical conductive layer 60 can be formed by the same method as the method for forming the first-1 electrical conductive layer 21 described above.

[0211] Further third insulating layers 32 and electrical conductive layers (not shown) can be formed on the third insulating pattern layer 33 and the third electrical conductive layer 60. The third insulating layer 32 and electrical conductive layers arranged on the third insulating pattern layer 33 and the third electrical conductive layer 60 can be formed by the method described above.

[0212] The manufacturing step may further include, if necessary, a process of forming an insulating pattern layer (not shown) and an electrical conductive layer (not shown) to be placed beneath the core layer 10. The insulating pattern layer and electrical conductive layer formed beneath the core layer 10 may be formed by the same method as described above.

[0213] In the manufacturing step, the formation of a redistribution layer having a pre-designed structure can be completed on the upper and / or lower side of the core layer 10, and the packaging substrate 200 can be provided.

[0214] If necessary, upper terminals and the like may be further formed on the top and / or sides of the packaging substrate 200 during the manufacturing step, and bumps may be further formed on the bottom of the packaging substrate 200. The bumps can be positioned in a predetermined form below the redistribution layer located below the core layer 10. Exemplariously, the bumps may be positioned on a portion of the bottom surface of the packaging substrate 200 so as to be in contact with the main board or the like.

[0215] The following examples will provide a more detailed explanation of the implementation through specific embodiments. These embodiments are merely illustrative to aid in understanding the implementation, and the scope of implementation is not limited to them.

[0216] Manufacturing example: Formation of packaging substrates Experimental Example 1: A 150 nm thick titanium layer and a 150 nm thick copper layer were formed on a 400 μm thick glass substrate via PVD. A 15 μm thick copper plating layer was formed on the copper layer by electroplating to complete the first-first electrical conductive layer. A 12.5 μm thick Ajinomoto Build-up Film (ABF), a build-up film, was vacuum laminated onto the first-first electrical conductive layer for 1 minute, heated and pressurized at 120°C and 7 kgf, and then cured at 180°C to form the first insulating layer. The Ra value, which is the arithmetic mean roughness of the upper surface of the first insulating layer according to ISO 4287:1997, was measured to be 3 μm to 5 μm.

[0217] A second seed layer was formed on the first insulating layer via PVD, by creating a 150 nm thick titanium layer and a 150 nm thick copper layer on the titanium layer, thereby completing the base substrate.

[0218] A 25 μm thick dry film was laminated onto the first insulating layer using an ATOCHEM Hot Roller laminator. During lamination, a roll temperature of 115°C, a roll pressure of 0.5 MPa, and a lamination speed of 1.5 m / min were applied.

[0219] The dry film was exposed in a hole pattern shape using an LDI (Low-Density Inspection) device. During exposure, the wavelength of the exposure light was 405 nm and the exposure energy was 55 mJ / cm². 2 The exposure offset was set to -2 μm.

[0220] After exposure, a resist pattern film was formed by spraying developer onto the dry film. The developer spray pressure was 1.5 kPa, the developer temperature was 30°C, and the base substrate movement speed during developer spraying was 1,000 mm / min.

[0221] After forming the resist pattern film, a 15 μm thick copper layer was formed on the second seed layer through an electroplating process to form a second electrical conductive layer. After forming the second electrical conductive layer, the resist pattern film was removed by spraying a stripping solution. When removing the resist pattern film, the spraying pressure of the stripping solution was set to 1.5 kPa and the temperature of the stripping solution was set to 55°C.

[0222] Subsequently, the second seed layer in the region where the second electrical conductive layer was not formed on the upper surface of the first insulating layer was removed by dry etching to complete the packaging substrate.

[0223] Experimental Example 2: A packaging substrate was manufactured under the same conditions as in Experimental Example 1, except that the thickness of the first-first electrical conductive layer was 13 μm, the thickness of the dry film during lamination was 40 μm, the heating roller pressure was 0.6 MPa, the temperature was 120°C, the lamination speed was 1 m / min, the exposure offset was -3 μm during dry film exposure, the base substrate movement speed was 700 mm / min during dry film development, the developer spray pressure was 2 kPa, and the peeling solution temperature was 60°C during the peeling of the resist pattern film.

[0224] Experimental Example 3: A packaging substrate was manufactured under the same conditions as in Experimental Example 2, except that the thickness of the first-1 electrical conductive layer was 14 μm, the exposure offset was -4 μm during dry film exposure, the peeling speed was 800 mm / min during resist pattern film peeling, the peeling solution spray pressure was 2 kPa, and the peeling solution temperature was 60°C.

[0225] Experimental Example 4: Thickness of the first electrical conductive layer: 15 μm, pressure applied during formation of the first insulating layer: 12 kgf, heating roller temperature during dry film lamination: 115°C, lamination speed: 1.5 m / min, exposure power during dry film exposure: 50 mJ / cm² 2 The packaging substrate was manufactured under the same conditions as in Experimental Example 3, except for the application of [specific technology / method].

[0226] The process conditions for each experimental example are listed in Tables 1 to 3 below.

[0227] Evaluation example: Evaluation of whether or not undulation short occurs. The top surface of each experimental example's packaging substrate was scanned and inspected using AOI (Automated Optical Inspection) equipment to evaluate the presence or absence of short circuits in the second electrical conductive layer pattern. The ratio of hole patterns with short circuits to the total number of hole patterns in the second electrical conductive layer of all measured samples was calculated and is shown in Table 3 below.

[0228] Evaluation example: Evaluation of whether or not a resist pattern film remains. While irradiating each experimental example's packaging substrate with UV light, we evaluated whether any dry film residue remained on the packaging substrate using AOI (Automated Optical Inspection) equipment. Specifically, we used the characteristic that dry film residue emits light when irradiated with UV light to confirm whether or not any light-emitting material remained on the packaging substrate via AOI equipment.

[0229] The evaluation results for each experimental example are shown in Table 3 below.

[0230] [Table 1]

[0231] [Table 2]

[0232] [Table 3]

[0233] Referring to Tables 1 to 3, in the evaluation of undulation shortness, experimental examples 2 to 4 were measured at 0%, while experimental example 1 was measured at 100%.

[0234] In evaluating the residue of the resist pattern film, experimental examples 2-4 were measured at 0%, while experimental example 1 was measured at 10%.

[0235] Manufacturing example: Manufacturing of packaging substrates Example 1: An insulating layer was formed on the upper surface of Corning's SG7.8 glass plate by vacuum laminating Ajinomoto's Build-up Film (ABF), and a base substrate was provided.

[0236] A metal base layer was formed on the insulating layer. Specifically, a metal base layer, which is a copper layer with a thickness of 300 nm, was formed on the upper surface of the insulating layer through a sputtering process using a copper target.

[0237] A 7μm thick negative resist dry film, model RY-5107, manufactured by Showa Denko Corporation, was laminated onto a metal base layer using an ATOCHEM Hot Roller laminator. During the lamination process, a roll temperature of 115°C, a roll pressure of 0.5 MPa, and a lamination speed of 1.5 m / min were applied.

[0238] Using Applied Materials' DLT (Digital Lithography Technology) equipment, a dry film was exposed to a hole pattern with a target diameter of 7 μm. During exposure, the wavelength of the exposure light was 405 nm, and the exposure dose was 210 mJ / cm². 2 The exposure focus was set to -3.

[0239] After exposure, the base substrate was guided via a conveyor belt to pass through the area where the developer solution was sprayed. The spray pressure of the developer solution sprayed onto the dry film was set to 0.15 MPa, the developer solution temperature to 27°C, and the base substrate's movement speed during developer spraying to 1700 mm / min. After the developer spraying was complete, the dry film was developed to form a resist pattern film.

[0240] A metal mask layer was formed by selectively wet etching the metal base layer using a resist pattern film. During wet etching, an etchant containing 10% by weight of sodium persulfate and water as the solvent was applied.

[0241] After forming a metal mask layer, a stripping solution was sprayed onto the composite resist pattern film, and then the composite resist pattern film was peeled off and removed.

[0242] A base substrate with a metal mask layer formed on it was placed in an etching chamber, and a hole pattern was formed on the insulating layer by plasma etching. During plasma etching, the plasma power was set to 1.5kW to 3kW, and 150 sccm of NF3 was supplied to the chamber as the first etching gas and 150 sccm of O2 as the second etching gas.

[0243] Subsequently, the metal mask layer was removed using the etchant applied during the formation of the metal mask layer, and the packaging substrate was manufactured.

[0244] Example 2: When exposing a dry film, the exposure amount was 180 mJ / cm². 2 The packaging substrate was manufactured under the same conditions as in Example 1, except that the exposure focus was set to -4.

[0245] Comparative Example 1: As the dry film, Showa Denko's RY-5110 model negative resist dry film with a thickness of 10 μm was used, and the exposure dose was 280 mJ / cm². 2The packaging substrate was manufactured under the same conditions as in Example 1, except that the developer temperature was set to 30°C, the developer spray pressure to 0.08 MPa, and the base substrate movement speed by the conveyor belt during developer spraying was set to 2100 mm / min.

[0246] Comparative Example 2: Exposure dose 165 mJ / cm² 2 The packaging substrate was manufactured under the same conditions as in Example 1, except that it was applied as exposure focus -5.

[0247] The process conditions for each example and comparative example are shown in Table 4 below.

[0248] Evaluation example: Evaluation of the diameter of hole patterns within a resist pattern film. During the manufacturing process of the packaging substrates for each example and comparative example, the average diameter of the hole patterns formed on the resist pattern film was measured and calculated using an optical microscope.

[0249] The ratio of the calculated average diameter to the target diameter of the hole pattern, which is 7 μm, was calculated.

[0250] The measured values ​​for each example and comparative example are shown in Table 5 below.

[0251] [Table 4]

[0252] [Table 5]

[0253] In Table 5 above, the ratio of the average diameter of the pattern hole to the target diameter was 100% for Examples 1 and 2, while the value for Comparative Example 1 was only 40%, and Comparative Example 2 showed a value exceeding 100%.

[0254] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements by those skilled in the art, utilizing the basic concepts of the present invention as defined in the appended claims, also fall within the scope of the present invention. [Explanation of symbols]

[0255] 100 base board 10 core layers 20 First electrical conduction layer 21. First-1 Electrical Conduction Layer 22. First and second electrical conduction layers 23. Second Seed Tier 24 Second electrical conduction layer 30 First insulating layer 31. Second insulating layer 32 Third insulating layer 33 Third insulating pattern layer 40 1st redistribution layer 41 Metal base layer 42 Metal mask layer 43. Resist pattern film for metal masks 50 Resist pattern film 60 Third electrical conduction layer 200 Packaging substrates

Claims

1. A packaging substrate is manufactured comprising: a preparation step of providing a base substrate including a core layer, a first redistribution layer disposed on the core layer, and a second seed layer disposed on the first redistribution layer; a resist pattern film formation step of forming a resist pattern film on the second seed layer; and a second electrical conductive layer formation step of forming a second electrical conductive layer from the second seed layer. The first redistribution layer includes a first electrical conductive layer and a first insulating layer surrounding at least a portion of the first electrical conductive layer. The first electrical conductive layer includes a first-first electrical conductive layer located closest to the second seed layer. A method for manufacturing a packaging substrate, wherein the ratio of the thickness of the resist pattern film to the thickness of the first-1 electrical conductive layer is 1.8 to 4.

2. The method for manufacturing a packaging substrate according to claim 1, wherein the thickness of the resist pattern film is 30 μm to 50 μm.

3. The method for manufacturing a packaging substrate according to claim 1, wherein the thickness of the first-1 electrical conductive layer is 20 μm or less.

4. The method for manufacturing a packaging substrate according to claim 1, wherein the resist pattern film formation step includes a dry film lamination step of laminating a dry film on the second seed layer, and a development step of patterning the dry film to form the resist pattern film.

5. The method for manufacturing a packaging substrate according to claim 4, wherein in the dry film lamination process, the dry film is laminated on the second seed layer using a roll laminator, and the roll pressure of the roll laminator is 0.55 MPa to 1 MPa.

6. The method for manufacturing a packaging substrate according to claim 4, wherein in the dry film lamination process, the roll temperature of the roll laminator is 110°C to 140°C.

7. The method for manufacturing a packaging substrate according to claim 4, wherein in the dry film lamination process, the lamination speed of the roll laminator is 2 m / min or less.

8. The method for manufacturing a packaging substrate according to claim 1, wherein the arithmetic mean roughness Ra of the first redistribution layer is 1 μm to 10 μm.

9. The process further includes a second insulating layer forming step of forming a second insulating layer including a hole pattern on the second electrical conductive layer, The method for manufacturing a packaging substrate according to claim 1, wherein the second insulating layer formation step includes a second insulating layer formation step of forming a second insulating layer on the second electrical conductive layer, a metal base layer formation step of forming a metal base layer disposed on the second insulating layer, and a metal mask resist pattern film formation step of forming a resist pattern film for a metal mask on the second insulating layer.

10. The process for forming a resist pattern film for a metal mask includes a lamination step of laminating a resist film for a metal mask on the metal base layer, and an exposure step of selectively exposing the resist film for a metal mask. The resist pattern film for the metal mask includes a hole pattern with a diameter of 20 μm or less. The resist film for the metal mask includes a negative resist, The exposure dose during the aforementioned exposure process was 170 mJ / cm². ２ ~215 mJ / cm² ２ The method for manufacturing a packaging substrate according to claim 9.

11. The step includes forming a resist pattern film for a metal mask on a base substrate which includes a core layer and a metal base layer formed on the core layer, The step of forming a resist pattern film for a metal mask includes a lamination process of laminating a resist film for a metal mask onto the base substrate, and an exposure process of selectively exposing the resist film for a metal mask. The resist pattern film for the metal mask includes a hole pattern with a diameter of 20 μm or less. The resist film for the metal mask includes a negative resist, The exposure dose during the aforementioned exposure process was 170 mJ / cm². ２ ~215 mJ / cm² ２ A method for manufacturing a packaging substrate.

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