Semiconductor device including a storage node and method for manufacturing it

Abstract

This paper presents a semiconductor device including a storage node and a method for manufacturing it. [Solution] The method for manufacturing a semiconductor device involves forming an insulating layer on a substrate and forming a first hole and a second hole penetrating the insulating layer. A recess is formed in the insulating layer superimposed on the first hole. The recess may be formed so as to superimpose on the first hole and extend outward from the first hole. A first conductive pattern is formed to fill the first hole and the recess, and a second conductive pattern is formed to fill the second hole. A third conductive pattern is formed connected to the second conductive pattern. The second and third conductive patterns can constitute a storage node for a capacitor.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit device, and more particularly, to a semiconductor device including a storage node and a manufacturing method thereof.

Background Art

[0002] With the high integration of semiconductor devices, the circuit patterns constituting the semiconductor devices are being miniaturized. Attempts have been made to increase the capacitance of capacitors among the circuit elements constituting the semiconductor devices.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure presents a method for manufacturing a semiconductor device including a storage node that improves the capacitance of a capacitor.

[0004] The present disclosure presents a semiconductor device including a storage node that improves the capacitance of a capacitor.

Means for Solving the Problems

[0005] The present disclosure presents a method for manufacturing a semiconductor device, including steps of forming an insulating layer on a substrate, forming a first hole and a second hole penetrating the insulating layer, forming a recess overlapping the first hole in the insulating layer, forming a first conductive pattern filling the first hole and the recess, and a second conductive pattern filling the second hole, and forming a third conductive pattern connected to the second conductive pattern.

[0006] This disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: forming an insulating layer on a substrate; forming a first hole, a trench, and a second hole so as to penetrate the insulating layer, wherein the trench divides the insulating layer into a first portion and a second portion; forming a first conductive pattern that fills the first hole, a fifth conductive pattern that fills the trench, and a second conductive pattern that fills the second hole; forming a third conductive pattern connected to the second conductive pattern; and removing the second portion of the insulating layer to expose the first side surface of the second conductive pattern.

[0007] This disclosure presents a semiconductor device comprising: an insulating layer formed on the first region of a substrate including a first region and a second region; a first conductive pattern penetrating the insulating layer; a second conductive pattern formed on the second region of the substrate; a third conductive pattern connected to the second conductive pattern; and a binding layer covering the first conductive pattern and the insulating layer and connected to the third conductive pattern. [Effects of the Invention]

[0008] According to embodiments of this disclosure, a method for manufacturing a semiconductor device including a storage node that improves the capacitance of a capacitor can be presented. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view showing a structure in which a protective layer has been formed on a semiconductor device according to one embodiment. [Figure 2] This is a schematic cross-sectional view showing a structure in which an insulating layer is formed on a protective layer of a semiconductor device according to one embodiment. [Figure 3] These are schematic cross-sectional and plan views showing a structure in which holes and trenches are formed in the insulating layer of a semiconductor device according to one embodiment. [Figure 4]These are schematic cross-sectional and plan views showing a structure in which holes and trenches are formed in the insulating layer of a semiconductor device according to one embodiment. [Figure 5] These are schematic cross-sectional and plan views showing a structure in which a recess is formed in the insulating layer of a semiconductor device according to one embodiment. [Figure 6] These are schematic cross-sectional and plan views showing a structure in which a recess is formed in the insulating layer of a semiconductor device according to one embodiment. [Figure 7] This is a schematic cross-sectional view showing a structure in which a conductive layer is formed on an insulating layer of a semiconductor device according to one embodiment. [Figure 8] This is a schematic cross-sectional view showing the structure of a semiconductor device with its conductive pattern separated according to one embodiment. [Figure 9] This is a schematic cross-sectional view showing a structure in which a binding layer has been formed on a semiconductor device according to one embodiment. [Figure 10] This is a schematic cross-sectional view showing a structure in which an opening is formed in the binding layer of a semiconductor device according to one embodiment. [Figure 11] This is a schematic cross-sectional view showing a structure in which a mold layer has been formed on a semiconductor device according to one embodiment. [Figure 12] This is a schematic cross-sectional view showing a structure in which holes are formed in the mold layer of a semiconductor device according to one embodiment. [Figure 13] This is a schematic cross-sectional view showing a structure in which a conductive pattern is formed on the mold layer of a semiconductor device according to one embodiment. [Figure 14] This is a schematic cross-sectional view showing a structure in which an opening is formed in another binding layer of a semiconductor device according to one embodiment. [Figure 15] This is a schematic cross-sectional view showing a structure in which a portion of the mold layer of a semiconductor device according to one embodiment has been removed. [Figure 16] This is a schematic cross-sectional view showing a structure in which an opening is formed in yet another binding layer of a semiconductor device according to one embodiment. [Figure 17] This is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment, with the mold layer removed. [Figure 18]It is a schematic cross-sectional view showing a structure in which a part of an insulating layer of a semiconductor device according to an embodiment is removed. [Figure 19] It is a schematic cross-sectional view showing a structure in which a capacitor dielectric layer of a semiconductor device according to an embodiment is formed. [Figure 20] It is a schematic cross-sectional view showing a structure in which other conductive patterns of a semiconductor device according to an embodiment are formed.

Mode for Carrying Out the Invention

[0010] The terms used in the description of the present disclosure are terms selected in consideration of the functions in the presented embodiments, and the meanings of those terms vary depending on the intentions or conventions of users and operators in the technical field. The meaning of the terms used shall be interpreted according to the defined definitions when specifically defined in this specification, and in the absence of a specific definition, it can be interpreted in the meaning generally recognized by those skilled in the art.

[0011] In the description of the present disclosure, descriptions such as "first", "second", etc. are for distinguishing components, and are not used as limiting the components themselves or meaning a specific order. In the description of the present disclosure, descriptions such as "top surface", "bottom surface", "side", etc. do not limit a specific direction, position, or component. Descriptions such as "below", "beneath", "lower", "above", "over", "upper", etc. can be used to describe the spatially relative positions between components.

[0012] Embodiments of the present disclosure are applicable to the technical field of realizing integrated circuit elements such as DRAM, PcRAM, or ReRAM elements. Also, embodiments of the present disclosure are applicable to the technical field of realizing memory elements for storing data and logic elements for performing logical operations. Embodiments of the present application are applicable to the technical field of realizing various products that require fine-sized conductive patterns.

[0013] Throughout the specification, the same reference numerals can refer to the same components. Even if the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they can be described by referring to other drawings. Also, even if the reference numerals are not shown, they can be described by referring to other drawings.

[0014] Figures 1 to 20 are schematic diagrams showing a semiconductor device and a manufacturing method according to an embodiment.

[0015] Figure 1 shows a schematic cross-sectional structure in which a protection layer (protection layer: 410) is formed on a substrate 100. The substrate 100 can have a surface extending in a first direction D1 and a second direction D2. The protection layer 410 may be formed spaced apart from the surface of the substrate 100 in a third direction D3. The first direction D1 intersects the second direction D2, and the third direction D3 may be a direction perpendicular to the first and second directions D1 and D2. The first, second, and third directions D1, D2, and D3 can indicate the X-axis, Y-axis, and Z-axis in the X - Y - Z coordinate system, but are not limited thereto.

[0016] The substrate 100 can include a semiconductor material such as silicon (Si). An integrated circuit such as a transistor can be integrated on the substrate 100. The substrate 100 can include silicon germanium (SiGe). The substrate 100 can include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0017] The substrate 100 may include an isolation layer 103 that defines an active region 101. The active region 101 may be doped with impurities. The active region 101 may be used as the source region, drain region, or channel of a transistor. The isolation layer 103 may include a field oxide layer. The isolation layer 103 may include silicon oxide 2 containing silicon dioxide (SiO2) or silicon nitride such as silicon tritetranitride (Si3N4).

[0018] The substrate 100 may include a first region 100P and a second region 100C. The first region 100P of the substrate 100 may be a peripheral region, and the second region 100C of the substrate 100 may be a cell region. The first region 100P of the substrate 100 may be a region surrounding the second region 100C of the substrate 100. Memory cells may be located in the second region 100C of the substrate 100, and peripheral circuits may be located in the first region 100P of the substrate 100. The memory cells may include elements that store data, such as transistors and / or capacitors. The peripheral circuits may include circuits that control the operation of the memory cells, such as sense amplifiers (SAs) and sub-word line drivers (SWDs).

[0019] Various substructures may be formed between the substrate 100 and the protective layer 410. The substructure may include various insulating and conductive layers. In an exemplary embodiment, a first insulating layer 310 may be formed on the substrate 100, and a first contact 210P, a second contact 210C, and a third contact 210G may be formed substantially through the first insulating layer 310. The first contact 210P and the second contact 210C may be connection elements that electrically connect to the active region 101 of the substrate 100. The connection elements may be conductive plugs or conductive vias. The first contact 210P may be located on a first region 100P of the substrate, and the second contact 210C may be located on a second region 100C of the substrate. The third contact 210G may be located at the boundary between the first region 100P and the second region 100C of the substrate. The third contact 210G is formed of a conductive material, but may also be a dummy pattern connected to the element isolation layer 103 of the substrate 100.

[0020] The first contact 210P, the second contact 210C, and the third contact 210G may contain conductive material. The first contact 210P, the second contact 210C, and the third contact 210G may contain tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium tungsten nitride (TiWN), tungsten silicon nitride (WSiN), or composite layers thereof. The first contact 210P, the second contact 210C, and the third contact 210G may contain impurity-doped polysilicon (polycrystalline silicon layer). The first insulating layer 310 may contain a dielectric material such as silicon oxide.

[0021] The protective layer 410 can cover, protect, or shield the underlying structure, including the first insulating layer 310, the first contact 210P, the second contact 210C, and the third contact 210G. The protective layer 410 may contain a dielectric material different from that of the first insulating layer 310. The protective layer 310 may be formed containing silicon nitride.

[0022] Figure 2 shows a schematic cross-sectional structure in which a second insulating layer 330 is formed on a protective layer 410. The second insulating layer 330, which contains a different insulating material or a different dielectric material than the protective layer 410, is formed on the protective layer 410. The second insulating layer 330 may be formed containing a different dielectric material than the protective layer 410. The second insulating layer 330 may be formed containing silicon oxide.

[0023] Figure 3 shows a schematic cross-sectional structure in which a first hole (510P), a trench (510G), and a second hole 510C are formed in the second insulating layer 330. Figure 4 shows a schematic planar structure in which a first hole 510P, a trench 510G, and a second hole 510C are formed in the second insulating layer 330. Figure 3 can show the cross-sectional shape along the A1-A2 cutting line in Figure 4. The first hole 510P, the trench 510G, and the second hole 510C can be formed by removing a portion of the second insulating layer 330. The first hole 510P, the trench 510G, and the second hole 510C can substantially penetrate the second insulating layer 330 in a third direction D3.

[0024] Multiple first holes 510P may be arranged on the first region 100P of the substrate 100. Multiple second holes 510C may be arranged in an array on the second region 100C of the substrate 100. A trench 510G may be formed at the boundary between the first region 100P and the second region 100C of the substrate 100. The trench 510G can extend along the boundary between the first region 100P and the second region 100C of the substrate 100. The trench 510G may be formed in a line shape that extends long in one direction. The trench 510G may extend to surround the second holes 510C or to surround an array of second holes 510C. The trench 510G may be formed in a ring shape or a loop shape.

[0025] Trench 510G can divide the second insulating layer 330 into a first portion 330P and a second portion 330C. The first portion 330P of the second insulating layer 330 can be superimposed on a first region 100P of the substrate 100, and the second portion 330C of the second insulating layer 330 can be superimposed on a second region 100C of the substrate 100. The first hole 510P can extend along a third direction D3 so as to substantially penetrate the first portion 330P of the second insulating layer 330. The second hole 510C can extend along a third direction D3 so as to substantially penetrate the second portion 330C of the second insulating layer 330. The first hole 510P, trench 510G, and second hole 510C can further extend along a third direction D3 so as to substantially penetrate the protective layer 410 beneath the second insulating layer 330. The first hole 510P may be formed to expose a portion of the lower first contact 210P. The trench 510G may be formed to expose a portion of the lower third contact 210G. The second hole 510C may be formed to expose a portion of the lower second contact 210C.

[0026] The first hole 510P, the trench 510G, and the second hole 510C may be formed simultaneously. The first hole 510P, the trench 510G, and the second hole 510C may be formed in a single, identical first patterning process. In an exemplary embodiment, the first hole 510P, the trench 510G, and the second hole 510C can be formed by forming a first etching mask (not shown) on the second insulating layer 330 by a first photolithography process, and etching a portion of the second insulating layer 330 exposed to the first etching mask. The first etching mask may include a first photoresist pattern or further include a first hard mask having a pattern shape substantially identical to that of the first photoresist pattern.

[0027] The first photoresist pattern that can be realized on the second insulating layer 330 by the first photolithography process can have a planar pattern shape substantially identical to the planar pattern shape on the surface of the second insulating layer 330 shown in Figure 4. Since the first holes 510P, trenches 510G, and second holes 510C may have different sizes, widths, or shapes from each other, the first photoresist pattern to realize this can be formed using a high numerical aperture extreme ultraviolet lithography apparatus.

[0028] Figure 5 shows a schematic cross-sectional structure in which recesses (510PD, 510GD) are formed in the second insulating layer 330. Figure 6 shows a schematic planar structure in which recesses 510PD, 510GD are formed in the second insulating layer 330. Figure 5 can show the cross-sectional shape along the A1-A2 cutting line in Figure 6. Recesses 510PD, 510GD can be formed by further removing an additional portion of the second insulating layer 330. Recesses 510PD, 510GD can have a groove shape that does not penetrate the second insulating layer 330 in the third direction D3, or a trench shape that does not penetrate the second insulating layer 330 in the third direction D3.

[0029] In an exemplary embodiment, a portion of the second insulating layer 330 may be further removed to form a first recess 510PD superimposed on the first hole 510P. The first recess 510PD may be formed in a line shape, with a portion superimposed on the first hole 510P and another portion extending away from the first hole 510P. The first recess 510PD may extend for a long distance in a first direction D1, a second direction D2, or a direction between the first direction D1 and the second direction D2. In an exemplary embodiment, a portion of the second insulating layer 330 may be further removed to form a second recess 510GD superimposed on the trench 510G. The second recess 510GD may be an upper trench extending to superimpose on the lower trench 510G. In other embodiments, the formation of the second recess 510PG may be omitted.

[0030] The first recess 510PD and the second recess 510GD may be formed simultaneously. The first recess 510PD and the second recess 510GD may be formed in a single, identical second patterning step. In an exemplary embodiment, the first recess 510PD and the second recess 510GD can be formed by a second photolithography step, which forms a second etching mask (not shown) on the second insulating layer 330, and etching a portion of the second insulating layer 330 exposed to the second etching mask. The second etching mask may further include a second photoresist pattern or a second hard mask having a pattern shape substantially identical to that of the second photoresist pattern.

[0031] Before etching the first recess 510PD and the second recess 510GD, a sacrificial layer (not shown) can be further formed to fill the first hole 510P, the trench 510G, and the second hole 510C. The sacrificial layer can protect the first hole 510P, the trench 510G, and the second hole 510C from the etching process of the first recess 510PD and the second recess 510PG. The sacrificial layer can suppress or reduce unintentional damage to the first hole 510P, the trench 510G, and the second hole 510C by the etching process of the first recess 510PD and the second recess 510PG. After the first recess 510PD and the second recess 510PG are formed, the sacrificial layer is removable. The sacrificial layer may be formed containing a different dielectric material than the second insulating layer 330. The sacrificial layer may contain the same carbon as the spin-on-carbon (SoC) layer.

[0032] Figure 7 shows a schematic cross-sectional structure in which conductive layers 610 and 620 are formed on the second insulating layer 330. Conductive layers 610 and 620 are formed by depositing a conductive material onto the second insulating layer 330. In an exemplary embodiment, a first conductive layer 610 can be formed on the second insulating layer 330. The first conductive layer 610 may be formed to fill the second hole 510C and extend into the first recess 510PD and the first hole 510P. The first conductive layer 610 may be formed to further extend into the second recess 510GD and the trench 510G. In an exemplary embodiment, the width of the first recess 510PD and the diameter of the first hole 510P may be wider than the diameter of the second hole 510C. The first conductive layer 610 may not completely fill the first recess 510PD and the first hole 510P. A second conductive layer 620 can be further formed on the first conductive layer 610, substantially filling the first recess 510PD and the first hole 510P. In exemplary embodiments, the widths of the second recess 510GD and the trench 510G may be wider than the diameter of the second hole 510C. The second conductive layer 620 can extend to substantially fill the second recess 510GD and the trench 510G. Since the second hole 510C is filled by the first conductive layer 610, the second conductive layer 620 does not extend into the second hole 510C.

[0033] The second conductive layer 620 may contain a different conductive material than the first conductive layer 610. The first conductive layer 610 may contain titanium nitride (TiN). The second conductive layer 620 may contain tungsten (W). The first conductive layer 610 may contain a barrier metal layer over the second conductive layer 620. The barrier metal layer can prevent the conductive material of the second conductive layer 620 from unintentionally diffusing or contaminating the surrounding area. The first conductive layer 610 may contain titanium nitride (TiN), tungsten nitride (WN), titanium tungsten nitride (TiWN), tungsten silicon nitride (WSiN), or a composite layer thereof.

[0034] Figure 8 shows a schematic cross-sectional structure in which conductive layers 610 and 620 are separated into a first conductive pattern 610P, a fifth conductive pattern 610G, and a second conductive pattern 610C. The designations "first conductive pattern," "second conductive pattern," and "fifth conductive pattern" are for distinction from the "third conductive pattern" and "fourth conductive pattern" described later, and do not indicate a specific order. Parts of conductive layers 610 and 620 can be removed to expose the surface of the underlying second insulating layer 330. Parts of the second conductive layer 620 can be removed, and the portion of the first conductive layer 610 that is exposed after the removal of the second conductive layer 620 can be further removed. Conductive layers 610 and 620 can be chemically mechanically polished (CMP) to expose the surface of the underlying second insulating layer 330. This allows the first conductive pattern 610P, the fifth conductive pattern 610G, and the second conductive pattern 610C to be separated from each other from the first and second conductive layers 610 and 620.

[0035] The first conductive pattern 610P is separable by an interconnection that fills the first recess 510PD and the first hole 510P. The interconnection may include a via portion that fills the first hole 510P and a wiring portion that fills the first recess 510PD. The via portion may be indicated by a conductive contact or a conductive plug. Since the via portion is electrically connectable to the active region 103 of the substrate 100, the interconnection is electrically connectable to the substrate 100.

[0036] The first conductive pattern 610P can be formed by a process in which a first hole 510P is formed in the second insulating layer 330, followed by the formation of a first recess 510PD, and then conductive layers 610 and 620 that fill the first recess 510PD and the first hole 510P. In this way, the first conductive pattern 610P can be formed by applying a dual damascene process.

[0037] The second conductive pattern 610C may include a first storage node filling the second hole 510C from the first conductive layer 610. To improve the semiconductor device, an attempt can be made to increase the capacitance of the capacitor by increasing the height of the capacitor's storage node. To increase the height of the capacitor's storage node, the capacitor's storage node can be configured in a multi-stage structure. The first storage node may be part of the multi-stage structure. In an exemplary embodiment, the second conductive pattern 610C may have a pillar shape filling the second hole 510C.

[0038] The fifth conductive pattern 610G may include a protection guard that fills the second recess 510GD and the trench 510G. As shown in Figure 4, since the trench 510G divides the second insulating layer 330 into a first portion 330P and a second portion 330C, the protection guard can divide the second insulating layer 330 into a first portion 330P and a second portion 330C.

[0039] Figure 9 shows a schematic cross-sectional structure in which a first binding layer (420) is formed covering the second insulating layer 330. The first binding layer 420 may be formed to cover the second insulating layer 330, the first conductive pattern 610P, and the second conductive pattern 610C. The first binding layer 420 may extend further to cover the fifth conductive pattern 610G. The first binding layer 420 can protect the second insulating layer 330 and cover and insulate the first conductive pattern 610P, the second conductive pattern 610C, and the fifth conductive pattern 610G.

[0040] The first binding layer 420 is formed by comprising a dielectric material different from that of the second insulating layer 330, or a different insulating material. In exemplary embodiments, the first binding layer 420 may include a silicon nitride such as trisilicon tetranitride (Si3N4). The first binding layer 420 may be formed to have a thinner thickness than the second insulating layer 330. The first binding layer 420 can indicate a nitride floating capacitor (NFC) structure.

[0041] Figure 10 shows a schematic cross-sectional structure in which a first opening (opening: 420H) is formed in the first binding layer 420. A portion of the first binding layer 420 is removed to form the first opening 420H that substantially penetrates the first binding layer 420. A portion of the second portion 330C of the second insulating layer 330 can be exposed in the first opening 420H. The first opening 420H is formed to be located on the second portion 330C of the second insulating layer 330, and not on the first portion 330P of the second insulating layer 330. The first opening 420H is formed closer to the second conductive pattern 610C than to the first conductive pattern 610P. The first opening 420H can be positioned to overlap a portion of the second portion 330C of the second insulating layer 330 between the second conductive patterns 610C.

[0042] Figure 11 shows a schematic cross-sectional structure in which mold layers 350 and 370 are formed on the first binding layer 420. The mold layers 350 and 370 are formed on the first binding layer 420 as sacrificial layers. The mold layers 350 and 370 may be formed containing a different dielectric material or a different insulating material than the first binding layer 420. In exemplary embodiments, the mold layers 350 and 370 may be formed containing a borophosphosilicate glass (BPSG) layer, a tetraethyl orthosilicate (TEOS) layer, an amorphous carbon layer, or a composite layer thereof. The mold layers 350 and 370 may also be formed containing an oxide-nitride (ON) layer in which silicon oxide layers and silicon nitride layers are alternately repeated.

[0043] In exemplary embodiments, the mold layers 350 and 370 may be formed as a multilayer structure including a lower first mold layer 350 and an upper second mold layer 370. A second binding layer 450 may be further formed between the first mold layer 350 and the second mold layer 370. After forming the first mold layer 350 and the second binding layer 450 covering the first mold layer 350, the second mold layer 370 can be formed covering the second binding layer 450. By forming the mold layers 350 and 370 in a multilayer structure in this way, the overall thickness of the mold layers 350 and 370 can be increased. A third binding layer 470 can be further formed covering the second mold layer 370. The second binding layer 450 and the third binding layer 470 may be formed containing a different dielectric material or a different insulating material than the mold layers 350 and 370. The second binding layer 450 and the third binding layer 470 may be formed to a thickness thinner than the first and second mold layers 350 and 370. In exemplary embodiments, the second binding layer 450 and the third binding layer 470 may be formed containing silicon nitride.

[0044] The molded layers 350 and 370 are connectable to the lower second insulating layer 330 via the first opening 420H of the first binding layer 420. Since the first molded layer 350 fills the first opening 420H of the first binding layer 420, the first molded layer 350 is connectable to the second portion 330C of the second insulating layer 330 that is exposed at the first opening 420H.

[0045] Figure 12 shows a schematic cross-sectional structure in which a third hole 550C is formed through the mold layers 350 and 370. A portion of the mold layers 350 and 370 and the binding layers 420, 450, and 470 are removed to form a third hole 550C that substantially penetrates the mold layers 350 and 370 and the binding layers 420, 450, and 470. Multiple third holes 550C may be formed on the second portion 330C of the second insulating layer 330. Multiple third holes 550C may be formed on the second region 100C of the substrate 100. The third hole 550C may be formed to expose a portion of the lower second conductive pattern 610C.

[0046] In an exemplary embodiment, a third etching mask (not shown) can be formed on the third binding layer 470 by a third photolithography step, and a portion of the third binding layer 470 exposed by the third etching mask can be etched and removed. The third etching mask may further include a third photoresist pattern or a third hard mask having a pattern shape substantially identical to that of the third photoresist pattern. The portion of the second mold layer 370 exposed after a portion of the third binding layer 470 has been removed can be sequentially removed, and the portion of the second binding layer 450 exposed after a portion of the second mold layer 370 has been removed can be further removed. The portion of the first mold layer 350 exposed after a portion of the second binding layer 450 has been removed can be further removed, and the portion of the first binding layer 420 exposed after a portion of the first mold layer 350 has been removed can be removed to form a third hole 550C.

[0047] Figure 13 shows a schematic cross-sectional structure in which a third conductive pattern 650C is formed and connected to a second conductive pattern 610C. A third conductive layer is formed on the third binding layer 470 so as to fill the third holes 550C. By removing a portion of the third conductive layer, the third conductive patterns 650C that each fill the third holes 550C can be separated from the third conductive layer. The third conductive pattern 650C may also be a second storage node connected to the second conductive pattern 610C, which is a first storage node. The second conductive pattern 610C and the third conductive pattern 650C can be stacked to form a storage node for a capacitor.

[0048] Figure 14 shows a schematic cross-sectional structure in which a second opening 470HC and a third opening 470HP are formed in the third binding layer 470. Further removal of an additional portion of the third binding layer 470 forms the second opening 470HC and the third opening 470HP that substantially penetrate the third binding layer 470. The second opening 470HC and the third opening 470HP can expose a portion of the second mold layer 370 located beneath the third binding layer 470. The second opening 470HC may be located on the second portion 330C of the second insulating layer 330, and the third opening 470HP may be located on the first portion 330P of the second insulating layer 330. The second opening 470HC may be located on the second region 100C of the substrate 100, and the third opening 470HP may be located on the first region 100P of the substrate 100.

[0049] Figure 15 shows a schematic cross-sectional structure with the second mold layer (370 in Figure 14) removed. Referring to Figures 14 and 15, the second mold layer 370 below the third binding layer 470 is removed through the second opening 470HC and the third opening 470HP of the third binding layer 470. Etchant can be allowed to flow into the second mold layer 370 through the second opening 470HC and the third opening 470HP of the third binding layer 470, and the second mold layer 370 can be removed by the incoming etchant.

[0050] The remaining portion of the third binding layer 470 is connected to the third conductive pattern 650C, allowing the third conductive pattern 650C to be bound together. The third conductive pattern 650C is bound together with the third binding layer 470, and the third conductive pattern 650C can be supported by the third binding layer 470 without falling over.

[0051] Figure 16 shows a schematic cross-sectional structure in which the fourth opening 450HC and the fifth opening 450HP are formed in the second binding layer 450. After removing the second mold layer 370, a portion of the second binding layer 450 that is exposed after the removal of the second mold layer 370 can be further removed. While a portion of the second binding layer 450 is removed, the fourth opening 450HC and the fifth opening 450HP that substantially penetrate the second binding layer 450 can be formed. The portion of the second binding layer 450 exposed to the remaining third binding layer 470 and the third conductive pattern 650C can be etched away. Such an etching process may be performed by an anisotropic etching process using the remaining third binding layer 470 and the third conductive pattern 650C as etching masks. The fourth opening 450HC of the second binding layer 450 can be aligned so as to overlap the second opening 470HC of the third binding layer 470 in the third direction D3. The fifth opening 450HP of the second binding layer 450 can be aligned so as to overlap the third opening 470HP of the third binding layer 470 in the third direction D3.

[0052] The fourth opening 450HC and the fifth opening 450HP can expose a portion of the first mold layer 350 located beneath the second binding layer 450. The fourth opening 450HC may be located on the second portion 330C of the second insulating layer 330, and the fifth opening 450HP may be located on the first portion 330P of the second insulating layer 330. The fourth opening 450HC may be located on the second region 100C of the substrate 100, and the fifth opening 450HP may be located on the first region 100P of the substrate 100.

[0053] Figure 17 shows a schematic cross-sectional structure with the first mold layer (350 in Figure 16) removed. Referring to Figures 16 and 17, the first mold layer 350 below the second binding layer 450 is removed through the fourth opening 450HC and the fifth opening 450HP of the second binding layer 450. Etchant can be allowed to flow into the first mold layer 350 through the fourth opening 450HC and the fifth opening 450HP of the second binding layer 450, and the first mold layer 350 can be removed by the incoming etchant. By removing the first mold layer 350 in this way, the first opening 420H of the first binding layer 420 can be exposed. A portion of the second part 330C of the lower second insulating layer 330 can be exposed at the first opening 420H of the first binding layer 420.

[0054] The remaining portion of the second binding layer 450 is connected to the third conductive pattern 650C, allowing the third conductive pattern 650C to be bound together. The third conductive pattern 650C is bound together with the second binding layer 450, and the third conductive pattern 650C can be supported by the second binding layer 450 without falling over.

[0055] Figure 18 shows a schematic cross-sectional shape after removing the second portion (330C in Figure 17) of the second insulating layer (330 in Figure 17). Referring to Figures 17 and 18, the second portion 330C, which is a part of the second insulating layer 330 below the first binding layer 420, is removed through the first opening 420H of the first binding layer 420. Etchant can be allowed to flow into the second portion 330C of the second insulating layer 330 through the first opening 420H of the first binding layer 420, so that the second portion 330C of the second insulating layer 330 is removed by the incoming etchant.

[0056] By removing the second portion 330C of the second insulating layer 330 in this way, the first side surface 610CS of the second conductive pattern 610C can be exposed. Since the fifth conductive pattern 610G is a protective guard that protects the first portion 330P of the second insulating layer 330, it is possible to prevent etchant from flowing into the first portion 330P of the second insulating layer 330. The fifth conductive pattern 610G covers the second side surface 330PS of the first portion 330P of the second insulating layer 330 and extends to connect to the first binding layer 420, and the first binding layer 420 covers and protects the upper surface 330PT of the first portion 330P of the second insulating layer 330, so that the first portion 330P of the second insulating layer 330 can be protected from etchant. The first binding layer 420 and the fifth conductive pattern 610G can block etchant from flowing into the first portion 330P of the second insulating layer 330, thus protecting the first portion 330P of the second insulating layer 330 from the process of removing the second portion 330C of the second insulating layer 330. Despite the removal of the second portion 330C of the second insulating layer 330, the first portion 330P of the second insulating layer 330 remains and can surround and insulate the first conductive pattern 610P. The third side surface 610GS, which is a part of the side surface of the fifth conductive pattern 610G, can be exposed after the removal of the second portion 330C of the second insulating layer 330.

[0057] The remaining portion of the first binding layer 420 is connected to the third conductive pattern 650C, allowing the third conductive pattern 650C to be bound together. The third conductive pattern 650C is bound together with the first binding layer 420, and the third conductive pattern 650C can be supported by the first binding layer 420 without falling over.

[0058] Figure 19 shows a schematic cross-sectional structure in which the dielectric layer 670 is formed. The dielectric layer 670 extends to cover the first side surface 610CS of the first conductive pattern 610C and to cover the third conductive pattern 650C through the first opening 420H of the first binding layer 420. The dielectric layer 670 can extend to cover the exposed surfaces of the first binding layer 420, the second binding layer 450, and the third binding layer 470. The dielectric layer 670 can further extend to cover the third side surface 610GS of the exposed fifth conductive pattern 610G.

[0059] The dielectric layer 670 may also be the dielectric layer of a capacitor. The dielectric layer 670 may include a high dielectric material layer having a high dielectric constant (k). The dielectric layer 670 may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), or tantalum oxide (Ta2O5).

[0060] Figure 20 shows a schematic cross-sectional structure in which a fourth conductive pattern 690 is formed covering the dielectric layer 670. The fourth conductive pattern 690 can extend to cover the dielectric layer 670. The fourth conductive pattern 690 may include a plate node of the capacitor. The fourth conductive pattern 690 may include layers of various electrode materials. The fourth conductive pattern 690 may include a metal layer or metal nitride layer such as titanium nitride (TiN). A capacitor structure may be formed comprising a storage node including the second conductive pattern 610C and the third conductive pattern 650C, the dielectric layer 670, and a plate node including the fourth conductive pattern 690.

[0061] In one embodiment of the method for manufacturing a semiconductor device, as shown in Figure 2, a second insulating layer 330 can be formed on a substrate 100, and as shown in Figure 3, a first hole 510P and a second hole 510C can be formed penetrating the second insulating layer 330. As shown in Figures 5 and 6, a first recess 510PD can be formed superimposed on the first hole 510P. As shown in Figures 7 and 8, a first conductive pattern 610P that fills the first hole 510P and the first recess 510PD can be formed simultaneously with a second conductive pattern 610C that fills the second hole 510C. A third conductive pattern 650C, as shown in Figure 13, can be formed so as to be connected to the second conductive pattern 610C.

[0062] In one embodiment of the method for manufacturing a semiconductor device, as shown in Figure 2, a second insulating layer 330 is formed on a substrate 100, and as shown in Figure 3, a first hole 510P, a trench 510G, and a second hole 510C can be simultaneously formed through the second insulating layer 330. The trench 510G can divide the second insulating layer 330 into a first portion 330P and a second portion 330C. As shown in Figures 7 and 8, a first conductive pattern 610P that fills at least the first hole 510P, a fifth conductive pattern 610G that fills at least the trench 510G, and a second conductive pattern 610C that fills the second hole 510C can be simultaneously formed. A third conductive pattern 650C, as shown in Figure 13, can be formed so as to be connected to the second conductive pattern 610C. As shown in Figures 17 and 18, the second portion 330C of the second insulating layer 330 can be removed to expose the first side surface 610CS of the second conductive pattern 610C.

[0063] In one embodiment, as shown in Figure 20, the semiconductor device includes a substrate 100 comprising a first region 100P and a second region 100C, and a second portion 330P of a second insulating layer formed on the first region 100P of the substrate 100. The semiconductor device may include a first conductive pattern 610P penetrating the second portion 330P of the second insulating layer, and a second conductive pattern 610C formed on the second region 100C of the substrate 10. The semiconductor device may further include a third conductive pattern 650C connected to the second conductive pattern 610C. The semiconductor device may include a first binding layer 420 covering the upper surface 330PT of the first conductive pattern 610P and the second portion 330P of the second insulating layer, and connected to the third conductive pattern 650C. The semiconductor device may further include a fifth conductive pattern 610G that covers the second side surface 330PS of the second portion 330P of the second insulating layer and extends in a third direction D3 so as to be connected to the first binding layer 420.

[0064] The above description focuses on the embodiments of this disclosure. A person with ordinary skill in the art to which this disclosure pertains will understand that this disclosure can be realized in modified forms that do not deviate from the essential characteristics of this disclosure. Therefore, the disclosed embodiments should be considered in an explanatory rather than restrictive manner. The scope of this disclosure is set forth in the claims, not in the above description, and all differences within an equivalent scope should be interpreted as being included in this disclosure.

Claims

1. The steps include forming an insulating layer on a substrate, The steps include forming a first hole and a second hole that penetrate the insulating layer, The steps include forming a recess superimposed on the first hole in the insulating layer, The steps include forming a first conductive pattern that fills the first hole and the recess, and a second conductive pattern that fills the second hole, A method for manufacturing a semiconductor device, comprising the step of forming a third conductive pattern connected to the second conductive pattern.

2. The first conductive pattern is This includes interconnection wiring connected to the aforementioned substrate, The second conductive pattern and the third conductive pattern are A method for manufacturing a semiconductor device according to claim 1, comprising forming a storage node for a capacitor.

3. After forming the third conductive pattern, the step of removing a portion of the insulating layer to expose the first side surface of the second conductive pattern, The steps include forming a dielectric layer that covers the first side surface of the second conductive pattern and extends to cover the third conductive pattern, A method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a fourth conductive pattern extending so as to cover the dielectric layer.

4. The aforementioned fourth conductive pattern is A method for manufacturing a semiconductor device according to claim 3, comprising a plate node of a capacitor.

5. Before forming the third conductive pattern, The steps include forming a binding layer that covers the insulating layer, the first conductive pattern, and the second conductive pattern, The method further includes the step of forming an opening that penetrates the binding layer at a position closer to the second conductive pattern than the first conductive pattern, A method for manufacturing a semiconductor device according to claim 3, wherein the portion of the insulating layer is removed through the opening.

6. The dielectric layer and the fourth conductive pattern are A method for manufacturing a semiconductor device according to claim 5, which extends to pass through the aforementioned opening.

7. The method for manufacturing a semiconductor device according to claim 3, wherein the remaining portion of the insulating layer remains and surrounds the first conductive pattern.

8. The step of forming the first conductive pattern and the second conductive pattern is: The steps include forming a first conductive layer on the insulating layer that fills the second hole and extends into the first hole and the recess, The steps include forming a second conductive layer on the first conductive layer that fills the first hole and the recess, A method for manufacturing a semiconductor device according to claim 1, comprising the step of removing a portion of the second conductive layer and a portion of the first conductive layer to separate the first conductive pattern and the second conductive pattern from the first and second conductive layers.

9. The first conductive layer is Contains titanium nitride (TiN), The aforementioned second conductive layer is A method for manufacturing a semiconductor device according to claim 8, comprising tungsten (W).

10. The recess is, A method for manufacturing a semiconductor device according to claim 1, wherein the device extends outward from the first hole.

11. A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of forming a first contact for connecting the first conductive pattern to the semiconductor substrate and a second contact for connecting the second conductive pattern to the semiconductor substrate.

12. The steps include forming an insulating layer on a substrate, The steps include forming a first hole, a trench, and a second hole so as to penetrate the insulating layer, wherein the trench divides the insulating layer into a first portion and a second portion, The steps include forming a first conductive pattern that fills the first hole, a fifth conductive pattern that fills the trench, and a second conductive pattern that fills the second hole, The steps include forming a third conductive pattern connected to the second conductive pattern, A method for manufacturing a semiconductor device, comprising the step of removing the second portion of the insulating layer to expose the first side surface of the second conductive pattern.

13. The first conductive pattern is This includes interconnection wiring connected to the aforementioned substrate, The second conductive pattern and the third conductive pattern are Configure the capacitor storage node, The fifth conductive pattern is, A method for manufacturing a semiconductor device according to claim 12, comprising a protection guard for protecting the first portion of the insulating layer.

14. The trench is A method for manufacturing a semiconductor device according to claim 12, extending so as to surround the second hole.

15. The process further includes the step of forming a first recess superimposed on the first hole and a second recess superimposed on the trench in the insulating layer, The fifth conductive pattern extends to fill the second recess, The method for manufacturing a semiconductor device according to claim 12, wherein the first conductive pattern extends to fill the first recess.

16. The step of forming the first conductive pattern and the second conductive pattern is: The steps include forming a first conductive layer on the insulating layer that fills the second hole, extends into the second recess and the trench, and extends into the first recess and the first hole, The steps include forming a second conductive layer on the first conductive layer that fills the second recess and the trench, and fills the first recess and the first hole, A method for manufacturing a semiconductor device according to claim 15, comprising the step of removing a portion of the second conductive layer and a portion of the first conductive layer to separate the first conductive pattern, the fifth conductive pattern, and the second conductive pattern from the first and second conductive layers.

17. The first conductive layer is Contains titanium nitride (TiN), The aforementioned second conductive layer is A method for manufacturing a semiconductor device according to claim 16, comprising tungsten (W).

18. Before forming the third conductive pattern, The steps include forming a binding layer that covers the insulating layer and the first conductive pattern, the fifth conductive pattern, and the second conductive pattern, The further step includes forming an opening that penetrates the binding layer at a position closer to the second conductive pattern than the first conductive pattern, A method for manufacturing a semiconductor device according to claim 12, wherein the second portion of the insulating layer is removed through the opening.

19. The steps include forming a dielectric layer that covers the first side surface of the second conductive pattern and extends through the opening to cover the third conductive pattern, A method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming a fourth conductive pattern covering the dielectric layer.

20. The aforementioned fourth conductive pattern is A method for manufacturing a semiconductor device according to claim 19, comprising a capacitor plate node.

21. The step of forming the third conductive pattern is: The steps include forming a mold layer on the aforementioned binding layer, The steps include forming a third hole that penetrates the mold layer and the binding layer to expose a portion of the second conductive pattern, The steps include forming a third conductive layer that fills the third hole, A method for manufacturing a semiconductor device according to claim 18, comprising the step of removing the mold layer.

22. The second portion of the insulating layer is removed through the opening that is exposed by removing the mold layer. The method for manufacturing a semiconductor device according to claim 21, wherein the first portion of the insulating layer remains protected by the binding layer and the fifth conductive pattern.

23. An insulating layer formed on the first region of a substrate including the first region and the second region, A first conductive pattern penetrating the insulating layer, A second conductive pattern formed on the second region of the substrate, A third conductive pattern connected to the second conductive pattern, A semiconductor device comprising a first conductive pattern and a binding layer that covers the insulating layer and is connected to the third conductive pattern.

24. The aforementioned binding layer is Connected to the third conductive pattern, The semiconductor device according to claim 23, comprising an opening that penetrates the binding layer.

25. A dielectric layer extending to cover the first side surface of the second conductive pattern and to cover the third conductive pattern through the opening, The semiconductor device according to claim 24, further comprising a fourth conductive pattern covering the dielectric layer.

26. The first conductive pattern is Includes connecting wiring connected to the aforementioned substrate, The second conductive pattern and the third conductive pattern are Forming a capacitor storage node, The aforementioned fourth conductive pattern is The semiconductor device according to claim 25, comprising the plate node of the capacitor.

27. The semiconductor device according to claim 23, further comprising a fifth conductive pattern that covers the second side surface of the insulating layer and extends to be connected to the binding layer.

28. The fifth conductive pattern is, The semiconductor device according to claim 27, comprising a protective guard for protecting the insulating layer.

29. A dielectric layer extending to cover the first side surface of the second conductive pattern and the third side surface of the fifth conductive pattern, The semiconductor device according to claim 27, further comprising a plate node covering the dielectric layer.

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