Method for forming a seed layer and plasma etching method
By forming ion passage holes and using a metal mask layer connected via side walls, the method addresses arc generation and dielectric breakdown in plasma etching and sputtering processes, ensuring reliable seed layer formation and etching on glass core substrates.
Patent Information
- Application Number
- JP2025260770
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-31
- Filing Date
- 2025-12-17
- Publication Date
- 2026-07-13
AI Technical Summary
Existing plasma etching and sputtering processes in forming seed layers on packaging substrates with glass cores are prone to arc generation and dielectric breakdown due to uneven ion surface charge distribution, leading to substrate cracking and equipment malfunction.
A method involving ion passage holes formed in the insulating layer, with a metal mask layer connected via the side walls, allowing charge movement and reducing potential differences, and a plasma etching process to create blind vias without dielectric breakdown.
The method effectively suppresses arc generation and dielectric breakdown, ensuring highly reliable seed layer formation and plasma etching processes, preventing substrate damage and equipment malfunction.
Smart Images
Figure 2026116811000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments relate to a method for forming a seed layer capable of suppressing the generation of arcs and executing a highly reliable process, a plasma etching method, and the like.
Background Art
[0002] There are many types of sputtering systems, which are used to deposit soft or conductive coatings. Sputtering is applied in the process of forming wiring on a packaging substrate.
[0003] Sputtering corresponds to a process of forming a thin film by colliding ionized gas atoms with a target substance. In other words, sputtering is a process of colliding ions having high energy at high speed with a target and depositing the ejected metal particles on a substrate, and can be classified into DC sputtering, RF sputtering, reactive ion sputtering, and the like.
[0004] DC sputtering corresponds to a process of applying a DC (direct current power supply) to a chamber equipped with a sputtering target to make an inert gas in the chamber into a plasma state for deposition, and RF sputtering corresponds to a process of applying an RF (Radio Frequency) voltage, that is, an AC (alternating current power supply) to a chamber equipped with a sputtering target to make an inert gas in the chamber into a plasma state for deposition.
[0005] When RF power is applied to the chamber during such an RF sputtering process, an arc may occur. Such an arc may cause damage to the substrate or cause malfunction of the equipment. Therefore, it is necessary to minimize the generation of arcs in the chamber.
[0006] Related prior art includes Korean Registered Patent No. 10-1324584 and Korean Registered Patent No. 10-2634683. [Overview of the project] [Problems that the invention aims to solve]
[0007] The purpose of this embodiment is to provide a method for forming a seed layer, a plasma etching method, etc., that suppresses arc generation and enables the execution of highly reliable processes.
[0008] The purpose of this embodiment is to provide a seed layer formation method, a plasma etching method, etc., that substantially suppresses phenomena such as cracking of the substrate or burning of electrically conductive patterns, etc., by suppressing dielectric breakdown phenomena caused by accumulated electrons in hole-shaped vias, particularly in the manufacturing of packaging substrates using glass cores, where an uneven distribution of ion surface charge due to plasma occurs in substrates with high insulating properties. [Means for solving the problem]
[0009] A method for forming a seed layer according to an embodiment for achieving the above objective includes a hole forming step of removing a part of the insulating layer to create ion passage holes in a workpiece arranged such that a metal pattern layer is below and an insulating layer is above; a masking step of placing a metal mask layer on the insulating layer; and a sputtering step of forming a seed layer on the insulating layer by plasma sputtering, wherein the metal mask layer is connected to the metal pattern layer via the side walls of the ion passage holes.
[0010] The ion passage holes may be provided such that at least a portion of the metal pattern layer is exposed.
[0011] The side walls of the ion passage holes can allow the movement of charge between the metal mask layer and the metal pattern layer.
[0012] A glass core may be placed beneath the aforementioned metal pattern layer.
[0013] The insulating layer may be an upper insulating layer disposed on the glass core.
[0014] The metal pattern layer may be a core electrically conductive layer or an upper electrically conductive layer.
[0015] The ion passage holes can be formed by laser drilling the insulating layer.
[0016] The sputtering step may involve positioning the object to be processed within a process chamber, creating a vacuum in the process chamber, and then generating plasma so that the target material is deposited onto the substrate.
[0017] The generation of a potential difference between the metal mask layer and the metal pattern layer can be suppressed through the ion passage holes.
[0018] The occurrence of dielectric breakdown can be substantially suppressed in the sputtering step.
[0019] Another embodiment for achieving the above objectives is a plasma etching method which includes a hole-forming step of removing a portion of the insulating layer to create ion-passage holes in a workpiece arranged such that a metal pattern layer is below and an insulating layer is above; a masking step of placing a metal mask layer on the insulating layer; and a via-forming step of creating blind vias on the insulating layer by plasma etching, wherein the metal mask layer is connected to the metal pattern layer via the sidewalls of the ion-passage holes.
[0020] The ion passage holes may be provided such that at least a portion of the metal pattern layer is exposed.
[0021] The side walls of the ion passage holes can allow the movement of charge between the metal mask layer and the metal pattern layer. [Effects of the Invention]
[0022] Methods for forming a seed layer in embodiments, plasma etching methods, etc. can provide methods for forming a seed layer, plasma etching methods, etc. that can suppress the occurrence of arcs during the plasma process and enable the execution of highly reliable processes.
[0023] Methods for forming a seed layer in embodiments, plasma etching methods, etc. can substantially suppress the occurrence of phenomena such as the substrate cracking or the electrical conductive pattern burning in the manufacture of a packaging substrate applying a glass core, where a bias of ionic surface charges due to plasma occurs on a substrate with high insulation, especially an insulation breakdown phenomenon caused by accumulated electrons in a hole-shaped via.
Brief Description of the Drawings
[0024] [Figure 1] It is a flowchart explaining in cross-section the process of forming an electrically conductive layer and an insulating layer on a glass core. [Figure 2] It is a flowchart explaining in cross-section the process of arc generation that occurs when performing a plasma sputtering process by an existing method. [Figure 3] It is a flowchart explaining the state of showing a stable ion distribution when performing a plasma sputtering process according to an embodiment.
Best Mode for Carrying Out the Invention
[0025] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement them. However, the present invention can be realized in various different forms and is not limited to the embodiments described herein. The same reference numerals are given to similar parts throughout the specification.
[0026] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.
[0027] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.
[0028] In this specification, "~system" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".
[0029] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.
[0030] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.
[0031] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.
[0032] In this specification, the form, relative size, angles, etc., of each component in the drawings are illustrative and may be exaggerated for illustrative purposes, and the rights shall not be construed as being limited to the drawings.
[0033] In this specification, "adjacent to A and B" means that A and B are located touching each other, or that A and B are not touching but are located close to each other. In this specification, the expression "adjacent to A and B" is not construed to mean that A and B are located touching each other unless otherwise specified.
[0034] Figure 1 is a flowchart illustrating the process of forming an electrically conductive layer and an insulating layer on a glass core in cross-section. Figure 2 is a flowchart illustrating the process of arc generation that occurs when performing a plasma sputtering process using an existing method, in cross-section. Figure 3 is a flowchart illustrating the stable ion distribution observed when performing a plasma sputtering process using a concrete example. The concrete example will be explained in more detail below with reference to Figures 1 to 3.
[0035] To achieve the above objective, a method for forming a seed layer according to one embodiment of the embodiment includes a hole formation step, a masking step, and a sputtering step.
[0036] The hole formation step involves removing a portion of the insulating layer to create ion passage holes 99 in an object to be processed, where the metal pattern layer is positioned below and the insulating layer is positioned above.
[0037] The ion passage holes 99 may be provided such that at least a portion of the metal pattern layer is exposed.
[0038] The ion passage holes 99 may, for example, be formed in the insulating layer by methods such as laser etching drilling, but are not limited thereto.
[0039] The ion passage hole 99 may, for example, have a diameter of 12 μm or more, 16 μm or more, 20 μm or more, 24 μm or more, or 28 μm or more. Alternatively, the diameter may be 100 μm or less, 80 μm or less, 60 μm or less, 50 μm or less, 45 μm or less, or 40 μm or less. If the diameter of the ion passage hole 99 is too small, the hole formation process is not easy, and if the diameter is too large, the process may be unnecessarily wasted.
[0040] The masking step is the step of placing a metal mask layer on the insulating layer.
[0041] The aforementioned metal mask layer can be formed using a conventional method for forming a metal mask layer.
[0042] Figure 2(a) shows how the metal mask layer 80 is positioned using an existing method. The metal mask layer is positioned over the area to be masked, and, as an example, on the upper surface of the object to be processed. If a hole H is positioned in the object to be processed, and the hole H is positioned in the area that needs to be masked, then in the process, the metal mask layer 80 is positioned only on the bottom surface of the hole.
[0043] Figure 3(a) shows how the metal mask layer 80 is positioned according to an example. The metal mask layer is placed on the portion to be masked, and exemplary, on the upper surface of the object to be processed. If a hole H is placed in the object to be processed, and the hole H is placed in the portion that needs to be masked, then, unlike the existing technology described above, the metal mask layer 80 is placed on the sides of the hole as well as the bottom surface during the process.
[0044] Specifically, the metal mask layer 80 is connected to the metal pattern layer via the side walls of the ion passage holes 99.
[0045] The sidewall surface of the ion passage hole 99 allows for the movement of charge between the metal mask layer 80 and the metal pattern layer.
[0046] The sputtering step is a step of forming a seed layer 50 on the insulating layer by plasma sputtering.
[0047] The seed layer 50 can be formed using a general method for forming a seed layer, and examples include, but are not limited to, titanium, titanium nitride, copper, tantalum, cobalt, nickel, etc. Furthermore, plasma sputtering may be performed by positioning the object to be processed in a process chamber where a metal target is placed, inducing a vacuum, and then performing sputtering, but is not limited to this method.
[0048] Figure 2(b) illustrates the process of forming a plasma seed layer on a substrate prepared by an existing method. During the plasma process, ions 3a collide with the surface of the substrate, and charge 3b accumulates on the surface of the substrate. In particular, when a metal mask layer is applied, the accumulated charge accumulates on the metal mask layer, and when the level of accumulated charge exceeds a certain level, an arc is generated. When charge accumulates on the metal mask layer on the insulating layer and on the metal mask layer or electrically conductive layer under the blind vias, the surface potential can momentarily concentrate and an arc is likely to occur, even though there is an insulating layer between them. This is called dielectric breakdown, and in specific phenomena, it can lead not only to simple arc generation but also to physical damage to the substrate such as cracking of the substrate, oxidation of electrodes, and oxidation of the insulating layer.
[0049] Figure 3(b) shows an example provided by a concrete example, in which the sidewall surface of the ion passage hole 99 allows the movement of charge 3a between the metal mask layer 80 and the metal pattern layer. This means that even if charge 3b accumulates on the metal mask layer 80 during the plasma sputtering process, it moves to the metal pattern layer through the sidewall surface, reducing the difference in charge density between the upper and lower parts of the ion passage hole 99. Since the metal pattern layer is often also placed below blind vias that are intended for seed layer formation, the difference in charge density between the upper surface of the insulating layer and the lower surface of the blind vias is reduced across the blind vias. Through this, the occurrence of dielectric breakdown can be substantially suppressed.
[0050] The sputtering step involves positioning the object to be processed within a process chamber, creating a vacuum in the process chamber, and then generating plasma so that the target material is deposited onto the substrate.
[0051] The generation of a potential difference between the metal mask layer 80 and the metal pattern layer can be suppressed through the ion passage holes 99.
[0052] The sputtering step described above can substantially suppress the occurrence of dielectric breakdown.
[0053] Subsequently, electrodes or electrically conductive layers can be formed using methods such as copper plating (Figure 3(c)), thereby enabling the reliable formation of electrically conductive layers such as via electrodes.
[0054] The application of the above method to a packaging substrate will be explained with reference to the drawings.
[0055] The glass core 10 is a highly insulating material, which reduces the risk of parasitic element formation and has the advantage of being able to be produced over a large area compared to substrates such as silicon. Its non-conductive properties offer the advantage of more stable operation, especially when high frequencies are applied. However, in the manufacturing process, its high insulating properties and the ability to be manufactured over a large area make it more susceptible to dielectric breakdown.
[0056] The glass core 10 has through electrodes, and a core electrical conductive layer 305 may be arranged on its surface in a predetermined pattern. Between them, a layer (not shown) may be arranged to enhance the adhesion between the glass and the electrical conductive layer, and examples include, but are not limited to, a primer layer, a sputtered layer, etc. (Figure 1(a)).
[0057] An insulating layer is placed on the glass core 10. The insulating layer formed inside the through electrode and on the surface of the glass core 10 is called the core insulating layer 45 (Figure 1(b)), and an organic insulating layer, an inorganic insulating layer, or an organic-inorganic composite insulating layer may be applied. For example, Ajinomoto build-up layer may be applied, but it is not limited to this.
[0058] An upper electrically conductive layer 307 may be placed on the core insulating layer 45. The pattern can be formed by a lithography process, and the electrically conductive layer can be formed using a method such as copper plating. It is preferable to form a seed layer before copper plating, but methods such as coating with an organic-inorganic composite primer layer containing copper seeds or forming a sputter layer can be applied. After that, copper plating is performed, and further processes such as surface etching can be carried out to provide one upper electrically conductive layer (Figure 1(c)).
[0059] An insulating layer may be placed on top of the upper electrically conductive layer, and vias or other features can be formed by etching a portion of it (Figure 1(d)). In Figure 1(d), the upper insulating layer 47 is shown in a different color for ease of explanation, but its boundary may not be visible in the cross-section.
[0060] The subsequent process will be explained with reference to Figure 3.
[0061] The vias formed in the upper insulating layer 47 can contain a mixture of ion passage holes 99 and blind vias 9. For example, ion passage holes 99 may be formed first by a method such as laser drilling, and then a metal mask layer 80 may be applied as described later, and blind vias 9 may be formed through plasma etching.
[0062] Although a metal mask layer 80 is formed before plasma etching, the metal mask layer 80 is positioned so that at least a portion of it is located on the sidewall surface of the ion passage layer. This metal mask layer 80 on the sidewall surface is connected to the electrically conductive layer on the underside of the ion passage layer, thereby preventing excessive charge accumulation in the ion passage.
[0063] Subsequently, a seed layer 50 can be provided on the blind via 9 through a plasma sputtering process, and a blind electrode, which is an upper electrically conductive layer 307, can be provided by methods such as electroplating.
[0064] Although the lower layer is omitted from the drawings and explanations, a lower electrically conductive layer 303 and a lower insulating layer 43 can be arranged in the lower layer, similar to the upper layer.
[0065] A plasma etching method according to another embodiment includes a hole formation step of removing a portion of the insulating layer to create ion passage holes in a workpiece arranged such that a metal pattern layer is below and an insulating layer is above; a masking step of placing a metal mask layer on the insulating layer; and a via formation step of creating blind vias on the insulating layer through plasma etching, wherein the metal mask layer is connected to the metal pattern layer via the side walls of the ion passage holes.
[0066] The ion passage holes are provided such that at least a portion of the metal pattern layer is exposed, and the side walls of the ion passage holes are capable of allowing the movement of charge between the metal mask layer and the metal pattern layer.
[0067] The plasma etching method, similar to the plasma sputtering process, can create blind vias without the application of dielectric breakdown.
[0068] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements by those skilled in the art, utilizing the basic concepts of the present invention as defined in the appended claims, also fall within the scope of the present invention. [Explanation of symbols]
[0069] 10 glass cores 30 Electrically conductive layer patterns 305 Core electrical conductive layer 307 Upper electrically conductive layer 303 Lower electrically conductive layer 45 Core insulating layer 47 Upper insulating layer 43 Lower insulating layer 80 Metal Mask Layers 50 Seed Layer 3a Ions 3b cumulative electron 9 Blind Beer 99 Aeon Passage Hall
Claims
1. A hole-forming step is performed on a workpiece in which a metal pattern layer is positioned below and an insulating layer is positioned above, by removing a portion of the insulating layer to create ion-passage holes. A masking step of placing a metal mask layer on the insulating layer, The process includes a sputtering step of forming a seed layer on the insulating layer by plasma sputtering, A method for forming a seed layer, wherein the metal mask layer is connected to the metal pattern layer via the side walls of the ion passage holes.
2. The method for forming a seed layer according to claim 1, wherein the ion passage holes are provided such that at least a portion of the metal pattern layer is exposed.
3. The method for forming a seed layer according to claim 1, wherein the side wall surface of the ion passage hole allows for the movement of charge between the metal mask layer and the metal pattern layer.
4. A glass core is placed beneath the aforementioned metal pattern layer. The insulating layer is an upper insulating layer disposed on the glass core, The method for forming a seed layer according to claim 1, wherein the metal pattern layer is a core electrically conductive layer or an upper electrically conductive layer.
5. The method for forming a seed layer according to claim 1, wherein the ion passage holes are formed by laser drilling the insulating layer.
6. The method for forming a seed layer according to claim 1, wherein the sputtering step is a step of positioning the object to be processed in a process chamber, creating a vacuum in the process chamber, and then generating plasma so that the target material is deposited onto the substrate.
7. The method for forming a seed layer according to claim 1, wherein the generation of a potential difference between the metal mask layer and the metal pattern layer is suppressed through the ion passage holes.
8. The method for forming a seed layer according to claim 1, wherein the occurrence of dielectric breakdown in the sputtering step is substantially suppressed.
9. A hole-forming step is performed on a workpiece in which a metal pattern layer is positioned below and an insulating layer is positioned above, by removing a portion of the insulating layer to create ion-passage holes. A masking step of placing a metal mask layer on the insulating layer, The process includes a via formation step of providing blind vias on the insulating layer by plasma etching, A plasma etching method wherein the metal mask layer is connected to the metal pattern layer via the side walls of the ion passage holes.
10. The ion passage holes are provided such that at least a portion of the metal pattern layer is exposed. The plasma etching method according to claim 9, wherein the side wall surface of the ion passage hole allows for the movement of charge between the metal mask layer and the metal pattern layer.