Indication device

Abstract

Improve the reliability of display devices. [Solution] An embodiment of the present invention may include a substrate including a display area and a non-display area outside the display area, an insulating layer and a planar layer disposed on the upper part of the substrate and extending from the display area to the non-display area, at least one trench disposed in the non-display area and formed by removing at least one of the insulating layer and the planar layer, a bank disposed on the planar layer and extending to the non-display area, an organic layer disposed on the bank, a cathode disposed on the organic layer and extending to the trench, and a protective layer disposed on the upper part of the cathode, and a gate-in-panel (GIP) circuit section disposed in the non-display area on at least one side of the left and right sides and located inside the trench, thereby minimizing the effects of moisture permeability.

Description

Technical Field

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[0001] The present invention relates to a display device, and more particularly to a display device capable of preventing moisture permeation.

Background Art

[0002] Currently, with the advent of the full-fledged information age, the field of display devices that visually display electrical information signals has been rapidly developing, and research has been continuing to develop performance such as thinning, weight reduction, and low power consumption for various display devices.

[0003] Typical display devices include a liquid crystal display device (LCD), an electro-wetting display device (EWD), and an organic light emitting display device (OLED).

[0004] Among these, the electroluminescent display device including the organic light emitting display device is a self-emitting display device, and unlike the liquid crystal display device, it does not require a separate light source and can be manufactured in a lightweight and thin form. In addition, the electroluminescent display device is not only advantageous in terms of power consumption due to low voltage driving, but also excellent in hue reproduction, response speed, viewing angle, and light and dark contrast ratio, and is expected to be utilized in various fields.

[0005] A certain bezel distance is essential for moisture permeation prevention and reliability assurance in the electroluminescent display device. However, during the deposition of the cathode and the organic layer, the shadow region generated by the gap between the mask and the substrate acts as the main factor limiting the bezel reduction. In addition, when the bezel is reduced, corrosion of the gate-in-panel (GIP) wiring due to moisture permeation is likely to occur, which may affect the reliability.

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem that this invention aims to solve is to provide a display device that can reduce the bezel width while simultaneously blocking moisture and oxygen.

[0007] Another problem that the present invention aims to solve is to provide a display device that can prevent corrosion of GIP circuit wiring.

[0008] The problems addressed by the present invention are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] To solve the problems described above, a display device according to one embodiment of the present invention may include a substrate including a display area and a non-display area outside the display area; an insulating layer and a planarizing layer disposed on the upper part of the substrate and extending from the display area to the non-display area; at least one trench disposed in the non-display area and formed by removing a portion of at least one of the insulating layer and the planarizing layer; a bank disposed on the planarizing layer and extending to the non-display area; an organic layer disposed on the bank; a cathode disposed on the organic layer and extending to the trench; a protective layer disposed on the upper part of the cathode; and a gate-in-panel (GIP) circuit section disposed in at least one of the left and right non-display areas and located inside the trench.

[0010] Specific details of other embodiments are included in the detailed description and drawings.

[0011] This invention can improve the reliability of moisture-proof performance while reducing the bezel width by forming trenches in the shadow areas generated by the use of a vapor deposition mask.

[0012] This invention minimizes the effects of moisture permeability by placing the GIP circuit inside the trench and sealing the GIP circuit with a cathode, thereby improving the reliability of the display device.

[0013] The effects of the present invention are not limited to those exemplified above, and a wide variety of other effects are included within the present invention. [Brief explanation of the drawing]

[0014] [Figure 1] This is a plan view of a display device according to the first embodiment of the present invention. [Figure 2] Figure 1 is a cross-sectional view of the display device with respect to its subpixels. [Figure 3] This figure shows a portion of the cross-section of the display device in Figure 1 along the line Ia-Ia'. [Figure 4] This figure shows a portion of the cross-section of the display device in Figure 1 along the line Ib-Ib'. [Figure 5] This figure shows a portion of the cross-section of the display device shown in Figure 1, along the line Ic-Ic'. [Figure 6] This is a plan view of a display device according to a second embodiment of the present invention. [Figure 7] This figure shows a cross-section of the display device along line IIa-IIa' in Figure 6. [Figure 8] This figure shows a cross-section of the display device along line IIb-IIb' in Figure 6. [Figure 9] This is a cross-sectional view of a display device according to a third embodiment of the present invention. [Figure 10] This is a cross-sectional view of a display device according to a fourth embodiment of the present invention. [Figure 11] This is a cross-sectional view of a display device according to a fifth embodiment of the present invention. [Modes for carrying out the invention]

[0015] The advantages and features of the present invention, and the method for achieving them, will become clear by referring to the embodiments described in detail below together with the attached drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. Merely, these embodiments are provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention. The present invention is only defined by the scope of the claims.

[0016] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, so the present invention is not limited to the illustrated matters. Also, when explaining the present invention, if it is determined that a detailed description of related known technologies may muddy the gist of the present invention unnecessarily, that detailed description will be omitted. Also, when terms such as "including", "having", "being made" as mentioned in this specification are used, unless "only" is used, other parts can be added. When a component is expressed in the singular, it includes the case of including a plurality unless there is a specific description to the contrary.

[0017] When interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0018] When it is an explanation of a positional relationship, for example, when the positional relationship between two parts is described such as "on", "above", "below", "next to", etc., unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0019] When an element or layer is referred to as being "on" another element or layer, it includes both the case of being immediately above the other element and the case of having another layer or another element intervening in the middle.

[0020] The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of the present invention.

[0021] Throughout the specification, the same reference numerals refer to the same components.

[0022] The size and thickness of each configuration shown in the drawings are shown for the convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the shown configuration.

[0023] The respective features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various linkages and drives are technically possible as can be fully understood by those skilled in the art. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0024] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] FIG. 1 is a plan view of a display device according to a first embodiment of the present invention.

[0026] Referring to FIG. 1, the display device 100 of the first embodiment of the present invention may include a substrate 111, a sealing substrate 160, and pad portions 107 and 108.

[0027] The display device 100 is a device for displaying an image to a user.

[0028] The display device 100 may include a display element for displaying an image, a drive element for driving the display element, and wiring for transmitting various signals to the display element and the drive element. The display element may be defined differently depending on the type of display device 100. For example, if the display device 100 is an organic light-emitting display device, the display element may be an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode. For example, if the display device 100 is a liquid crystal display device, the display element may be a liquid crystal display element.

[0029] In the following, we assume that the display device 100 is an organic light-emitting display device, but the display device 100 is not limited to an organic light-emitting display device.

[0030] The display device 100 may include a display area AA and a non-display area NA.

[0031] Display area AA is the area where the image is displayed on the display device 100.

[0032] Display area AA may contain multiple subpixels that constitute multiple pixels, and circuits for driving the multiple subpixels. Multiple subpixels are the smallest units that constitute display area AA, and display elements may be placed in each of the multiple subpixels, and multiple subpixels can constitute a pixel. For example, each of the multiple subpixels may contain an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode, but is not limited to this. Furthermore, the circuits for driving the multiple subpixels may include driving elements and wiring, etc. For example, the circuits may consist of thin-film transistors, storage capacitors, gate wiring, data wiring, etc., but is not limited to this.

[0033] The non-display area (NA) is the region where the image is not displayed.

[0034] In Figure 1, the non-display area NA is shown to surround the rectangular display area AA; however, the shape and arrangement of the display area AA and the non-display area NA are not limited to the example shown in Figure 1.

[0035] In other words, the display area AA and the non-display area NA may be in a form suitable for the design of the electronic device equipped with the display device 100. For example, exemplary forms of the display area AA may be a pentagon, hexagon, circle, ellipse, etc.

[0036] Various wiring and circuits for driving the organic light-emitting elements of the display area AA may be arranged in the non-display area NA. For example, link wiring for transmitting signals to multiple subpixels and circuits of the display area AA, drive ICs such as gate driver ICs and data driver ICs, or pad sections 107, 108, etc., may be arranged in the non-display area NA, but are not limited to these.

[0037] The display device 100 may include a variety of additional elements for generating a variety of signals or driving pixels within the display area AA. Additional elements for driving pixels may include inverter circuits, multiplexers, electrostatic discharge (ESD) circuits, etc. The display device 100 may also include additional elements associated with functions other than pixel driving. For example, the display device 100 may include additional elements that provide touch sensing functionality, user authentication functionality (e.g., fingerprint recognition), multi-level pressure sensing functionality, tactile feedback functionality, etc. The aforementioned additional elements may be located in external circuits connected to the non-display area NA and / or the coupling interface.

[0038] The pads 107 and 108 may be positioned to receive signals from an external source.

[0039] The pads 107 and 108 are located in the non-display area NA of the display device 100 and can be electrically connected to various wiring and printed circuit boards located in the display area AA.

[0040] For example, the pad sections 107 and 108 can perform functions for transmitting signals to gate wiring and data wiring, respectively, and may include, but are not limited to, a gate pad section 108 for transmitting gate signals to gate wiring and a data pad section 107 for transmitting data signals to data wiring.

[0041] The gate pad portion 108 may, but is not limited to, be located on at least one side of the display device 100, for example, in the non-display area NA on the first side of the display device 100. For example, the first side may mean one of the left or right sides of the display device 100 adjacent to the upper and lower sides.

[0042] The data pad section 107 may, but is not limited to, be located on the other side of the display device 100, for example, in the non-display area NA on the second side of the display device 100. For example, the second side may mean the upper side of the display device 100. However, the present invention is not limited thereto, and each side of the non-display area NA may be referred to as at least one of the first, second, third, and fourth sides.

[0043] For example, the data pad section 107 can be electrically connected to a data driver that supplies data voltage to multiple data lines. The data driver can receive video data input from a timing controller and supply data voltage to multiple data lines to drive the multiple data lines. The data driver may be implemented by including one or more source driver integrated circuits.

[0044] For example, each source driver integrated circuit may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. The data driver may optionally further include one or more analog-to-digital converters (ADCs).

[0045] On the other hand, a gate driver can drive multiple gate wires by outputting scan signals to them. For example, a gate driver can sequentially drive multiple gate wires by sequentially supplying scan signals to them. A gate driver can sequentially supply on-voltage and off-voltage scan signals to multiple gate wires under the control of a timing controller.

[0046] A gate driver can consist of multiple gate drive circuits, each corresponding to a separate gate wiring.

[0047] For example, each gate drive circuit may include a shift register and a level shifter, etc.

[0048] Each gate drive circuit can be implemented in a gate-in-panel (GIP) type and integrated into the display device 100. For example, each gate drive circuit can be directly located on the gate pad section 108, in which case the gate pad section 108 can be referred to as the GIP circuit section.

[0049] On the other hand, the display device 100 of the first embodiment of the present invention may be provided with a trench 180 in the non-display area NA in order to ensure reliability, such as preventing moisture permeability.

[0050] Trench 180 may, but is not limited to, be positioned to surround display area AA, excluding the upper part.

[0051] Furthermore, in the first embodiment of the present invention, the display device 100 can minimize the effect of moisture permeation on the GIP circuit section 108 by arranging it inside the trench 180 such that the GIP circuit section 108 is separated from the trench 180 by a certain distance G. This will be explained in detail with reference to Figures 3 to 5.

[0052] Figure 2 is a cross-sectional view of the subpixels of the display device shown in Figure 1.

[0053] Figure 3 shows a portion of the cross-section of the display device shown in Figure 1 along the line Ia-Ia'.

[0054] Figure 4 shows a portion of the cross-section of the display device in Figure 1 along the line Ib-Ib'.

[0055] Figure 5 shows a portion of the cross-section of the display device shown in Figure 1 along the line Ic-Ic'.

[0056] Figure 3 shows a portion of the non-display area NA on the second side of the display device 100 in Figure 1, and Figure 4 shows a portion of the non-display area NA on the first side of the display device 100 in Figure 1. Furthermore, Figure 5 shows a portion of the non-display area NA on the third side of the display device 100 in Figure 1.

[0057] For example, the first side may mean the left side of the display device 100, the second side may mean the upper side of the display device 100, and the third side may mean the lower side located opposite the upper side, but is not limited to this.

[0058] In Figure 4, for the sake of explanation, the GIP circuit section 108 within the non-display area NA is schematically shown.

[0059] In Figures 3 to 5, for the sake of explanation, at least some of the buffer layer 112, gate insulating layer 113, and interlayer insulating layer 114 are shown as insulating layer 117.

[0060] Referring to Figures 2 to 5, in the first embodiment of the present invention, the display device (100 in Figure 1) may have a drive element 120 arranged on the substrate 111.

[0061] Furthermore, a planarization layer 115 may be placed on the drive element 120.

[0062] Then, a light-emitting element 130 electrically connected to a driving element 120 is placed on top of the planarization layer 115, and a protective layer 140 may be placed on top of the light-emitting element 130.

[0063] An adhesive layer 165 and a sealing substrate 160 may be arranged in order on the protective layer 140. However, the display device 100 according to the first embodiment of the present invention is not limited to such a laminated structure.

[0064] On the other hand, a trench 180 may be provided at the edge of the non-display area NA between the substrate 111 and the sealing substrate 160.

[0065] The substrate 111 may be a glass or plastic substrate. If it is a plastic substrate, a polyimide or polycarbonate series material can be used to provide flexibility. In particular, polyimide is often used as a plastic substrate because it can be applied to high-temperature processes and is a material that can be coated.

[0066] A buffer layer 112 may be placed on the substrate 111.

[0067] On the other hand, although not shown in the diagram, a light-shielding layer may be placed on the top of the substrate 111 to block light flowing in from the bottom of the substrate 111.

[0068] A light-shielding layer may be placed on the upper part of the substrate 111 at the location where the active layer 124 is formed. In particular, it is preferable that the size of the light-shielding layer be slightly larger so that it can completely cover the active layer 124.

[0069] A buffer layer 112 can be placed on the entire surface of the substrate 111 on which the light-shielding layer is formed.

[0070] The buffer layer 112 is a layer for protecting various electrodes and wiring from impurities such as alkali ions flowing out from the substrate 111 or the lower layer, and may, but is not limited to, a multilayer structure consisting of a first buffer layer 112a and a second buffer layer 112b. For example, the buffer layer 112 may consist of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0071] The buffer layer 112 can delay the diffusion of moisture and / or oxygen that has penetrated the substrate 111. The buffer layer 112 can also include a multi-buffer and / or an active buffer. The active buffer can protect the active layer 124, which is made of semiconductor material, of the driving element 120, and block various types of defects flowing in from the substrate 111. The active buffer can be formed from amorphous silicon (a-Si) or the like.

[0072] On the other hand, various wirings and circuits for driving the light-emitting elements 130 of the display area AA may be arranged in the non-display area NA. For example, link wiring for transmitting signals to multiple subpixels and circuits of the display area AA, drive ICs such as gate driver ICs and data driver ICs, or pad sections 107, 108 may be arranged in the non-display area NA, but are not limited to these.

[0073] For example, a grounding wire GW may be placed on top of the substrate 111 in the non-display area NA.

[0074] The grounding wire GW may be placed at the very edge of the non-display area NA, excluding the second side.

[0075] The grounding wire GW may be positioned adjacent to the edge of the sealing substrate 160.

[0076] A first light-shielding pattern PP1 may be placed inside the grounding wiring GW. The first light-shielding pattern PP1 may be placed between the grounding wiring GW and the trench 180.

[0077] Link wiring LW may be placed on the upper part of the substrate 111 of the second non-display area NA.

[0078] In the non-display areas NA on the left and right, the GIP circuit section 108 can be located inside the trench 180. A detailed explanation related to this will be given later with reference to Figure 4.

[0079] The GIP circuit section 108 may include, but is not limited to, a control signal clock wiring CW, a logic section LP, a buffer TFT section B-TFT, and a power supply wiring GVSS.

[0080] For example, control signal clock wiring CW, logic section LP, buffer TFT section B-TFT, and power supply wiring GVSS may be sequentially arranged from trench 180, but the present invention is not limited thereto.

[0081] In this case, the control signal clock wiring CW, logic section LP, buffer TFT section B-TFT, and power supply wiring GVSS may, but are not limited to, be composed of the light-shielding layer of the display area AA and / or the material constituting the driving element 120.

[0082] Furthermore, in the non-display area NA on the third side, the second light-shielding pattern PP2 and the high-potential power supply wiring EVDD may be placed inside the trench 180.

[0083] For example, the trench 180, the second light-shielding pattern PP2, and the high-potential power supply wiring EVDD may be arranged sequentially, but the present invention is not limited thereto.

[0084] The second light-shielding pattern PP2 and the high-potential power supply wiring EVDD may be composed of the material constituting the light-shielding layer of the display area AA and / or the driving element 120, but the present invention is not limited thereto.

[0085] The driving element 120 may consist of an active layer 124, a gate insulating layer 113, a gate electrode 121, an interlayer insulating layer 114, a source electrode 122, and a drain electrode 123. The driving element 120 is also electrically connected to the light-emitting element 130 through a connecting electrode 125, and can transmit current or signals to the light-emitting element 130. In addition to the illustrated top-gate structure, the driving element 120 can be applied in various ways, such as a bottom-gate structure where the gate electrode is located below the active layer, and a coplanar structure where the gate electrode, source electrode, and drain electrode are arranged on the same plane.

[0086] The active layer 124 may be located on the buffer layer 112. The active layer 124 may be made of polysilicon (p-Si), in which case a certain region may be doped with impurities. Alternatively, the active layer 124 may be made of amorphous silicon (a-Si), or of an organic semiconductor material such as pentacene. Furthermore, the active layer 124 may be made of an oxide semiconductor.

[0087] The gate insulating layer 113 may be located on the active layer 124. For example, the gate insulating layer 113 may be formed of an insulating inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), or it may be formed of an insulating organic material or the like.

[0088] The gate electrode 121 may be located on the gate insulating layer 113. For example, the gate electrode 121 may be formed from a variety of conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof.

[0089] The interlayer insulating layer 114 may be located on the gate electrode 121. For example, the interlayer insulating layer 114 may be formed of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), or it may be formed of an insulating organic material or the like.

[0090] Selective removal of the gate insulating layer 113 and the interlayer insulating layer 114 can form contact holes that expose the source and drain regions. The source electrode 122 and drain electrode 123 can be formed on the interlayer insulating layer 114 in a single-layer or multi-layer structure using electrode material.

[0091] If necessary, an additional protective layer (passivation layer) made of an inorganic insulating material may be formed to cover the source electrode 122 and the drain electrode 123.

[0092] On the other hand, at least some of the buffer layer 112, gate insulating layer 113, and interlayer insulating layer 114, i.e., insulating layer 117, may extend into the non-display region NA.

[0093] A planarization layer 115 can be placed on the drive element 120 configured in this way.

[0094] The planarization layer 115 may have a multilayer structure consisting of at least two layers. For example, referring to Figure 2, the planarization layer 115 may, but is not limited to, include a first planarization layer 115a and a second planarization layer 115b.

[0095] For example, the first planarization layer 115a may be positioned to cover the drive element 120, such that a portion of the source electrode 122 or drain electrode 123 of the drive element 120 is exposed.

[0096] The planarization layer 115 may extend into the non-display region NA.

[0097] The planarization layer 115 may be, but is not limited to, an overcoat layer.

[0098] A connecting electrode 125 for electrically connecting the driving element 120 and the light-emitting element 130 may be placed on the first planarization layer 115a. Although not shown in Figure 2, various metal layers serving as wires / electrodes for data wiring, signal wiring, etc., may also be placed on the first planarization layer 115a. Furthermore, while a color filter CF may be placed on the first planarization layer 115a, it is not limited to this, and the color filter CF may be omitted depending on the type of organic light-emitting element 130. The color filter CF for each subpixel may have one of the colors red, green, or blue. Also, in the case of a subpixel where white is realized, a color filter CF may not be placed. The arrangement of red, green, and blue can be formed in various forms.

[0099] Furthermore, a second planarization layer 115b may be arranged on the first planarization layer 115a and the connecting electrode 125. The reason that the planarization layer 115 in the first embodiment of the present invention consists of two layers is that as the resolution of the display device 100 has increased, the number of various signal wirings has increased. Therefore, it is difficult to arrange all the wirings on a single layer while ensuring the minimum spacing, so an additional layer is provided. The addition of such an additional layer (i.e., the second planarization layer 115b) creates more leeway in wiring arrangement, which can make wiring / electrode arrangement design even easier. Also, if a dielectric material is used as the multilayer planarization layer 115, it can be used to form capacitance between metal layers.

[0100] The second planarization layer 115b may be formed such that a portion of the connecting electrode 125 is exposed. The connecting electrode 125 can then electrically connect the drain electrode 123 of the driving element 120 and the anode 131 of the light-emitting element 130.

[0101] In this case, the light-emitting element 130 may be constructed by sequentially arranging an anode 131, a plurality of organic layers 132, and a cathode 133. That is, the light-emitting element 130 may consist of an anode 131 arranged on the planarization layer 115, an organic layer 132 arranged on the anode 131, and a cathode 133 arranged on the organic layer 132.

[0102] The display device 100 can be implemented using either a top emission method or a bottom emission method. In the case of the top emission method, a reflective layer made of a highly reflective, opaque conductive material, such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof, may be added below the anode 131 so that the light emitted from the organic layer 132 is reflected by the anode 131 and directed upward, i.e., towards the upper cathode 133. Conversely, in the case of the bottom emission method, the anode 131 may consist only of a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). In the following description, the display device 100 of the present invention will be described assuming that it is a bottom emission method. However, the present invention is not limited thereto.

[0103] A bank 116 may be formed in the remaining region of the planarized layer 115, excluding the light-emitting region. That is, the bank 116 has bank holes that expose the anode 131 corresponding to the light-emitting region. The bank 116 may consist of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as BCB, acrylic resin, or imide resin.

[0104] Bank 116 may extend into the hidden region NA.

[0105] An organic layer 132 may be placed on the anode 131 exposed by the bank 116. The organic layer 132 may include an emissive layer, an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, and the like.

[0106] The organic layer 132 may extend into the non-display region NA.

[0107] A cathode 133 can be placed on the organic layer 132.

[0108] In the case of an upper emission method, the cathode 133 may include a transparent conductive material. For example, the cathode 133 may consist of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), etc. In the case of a lower emission method, the cathode 133 may include any one of the group consisting of metallic materials such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), magnesium (Mg), palladium (Pd), copper (Cu), etc., or alloys thereof. Alternatively, cathode 133 may be constructed by laminating a layer of a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide) with a layer of a metallic material such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), magnesium (Mg), palladium (Pd), copper (Cu), or an alloy thereof.

[0109] Cathode 133 may extend into the non-display region NA.

[0110] Although not shown in the diagram, a capping layer may be placed on the cathode 133. The capping layer may be made of a material with a high refractive index and light absorption rate in order to reduce diffuse reflection of external light.

[0111] A protective layer 140 can be placed on top of the light-emitting element 130 configured in this way.

[0112] The protective layer 140 may be an inorganic layer, in which case it may consist of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0113] The protective layer 140 may extend into the non-display area NA.

[0114] An adhesive layer 165 and a sealing substrate 160 may be placed on top of the protective layer 140.

[0115] However, the present invention is not limited thereto, and a sealing structure of a multilayer structure composed of a sealing member and a reinforcing substrate may be arranged on top of the protective layer 140.

[0116] The adhesive layer 165 may be placed between the protective layer 140 and the sealing substrate 160.

[0117] For example, the adhesive layer 165 can play a role in delaying lateral moisture permeation.

[0118] For example, the adhesive layer 165 may further contain a desiccant such as a getter in addition to the isobutyl rubber resin. The desiccant may include calcium oxide.

[0119] The desiccant may be a hygroscopic particle, which can absorb moisture and oxygen from the outside, minimizing the penetration of moisture and oxygen into the display area AA.

[0120] A sealing substrate 160 can be placed on the adhesive layer 165.

[0121] The encapsulating substrate 160, together with the adhesive layer 165, can protect the light-emitting element 130 from external moisture, oxygen, shock, and other elements.

[0122] For example, the sealing substrate 160 can serve to prevent moisture from permeating from the front surface.

[0123] For example, the encapsulating substrate 160 may be made of stainless steel (Steel Use Stainless; SUS) or Invar, but is not limited to these. Invar is an alloy composed of nickel and iron, and has a very low coefficient of thermal expansion, giving it relatively stable properties against temperature changes.

[0124] In the non-display region NA, the insulating layer 117, i.e., at least some of the buffer layer 112, gate insulating layer 113, and interlayer insulating layer 114, may extend.

[0125] Furthermore, the planarization layer 115 may extend into the non-display region NA.

[0126] For example, the insulating layer 117 and planarizing layer 115 extending into the non-display area NA may, but are not limited to, extend to the edge of the substrate 111.

[0127] On the other hand, a minimum bezel distance is required to ensure reliability such as moisture permeability prevention in the display device 100. In line with the demand for slimmer display devices 100, there is also an increasing demand for slimmer non-display area NA, excluding the display area AA where the image is displayed. However, during the deposition of the cathode 133 and the organic layer 132, a shadow area is generated due to the gap between the mask and the substrate, which limits the reduction of the bezel.

[0128] Therefore, in the first embodiment of the present invention, a trench 180 is arranged in the shadow region within the non-display region NA. That is, in the first embodiment of the present invention, the rate of moisture penetration to the side surface of the display device 100 can be delayed through the trench 180. Furthermore, by converting the existing shadow region into a reliability bezel region L in this way, the bezel width can be reduced. The reliability bezel region L can be defined as extending from the edge of the sealing substrate 160 to the edge of the cathode 133.

[0129] The trench 180 may be formed across the left, right, and lower non-display areas NA of the four sides of the display device 100, excluding the upper side where the data pad area 107 is located (see Figure 1), but is not limited thereto. In this case, for example, the trench 180 may be formed by removing a portion of the insulating layer 117 and planarization layer 115 in the shadow area within the non-display area NA through laser ablation. This expands the reliability bezel area L, and the bezel width may be reduced by the length of the added reliability bezel area L. In this case, for example, the trench 180 may expose at least a portion of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114.

[0130] For example, the trench 180 can have a certain width to prevent a decrease in moisture permeability, regardless of the formation position of the cathode 133, taking into account process errors and margins.

[0131] On the other hand, low-potential power supply wiring 135 can be placed inside the trench 180.

[0132] For example, the low-potential power wiring 135 may be positioned to cover the inside of the trench 180. That is, the low-potential power wiring 135 may be positioned to cover the top and side surfaces of the insulating layer 117 and the planarization layer 115 exposed by the trench 180.

[0133] For example, the low-potential power supply wiring 135 may be arranged along the trench 180 across the left, right, and lower non-display areas NA of the display device 100, but is not limited thereto.

[0134] The low-potential power line 135 may include an inner portion and an outer portion positioned on the inclined side surface of the trench 180. For example, in the non-display area NA excluding the second side, the bank 116 may extend into the non-display area NA so as to cover the inner portion of the low-potential power line 135. Here, the inner portion of the low-potential power line 135 may be defined as the side adjacent to the display area AA and may be the side opposite the outer portion adjacent to the non-display area NA. In this case, the inner portion of the low-potential power line 135 may be positioned to have a predetermined taper on the inner surface of the trench 180. For example, the side surface of the trench 180 and the side surface of the low-potential power line 135 may have a gentle taper of about 30 degrees or less. This gentle taper allows for a cathode 133 thickness of 1,000 Å or more to be deposited on its upper surface.

[0135] The outer bank 116' can cover the outer portion of the low-potential power wiring 135 in an island configuration. On the other hand, bank 116 and the outer bank 116' are separated and arranged on either side of the trench 180, and a portion of the upper surface of the low-potential power wiring 135 may be exposed without being covered by the outer bank 116'.

[0136] The outer bank 116' can be positioned at a certain distance from the edges of the adhesive layer 165 and the sealing substrate 160. That is, in the first embodiment of the present invention, the outer bank 116' is formed to cover the tapered portion of the low-potential power wiring 135 and the planarization layer 115, and is removed in the remaining area. Thus, the water transfer velocity (WTV) can be suppressed. For example, when the bank in the outer region is removed, it can be seen that the water transfer velocity is reduced by about 10%.

[0137] In contrast, in the second non-display region NA, bank 116 may, but is not limited to, extend along the flattening layer 115 into the non-display region NA.

[0138] On the other hand, in the non-display region NA, the organic layer 132 can be placed on bank 116.

[0139] The organic layer 132 may, but is not limited to, extend into the non-display region NA, with its edge positioned inward relative to the edge of bank 116.

[0140] In the non-display region NA, the cathode 133 may be placed on the organic layer 132.

[0141] In this case, the cathode 133 may, but is not limited to, extend into the trench 180 so as to cover a portion of the upper surface of the exposed low-potential power supply wiring 135.

[0142] For example, the cathode 133 may extend into the interior of the trench 180 so as to cover the inner bank 116 and the organic layer 132 of the trench 180.

[0143] The cathode 133 may be in contact with the upper surface of the exposed low-potential power supply wiring 135, where it can receive low-potential power from the low-potential power supply wiring 135. The cathode 133 may be located in display area AA and extend to trench 180 and connected to the low-potential power supply line 135.

[0144] Furthermore, the protective layer 140 may, but is not limited to, extend into the trench 180 so as to cover the cathode 133. The protective layer 140 may be positioned on the cathode 133. For example, the protective layer 140 may be positioned to surround the cathode 133, except for the second non-display area NA. Alternatively, the protective layer 140 may cover a portion of the upper surface of the cathode 133 in the second non-display area NA.

[0145] For example, the protective layer 140 may consist of an inorganic insulating material.

[0146] The protective layer 140 can delay moisture permeation at the top, thereby suppressing defects caused by cutting or foreign matter.

[0147] The protective layer 140 may, but is not limited to, silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer structure thereof in order to delay moisture permeation.

[0148] An adhesive layer 165 can be interposed between the protective layer 140 and the sealing substrate 160.

[0149] On the other hand, the display device 100 of the first embodiment of the present invention, configured in this way, is characterized in that the GIP circuit section 108 is located inside the trench 180.

[0150] In other words, if the GIP circuit is located at the bottom of the trench or at the edge of the sealing substrate, as in existing designs, drive failures due to wiring corrosion will occur frequently as moisture permeates the circuit. For example, in existing designs, the GIP circuit was positioned approximately 0.2 mm away from the edge of the sealing substrate, which sometimes caused moisture to corrode the GIP circuit and lead to drive abnormalities.

[0151] A first embodiment of the present invention is characterized by arranging a trench 180 at the edge of the non-display area NA, and arranging a GIP circuit section 108 inside the trench 180 so as to be separated from the trench 180 by a certain distance G. As a result, for example, the GIP circuit section 108 can be positioned at a distance of 1.5 mm or more from the edge of the sealing substrate 160.

[0152] Furthermore, in the first embodiment of the present invention, the main wiring (i.e., the high-potential power supply wiring EVDD) can be relocated inside the trench 180.

[0153] In the first embodiment of the present invention, the cathode 133 can be extended into the trench 180 to seal the GIP circuit section 108. That is, in existing designs, moisture could penetrate into the interior along the organic film material of the bank and planarization layer, damaging not only the GIP circuit section but also the light-emitting element. However, by extending the cathode 133 into the trench 180 and contacting the low-potential power supply wiring 135, sealing the entire GIP circuit section 108 and the display area AA, the penetration of moisture and oxygen can be prevented.

[0154] As a result, the present invention can minimize the effects of moisture permeability and dramatically improve the stability and durability of the GIP circuit section 108. Consequently, the reliability of the display device 100 can be improved.

[0155] On the other hand, the present invention allows for the placement of further trenches inside the trench, which will be described in detail with reference to the drawings.

[0156] Figure 6 is a plan view of a display device according to a second embodiment of the present invention.

[0157] Figure 7 shows a cross-section of the display device shown in Figure 6 along line IIa-IIa'.

[0158] Figure 8 shows a cross-section of the display device in Figure 6 along the line IIb-IIb'.

[0159] The second embodiment shown in Figures 6 to 8 differs from the first embodiment shown in Figures 1 to 5 in the configuration of trenches 280 and 285, but the other configurations are substantially the same, so redundant explanations will be omitted. The same reference numerals will be used for the same configurations. For explanations of the same reference numerals, please refer to Figures 1 to 5 below.

[0160] Figure 7 shows a portion of the non-display area NA on the second side of the display device 200 in Figure 6, and Figure 8 shows a portion of the non-display area NA on the first side of the display device 200 in Figure 6.

[0161] In Figure 8, for the sake of explanation, the GIP circuit section 108 within the non-display area NA is schematically shown.

[0162] In Figures 7 and 8, for the sake of explanation, at least some of the buffer layer, gate insulating layer, and interlayer insulating layer are shown as insulating layer 117.

[0163] Referring to Figures 6 to 8, in the second embodiment of the present invention, the display device 200 may have a planarization layer 215 placed on top of the substrate 111.

[0164] A grounding wire GW may be placed on top of the substrate 111 in the non-display area NA, excluding the second side. The grounding wire GW may be placed outside the trenches 280 and 285 in the non-display area NA on the first and third sides.

[0165] A first light-shielding pattern PP1 may be placed inside the grounding wiring GW.

[0166] Link wiring LW may be placed on the upper part of the substrate 111 of the second non-display area NA.

[0167] In the second embodiment of the present invention, the GIP circuit section 108 can be arranged inside the trenches 280 and 285 in the left and right non-display areas NA.

[0168] The GIP circuit section 108 may include, but is not limited to, a control signal clock wiring CW, a logic section LP, a buffer TFT section B-TFT, and a power supply wiring GVSS.

[0169] A light-emitting element (130 in Figure 2) electrically connected to a driving element (120 in Figure 2) may be placed on the planarization layer 215 of the display area AA.

[0170] A bank 216 can be formed in the remaining region of the planarized layer 215, excluding the light-emitting region.

[0171] The insulating layer 117, the planarization layer 215, and the bank 216 may extend into the non-display region NA.

[0172] For example, the insulating layer 117 and planarization layer 215 extending into the non-display area NA may, but are not limited to, extend to the edge of the substrate 111.

[0173] On the other hand, the second embodiment of the present invention is characterized by arranging a plurality of trenches 280, 285 in the shadow region within the non-display region NA.

[0174] Trenches 280, 285 may include a first trench 280 and a plurality of second trenches 285.

[0175] The first trench 280 may be formed over the left, right, and lower non-display areas NA of the four sides of the display device 200, excluding the upper side where the data pad portion 107 is located (see Figure 6), but is not limited thereto. In this case, for example, the first trench 280 may be formed by removing a portion of the insulating layer 117 and the planarization layer 215 in the non-display area NA. Thus, for example, the first trench 280 may expose at least a portion of the buffer layer, gate insulating layer, and interlayer insulating layer.

[0176] The second trench 285 may be formed across four sides of the display device 200, namely the upper, left, right, and lower non-display areas NA (see Figure 6), but is not limited thereto. In this case, for example, the second trench 285 may be formed by removing a portion of the planarization layer 215 of the non-display area NA. The second trench 285 may then expose at least some of the buffer layer, gate insulating layer, and interlayer insulating layer.

[0177] Multiple trenches 285 may be arranged.

[0178] The first trench 280 may have a wider width than the second trench 285. For example, the first trench 280 may be called an OC (overcoat) hole, and the second trench 285 may be called a bar trench.

[0179] For example, multiple dams 250 may be located between the second trench 285.

[0180] For example, multiple dams 250 may be located between the first trench 280 and the second trench 285, and between the second trench 285, but are not limited to this.

[0181] Dam 250 may, but is not limited to, consist of a flattening layer 215.

[0182] Dam 250 may, but is not limited to, having a lower height than the surrounding flattening layer 215.

[0183] On the other hand, a first low-potential power supply wiring 235 may be placed inside the first trench 280.

[0184] The first low-potential power wiring 235 may be positioned to cover the interior of the first trench 280. That is, the first low-potential power wiring 235 may be positioned to cover the upper and side surfaces of the insulating layer 117 and the planarization layer 215 exposed by the first trench 280. The first low-potential power line 235 may be positioned to cover the upper surface of the insulating layer 117, as well as a portion of the upper and side surfaces of the planarization layer 215 exposed by the first trench 280.

[0185] In this case, the first low-potential power supply wiring 235 may, but is not limited to, be arranged along the first trench 280 across the left, right, and lower non-display areas NA of the display device 200.

[0186] Furthermore, a second low-potential power supply wiring 236 may be placed inside the second trench 285.

[0187] The second low-potential power supply wiring 236 may be positioned to cover the interior of the second trench 285. That is, the second low-potential power supply wiring 236 may be positioned to cover the insulating layer 117 and a portion of the sides and top of the dam 250 that are exposed by the second trench 285.

[0188] In this case, the second low-potential power supply wiring 236 may, but is not limited to, be arranged along the second trench 285 across the upper, left, right, and lower non-display areas NA of the display device 200.

[0189] For example, outside the GIP circuit section 108, an outer bank 216' and an inner bank 216'' may be arranged in an island configuration, separated from bank 216.

[0190] For example, the outer bank 216' can cover the outer portion of the first low-potential power supply wiring 235 in an island configuration. On the other hand, the outer bank 216' and the inner bank 216'' are separated and arranged on either side of the first trench 280, and a portion of the upper surface of the first low-potential power supply wiring 235 may be exposed without being covered by the outer bank 216'.

[0191] The outer bank 216' may be positioned at a certain distance from the edges of the adhesive layer 165 and the sealing substrate 160. That is, in the second embodiment of the present invention, the outer bank 216' is formed to cover the tapered portion of the first low-potential power wiring 235 and the planarization layer 215 outside the first trench 280, and is removed in the remaining area.

[0192] For example, an inner bank 216'' can cover the inner portion of the first low-potential power supply wiring 235 and / or the side portion of the second low-potential power supply wiring 236 in an island configuration. That is, there are multiple inner banks 216'', one inner bank 216'' can cover the inner portion of the first low-potential power supply wiring 235 and the side portion of the second low-potential power supply wiring 236, and another inner bank 216'' can cover the side portion of one second low-potential power supply wiring 236 and the side portion of another second low-potential power supply wiring 236.

[0193] In contrast, in the second non-display region NA, bank 216 may, but is not limited to, extend along the planarization layer 215 into the non-display region NA.

[0194] On the other hand, in the non-display region NA, the organic layer 132 can be placed on bank 216.

[0195] The organic layer 132 may, but is not limited to, extend into the non-display region NA, with its edge positioned inward relative to the edge of bank 216.

[0196] In the non-display region NA, cathode 233 may be located on the organic layer 132.

[0197] In this case, the cathode 233 may, but is not limited to, extend into the first trench 280 so as to cover a portion of the upper surface of the exposed first low-potential power supply wiring 235.

[0198] For example, except for the second non-display region NA, the cathode 233 may extend into the first trench 280 to cover the inner bank 216'' and the second low-potential power supply wiring 236. In contrast, in the second non-display region NA, the cathode 233 may extend into the non-display region NA to cover the inner bank 216'' and the second trench 285.

[0199] The cathode 233 can contact the upper surface of the exposed first low-potential power supply wiring 235, where it can receive low-potential power from the first low-potential power supply wiring 235.

[0200] Furthermore, the protective layer 240 may, but is not limited to, extend into the interior of the trenches 280 and 285 so as to cover the cathode 233. In this case, for example, the protective layer 240 may be positioned to surround the cathode 233, except for the second non-display area NA. In contrast, in the second non-display area NA, the protective layer 240 may cover a portion of the upper surface of the cathode 233 inside the second trench 285. Also, the protective layer 240 may cover the interior of the second trench 285.

[0201] An adhesive layer 165 can be interposed between the protective layer 140 and the sealing substrate 160.

[0202] On the other hand, the display device 200 of the second embodiment of the present invention configured in this way is characterized in that the GIP circuit section 108 is located inside the second trench 285.

[0203] A second embodiment of the present invention is characterized in that a first trench 280 and a plurality of second trenches 285 are arranged at the edge of the non-display area NA, and a GIP circuit section 108 is arranged inside the second trenches 285 so as to be spaced at a certain distance G1 from the innermost second trench 285.

[0204] Thus, in the second embodiment of the present invention, the rate of moisture penetration into the side surface of the display device 200 can be further delayed by arranging a plurality of second trenches 285 in the first trench 280. Furthermore, in the second embodiment of the present invention, the penetration of moisture and oxygen can be prevented even more effectively by arranging the GIP circuit section 108 inside the second trenches 285, which are located further inside than the first trench 280.

[0205] On the other hand, the present invention may involve arranging a sealing structure of a multilayer structure composed of a sealing member and a reinforcing substrate on top of the cathode, which will be described in detail with reference to the drawings.

[0206] Figure 9 is a cross-sectional view of a display device according to a third embodiment of the present invention.

[0207] The third embodiment shown in Figure 9 differs from the second embodiment shown in Figures 6 to 8 above only in that a sealing structure of a multilayer structure composed of a sealing member 365 and a reinforcing substrate 360 ​​is applied. Since the other components are substantially the same, redundant explanations will be omitted. The same reference numerals will be used for the same components. For explanations of the same reference numerals, please refer to Figures 1 to 8 below.

[0208] Figure 9 shows, as an example, a part of the non-display area NA on the first side in a display device 300 according to a third embodiment of the present invention.

[0209] Referring to Figure 9, in the third embodiment of the present invention, the display device 300 may have a first trench 280 and a plurality of second trenches 285 arranged in the non-display area NA.

[0210] Multiple dams 250 may be located between the second trench 285.

[0211] A first low-potential power supply wiring 235 may be placed inside the first trench 280.

[0212] Furthermore, a second low-potential power supply wiring 236 may be placed inside the second trench 285.

[0213] In the third embodiment of the present invention, the GIP circuit section 108 can be arranged inside the second trench 285 in the left and right non-display areas NA.

[0214] Outside the GIP circuit section 108, an outer bank 216' and an inner bank 216'' may be arranged in an island configuration, separated from bank 216.

[0215] Furthermore, cathode 233 may extend into the interior of the first trench 280 to cover a portion of the upper surface of the exposed first low-potential power supply wiring 235. Cathode 233 may also extend into the interior of the first trench 280 to cover the inner bank 216'' and the second low-potential power supply wiring 236.

[0216] A sealing structure consisting of a multilayer structure comprising a sealing member 365 and a reinforcing substrate 360 ​​may be placed above the cathode 233.

[0217] Small display panels used in mobile and portable devices have a small surface area, allowing heat to dissipate quickly from the elements and resulting in fewer bonding problems. However, large display panels used in monitors, tablets, and television receivers have a large surface area, requiring a sealing structure that provides optimal heat dissipation and bonding strength.

[0218] In addition, to compensate for the lack of rigidity, the display device may be further equipped with a separate inner plate on top of the encapsulating substrate. In this case, it is necessary to secure space for the separate inner plate, and there is a problem that the weight of the inner plate limits the slimming and weight reduction of the display device. Furthermore, there is a limitation that the thickness of the adhesive tape used to bond the encapsulating substrate and the inner plate creates an air gap between them, resulting in a vertical separation space and reducing heat dissipation performance.

[0219] Therefore, in the third embodiment of the present invention, a sealing structure for a multilayer structure is applied that includes a sealing member 365, which allows a relatively thick reinforcing substrate 360 ​​to be fixed while removing a separate inner plate, thereby preventing process defects.

[0220] For example, the sealing member 365 according to the third embodiment of the present invention may include a first adhesive layer 365a facing the substrate 111, a second adhesive layer 365c facing the reinforcing substrate 360, and a barrier layer 365b disposed between the first adhesive layer 365a and the second adhesive layer 365c.

[0221] In this case, the first adhesive layer 365a and the second adhesive layer 365c may each consist of an adhesive polymer material. For example, the first adhesive layer 365a may consist of one polymer material from the olefin series, epoxy series, or acrylate series. The second adhesive layer 365c may consist of one polymer material from the olefin series, epoxy series, acrylate series, amine series, phenol series, or acid anhydride series that does not contain a carboxyl group.

[0222] For heat dissipation of the substrate 111, at least the first adhesive layer 365a of the first and second adhesive layers 365a and 365c may consist of a mixture containing an adhesive polymer material and metallic material particles. As an example, the metallic material particles may be nickel (Ni) powder.

[0223] In this way, the rate at which the heat generated on the substrate 111 is released through the sealing member 365 can be improved, thus improving the heat dissipation effect on the substrate 111.

[0224] Furthermore, to prevent moisture permeability, the first adhesive layer 365a may consist of a mixture further containing a hygroscopic inorganic filler. The hygroscopic inorganic filler may be at least one of barium oxide (BaO), calcium oxide (CaO), and magnesium oxide (MgO).

[0225] Furthermore, forming a multilayer structure with a first adhesive layer 365a and a second adhesive layer 365c has the advantage of reducing the warpage phenomenon, which causes the display panel to warp, and also improves reliability.

[0226] The barrier layer 365b may consist of either a metallic material or an inorganic insulating material. That is, the barrier layer 365b may contain metallic materials such as Al, Cu, Sn, Ag, Fe, and Zn. In other examples, the barrier layer 365b may consist of a thin film of an inorganic insulating material such as SiOx and SiONx.

[0227] Thus, since the sealing member 365 of the third embodiment of the present invention includes first and second adhesive layers 365a and 365c separated by a barrier layer 365b, it can be realized with a thickness approximately twice that of a single layer of adhesive material without process defects. As a result, the reinforcing substrate 360 ​​fixed by the sealing member 365 can be provided with a thicker thickness, which has the advantage of easily achieving increased rigidity and improved heat dissipation effect.

[0228] For example, the reinforcing substrate 360 ​​may consist of one of the following materials: glass, metal, and plastic polymer. For example, the reinforcing substrate 360 ​​may consist of a metallic material containing Al, Cu, Sn, Ag, Fe, or Zn components.

[0229] On the other hand, the cathode of the present invention may be arranged to completely cover the inside of the trench, which will be described in detail with reference to the drawings.

[0230] Figure 10 is a cross-sectional view of a display device according to a fourth embodiment of the present invention.

[0231] Figure 11 is a cross-sectional view of a display device according to a fifth embodiment of the present invention.

[0232] The fourth embodiment in Figure 10 differs from the first embodiment in Figures 1 to 5 described above only in the configuration of the cathode 433 and the protective layer 440; the other configurations are substantially the same, so redundant explanations are omitted. Similarly, the fifth embodiment in Figure 11 differs from the third embodiment in Figures 7 to 9 described above only in the configuration of the cathode 533; the other configurations are substantially the same, so redundant explanations are omitted. The same reference numerals will be used for the same configurations. For explanations of the same reference numerals below, please refer to Figures 1 to 9.

[0233] Figures 10 and 11 show, as examples, a portion of the non-display area NA on the first side in the display devices 400 and 500 of the fourth and fifth embodiments of the present invention, respectively.

[0234] Referring to Figure 10, a trench 180 may be provided at the edge of the non-display area NA between the substrate 111 and the sealing substrate 160.

[0235] In the non-display areas NA on the left and right, the GIP circuit section 108 can be placed inside the trench 180.

[0236] Low-potential power supply wiring 135 may be placed inside the trench 180.

[0237] For example, bank 116 may extend into the non-display area NA so as to cover the inner portion of the low-potential power supply wiring 135. On the other hand, an outer bank 116', separated from bank 116 around the trench 180, can cover the outer portion of the low-potential power supply wiring 135 in an island configuration, and a portion of the upper surface of the low-potential power supply wiring 135 may be exposed without being covered by the outer bank 116'.

[0238] In the non-display region NA, cathode 433 can be placed on the organic layer 132.

[0239] In the fourth embodiment of the present invention, the cathode 433 may extend into the non-display area NA so as to cover the entire trench 180. That is, for example, the cathode 433 may extend into the non-display area NA so as to cover the upper surface of the exposed low-potential power supply wiring 135 and a portion of the sides and upper surface of the outer bank 116'.

[0240] Furthermore, the protective layer 440 may, but is not limited to, extend into the non-display area NA so as to cover the cathode 433. For example, the protective layer 440 may also extend into the non-display area NA so as to surround the cathode 433 and the outer bank 116'.

[0241] Referring to Figure 11, the GIP circuit section 108 may be located inside the trenches 280 and 285 in the non-displayed areas NA on the left and right. The GIP circuit section 108 may be located on both the first side and the second side opposite the first side.

[0242] Trenches 280 and 285 may include, in order from the outside, a first trench 280 and a plurality of second trenches 285.

[0243] For example, multiple dams 250 may be located between the second trench 285.

[0244] A first low-potential power supply wiring 235 may be placed inside the first trench 280.

[0245] Furthermore, a second low-potential power supply wiring 236 may be placed inside the second trench 285.

[0246] For example, outside the GIP circuit section 108, an outer bank 216' and an inner bank 216'' may be arranged in an island configuration, separated from bank 216.

[0247] For example, the outer bank 216' can cover the outer portion of the first low-potential power supply wiring 235 in an island configuration. The inner bank 216'' can also cover the inner portion of the first low-potential power supply wiring 235 and / or the side portion of the second low-potential power supply wiring 236 in an island configuration.

[0248] In the non-display region NA, cathode 533 can be placed on the organic layer 132.

[0249] In the fifth embodiment of the present invention, the cathode 533 may extend into the non-display area NA to cover the entire trenches 280, 285. For example, the cathode 533 may include the inner bank 216'' and the second low-potential power supply wiring 236, and may extend into the non-display area NA to cover the top surface of the exposed low-potential power supply wiring 235 and part of the sides and top surface of the outer bank 216'. Furthermore, the protective layer 540 may extend to the non-display area NA to cover the cathode 533, but is not limited thereto. For example, the protective layer 540 may extend to the non-display area NA to surround the cathode 533 and the outer bank 216'.

[0250] The display device according to an embodiment of the present invention can be described as follows.

[0251] A display device according to one embodiment of the present invention may include a substrate including a display area and a non-display area outside the display area; an insulating layer and a planar layer disposed on the upper part of the substrate and extending from the display area to the non-display area; at least one trench disposed in the non-display area and formed by removing a portion of at least one of the insulating layer and the planar layer; a bank disposed on the planar layer and extending to the non-display area; an organic layer disposed on the bank; a cathode disposed on the organic layer and extending to the trench; a protective layer disposed on top of the cathode; and a gate-in-panel (GIP) circuit section disposed in at least one of the left and right non-display areas and located inside the trench.

[0252] According to another feature of the present invention, the trench may be arranged in a manner that surrounds the display area, excluding the upper part.

[0253] According to yet another feature of the present invention, the display device may further include a grounding wire positioned on the upper part of the substrate of the non-display area excluding the upper part, a first light-shielding pattern positioned inside the grounding wire, a linking wire positioned on the upper part of the substrate of the upper non-display area, and a second light-shielding pattern and a high-potential power supply wire positioned in the lower non-display area and inside the trench.

[0254] According to yet another feature of the present invention, the display device further includes low-potential power supply wiring disposed inside the trench so as to cover the inside of the trench, the low-potential power supply wiring may be disposed so as to cover the upper surface of the insulating layer and a portion and side of the upper surface of the planarizing layer exposed by the trench.

[0255] According to yet another feature of the present invention, the low-potential power wiring includes an inner portion and an outer portion located on the inclined side of the trench, the bank extends into the non-display area, except the upper portion, so as to cover the inner portion of the low-potential power wiring, and the bank may extend into the non-display area along the planarization layer in the upper non-display area.

[0256] According to yet another feature of the present invention, the display device further includes an outer bank separated from the bank around the trench and covering the outer portion of the low-potential power supply wiring in an island configuration, wherein a portion of the upper surface of the low-potential power supply wiring may be exposed without being covered by the outer bank.

[0257] According to yet another feature of the present invention, a sealing substrate may be placed on top of the protective layer with an adhesive layer interposed therebetween, and the outer bank may be positioned at a certain distance from the edges of the adhesive layer and the sealing substrate.

[0258] According to yet another feature of the present invention, the cathode extends into the trench so as to cover a portion of the upper surface of the exposed low-potential power supply wiring, the cathode is in contact with the upper surface of the exposed low-potential power supply wiring, and the cathode can cover the bank and the organic layer inside the trench.

[0259] According to another feature of the present invention, in the non-display area excluding the upper part, the protective layer is arranged to surround the cathode, and in the upper non-display area, the protective layer can cover a portion of the upper surface of the cathode.

[0260] According to yet another feature of the present invention, the trench may include a first trench positioned over the non-visible area excluding the upper side, and a second trench located inside the first trench and positioned over the upper side and the left, right, and lower non-visible areas.

[0261] According to yet another feature of the present invention, the first trench may be constructed by removing a portion of the insulating layer and the planarizing layer in the non-display area, and the second trench may be constructed by removing a portion of the planarizing layer in the non-display area.

[0262] According to yet another feature of the present invention, the second trenches are arranged in a plurality, and the display device is arranged between the plurality of second trenches and further includes a plurality of dams composed of the flattening layer.

[0263] According to yet another feature of the present invention, the display device further includes low-potential power supply wiring disposed inside the first trench so as to cover the interior of the first trench, the low-potential power supply wiring may be disposed so as to cover the upper surface of the insulating layer and a portion and side of the upper surface of the planarization layer exposed by the first trench.

[0264] According to yet another feature of the present invention, the display device further includes a second low-potential power supply wiring disposed inside the second trench so as to cover the interior of the second trench, the second low-potential power supply wiring may be disposed so as to cover the upper surface of the insulating layer and a portion and side of the upper surface of the dam that are exposed by the second trench.

[0265] According to yet another feature of the present invention, the display device further includes an outer bank and an inner bank arranged in an island configuration, separated from the bank outside the GIP circuit section, wherein the outer bank covers the outer portion of the low-potential power supply wiring in the non-display area except the upper portion, and a portion of the upper surface of the low-potential power supply wiring may be exposed without being covered by the outer bank.

[0266] According to yet another feature of the present invention, a sealing substrate may be placed on top of the protective layer with an adhesive layer interposed therebetween, and the outer bank may be positioned at a certain distance from the edges of the adhesive layer and the sealing substrate.

[0267] According to yet another feature of the present invention, the inner bank and the second low-potential power supply wiring are composed of a plurality, and one inner bank can cover the inner portion of the low-potential power supply wiring and the side portion of one second low-potential power supply wiring, and another inner bank can cover the side portion of one second low-potential power supply wiring and the side portion of another second low-potential power supply wiring.

[0268] According to yet another feature of the present invention, in the non-display area excluding the upper part, the cathode may extend into the first trench so as to cover the inner bank and the second low-potential power supply wiring, and in the upper non-display area, the cathode may extend into the non-display area so as to cover the inner bank and the second trench.

[0269] According to yet another feature of the present invention, the protective layer is positioned to surround the cathode in the non-display area excluding the upper part, and the protective layer can cover a portion of the upper surface of the cathode inside the second trench in the non-display area.

[0270] According to yet another feature of the present invention, the cathode may extend into the non-display area so as to cover the entire trench, and the protective layer may extend into the non-display area so as to surround the cathode.

[0271] Although embodiments of the present invention have been described in more detail above with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of the present invention. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. Therefore, the embodiments described above should be understood to be illustrative and non-limiting in all respects. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A substrate including a display area and a non-display area outside the display area, An insulating layer and a planarizing layer are disposed on the substrate and extend from the display area to the non-display area. At least one trench is located in the non-display area and is formed by removing a portion of at least one of the insulating layer and the planarizing layer, A bank arranged on the flattening layer and extending into the non-display area, An organic layer placed on the bank, A cathode is placed on the organic layer and extends into the trench. A protective layer disposed on the cathode, and A display device including a gate-in-panel (GIP) circuit section located on the first side of the non-display area and inside the trench.

2. The display device according to claim 1, wherein a data pad section is arranged on a second side adjacent to the first side where the gate-in-panel circuit section is arranged.

3. The display device according to claim 2, wherein the trench is arranged to surround the display area excluding the second side.

4. Grounding wiring, which is located on the upper part of the substrate in the non-display area excluding the second side, A first light-shielding pattern is placed inside the grounding wiring, and The display device according to claim 2, further comprising link wiring disposed on the upper part of the substrate of the second non-display area.

5. The display device according to claim 4, further comprising a second light-shielding pattern and high-potential power supply wiring, disposed on the third and / or fourth side of the non-display area where the gate-in-panel circuit section and the data pad section are absent, and located inside the trench.

6. The system further includes a first low-potential power supply wiring positioned inside the trench so as to cover the inside of the trench, The display device according to claim 2, wherein the first low-potential power supply wiring is arranged to cover the upper surface of the insulating layer and a portion of the upper surface and side of the flattening layer exposed by the trench.

7. The first low-potential power supply wiring includes an inner portion and an outer portion that are positioned on the inclined side surface of the trench. In the non-display area excluding the second side, the bank extends into the non-display area so as to cover the inner part of the first low-potential power supply wiring, The display device according to claim 6, wherein in the non-display region on the second side, the bank extends to the non-display region along the planarization layer.

8. The system further includes an outer bank, separated from the bank around the trench, and covering the outer portion of the first low-potential power supply wiring in an island configuration. The display device according to claim 7, wherein a portion of the upper surface of the first low-potential power supply wiring is exposed without being covered by the outer bank.

9. An adhesive layer is placed on top of the protective layer, with a sealing substrate in between. The display device according to claim 8, wherein the outer bank is positioned at a certain distance from the edges of the adhesive layer and the sealing substrate.

10. The cathode extends into the trench so as to cover a portion of the upper surface of the exposed first low-potential power supply wiring, The cathode is in contact with the upper surface of the exposed first low-potential power supply wiring. The display device according to claim 8, wherein the cathode covers the bank and the organic layer inside the trench.

11. In the non-display area excluding the second side, the protective layer is arranged to surround the cathode. The display device according to claim 2, wherein the protective layer covers a portion of the upper surface of the cathode in the non-display area on the second side.

12. The trench is A first trench is arranged across the non-display area excluding the second side, and The display device according to claim 5, further comprising a second trench located inside the first trench and extending across the non-display areas on the first to fourth sides.

13. The first trench is formed by removing a portion of the insulating layer and the planarizing layer in the non-display area. The display device according to claim 12, wherein the second trench is formed by removing a portion of the planarization layer in the non-display area.

14. Multiple of the aforementioned second trenches are arranged, The display device according to claim 12, further comprising a plurality of dams arranged between the plurality of second trenches and composed of the flattening layer.

15. The first low-potential power supply wiring is further arranged inside the first trench so as to cover the inside of the first trench, The display device according to claim 14, wherein the first low-potential power supply wiring is arranged to cover the upper surface of the insulating layer and a portion of the upper surface and side of the planarization layer exposed by the first trench.

16. The second low-potential power supply wiring is further arranged inside the second trench so as to cover the inside of the second trench, The display device according to claim 15, wherein the second low-potential power supply wiring is arranged to cover the upper surface of the insulating layer and a portion of the upper surface and side of the dam that are exposed by the second trench.

17. The gate-in-panel circuit section further includes an outer bank and an inner bank, which are separated from the bank and arranged in an island configuration outside the gate-in-panel circuit section. In the non-display area excluding the second side, the outer bank covers the outer portion of the first low-potential power supply wiring. The display device according to claim 16, wherein a portion of the upper surface of the first low-potential power supply wiring is exposed without being covered by the outer bank.

18. An adhesive layer is placed on top of the protective layer, with a sealing substrate in between. The display device according to claim 17, wherein the outer bank is positioned at a certain distance from the edges of the adhesive layer and the sealing substrate.

19. The aforementioned inner bank and the second low-potential power supply wiring are composed of multiple components. One inner bank covers the inner portion of the first low-potential power supply wiring and the side portion of the second low-potential power supply wiring. The display device according to claim 17, wherein another inner bank covers the side of one second low-potential power supply wiring and the side of another second low-potential power supply wiring.

20. In the non-display area excluding the second side, the cathode extends into the interior of the first trench so as to cover the inner bank and the second low-potential power supply wiring. The display device according to claim 17, wherein in the non-display region on the second side, the cathode extends into the non-display region so as to cover the inner bank and the second trench.

21. In the non-display area excluding the second side, the protective layer is arranged to surround the cathode. The display device according to claim 17, wherein in the non-display area on the second side, the protective layer covers a portion of the upper surface of the cathode inside the second trench.

22. The cathode extends into the non-display area so as to cover the entire trench, The display device according to claim 1, wherein the protective layer extends to the non-display area so as to surround the cathode.

23. The display device according to claim 1, wherein the gate-in-panel circuit section is arranged on both the first side and the second side facing the first side.

24. A substrate including a display area and a non-display area outside the display area, At least one trench provided in the non-display area, First low-potential power supply wiring arranged in the trench, A cathode located in the display area, extending to the trench and connected to the first low-potential power supply wiring, The gate-in-panel circuit section, which is located on the first side of the non-display area and inside the trench, and A display device including grounding wiring located outside the trench on the first and third sides of the non-display area.

25. The trench is A first trench provided above the non-display area, and The display device according to claim 24, comprising one or more second trenches provided on the first, second, third, and fourth sides of the non-display area.

26. The display device according to claim 24, further comprising a first light-shielding pattern disposed between the grounding wiring and the trench.

27. The display device according to claim 24, further comprising a second light-shielding pattern and high-potential power supply wiring disposed inside the trench.

28. The display device according to claim 25, comprising one or more second low-potential power supply wirings arranged in one or more second trenches and connected to the cathode.

29. The display device according to claim 25, wherein the width of the first trench is greater than the width of one or more second trenches.

30. The display device according to claim 25, comprising a plurality of dams positioned between one or more second trenches.

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