Photodiode and method for fabricating the same

Abstract

The present invention provides a photodiode and a method for fabricating the same that minimizes photon absorption in the target wavelength range and simplifies the device fabrication process. [Solution] A photodiode is described having a p-doped semiconductor layer 226, an n-doped semiconductor layer 222, and an intrinsic layer 224 forming a PIN junction of the photodiode 220. The photodiode further comprises a multifunctional layer 228 of a material such as InGaAsP or InGaAsAl formed on the p-doped semiconductor layer, the multifunctional layer being configured to (1) act as a contact layer between the p-doped semiconductor layer and one or more metal contacts formed on the p-doped semiconductor layer, and (2) minimize photon absorption in a target wavelength range. In some embodiments of the photodiode in a p-down configuration, the multifunctional layer acts as an etch-stop layer that does not need to be removed after etching, simplifying the device fabrication process.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 740,458, filed on 31 December 2024, the entirety of which is incorporated herein by reference.

[0002] This application relates to an optoelectronic semiconductor device, and more specifically, to a photodiode that converts optical signals into electrical signals and a method for manufacturing the same. [Background technology]

[0003] In wafer fabrication, heterogeneous integration is used to combine components formed on different material platforms and place them on a single photonic chip, thereby minimizing losses resulting from off-chip coupling. This semiconductor fabrication method is particularly interesting in the manufacture of photodiodes used in quantum photonic applications, as the photodiodes provide on-chip photonic detection capabilities.

[0004] To perform heterogeneous integration, a technique known as bonding may be used. During bonding, an unpatterned wafer / die is combined with a patterned photonic chip by forming chemical bonds at the material interface, enabling the simultaneous fabrication of multiple devices. This requires the removal of the original substrate of the wafer material, which is typically achieved through a chemical wet etching process. To stop etching and prevent damage to the wafer's epitaxial material, a highly selective etch stop layer is usually used for the substrate material. For example, indium gallium arsenide (InGaAs) is a typical etch stop material for InP substrate removal. However, because etch stop layers such as InGaAs can absorb light of the target wavelength, they cannot efficiently collect carriers generated within the etch stop layer, thereby introducing additional losses.

[0005] Therefore, it is desirable to provide an improved photodiode that addresses at least partially one or more of the above concerns. [Overview of the Initiative]

[0006] In one embodiment, a photodiode is provided comprising a first layer of a first type semiconductor, a second layer of a second type semiconductor, a third intrinsic layer between the first and second layers, and a fourth multifunctional layer formed on the first layer, wherein the fourth multifunctional layer is configured to (1) function as a contact layer between the first layer and one or more metal contacts, and (2) minimize photon absorption in a target wavelength range.

[0007] In another embodiment, a method is provided comprising the steps of: fabricating a photonic waveguide platform; growing an epitaxial structure on a substrate, wherein the epitaxial structure has a first semiconductor layer, a second semiconductor layer, a third intrinsic layer between the first and second semiconductor layers, and a fourth multifunctional layer directly beneath the first semiconductor layer, the fourth multifunctional layer being configured to minimize photon absorption in a target wavelength range; integrating the epitaxial structure onto the surface of the photonic waveguide platform in an inverted state such that the substrate forms the uppermost surface; removing the substrate by an etching process; forming a mesa structure from the epitaxial structure so that a portion of the multifunctional layer remains as a contact layer; and forming one or more contact elements on the mesa structure, which includes at least one contact element on the multifunctional layer, such that the multifunctional layer functions as a contact layer.

[0008] In any of the above embodiments, the material of the fourth multifunctional layer may be either InGaAsP or InGaAsAl.

[0009] In any of the above embodiments, the composition of phosphorus (P) or aluminum (Al) in the fourth multifunctional layer material may be configured to achieve a target wavelength range.

[0010] In any of the above embodiments, the first and second layers may be arranged in an n-down structure, and the fourth multifunctional layer also functions as an etch stop layer during the wet etching process.

[0011] In any of the above embodiments, the target wavelength range may include 1260 nm to 1625 nm.

[0012] In any of the above embodiments, the fourth multifunctional layer can maintain lattice alignment with the first layer.

[0013] In any of the above aspects, the first type of semiconductor may be a p-type doped semiconductor material, and the second type of semiconductor is an n-type doped semiconductor material.

[0014] In any of the above aspects, the photodiode may be coupled to a photonic waveguide platform, and the photonic waveguide platform includes a waveguide formed within the photonic waveguide platform configured to direct a photonic signal towards the photodiode.

[0015] In any of the above aspects, the photodiode can be a III-V semiconductor mesa structure bonded on the topmost surface of the photonic waveguide platform.

[0016] In any of the above aspects, the first layer and the second layer can be arranged in a p-down structure.

[0017] In any of the above aspects, the growing step can include forming a fourth multifunctional layer from either InGaAsP or InGaAsAl.

[0018] In any of the above aspects, the growing step can include forming a fourth multifunctional layer directly above the substrate, the etching process is a wet etching process, and the fourth multifunctional layer functions as an etch stop.

[0019] Any of the above aspects can further include the step of forming a passivation layer covering the mesa structure before forming one or more contact elements.

[0020] In any of the above aspects, the growing step can further include forming the first semiconductor layer from the first type of semiconductor and forming the second semiconductor layer from the second type of semiconductor.

[0021] In any of the above embodiments, the first type semiconductor may be a p-type semiconductor, and the second semiconductor may be an n-type semiconductor.

[0022] Any of the above embodiments may further include the step of forming a waveguide within a photonic waveguide platform, the waveguide being configured to direct a photonic signal toward an epitaxial structure.

[0023] Any of the above embodiments may further include the step of configuring the chemical composition of the multifunctional layer to achieve a target wavelength range.

[0024] In any of the above embodiments, the target wavelength range may include 1260 nm to 1625 nm.

[0025] In any of the above embodiments, the growth step may include forming a second semiconductor layer directly on the substrate.

[0026] Here, as an example, we refer to the attached diagrams illustrating embodiments of this application. [Brief explanation of the drawing]

[0027] [Figure 1A] This figure shows a possible epitaxial structure p-down of a photodiode resulting from a possible epitaxy layer arrangement for a PIN junction based on the position of the p-type doped semiconductor layer relative to the waveguide below. [Figure 1B] This figure shows a possible epitaxial structure n-down of a photodiode resulting from a possible epitaxy layer arrangement of a PIN junction based on the position of the n-type doped semiconductor layer relative to the waveguide below.

[0028] [Figure 2] This is a side view of the epitaxial structure of an integrated photonic device with a p-down configuration according to some embodiments of the present disclosure.

[0029] [Figure 3]This is a side view of the epitaxial structure of an n-down configuration integrated photonic device according to some embodiments of the present disclosure.

[0030] [Figure 4] This is a flowchart of a method for manufacturing an integrated photonic device as shown in Figures 2 and 3, according to one aspect of the present disclosure.

[0031] [Figure 5A] Figure 4 shows high-level conceptual diagrams of the photodiode device according to this disclosure at various stages of the method shown. [Figure 5B] Figure 4 shows high-level conceptual diagrams of the photodiode device according to this disclosure at various stages of the method shown. [Figure 5C] Figure 4 shows high-level conceptual diagrams of the photodiode device according to this disclosure at various stages of the method shown. [Figure 5D] Figure 4 shows high-level conceptual diagrams of the photodiode device according to this disclosure at various stages of the method shown. [Figure 5E] Figure 4 shows high-level conceptual diagrams of the photodiode device according to this disclosure at various stages of the method shown. [Modes for carrying out the invention]

[0032] Similar reference numerals are used throughout the figures to indicate similar elements and features. While aspects of the invention will be described in conjunction with the illustrated embodiments, it will be understood that the invention is not intended to be limited to such embodiments.

[0033] A photodiode is essentially a PIN structure comprising p-type doped and n-type doped semiconductors separated in the intrinsic region. Upon absorbing a photon with sufficient energy, electron-hole pairs are created, and thus the positively charged holes and negatively charged electrons are directed toward the anode and cathode of the device by the built-in electric field, thereby generating a photocurrent. Therefore, photodiodes are well-suited to providing photodetection capability in semiconductor devices.

[0034] Figures 1A and 1B show two possible epitaxial structures of a photodiode, p-down and n-down, resulting from two possible epitaxy layer arrangements of a PIN junction, based on the positions of the p-type doped and n-type doped semiconductor layers relative to the underlying waveguide, respectively. The term “semiconductor layer” generally refers to the horizontal epitaxial portion within the photodiode that responds at least partially to light / photons of a particular wavelength and thereby contributes to one or more of the photonic properties of the photodiode. As shown in Figure 1A, in the p-down structure, the p-type doped semiconductor layer is further down in the epitaxial layer stack and therefore close to the waveguide WG formed in the photonic chip / wafer on the substrate. As shown in Figure 1B, in the n-down structure, the n-type doped semiconductor layer is further down in the epitaxial layer stack and therefore close to the waveguide WG.

[0035] III-V semiconductors refer to a group of preferred semiconductor materials often used in the manufacture of semiconductor photodiodes. III-V compounds are compounds created by combining elements from Group III (e.g., B, Al, Ga, In) and Group V (e.g., N, P, As, Sb) of the periodic table. Silicon, the most prominent semiconductor material, has an "indirect" band gap, which means that excited electrons must travel through multiple paths to reach the lowest energy state in the conduction band. In contrast, III-V semiconductors such as GaN, GaAs, and InP have a "direct" band gap, which gives these materials the ability to absorb photons more efficiently. Furthermore, the band gap can be designed to achieve a desired value by configuring the chemical composition of the III-V semiconductor material. This makes III-V semiconductors well-suited for optoelectronic applications such as photodiodes.

[0036] In some embodiments, the photodiode described herein is a III-V semiconductor photodiode comprising multiple semiconductor layers including a multifunctional layer, the multifunctional layer not only improves the contact performance of the p-mesa contact structure formed thereon, but the material composition of the multifunctional layer may also be configured to achieve a desired bandgap in order to minimize the photon absorption of the layer at a particular wavelength (therefore reducing optical loss).

[0037] Figure 2 shows a side view of the epitaxial structure of an integrated photonic device 200 in a p-down configuration according to several embodiments of the present disclosure. Dimensions of some features may be exaggerated for illustrative purposes. The epitaxial structure in Figure 2 includes a photodiode 220 supported on a photonic waveguide platform 210. In some embodiments, the photodiode 220 is formed from a molecular die of a group III-V material and heterogeneously integrated on the photonic waveguide platform 210, as described in more detail below. Such techniques enable the use of silicon wafer processing techniques, as well as the high performance and configurability of group III-V materials in photonic applications.

[0038] The photonic waveguide platform 210 may be a multilayer silicon wafer including a substrate 212 supporting a cladding layer 214 on which waveguides (WG) 216 are formed. The substrate 212 may be fabricated from any suitable material, including, for example, silicon, diamond, gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP). The thickness of the substrate 212 may depend on the fabrication technique and / or application, typically ranging from 100 μm to 1000 μm. The photonic waveguide platform 210 may be configured to perform one or more photonic application functionalities.

[0039] The cladding layer 214 is supported on the substrate 212. One example of the cladding layer 214 and waveguide 216 is shown in Figure 2, but it is understood that multiple examples of each may exist. At least one optical waveguide 216 is formed within the cladding layer 214. The cladding layer 214 may consist of any suitable cladding material to provide a refractive index in contrast to the material of the waveguide 216, such that any transmission mode is partially, substantially, or completely restricted by internal total internal reflection. As a non-limiting example, in the case of a cladding layer 214 made of SiO2, the optical waveguide 216 may be fabricated from SiN or lithium niobate (LN) to achieve internal total internal reflection in the selected cladding material. In some embodiments, the photonic waveguide platform 210 is a patterned wafer on which one or more integrated circuit elements (not shown), such as modulators, resonators, directional couplers, and fiber-to-chip couplers, can be fabricated by any suitable means, such as etching (mechanically or chemically), engraving, bonding, and / or lithography. In a non-limiting example, the photonic waveguide platform 210 may be a thin-film lithium niobate (TFLN) chip. The optical modes may be led from the waveguide 216 and evanescently coupled to the photodiode 220 by any suitable means, such as an adiabatic tapered waveguide as described in U.S. Provisional Patent Application No. 63 / 613,131, the disclosure of which is incorporated herein by reference in whole. Other known methods for directing the optical signal toward the photodiode, such as lattice couplers, can also be used.

[0040] In a preferred embodiment, the bare die on which the photodiode 220 will be formed is fabricated independently of the photonic waveguide platform 210 and can be integrated onto the photonic waveguide platform 210 by heterogeneous integration, as will be described in more detail herein. Figure 2 shows the photodiode 220 after integration onto the photonic waveguide platform 210.

[0041] The photodiode 220 includes a PIN junction formed by an n-type doped semiconductor layer 222, an intrinsic layer 224, and a p-type doped semiconductor layer 226. One or more optional layers, such as a shielding layer or a light-doped layer (not shown) for preventing leakage current, can be present in the photodiode 220 without departing from the scope of the present disclosure. The embodiment shown in FIG. 2 is a vertical stacking configuration called "p-down" in which the p-type doped semiconductor layer 226 is closest to the waveguide 216. In some embodiments, the n-type doped semiconductor layer 222 is made of indium phosphide (InP) doped with an n-type dopant such as silicon, phosphorus, arsenic, antimony, bismuth, and group V elements including lithium having a doping concentration of about 6×10 19 cm -3 The thickness of layer 222 can be 50 to 1000 nm. In some embodiments, the p-type doped semiconductor layer 226 is made of InP doped with a suitable p-type dopant such as zinc, beryllium, boron, aluminum, gallium, and group III elements including indium having a doping concentration of about 5×10 14 cm -3 The thickness of layer 226 can be 50 to 1000 nm. The intrinsic layer 224 can be made of undoped InP having a layer thickness of 50 to 1000 nm. In some embodiments, the intrinsic layer 224 undergoes unintentional doping by dopant diffusion from layers 222 and 226, and as a result, the doping concentration can be 1×10 13 ~1×10 17 cm -3

[0042] A multifunctional layer 228 is disposed on the uppermost surface of the p-type doped semiconductor layer 226 with a layer thickness of 10 to 500 nm. For proper lattice matching, the multifunctional layer 228 contains the same p-type dopant as layer 226 at 1×10 17 ~6×10 19 cm -3 ​It can be doped at the concentration of. In some embodiments, the material of the multifunctional layer 228 is selected to achieve lattice matching with the semiconductor layer on which the multifunctional layer is formed. As a non-limiting example, in a preferred embodiment where the p-type doped semiconductor layer 226 is made of InP, the multifunctional layer 228 is made of indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y (0 < x, y < 1), or having the general formula of InGaAsP for short), InGaAsAl, or InGaAs (with appropriate elements added). This matching of the geometric lattice parameters enables the formation of bandgap variations without introducing crystal defects that would degrade the optical properties of the device. The amount of lattice mismatch can be determined by comparing the lattice constant of either the p-type doped semiconductor layer 226 with the lattice constant of the multifunctional layer 228. When the lattice constants of two adjacent layers are approximately the same, the lattice is said to be matched.

[0043] Furthermore, the bandgap of the InGaAsP multifunctional layer can be configured by manipulating the chemical composition (x, y) of InGaAsP to achieve the desired bandgap. The bandgap energy of InGaAsP can be correlated with the composition (1 - y) of the phosphide contained in InGaAsP. As a non-limiting example, it may be desirable to minimize the absorption of photons having wavelengths within the C band (i.e., 1530 nm to 1565 nm). In some examples, it may be desirable to minimize the absorption of photons having a wavelength of about 1550 nm. In further exemplary embodiments, the target wavelength can be in the range of 1260 nm to 1625 nm. For this purpose, the composition of In x Ga 1-x As y P 1-y can be changed, for example, by having a composition of P (1 - y) within the range of 0.26 to 0.66.

[0044] In some embodiments, the multifunctional layer 228 can also function to improve the contact resistance of the p-mesa contact 230B. At high free carrier concentrations, n-type doped semiconductors typically exhibit higher conductivity than their p-type counterparts. On the other hand, p-type doped semiconductors have an excess of positively charged holes, resulting in lower conductivity compared to n-type semiconductors. For example, the n-type dopants phosphorus, arsenic, and antimony exhibit lower conductivity at 1500 cm⁻¹, respectively. 2 / Vs, 1200cm 2 / Vs, and 500cm 2 They exhibit charge carrier mobility of / Vs. In contrast, the p-type dopants boron, aluminum, and gallium exhibit 450 cm³, respectively. 2 / Vs, 200cm 2 / Vs, and 250cm 2 It exhibits a charge carrier mobility of / Vs. The multi-functional layer 228 of InGaAsP has a capacity of approximately 6500 cm². 2 With a charge carrier mobility of / Vs, InP is approximately 5400 cm⁻¹. 2 It has a charge carrier mobility of / Vs. Therefore, the electrical conductivity of the device can be improved by forming the metal contact 230B on the multifunctional layer 228 instead of the p-type doped semiconductor layer 226.

[0045] Figure 3 shows a side view of the epitaxial structure of an n-down configuration integrated photonic device 300 according to some embodiments of the present disclosure. Dimensions of some features may be exaggerated for illustrative purposes. The epitaxial structure of Figure 3 includes a photodiode 320 having an n-down epitaxial structure supported on a photonic waveguide platform 210. In some embodiments, the photodiode 320 is formed from a molecular die of a group III-V material and heterogeneously integrated on the photonic waveguide platform 210, as will be described in more detail below.

[0046] In a preferred embodiment, the bare die on which the photodiode 320 will be formed is fabricated independently of the photonic waveguide platform 210 and can be integrated onto the photonic waveguide platform 210 by heterogeneous integration, as will be described in more detail herein. Figure 3 shows the photodiode 320 after integration onto the photonic waveguide platform 210.

[0047] The photodiode 320 includes a PIN junction formed by an n-type doped semiconductor layer 322, an intrinsic layer 324, and a p-type doped semiconductor layer 326. One or more optional layers, such as a shielding layer or a low-density doped layer (not shown) for preventing leakage current, can be present in the photodiode 320 without departing from the scope of this disclosure. The embodiment shown in Figure 3 is a vertical stacking configuration called "n-down," in which the n-type doped semiconductor layer 322 is closest to the waveguide 216. In some embodiments, the n-type doped semiconductor layer 322 consists of indium phosphide (InP) doped with n-type dopants such as group V elements including phosphorus, arsenic, antimony, bismuth, and lithium. In some embodiments, the p-type doped semiconductor layer 326 consists of InP doped with appropriate p-type dopants such as group III elements including boron, aluminum, gallium, and indium. The intrinsic layer 324 may consist of undoped InP.

[0048] The integrated multifunctional layer 328 described herein lies directly above the top surface of the p-type doped semiconductor layer 326. In some embodiments, the material of the multifunctional layer 328 is selected so as to achieve lattice matching between the multifunctional layer and the semiconductor layer formed on top of it.

[0049] As described with respect to the embodiment shown in Figure 2, the bandgap of the multifunctional layer can be configured to target a specific frequency range by manipulating one or more chemical compositions of the multifunctional layer material. For example, the bandgap energy of multifunctional layer 328 made of InGaAsP may correlate with the composition (1-y) of phosphides contained in the multifunctional layer. As a non-limiting example, it may be desirable to minimize the absorption of photons having wavelengths in the C band (i.e., 1530 nm to 1565 nm). In some examples, it may be desirable to minimize the absorption of photons having a wavelength of about 1550 nm. For this purpose, In x Ga 1-x As y P 1-y The composition can be varied, for example, by having a P composition (1-y) in the range of 0.26 to 0.66.

[0050] In some embodiments, the multifunctional layer 328 can also function to improve the contact resistance of the p-mesa contact 330A, thereby improving the electrical conductivity of the integrated photonic device 300.

[0051] In some embodiments, the multifunctional layer 328 can also act as an etch stop layer during substrate removal. In an n-down epitaxial configuration, the multifunctional layer 328 after heterogeneous integration is located directly beneath the substrate layer of the die structure on which the photodiode 320 grows, and directly above the p-type semiconductor layer 326. The substrate layer can be removed by a wet etching process in which the integrated device is immersed in an aqueous etchant, such as a hydrochloric acid (HCl)-based solution, which is highly selective for the substrate material. HCl-based etchants have low selectivity for, for example, InGaAsP, thereby allowing the InGaAsP multifunctional layer 328 to substantially slow down or stop the etching process.

[0052] Figure 4 shows a flowchart 400 of a method for manufacturing an integrated photonic device such as device 200 or device 300 described herein, according to one embodiment of the present disclosure. Method 400 comprises fabrication process operations / steps 402-414, one or more of which are optional, as will be described in more detail below. Figure 4 is described in relation to Figures 5A-5E, which show high-level conceptual diagrams of the photodiode device according to the present disclosure at various stages of Method 400.

[0053] Step 402 includes fabricating a photonic waveguide platform such as a semiconductor chip or wafer 210. In some embodiments, wafer fabrication may include layer deposition, in which one or more semiconductor layers of one or more semiconductor materials are deposited on a substrate material / layer. The epitaxial semiconductor layers can be deposited by suitable means such as chemical vapor deposition, physical vapor deposition, or other deposition methods. In some embodiments, the semiconductor wafer may be a TFLN wafer, which exhibits favorable operating characteristics for electro-optical applications.

[0054] One or more optical waveguides configured to facilitate optical signal propagation may be formed within the semiconductor cladding layer of the photonic waveguide platform. The waveguides may be configured to direct the optical waveguides toward photodiodes such as photodiodes 220 and 320 by any suitable means, such as adiabatic tapering or grated coupling.

[0055] In some embodiments, a semiconductor wafer may be patterned with a desired circuit pattern applied to the wafer by any suitable means, such as lithography, including projection photolithography. In a non-limiting example, the wafer may be coated with a photosensitive polymer film known as a photoresist. The circuit design pattern is transferred onto an opaque mask. Using photolithography, the mask pattern is projected onto the photoresist, where the exposed areas of the photoresist are chemically altered and made susceptible to etching. Etching can be performed by dry etching and / or wet etching. Dry etching methods may include ion beam etching (IBE), reactive ion etching (RIE), and inductively coupled plasma (ICP) etching, and can be used for anisotropic etching (i.e., etching in a specific direction). Wet etching methods may include any etching process in which the patterned wafer is sprayed with or immersed in a chemical solution, i.e., an etchant, to selectively remove each portion of the semiconductor layer by chemical reaction with the material of one or more exposed portions of the semiconductor layer. Wet etching can be used to perform isotropic etching (i.e., etching in all directions). Additional optional steps of surface cleaning and surface treatment may include, but are not limited to, passivation, planarization, and metallization. One or more of the above semiconductor fabrication methods may be repeated once or more times.

[0056] In step 404, an epitaxial structure is grown to be fabricated within the photodiodes 220, 320. In some embodiments, the epitaxial structure can be formed separately from the semiconductor wafer fabrication step 402. Therefore, in some embodiments, step 404 can be performed before, after, or concurrently with step 402. The epitaxial structure includes a plurality of semiconductor layers grown epitaxily on the substrate or deposited by appropriate means such as chemical vapor deposition or physical vapor deposition. The semiconductor layers include multifunctional layers 228, 328, which can be arranged in either a p-down configuration or an n-down configuration, with the multifunctional layer 328 grown directly beneath the p-type semiconductor layer. The semiconductor layers of the epitaxial structure correspond to the layers of the photodiodes without metal contacts 230, 330, but are grown in the reverse order of the photodiodes. Figure 5A shows the patterned photonic chip / wafer at the end of steps 402 and 404 (left) and the independently fabricated epitaxial structure (right).

[0057] In some embodiments, each layer of the epitaxial structure can be grown in an n-down configuration, as shown in Figures 5A to 5E. In an n-down configuration epitaxial structure, the n-type doped semiconductor layer 322 is grown as the top layer, and the multifunctional layer 328 is grown directly on top of the substrate. The material of the multifunctional layer 328 is a III-V group material selected with high selectivity to favor the substrate material and one or more semiconductor layers on it during etching. As a non-limiting example, in the case of a substrate material and a semiconductor layer of InP, the multifunctional layer 328 may be formed from InGaAsP.

[0058] In other embodiments, the epitaxial structure may be grown in a p-down configuration, where the p-type doped semiconductor layer 222 is grown as the upper epitaxial layer, and the multifunctional layer 228 is grown between the p-type semiconductor layer 222 and the intrinsic layer 224.

[0059] In step 406, the epitaxial structure from step 404 is integrated onto the photonic waveguide platform from step 402, as shown in Figure 5B. Integration can be performed by heterogeneous integration, a technique commonly used to connect multiple PICs or photonic chips from different material technologies into a single package. Heterogeneous integration is typically performed at the packaging stage after the fabrication of individual components. This integration process enables the simultaneous fabrication of components and further allows for modular testing and characterization of each component before the integration process. In some embodiments, the epitaxial structure is integrated onto the photonic waveguide platform by bonding the structure in an inverted form. For example, as shown in Figure 5B, the epitaxial structure is bonded onto the top surface of the photonic waveguide platform with the substrate of the structure as the top layer. Integration can be performed by any suitable method, such as direct bonding or adhesive bonding. In embodiments where adhesive bonding is applied, the method may include the deposition of an intermediate layer coating onto the photonic waveguide platform 210. For example, a layer of benzocyclobutene (BCB) polymer or SU-8 may be spin-coated onto the top surface of the substrate portion to act as a bonding agent. Optionally, following spin-coating, the bonding agent intermediate layer may be soft-baked at temperatures up to approximately 100°C to remove excess solvent. The epitaxial structure can then be brought into physical contact with the top surface of the photonic waveguide platform. The entire integrated device may be fully cured by a hard-baking process at high baking temperatures of 110–220°C after or during bonding. In direct bonding, no bonding agent layer is required, and the epitaxial structure and substrate portion are bonded at temperatures of approximately 120–300°C.

[0060] In step 408, the substrate layer on top of the heterogeneous integrated device, or the substrate layer on which the epitaxial structure is formed, is removed by an etching process. In some embodiments, the substrate layer has a thickness of >100 μm. The etching of the substrate layer can be carried out by one or more of the following processes: dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable processes. For example, the etching of the integrated photonic device 300 can be carried out by wet etching using a hydrochloric acid (HCl) etchant. A substrate layer, such as the InP substrate layer shown in Figure 5A on which the photodiode 320 is formed, can be etched vertically down to the multifunctional layer 328 so that the multifunctional layer is the uppermost layer, as shown in Figure 5C. Since the wet etchant acts only on the substrate material, e.g., InP, the multifunctional layer 328 can act as an etch stop layer, precisely stopping the etching process and ensuring the structural integrity of the semiconductor layer below. Compared to a typical etch stop layer made from a material such as InGaAs, a multifunctional layer made from InGaAsP has several advantages. In photonic applications, InGaAs can be used to convert light with a wavelength of around 1550 nm into 6000 cm⁻¹. -1 ~7000cm -1 It tends to absorb with an absorption coefficient of approximately 600 cm³, and the resulting carriers generated within this layer are difficult to collect, leading to increased signal loss. In clear contrast, InGaAsP absorbs approximately 600 cm³. -1 It has a much higher band gap compared to InGaAs for 1550nm wavelength light with an absorption coefficient, thereby minimizing photonic absorption in the desired wavelength range.

[0061] Due to the poor optical efficiency of InGaAs, conventional InGaAs etch-stop layers need to be removed during substrate removal (e.g., by dry etching, wet etching, or a combination of dry and wet etching), which further complicates the fabrication process. In contrast, multi-functional layers made of InGaAsP can be retained after substrate removal because this layer does not negatively affect signal loss.

[0062] As an example, in embodiments where a wet etching technique is applied, the III-V epitaxial InP substrate can be removed by wet etching with a hydrochloric acid (HCl) etchant (e.g., H3PO4:HCl=3:1) with high selectivity favorable to the InP substrate layer. As shown in Figure 5C, after the substrate is removed, the multifunctional layer 328, which is the top semiconductor layer here, and one or more semiconductor layers beneath it remain intact. The InGaAsP multifunctional layer is preserved and functions as a contact layer for the photodiode device.

[0063] As described above, in some embodiments, substrate removal can be performed by dry etching techniques such as plasma treatment using an InGaAs etch stop layer. Dry etching may be preferred in some applications because it provides high selectivity and control over the machined shape. However, dry etching techniques may require longer processing times and more specialized, prohibitively expensive equipment.

[0064] In step 410, the epitaxial portion of the photodiode device is further etched to form one or more mesa structures by mesa etching. Mesa etching can be performed by any suitable method of wet chemical etching, gas plasma etching, or a combination of the two. The mesa etching process may include one or more iterations of photoresist mask deposition, etchant application, and mask removal until a desired mesa profile, such as the photodiode shown in Figure 5D, is achieved. In some embodiments, the mesa structures have a step height of less than 10 μm. For example, following lithographic patterning of the epitaxial layer, the device may be immersed in a chemical etchant such as an HCl etchant. The duration of the etching process can be adjusted accordingly based on the known etching rate of the etchant.

[0065] Optionally, in step 412, a passivation layer can be formed covering a portion of the mesa structure, as shown in Figure 5E. Passivation of a semiconductor device refers to the step of inactivating the semiconductor surface without altering the device properties when the semiconductor surface interacts with air or other materials. The passivation layer can be formed from a dielectric material such as undoped silicate glass (USG), silicon nitride, silicon oxide, or other low refractive index materials by any suitable method, such as chemical vapor deposition or physical vapor deposition. One or more openings penetrating the passivation layer can be patterned to expose one or more contact pad areas on the multifunctional layer. Advantageously, InGaAsP can further function to improve the electrical conductivity of any metal contacts deposited thereon, such as contact 330A in Figure 3. For example, InGaAsP can be approximately 6500 cm². 2 It can have a charge carrier mobility of / Vs, and InP is approximately 5400 cm⁻¹. 2 It can have a charge carrier mobility of / Vs.

[0066] In step 414, one or more contact elements are formed on a mesa structure that includes at least one contact element on a multifunctional layer. For example, as shown in Figure 3, contact 330A is formed on the multifunctional layer 328 as a p-type terminal of the integrated photonic device 300, and contact 330B is formed on the n-type doped semiconductor layer as an n-type terminal of the integrated photonic device 300. In embodiments where a passivation layer is present, one or more contact elements are formed on one or more openings patterned within the passivation layer such that the contacts form a conductive connection with the layer below. The contact elements can be made of an Au structure or a Cu structure, or another conductive material such as tin / lead (SnPb) solder, copper / zinc (CuZn) solder, or copper / silver (CuAg) solder, each optionally containing a flux material. The solder material can be deposited using ball drop, stencil printing, and / or plating processes.

[0067] This disclosure may describe methods and processes having steps in a specific order, but one or more steps of these methods and processes may be omitted or modified as necessary. One or more steps may be performed in an order other than the order in which they are described, if necessary.

[0068] While this disclosure may describe methods at least in part, those skilled in the art will understand that this disclosure also covers a variety of components for performing at least some of the aspects and features of the methods described herein, whether hardware components, software, or any combination thereof. Accordingly, the technical solutions of this disclosure can be embodied in the form of software products. A suitable software product may be stored on a pre-recorded storage device or other similar non-volatile or non-temporary computer-readable medium, including, for example, a DVD, CD-ROM, USB flash disk, removable hard disk, or other storage medium. The software product includes instructions tangibly stored in the software product that enable a processing device (e.g., a personal computer, server, or network device) to perform an example of the methods disclosed herein.

[0069] This disclosure may be embodied in other specific forms without departing from the subject matter of the claims. The embodiments described should be considered in all respects to be illustrative and not limiting. Selected features from one or more of the embodiments described above may be combined to create alternative embodiments not expressly described, and features suitable for such combinations are understood within the scope of this disclosure.

[0070] All values ​​and sub-ranges within the disclosed scope are also disclosed. Furthermore, while the systems, devices, and processes disclosed and illustrated herein may include a certain number of elements / components, the systems, devices, and assemblies can be modified to include additional or fewer such elements / components. For example, any of the disclosed elements / components may be referred to singly, but the embodiments disclosed herein can be modified to include multiple such elements / components. The subject matter described herein is intended to encompass and include all appropriate modifications of the art.

Claims

1. The first layer of the first type semiconductor, The second layer of the second type semiconductor, A third intrinsic layer between the first layer and the second layer, A fourth multi-functional layer formed on the first layer and A photodiode equipped with, The fourth multifunctional layer is configured to (1) function as a contact layer between the first layer and one or more metal contacts, and (2) minimize photon absorption in the target wavelength range. Photodiode.

2. The photodiode according to claim 1, wherein the material of the fourth multifunctional layer is one of InGaAsP and InGaAsAl.

3. The photodiode according to claim 2, wherein the composition of phosphorus (P) or aluminum (Al) in the material of the fourth multifunctional layer is configured to achieve the target wavelength range.

4. The photodiode according to claim 1, wherein the first layer and the second layer are arranged in an n-down structure, and the fourth multifunctional layer also functions as an etch stop layer during a wet etching process.

5. The photodiode according to claim 1, wherein the fourth multifunctional layer maintains lattice matching with the first layer.

6. The photodiode according to claim 1, wherein the first type of semiconductor is a p-type doped semiconductor material, and the second type of semiconductor is an n-type doped semiconductor material.

7. The photodiode according to claim 1, wherein the photodiode is coupled to a photonic waveguide platform, and the photonic waveguide platform includes a waveguide formed within the photonic waveguide platform, configured to direct a photonic signal toward the photodiode.

8. The photodiode according to claim 7, wherein the photodiode is a III-V semiconductor mesa structure bonded to the uppermost surface of the photonic waveguide platform.

9. Steps for fabricating a photonic waveguide platform, A step of growing an epitaxial structure on a substrate, wherein the epitaxial structure comprises a first semiconductor layer, a second semiconductor layer, a third intrinsic layer between the first and second semiconductor layers, and a fourth multifunctional layer directly beneath the first semiconductor layer, wherein the fourth multifunctional layer is configured to minimize photon absorption in a target wavelength range. The steps include: integrating the epitaxial structure onto the surface of the photonic waveguide platform in an inverted state such that the substrate forms the uppermost surface; The steps include removing the aforementioned substrate by an etching process, The steps include forming a mesa structure from the epitaxial structure, with a portion of the multifunctional layer remaining as a contact layer, A step of forming one or more contact elements on the mesa structure which includes at least one contact element on the multifunctional layer, wherein the multifunctional layer functions as a contact layer. Methods that include...

10. The method according to claim 9, wherein the growth step includes forming the fourth multifunctional layer from one of InGaAsP and InGaAsAl.

11. The method according to claim 9, wherein the growing step includes forming the fourth multifunctional layer directly on the substrate, the etching process is a wet etching process, and the fourth multifunctional layer functions as an etch stop.

12. The aforementioned growth step is The first semiconductor layer is formed of a first type of semiconductor, and The second semiconductor layer is formed of a second type of semiconductor. The method according to claim 9, further comprising:

13. The method according to claim 12, wherein the first type of semiconductor is a p-type semiconductor and the second type of semiconductor is an n-type semiconductor.

14. The method according to claim 9, further comprising the step of forming a waveguide within the photonic waveguide platform, wherein the waveguide is configured to direct a photonic signal toward the epitaxial structure.

15. The method according to claim 9, further comprising the step of configuring the chemical composition of the multifunctional layer to achieve the target wavelength range.

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