Manufacturing method for semiconductor devices and switching elements
A two-step silicide film formation process with varying temperatures addresses the challenge of inconsistent contact resistance in semiconductor devices by optimizing carbon concentration, enhancing device performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2025-01-07
- Publication Date
- 2026-07-17
AI Technical Summary
Existing semiconductor manufacturing methods face challenges in achieving low contact resistance at both the n-type and p-type layers due to varying temperature conditions affecting carbon precipitation in silicide films, leading to inconsistent performance.
A method involving two-step silicide film formation with different temperature regimes: forming a first silicide film at a higher temperature to increase carbon concentration and a second silicide film at a lower temperature to decrease carbon concentration, ensuring low contact resistance at both interfaces.
The method achieves low contact resistance at both the n-type and p-type layer interfaces by controlling carbon concentration in the silicide films, improving semiconductor device performance.
Smart Images
Figure 2026119459000001_ABST
Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a switching element.
Background Art
[0002] The semiconductor device of Patent Document 1 has a SiC substrate having an n-type layer and a p-type layer in a range including the surface. Further, the semiconductor device has a silicide film covering the surfaces of the n-type layer and the p-type layer. In this method for manufacturing a semiconductor device, first, a metal film covering the surfaces of the n-type layer and the p-type layer is formed. Next, the SiC substrate and the metal film are reacted by heat treatment to form a silicide film covering the surfaces of the n-type layer and the p-type layer.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In the step of forming the silicide film, when heat treatment is performed at a high temperature, the contact resistance between the n-type layer and the silicide film decreases, but the contact resistance between the p-type layer and the silicide film deteriorates. On the other hand, in the step of forming the silicide film, when heat treatment is performed at a low temperature, the contact resistance between the p-type layer and the silicide film decreases, but the contact resistance between the n-type layer and the silicide film deteriorates. In this specification, a technique for obtaining a low contact resistance at each of the interfaces between the n-type layer and the silicide film and between the p-type layer and the silicide film is provided.
Means for Solving the Problems
[0005] A method for manufacturing a semiconductor device disclosed herein may include a step of preparing a SiC substrate having an n-type layer and a p-type layer. The method may also include a step of forming a shielding film covering at least a portion of the surface of the p-type layer and a first metal film covering at least a portion of the surface of the n-type layer. The method may also include a step of forming a first silicide film at the interface between the first metal film and the n-type layer by heat-treating the SiC substrate at a first temperature while the shielding film and the first metal film are present. After the step of forming the first silicide film, the method may include a step of removing the shielding film. The method may also include a step of forming a second metal film covering the surface of the p-type layer exposed by the removal of the shielding film. The method may also include a step of forming a second silicide film at the interface between the second metal film and the p-type layer by heat-treating the SiC substrate at a second temperature lower than the first temperature while the second metal film is present.
[0006] When a silicide film is formed, carbon from the SiC substrate may precipitate into the silicide film. If the temperature during silicide film formation is high, the amount of carbon precipitated into the silicide film increases. That is, a higher temperature during silicide film formation results in a higher carbon concentration in the silicide film. If the temperature during silicide film formation is low, the amount of carbon precipitated into the silicide film is suppressed. That is, a lower temperature during silicide film formation results in a lower carbon concentration in the silicide film. The inventors of this invention have found that at the interface between the n-type semiconductor layer and the silicide film, the higher the carbon concentration in the silicide film, the lower the contact resistance. The inventors of this invention have also found that at the interface between the p-type semiconductor layer and the silicide film, the lower the carbon concentration in the silicide film, the lower the contact resistance. In the above semiconductor device manufacturing method, the first temperature in the step of forming the first silicide film is higher than the second temperature in the step of forming the second silicide film. Therefore, the amount of carbon deposited in the first silicide film is greater than the amount of carbon deposited in the second silicide film. As a result, low contact resistance can be obtained at both the interface between the n-type layer and the first silicide film, and at the interface between the p-type layer and the second silicide film.
[0007] A switching element disclosed herein may include a SiC substrate and a source electrode covering the surface of the SiC substrate. The SiC substrate may include an n-type source layer disposed in a region including the surface of the SiC substrate, a p-type body layer, and a p-type contact layer disposed in a region including the surface of the SiC substrate and connecting the body layer to the source electrode. The source electrode may include a first silicide film in contact with the source layer and a second silicide film in contact with the contact layer. The carbon concentration of the first silicide film may be higher than the carbon concentration of the second silicide film.
[0008] In the above switching element, low contact resistance can be obtained at both the interface between the source layer and the first silicide film, and at the interface between the contact layer and the second silicide film. [Brief explanation of the drawing]
[0009] [Figure 1] This is a schematic diagram of a semiconductor device. [Figure 2] This describes a method for manufacturing a semiconductor device of an example. [Figure 3] This describes a method for manufacturing a semiconductor device of an example. [Figure 4] This describes a method for manufacturing a semiconductor device of an example. [Figure 5] This describes a method for manufacturing a semiconductor device of an example. [Figure 6] This describes a method for manufacturing a semiconductor device of an example. [Figure 7] This describes a method for manufacturing a semiconductor device of an example. [Figure 8] This describes a method for manufacturing a semiconductor device of an example. [Figure 9] This describes a method for manufacturing a semiconductor device of an example. [Figure 10] This describes a method for manufacturing a semiconductor device of an example. [Figure 11] This describes a method for manufacturing a semiconductor device of an example. [Figure 12] This describes a method for manufacturing a semiconductor device of an example.
Best Mode for Carrying Out the Invention
[0010] In a method for manufacturing a semiconductor device according to an example disclosed in this specification, the semiconductor device is a trench gate type switching element, the first silicide film and the second silicide film are source electrodes, the n-type layer is a source layer, and the p-type layer may be a contact layer that connects a p-type body layer to the source electrode.
[0011] In a method for manufacturing a semiconductor device according to an example disclosed in this specification, the first temperature may be 900 °C or higher.
[0012] In a method for manufacturing a semiconductor device according to an example disclosed in this specification, the second temperature may be 800 °C or higher and less than 900 °C.
[0013] In a method for manufacturing a semiconductor device according to an example disclosed in this specification, the thickness of the first silicide film may be greater than the thickness of the second silicide film.
[0014] In a method for manufacturing a semiconductor device according to an example disclosed in this specification, the carbon concentration of the first silicide film may be higher than the carbon concentration of the second silicide film.
[0015] In a switching element according to an example disclosed in this specification, the thickness of the first silicide film may be greater than the thickness of the second silicide film.
Examples
[0016] (Structure of Semiconductor Device 100) The semiconductor device 100 of the embodiment shown in FIG. 1 is a MOSFET (metal-oxide-semiconductor field-effect transistor). The semiconductor device 100 has a semiconductor substrate 10. The semiconductor substrate 10 is a SiC substrate. A trench 12 is provided on the surface 10a (hereinafter referred to as the upper surface 10a) of the semiconductor substrate 10. A plurality of trenches 12 may be provided on the upper surface 10a. A gate insulating film 14, a gate electrode 16, and an interlayer insulating film 18 are provided in the trench 12. The gate insulating film 14 covers the inner surface of the trench 12. The gate electrode 16 is provided inside the gate insulating film 14. Also, the gate electrode 16 is insulated from the semiconductor substrate 10 by the gate insulating film 14. The interlayer insulating film 18 covers the upper surface of the gate electrode 16.
[0017] The semiconductor substrate 10 has a source layer 20, a contact layer 22, a body layer 24, a drift layer 26, and a drain layer 28. The source layer 20 is an n-type layer with a high n-type impurity concentration. The source layer 20 is disposed in a range including the upper surface 10a of the semiconductor substrate 10. The source layer 20 is in contact with the gate insulating film 14 on the side surface of the trench 12.
[0018] The contact layer 22 is a p-type layer with a high p-type impurity concentration. The contact layer 22 is disposed in a range including the upper surface 10a of the semiconductor substrate 10. The contact layer 22 is in contact with the gate insulating film 14 on the side surface of the trench 12 on the opposite side where the source layer 20 is in contact.
[0019] The body layer 24 is a p-type layer with a lower p-type impurity concentration than the contact layer 22. The body layer 24 is in contact with the lower surface of the source layer 20 and the lower surface of the contact layer 22. The body layer 24 is in contact with the gate insulating film 14 on the side surface of the trench 12 below the source layer 20 and the contact layer 22.
[0020] The drift layer 26 is an n-type layer with a lower n-type impurity concentration than the source layer 20. The drift layer 26 is in contact with the lower surface of the body layer 24. The drift layer 26 is in contact with the gate insulating film 14 at the side surface and bottom surface of the trench 12 below the body layer 24.
[0021] The drain layer 28 is an n-type layer with a higher n-type impurity concentration than the drift layer 26. The drain layer 28 is in contact with the lower surface of the drift layer 26. The drain layer 28 is located in a region that includes the lower surface 10b of the semiconductor substrate 10.
[0022] The semiconductor device 100 has a source electrode 40 and a drain electrode 60. The source electrode 40 covers the upper surface 10a of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 18. The source electrode 40 is in ohmic contact with the source layer 20 and the contact layer 22 on the upper surface 10a. The source electrode 40 is connected to the body layer 24 via the contact layer 22. In other words, the contact layer 22 connects the body layer 24 to the source electrode 40.
[0023] The source electrode 40 has a first silicide film 42, a second silicide film 44, and an electrode film 46. The first silicide film 42 is in contact with the upper surface of the source layer 20. The first silicide film 42 is composed of nickel silicide. The carbon concentration of the first silicide film 42 is high.
[0024] The second silicide film 44 is in contact with the upper surface of the contact layer 22. The second silicide film 44 is made of the same type of material as the first silicide film 42. In this embodiment, the second silicide film 44 is made of nickel silicide. The carbon concentration of the second silicide film 44 is lower than that of the first silicide film 42. The thickness of the second silicide film 44 is thinner than that of the first silicide film 42.
[0025] The electrode film 46 covers the upper surface of the interlayer insulating film 18, the first silicide film 42, and the second silicide film 44. The electrode film 46 is made of a metal such as aluminum.
[0026] The drain electrode 60 is in contact with the lower surface 10b of the semiconductor substrate 10. The drain electrode 60 is in ohmic contact with the drain layer 28.
[0027] (Method of manufacturing semiconductor device 100) Next, a method for manufacturing the semiconductor device 100 will be described. First, a semiconductor substrate 10 made of SiC is prepared. Figure 2 shows the semiconductor substrate 10 before processing. The semiconductor substrate 10 shown in Figure 2 has the source layer 20, contact layer 22, body layer 24, drift layer 26, and drain layer 28 described above. The source layer 20 and contact layer 22 are exposed on the upper surface 10a.
[0028] Next, as shown in Figure 3, a trench 12 is formed on the upper surface 10a of the semiconductor substrate 10 by selective etching. The trench 12 is formed so as to penetrate the body layer 24 from the upper surface 10a to the drift layer 26. Next, a gate insulating film 14 is formed on the upper surface 10a and the inner surface of the trench 12, for example by CVD. After the gate insulating film 14 is formed, a gate electrode 16 is formed in the trench 12. Here, the gate electrode 16 is formed so that its upper surface is located below the upper surface 10a of the semiconductor substrate 10.
[0029] Next, as shown in Figure 4, the insulating film 30 is grown over an area spanning the surface of the gate insulating film 14 and the upper surface of the gate electrode 16, for example, by the CVD method.
[0030] Next, as shown in Figure 5, the insulating film 30 is etched back. At this time, the upper surface 10a of the semiconductor substrate 10 is exposed from the insulating film 30, while the insulating film 30 remains inside the trench 12 (i.e., above the gate electrode 16). The insulating film 30 remaining inside the trench 12 becomes the interlayer insulating film 18.
[0031] Next, as shown in Figure 6, a shielding film 32 is formed on the upper surface 10a of the semiconductor substrate 10, for example, by photolithography. The shielding film 32 is made of carbon, for example.
[0032] Next, as shown in Figure 7, the shielding film 32 on the source layer 20 is removed, for example, by dry etching, leaving the shielding film 32 on the contact layer 22. The remaining shielding film 32 may cover the entire contact layer 22 or cover a part of it. Hereinafter, the remaining shielding film 32 will be referred to as the shielding film 32a. Next, as shown in Figure 7, a metal film 50 is formed on the semiconductor substrate 10, for example, by a sputtering method. Here, the metal film 50 is formed so as to cover the interlayer insulating film 18, the source layer 20, and the shielding film 32a. The metal film 50 is in contact with the upper surface of the source layer 20. The metal film 50 may cover the entire source layer 20 or cover a part of it. At this time, the metal film 50 is separated from the contact layer 22 by the shielding film 32a. The metal film 50 is composed of a nickel film.
[0033] Next, the semiconductor substrate 10 is heat-treated at a temperature of, for example, 900°C or higher to cause a reaction between the source layer 20 and the metal film 50 at their interface. As a result, as shown in Figure 8, a first silicide film 42 (i.e., a nickel silicide film) is formed at the interface between the source layer 20 and the metal film 50. At this time, the metal film 50 is separated from the contact layer 22 by the shielding film 32a. Since the contact layer 22 and the metal film 50 do not react, no silicide film is formed on the contact layer 22. The first silicide film 42 is a film formed by the reaction of silicon in the SiC constituting the source layer 20 and nickel constituting the metal film 50 to form a silicide. When the source layer 20 and the metal film 50 form a silicide, carbon in the SiC constituting the source layer 20 is deposited in the silicide film. Therefore, a carbon deposition layer exists within the first silicide film 42. The first silicide film 42 is in ohmic contact with the source layer 20.
[0034] Next, the unreacted metal film 50 and shielding film 32a are removed, for example, by etching. As a result, the first silicide film 42, the interlayer insulating film 18, and the contact layer 22 are exposed, as shown in Figure 9.
[0035] Next, as shown in Figure 10, a metal film 52 is formed on the semiconductor substrate 10, for example, by a sputtering method. Here, the metal film 52 is formed so as to cover the first silicide film 42, the interlayer insulating film 18, and the contact layer 22. The metal film 52 is in contact with the upper surface of the contact layer 22. The metal film 52 may cover the entire contact layer 22 or a part of the contact layer 22. The same type of material as the metal film 50 is used for the metal film 52. In this embodiment, the metal film 52 is the same nickel film as the metal film 50.
[0036] Next, the semiconductor substrate 10 is heat-treated at a temperature of, for example, 800°C or higher but less than 900°C to cause a reaction between the contact layer 22 and the metal film 52 at their interface. This forms a second silicide film 44 (i.e., a nickel silicide film) at the interface between the contact layer 22 and the metal film 52, as shown in Figure 11. The second silicide film 44 is a film formed by the reaction of silicon in the SiC constituting the contact layer 22 with the metal film 52, resulting in silicide formation. When the contact layer 22 and the metal film 52 undergo silicide formation, carbon in the SiC constituting the contact layer 22 is deposited into the silicide film. Therefore, a carbon deposition layer exists within the second silicide film 44. The reaction temperature in the formation process of the second silicide film 44 (i.e., a temperature of 800°C or higher but less than 900°C) is lower than the reaction temperature in the formation process of the first silicide film 42 (i.e., a temperature of 900°C or higher). Therefore, the amount of carbon deposited in the second silicide film 44 is less than the amount of carbon deposited in the first silicide film 42. Consequently, the carbon concentration of the second silicide film 44 is lower than that of the first silicide film 42. Since the reaction temperature in the formation process of the second silicide film 44 is lower than that in the formation process of the first silicide film 42, the thickness of the second silicide film 44 is thinner than that of the first silicide film 42. The second silicide film 44 makes ohmic contact with the contact layer 22.
[0037] Next, as shown in Figure 12, the unreacted metal film 52 is removed, for example, by etching, and an electrode film 46 is formed on the semiconductor substrate 10. Here, the electrode film 46 is formed so as to cover the upper surface of the interlayer insulating film 18, the first silicide film 42, and the second silicide film 44. The source electrode 40 is formed by the first silicide film 42, the second silicide film 44, and the electrode film 46. After that, the semiconductor device 100 shown in Figure 1 is completed by forming a drain electrode 60 on the lower surface 10b of the semiconductor substrate 10.
[0038] Research by the inventors of this invention has revealed that at the interface between the n-type semiconductor layer and the silicide film, the contact resistance decreases as the carbon concentration in the silicide film increases, and at the interface between the p-type semiconductor layer and the silicide film, the contact resistance decreases as the carbon concentration in the silicide film decreases. In the semiconductor device 100 formed by the above-described manufacturing method, the carbon concentration of the first silicide film 42 in contact with the n-type source layer 20 is higher than that of the second silicide film 44 in contact with the p-type contact layer 22. Therefore, low contact resistance can be obtained at both the interface between the source layer 20 and the first silicide film 42, and at the interface between the contact layer 22 and the second silicide film 44.
[0039] In the embodiment described above, the semiconductor device 100 was a MOSFET. However, the semiconductor device 100 can be any element having electrodes in contact with an n-type layer and a p-type layer.
[0040] In the above-described embodiment, the reaction temperature in the formation step of the second silicide film 44 was between 800°C and 900°C. However, the reaction temperature in the formation step of the second silicide film 44 only needs to be lower than the reaction temperature in the formation step of the first silicide film 42.
[0041] In the semiconductor device 100 described above, the first silicide film 42 and the second silicide film 44 were made of nickel silicide, but the first silicide film 42 and the second silicide film 44 may be made of titanium silicide, tungsten silicide, molybdenum silicide, or the like.
[0042] In the embodiment described above, the first silicide film 42 and the second silicide film 44 were made of the same type of material. However, the first silicide film 42 and the second silicide film 44 may be made of different types of materials.
[0043] The method for manufacturing a semiconductor device and the configuration of a switching element disclosed herein are described below. (Composition 1) A method for manufacturing a semiconductor device, A step of preparing a SiC substrate having an n-type layer and a p-type layer, A step of forming a shielding film that covers at least a portion of the surface of the p-type layer and a first metal film that covers at least a portion of the surface of the n-type layer, A step of forming a first silicide film at the interface between the first metal film and the n-type layer by heat-treating the SiC substrate at a first temperature while the shielding film and the first metal film are present, After the step of forming the first silicide film, the step of removing the shielding film is performed. A step of forming a second metal film that covers the surface of the p-type layer exposed by the removal of the shielding film, A step of forming a second silicide film at the interface between the second metal film and the p-type layer by heat-treating the SiC substrate at a second temperature lower than the first temperature while the second metal film is present. A method for manufacturing a semiconductor device, comprising: (Configuration 2) The semiconductor device is a trench gate type switching element, The first silicide film and the second silicide film are source electrodes. The aforementioned n-type layer is the source layer, The manufacturing method according to configuration 1, wherein the p-type layer is a contact layer that connects the p-type body layer to the source electrode. (Composition 3) The manufacturing method according to configuration 1 or 2, wherein the first temperature is 900°C or higher. (Composition 4) The manufacturing method according to any one of configurations 1 to 3, wherein the second temperature is 800°C or higher and less than 900°C. (Composition 5) The manufacturing method according to any one of configurations 1 to 4, wherein the thickness of the first silicide film is greater than the thickness of the second silicide film. (Composition 6) The manufacturing method according to any one of configurations 1 to 5, wherein the carbon concentration of the first silicide film is higher than the carbon concentration of the second silicide film. (Composition 7) A switching element, SiC substrate and A source electrode covering the surface of the SiC substrate, It has, The aforementioned SiC substrate An n-type source layer is disposed in a region including the surface of the SiC substrate, p-type body layer, A p-type contact layer is disposed in a region including the surface of the SiC substrate, and connects the body layer to the source electrode. It has, The source electrode is A first silicide film in contact with the source layer, A second silicide film in contact with the aforementioned contact layer, It has, A switching element in which the carbon concentration of the first silicide film is higher than the carbon concentration of the second silicide film. (Composition 8) The switching element according to configuration 7, wherein the thickness of the first silicide film is greater than the thickness of the second silicide film.
[0044] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]
[0045] 10: Semiconductor substrate, 10a: Surface, 12: Trench, 20: Source layer, 22: Contact layer, 24: Body layer, 32, 32a: Shielding film, 40: Source electrode, 42: First silicide film, 44: Second silicide film, 50: Metal film, 52: Metal film, 100: Semiconductor device
Claims
1. A method for manufacturing a semiconductor device, A step of preparing a SiC substrate (10) having an n-type layer and a p-type layer, A step of forming a shielding film that covers at least a portion of the surface of the p-type layer and a first metal film (50) that covers at least a portion of the surface of the n-type layer, The process involves heat-treating the SiC substrate at a first temperature while the shielding film and the first metal film are present, thereby forming a first silicide film (42) at the interface between the first metal film and the n-type layer. After the step of forming the first silicide film, the step of removing the shielding film is performed. A step of forming a second metal film (52) that covers the surface of the p-type layer exposed by the removal of the shielding film, A step of forming a second silicide film (42) at the interface between the second metal film and the p-type layer by heat-treating the SiC substrate at a second temperature lower than the first temperature while the second metal film is present, A method for manufacturing a semiconductor device, comprising:
2. The semiconductor device is a trench gate type switching element, The first silicide film and the second silicide film form a source electrode (40). The aforementioned n-type layer is the source layer (20), The manufacturing method according to claim 1, wherein the p-type layer is a contact layer (22) that connects a p-type body layer (24) to the source electrode.
3. The manufacturing method according to claim 1 or 2, wherein the first temperature is 900°C or higher.
4. The manufacturing method according to claim 3, wherein the second temperature is 800°C or higher and less than 900°C.
5. The manufacturing method according to claim 1 or 2, wherein the thickness of the first silicide film is greater than the thickness of the second silicide film.
6. The manufacturing method according to claim 1 or 2, wherein the carbon concentration of the first silicide film is higher than the carbon concentration of the second silicide film.
7. A switching element, SiC substrate (10) and A source electrode (40) covering the surface (10a) of the SiC substrate, It has, The aforementioned SiC substrate, An n-type source layer (20) is disposed in the area including the surface of the SiC substrate, p-type body layer (24), A p-type contact layer (22) is arranged in a region including the surface of the SiC substrate and connects the body layer to the source electrode. It has, The source electrode is A first silicide film (42) in contact with the source layer, A second silicide film (44) in contact with the contact layer, It has, A switching element in which the carbon concentration of the first silicide film is higher than the carbon concentration of the second silicide film.
8. The switching element according to claim 7, wherein the thickness of the first silicide film is greater than the thickness of the second silicide film.