Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can suppress the decrease in gate voltage. [Solution] The semiconductor device according to this disclosure comprises an inverter circuit connecting an upper arm and a lower arm, a high-side IC, and a low-side IC. The low-side IC has a first grounding terminal connected to the main terminal of the lower arm via a shunt resistor, a first power supply terminal to which a first power supply is supplied with reference to the first grounding terminal, a second grounding terminal connected to the connection point between the main terminal and the shunt resistor, a second power supply terminal to which a second power supply is supplied with reference to the second grounding terminal, a diode with its anode connected to the first power supply terminal and its cathode connected to the second power supply terminal, an input-side circuit to which power is supplied from the first power supply terminal, and an output-side circuit to which the voltage of the second power supply terminal is applied to the gate terminal of the lower arm. The second power supply is generated by supplying current from the first power supply terminal via the diode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a power conversion device including an upper arm switching element and a lower arm switching element connected in series with each other. An upper arm diode is connected in antiparallel to the upper arm switching element. A lower arm diode is connected in antiparallel to the lower arm switching element. An upper arm driver circuit drives the upper arm switching element, and a lower arm driver circuit drives the lower arm switching element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an inverter system such as that of Patent Document 1, the power elements constituting the upper arm and the lower arm receive a gate signal from a control IC (Integrated Circuit) and perform an on / off operation. Here, a shunt resistor may be connected to the lower arm to perform current detection. The current from the source or emitter of the lower arm passes through the shunt resistor and flows to the control ground. At this time, due to the influence of the shunt resistor, the source or emitter potential rises when the lower arm turns on. As a result, the gate voltage of the lower arm may decrease.

[0005] This disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor device capable of suppressing a decrease in gate voltage.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure comprises an inverter circuit in which an upper arm and a lower arm are connected in series with respect to each other, a high-side IC configured to control the on / off switching of the upper arm, and a low-side IC configured to control the on / off switching of the lower arm, wherein the low-side IC has a first grounding terminal connected via a shunt resistor to the main terminal of the lower arm opposite to the upper arm, a first power supply terminal configured to supply a first power supply with reference to the first grounding terminal, a second grounding terminal connected to the connection point between the main terminal and the shunt resistor, a second power supply terminal configured to supply a second power supply with reference to the second grounding terminal, a diode with its anode connected to the first power supply terminal and its cathode connected to the second power supply terminal, an input-side circuit configured to receive power from the first power supply terminal, and an output-side circuit configured to apply the voltage of the second power supply terminal to the gate terminal of the lower arm in response to an input signal for turning the lower arm on and off, wherein the second power supply is generated by supplying current from the first power supply terminal via the diode. [Effects of the Invention]

[0007] The second power supply terminal of the semiconductor device according to this disclosure is supplied with a second power supply based on a second grounding terminal connected to the connection point between the main terminal of the lower arm and the shunt resistor. The voltage of this second power supply terminal is applied to the gate terminal of the lower arm. When the lower arm is turned on, the potential of the main terminal rises due to the effect of the shunt resistor, and the potential of the second power supply terminal also rises. Therefore, a decrease in the gate voltage of the lower arm can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram shows the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This diagram illustrates the MOS structure of the input and output circuits according to Embodiment 1. [Figure 3]This is a diagram showing a level shift circuit according to Embodiment 1. [Figure 4] This is a diagram showing the configuration of a semiconductor device related to a comparative example. [Figure 5] This diagram shows the configuration of the semiconductor device according to Embodiment 2. [Figure 6] This is a plan view of the semiconductor device according to Embodiment 2. [Figure 7] This diagram shows the configuration of the semiconductor device according to Embodiment 3. [Figure 8] This is a plan view of the semiconductor device according to Embodiment 3. [Figure 9] This diagram shows the relationship between VNC and GND'u during recirculation. [Figure 10] This figure shows a signal generation circuit according to Embodiment 4. [Figure 11] This is a diagram showing a switch control circuit according to Embodiment 5. [Modes for carrying out the invention]

[0009] The semiconductor devices according to each embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repetition of the description may be omitted.

[0010] Embodiment 1. Figure 1 shows the configuration of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 is, for example, an IPM (Intelligent Power Module) that integrates a switching element and a drive circuit. The semiconductor device 100 is also called a power converter or power module. The semiconductor device 100 includes an inverter circuit 10 in which an upper arm 11 and a lower arm 12 are connected in series with each other, a high-side IC 20 configured to control the on / off state of the upper arm 11, and a low-side IC 30 configured to control the on / off state of the lower arm 12.

[0011] The upper arm 11 and lower arm 12 are switching elements such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), respectively. The upper arm 11 and lower arm 12 are also called power elements. In the upper arm 11 and lower arm, diodes are connected in antiparallel to the switching elements. The diodes may be configured on the same chip as the switching elements, such as in an RC-IGBT (Reverse Conductive IGBT). Alternatively, the body diode of a MOSFET may be used as the diode.

[0012] The lower arm 12 has a gate terminal 12a and main terminals 12b and 12c. Main terminal 12b is the collector terminal if the lower arm 12 is an IGBT, and the drain terminal if it is a MOSFET. Main terminal 12c is the emitter terminal if the lower arm 12 is an IGBT, and the source terminal if it is a MOSFET. A shunt resistor Rs is connected to the main terminal 12c of the lower arm 12 on the side opposite the upper arm 11. The shunt resistor Rs is used for current sensing. A capacitor C4 is connected between the collector terminal or drain terminal of the upper arm 11 and the control ground SGND to supply power VCC to both ends of the inverter circuit 10. In addition to the shunt resistor Rs, parasitic inductance L1 due to the internal pattern of the package and parasitic inductance L2 due to the external pattern are connected to the main terminal 12c.

[0013] The high-side IC 20 has a ground terminal VNC and a power supply terminal VP1. The ground terminal VNC is connected to the control ground SGND. A capacitor C1 for supplying the power supply VDD is connected between the ground terminal VNC and the power supply terminal VP1. Also, a bootstrap diode BSD is connected to the power supply terminal VP1. An input signal is input from the signal source 16 to the input terminal IN of the high-side IC 20. The high-side IC 20 outputs a drive signal from the output terminal OUT to the gate terminal of the upper arm 11 according to the input signal. Thereby, the high-side IC 20 controls the on / off of the upper arm 11.

[0014] The low-side IC 30 has a first ground terminal VNC, a second ground terminal GND’, a first power supply terminal VN1, a second power supply terminal 32, an input terminal IN, and an output terminal OUT. The first ground terminal VNC is connected to the main terminal 12c of the lower arm 12 via a shunt resistor Rs. The first ground terminal VNC is connected to the control ground SGND. The first power supply terminal VN1 is configured such that the power supply VDD is supplied with reference to the first ground terminal VNC. A capacitor C2 for supplying the power supply VDD is connected between the first power supply terminal VN1 and the first ground terminal VNC. The first power supply terminal VN1 may be connected to the aforementioned power supply terminal VP1.

[0015] The second ground terminal GND’ is connected to the connection point 14 between the main terminal 12c of the lower arm 12 and the shunt resistor Rs. That is, the main terminal 12c of the lower arm 12 and the second ground terminal GND’ are Kelvin-connected. The second power supply terminal 32 is configured such that the power supply VCC’ is supplied with reference to the second ground terminal GND’. A capacitor C3 for supplying the power supply VCC’ is connected between the second power supply terminal 32 and the second ground terminal GND’. The capacitor C3 is an external capacitor for gate charging of the lower arm 12.

[0016] An input signal is input from the signal source 16 to the input terminal IN of the low-side IC 30. The low-side IC 30 outputs a drive signal from the output terminal OUT to the gate terminal 12a of the lower arm 12 according to the input signal. Thereby, the low-side IC 30 controls the on / off of the lower arm 12.

[0017] The low-side IC 30 has a diode D1 with its anode connected to the first power supply terminal VN1 and its cathode connected to the second power supply terminal 32. The power supply VCC’ is generated by supplying current from the first power supply terminal VN1 through the diode D1. The diode D1 functions as a reverse current prevention diode.

[0018] The low-side IC 30 has an input-side circuit 35 and an output-side circuit 50. The input-side circuit 35 is configured to be supplied with power from the first power supply terminal VN1. The input-side circuit 35 operates with reference to the first ground terminal VNC. The input-side circuit 35 transmits the input signal input from the input terminal IN to the output-side circuit 50. In addition, the input-side circuit 35 may have functions such as a protection function of the inverter circuit 10 or a function of matching the delay times of the high-side IC 20 and the low-side IC 30.

[0019] The output-side circuit 50 is configured to be supplied with power from the second power supply terminal 32. The output-side circuit 50 operates with reference to the second ground terminal GND’. The output-side circuit 50 is configured to apply the voltage of the second power supply terminal 32 to the gate terminal 12a of the lower arm 12 according to an input signal for turning on / off the lower arm 12. In FIG. 1, an example of the output-side circuit 50 in which the voltage of the second power supply terminal 32 is applied to the gate terminal 12a through the output terminal OUT according to an input signal input to the NOT circuit is shown.

[0020] Figure 2 illustrates the MOS structure of the input circuit 35 and output circuit 50 according to Embodiment 1. The n-MOS and p-MOS shown in Figure 2 are examples of one of the multiple MOS structures that make up the input circuit 35 and output circuit 50. In the low-side IC 30, the diffusion layer 51 that forms the output circuit 50 and the diffusion layer 36 that forms the input circuit 35 are formed independently at the position indicated by the dashed line A1. In other words, at the position indicated by the dashed line A1, the CMOS of the input circuit 35 and the CMOS of the output circuit 50 are separated, and the input circuit 35 and the output circuit 50 can be operated at different reference potentials.

[0021] Figure 3 shows a level shift circuit 40 according to Embodiment 1. The low-side IC 30 may include a level shift circuit 40 configured to transmit an input signal from the input circuit 35 to the output circuit 50. In Figure 3, the portion of the level shift circuit 40 to the left of the dashed line A1 is formed in the input circuit 35. The level shift circuit 40 allows the input signal received from the input terminal IN to be transmitted from the input circuit 35, which has a different reference potential, to the output circuit 50. Note that any circuit other than the one shown in Figure 3 may be used as long as it is possible to transmit the input signal received from the input terminal IN from the input circuit 35 to the output circuit 50.

[0022] Figure 4 shows the configuration of a semiconductor device 800 in a comparative example. In the semiconductor device 800, the main terminal of the lower arm 12 is not Kelvin connected. Also, the low-side IC 830 does not have a second grounding terminal GND' and a second power supply terminal 32. The low-side IC 830 applies the voltage of the power supply terminal VN1 to the gate terminal of the lower arm 12 with reference to the grounding terminal VNC, according to the input signal.

[0023] Here, the current from the main terminal of the lower arm flows to the control ground through the shunt resistor Rs and the parasitic inductance L3 caused by the pattern. At this time, due to the influence of the shunt resistor Rs or the parasitic inductance L3, the potential of the main terminal of the lower arm 12 rises when the lower arm 12 is turned on. Therefore, there was a risk that the gate voltage of the lower arm 12 would decrease. This could increase the switching loss of the lower arm 12 under certain conditions. In addition, there was a risk of oscillation occurring due to the influence of the parasitic inductance.

[0024] In contrast, in the semiconductor device 100 according to this embodiment, a capacitor C3 is installed between the main terminal 12c and the second power supply terminal 32. Therefore, the second power supply terminal 32 is supplied with power supply VCC' with reference to the second grounding terminal GND' connected to the connection point 14 between the main terminal 12c of the lower arm and the shunt resistor Rs. The voltage of this second power supply terminal 32 is applied to the gate terminal 12a of the lower arm 12. Therefore, when the lower arm 12 is turned on, the potential of the main terminal 12c rises due to the effects of the shunt resistor Rs and parasitic inductance, and at the same time, the potential of the second power supply terminal 32 also rises. Consequently, a decrease in the gate voltage of the lower arm 12 can be suppressed. This suppresses a decrease in switching speed and reduces switching loss. Furthermore, the effect of parasitic inductance connected to the main terminal 12c of the lower arm 12 can be suppressed. This suppresses oscillation and improves the robustness of the system.

[0025] Although only one inverter circuit 10 is shown in Figure 1, this embodiment may also be applied to a three-phase inverter circuit, for example. In this case, for example, a second power supply terminal 32, from which the power supply VCC' of the output circuit 50 is taken, is provided for each of the U, V, and W phases. Furthermore, the configurations of the input circuit 35, level shift circuit 40, and output circuit 50 described above are examples and can be replaced with other circuits that have similar functions.

[0026] At least one of the upper arm 11 and the lower arm 12 may be formed of a wide-bandgap semiconductor. The wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. The same effects as in this embodiment can be obtained even when the power element is formed of a wide-bandgap semiconductor.

[0027] The modifications described above can be appropriately applied to the semiconductor device according to the following embodiments. Since the semiconductor device according to the following embodiments has many similarities with Embodiment 1, the explanation will focus on the differences from Embodiment 1.

[0028] Embodiment 2. Figure 5 is a diagram showing the configuration of the semiconductor device 200 according to Embodiment 2. Figure 6 is a plan view of the semiconductor device 200 according to Embodiment 2. The package 80 of the semiconductor device 200 includes a sense terminal 218 connected to the main terminal 12c. The second power supply terminal 32 is connected to the connection point 14 via the sense terminal 218 and capacitor C3. The other configurations are the same as those of Embodiment 1.

[0029] Figure 6 shows an example where the semiconductor device 200 is equipped with a three-phase inverter circuit 10. The high-side IC 20 controls the on / off state of the upper arms 11u, 11v, and 11w of the U, V, and W phases. The low-side IC 30 controls the on / off state of the lower arms 12u, 12v, and 12w of the U, V, and W phases. The sense terminals 218u, 218v, and 218w are connected to the emitter electrodes of the lower arms 12u, 12v, and 12w, respectively. In the case of a MOSFET, the emitter electrode becomes the source electrode.

[0030] In this embodiment, by providing a sense terminal 218, the external capacitor C3 can be mounted with reference to the potential of the emitter or source electrode of the lower arm 12. This makes it possible to reduce the parasitic inductance between the capacitor C3 and the main terminal 12c, including the component inside the package, to almost zero. Therefore, the reduction in switching speed and switching loss of the lower arm 12 can be suppressed to the greatest extent possible. Furthermore, oscillation can be further suppressed.

[0031] Embodiment 3. Figure 7 shows the configuration of the semiconductor device 300 according to Embodiment 3. Figure 8 is a plan view of the semiconductor device 300 according to Embodiment 3. The semiconductor device 300 includes a plurality of inverter circuits 10. For convenience, only the U-phase inverter circuit 10u of the three-phase inverter circuit 10 is shown in Figure 7. The main terminals 12c of the lower arms 12u, 12v, and 12w of the U-phase, V-phase, and W-phase are connected in Kelvin. Therefore, as shown in Figure 7, the low-side IC 330 has second grounding terminals GND'u, GND'v, and GND'w for the U-phase, V-phase, and W-phase. Also, as shown in Figure 8, emitter wiring Eu, Ev, and Ew and output wiring OUT_u, OUT_v, and OUT_w extend from the lower arms 12u, 12v, and 12w, respectively.

[0032] The low-side IC 330 receives multiple input signals corresponding to the three-phase inverter circuit 10. Multiple output circuits 50u, 50v, and 50w are also provided to correspond to the three-phase inverter circuit 10. The multiple input signals are input to the multiple output circuits 50u, 50v, and 50w via the level shift circuit 40. The multiple output circuits 50u, 50v, and 50w are configured to apply the voltage from the second power supply terminal 32 to the gate terminal 12a of the lower arm 12 of the multiple inverter circuits 10, in accordance with the multiple input signals corresponding to the multiple inverter circuits 10.

[0033] The low-side IC 330 has one second power supply terminal 32 and a switch circuit 60. The switch circuit 60 is composed of, for example, switching elements 61u, 62u connected to the output circuit 50u, switching elements 61v, 62v connected to the output circuit 50v, and switching elements 61w, 62w connected to the output circuit 50w. Thus, the switching circuit can be constructed using, for example, NMOS.

[0034] The switching element 61u receives the signal Vcc'_INu, which is the U-phase input signal converted by the level shift circuit 40. The signal Vcc'_INu is synchronized with the input signal. Therefore, when the lower arm 12u of the U-phase is ON, the switching elements 61u and 62u are turned ON. In other words, when an ON signal that turns on the lower arm 12u is input to the switching element 61u as the signal Vcc'_INu, the connection point 14 of the inverter circuit 10u and the second power supply terminal 32 are connected via the capacitor C3. The operation of the V-phase and W-phase is similar.

[0035] In other words, the switch circuit 60 is configured to connect the second power supply terminal 32 to one of the connection points 14 of the multiple inverter circuits 10 in response to multiple input signals. Specifically, the switch circuit 60 connects the second power supply terminal 32 to the connection point 14 of the inverter circuit 10 that receives an ON signal to turn on the lower arm 12 as the corresponding input signal.

[0036] The switch circuit 60 in this embodiment connects the power element that is turned on to the capacitor C3. Therefore, the main terminal 12c of the power element and the capacitor C3 are connected only when the potential of the main terminal 12c is high, and the potential of the second power supply terminal 32 rises. Thus, in this embodiment, the functions of Embodiment 1 can be realized with only one second power supply terminal 32. This reduces the number of terminals required for the power module. Also, only one capacitor C3 is required. Therefore, the power module, including the semiconductor device 300 and surrounding capacitors, can be miniaturized. In addition, the wiring pattern from the pins of the second power supply terminal 32 to the capacitor C3 can be simplified. For example, the power for the first power supply terminal VN1 may be supplied from the power supply terminal VP1 of the high-side IC 20, and the second power supply terminal 32 may be provided at the position of the first power supply terminal VN1.

[0037] Embodiment 4. Figure 9 shows the relationship between VNC and GND'u during recirculation. During recirculation, the potential of the second grounding terminal GND'u is lower than the potential of the first grounding terminal VNC. Therefore, for example, in Embodiment 3, when an ON signal is input to the power element during recirculation, the capacitor C3 and connection point 14 will be connected even in the state shown in Figure 9 where the potential of the second grounding terminal GND'u is low. For this reason, Embodiment 3 is difficult to apply to control methods that involve synchronous rectification, that is, control methods in which an ON signal is input to the power element during recirculation.

[0038] Figure 10 shows a signal generation circuit 64 according to Embodiment 4. In response to the above-mentioned problem, the switch circuit 60 of this embodiment generates the signal Vcc'_INu using the signal generation circuit 64. The operation of the signal generation circuit 64 will be explained below using the U phase as an example, but the V phase and W phase signals Vcc'_INv and Vcc'_INw can also be generated by a similar circuit.

[0039] In the signal generation circuit 64, the comparator uses the potential of the second grounding terminal GND'u as a reference to determine whether the voltage at the first grounding terminal VNC exceeds a predetermined reference voltage Vref. The reference voltage Vref should be set so that, when the inverter circuit 10u is in freewheeling operation, the connection point 14 corresponding to the inverter circuit 10u and the second power supply terminal 32 are not connected. As shown in Figure 9, during freewheeling operation, the potential of GND'u drops by -Ic × Rs relative to the potential of VNC. Therefore, it is possible to determine whether freewheeling operation is occurring based on the VNC potential as seen from the potential of GND'u. The signal generation circuit 64 is configured to output a signal Vcc'_INu synchronized with the input signal INu only when it is determined that freewheeling operation is not occurring.

[0040] In other words, the switch circuit 60 connects the connection point 14 of the inverter circuit 10, which receives an ON signal as its corresponding input signal and whose voltage at the corresponding first grounding terminal VNC is lower than the reference voltage Vref, to the second power supply terminal 32. As a result, the capacitor C3 and the connection point 14 are connected only when the power element is in the ON state with forward current flow. Therefore, even in control methods that involve synchronous rectification, a circuit configuration with only one second power supply terminal 32 can be adopted. Consequently, the power module can be miniaturized.

[0041] Embodiment 5. Figure 11 shows a switch control circuit 70 according to Embodiment 5. The switch control circuit 70 is positioned before the switch circuit 60 in the low-side IC 330. The signal SRFFu_OUT in Figure 11 is input to the switch circuit 60 as the signal Vcc'_INu in Figure 7. Here, the operation of the switch control circuit 70 is explained using the U phase as an example, but the V phase and W phase signals Vcc'_INv and Vcc'_INw can also be generated by a similar circuit.

[0042] In the switch control circuit 70, an SRFF (flip-flop) 72 is placed before the switch circuit 60. When an ON signal is input to the U-phase input signal INu, the shot pulse generation circuit 71 generates a shot pulse INU_shot and inputs it to the Set of the U-phase SRFF 72. As a result, the signal SRFFu_OUT turns ON, and the U-phase connection point 14 and capacitor C3 are connected. Similarly, shot pulses INv_shot and INw_shot are generated in the V-phase and W-phase. The V-phase and W-phase shot pulses INv_shot and INw_shot are input to the Reset of the U-phase SRFF 72. As a result, the signal SRFFu_OUT turns OFF.

[0043] In this manner, when the switch control circuit 70 receives an ON signal that turns on the corresponding lower arm 12u as one of the multiple input signals INu, INv, and INw, it outputs an ON output SRFFu_OUT to the switch circuit 60. This ON output SRFFu_OUT connects the connection point 14 of the inverter circuit 10u corresponding to the input signal INu to the second power supply terminal 32. The switch control circuit 70 also stops the ON output SRFFu_OUT when it receives an ON signal that turns on the corresponding lower arm 12 as an input signal other than the input signal INu, such as INv or INw.

[0044] In this embodiment, when capacitor C3 and connection point 14 are connected in one phase, if an ON signal is input from another phase, the connection between capacitor C3 and connection point 14 is released. This prevents the second grounding terminals GND'u, GND'v, and GND'w from short-circuiting. Therefore, even in a control method where multiple phases are turned on simultaneously, a single circuit configuration can be adopted for the second power supply terminal 32. Consequently, the power module can be miniaturized.

[0045] Furthermore, the determination of the recirculation operation in Embodiment 4 may be combined with this embodiment. The technical features described in each embodiment may be used in combination as appropriate.

[0046] The various aspects of this disclosure are summarized below as an appendix. (Note 1) An inverter circuit in which the upper arm and the lower arm are connected in series with each other, A high-side IC configured to control the on / off state of the upper arm, A low-side IC configured to control the on / off state of the lower arm, Equipped with, The aforementioned low-side IC is A first grounding terminal is connected via a shunt resistor to the main terminal on the lower arm opposite to the upper arm, A first power supply terminal configured such that a first power supply is supplied with reference to the first grounding terminal, A second grounding terminal connected to the connection point between the main terminal and the shunt resistor, A second power supply terminal configured to supply a second power supply with reference to the second grounding terminal, A diode having its anode connected to the first power supply terminal and its cathode connected to the second power supply terminal, An input circuit configured to receive power from the first power supply terminal, An output circuit configured to apply the voltage of the second power supply terminal to the gate terminal of the lower arm in response to an input signal for turning the lower arm on and off, It has, The semiconductor device is characterized in that the second power supply is generated by supplying current from the first power supply terminal via the diode. (Note 2) The semiconductor device according to Appendix 1, characterized in that, in the low-side IC, the diffusion layer forming the output circuit and the diffusion layer forming the input circuit are formed independently. (Note 3) The semiconductor device according to Appendix 1 or 2, characterized in that the low-side IC includes a level shift circuit configured to transmit the input signal from the input circuit to the output circuit. (Note 4) The package of the semiconductor device includes a sense terminal connected to the main terminal, The semiconductor device according to any one of appendices 1 to 3, characterized in that the second power terminal is connected to the connection point via the sense terminal. (Note 5) The inverter circuit comprises multiple inverter circuits, The aforementioned low-side IC is One of the aforementioned second power terminals, A plurality of output circuits are provided to correspond to the plurality of inverter circuits and are configured to apply the voltage of the second power supply terminal to the gate terminal of the lower arm of the plurality of inverter circuits in accordance with the plurality of input signals corresponding to the plurality of inverter circuits, A switch circuit configured to connect the connection point of any of the plurality of inverter circuits to the second power supply terminal in accordance with the plurality of input signals, A semiconductor device according to any one of the appendices 1 to 4, characterized by having the following: (Note 6) The semiconductor device according to Appendix 5, characterized in that the switch circuit connects the connection point of the inverter circuit among the plurality of inverter circuits to which an ON signal for turning on the lower arm is input as the corresponding input signal, to the second power terminal. (Note 7) The switch circuit connects the connection point of one of the plurality of inverter circuits, in which the ON signal is input as the corresponding input signal and the voltage of the corresponding first grounding terminal is lower than a predetermined reference voltage, to the second power supply terminal. The semiconductor device according to Appendix 5, characterized in that the reference voltage is set so as not to connect the corresponding connection point and the second power supply terminal during the recirculation operation of the inverter circuit. (Note 8) The low-side IC has a switch control circuit, The aforementioned switch control circuit is When an ON signal that turns on the corresponding lower arm is input as one of the plurality of input signals, the switch circuit is given an ON output that connects the connection point of the inverter circuit corresponding to the one of the plurality of inverter circuits to the second power terminal. The semiconductor device according to any one of the appendices 5 to 7, characterized in that when an ON signal that turns on the corresponding lower arm is input as an input signal other than the one input signal among the plurality of input signals, the ON output is stopped. (Note 9) The semiconductor device according to any one of appendices 1 to 8, characterized in that at least one of the upper arm and the lower arm is formed of a wide-bandgap semiconductor. (Note 10) The semiconductor device according to Appendix 9, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. [Explanation of Symbols]

[0047] 10, 10u, 10v, 10w Inverter circuit, 11, 11u, 11v, 11w Upper arm, 12, 12u, 12v, 12w Lower arm, 12a Gate terminal, 12b, 12c Main terminal, 14 Connection point, 16 Signal source, 20 High-side IC, 30 Low-side IC, 32 Second power supply terminal, 35 Input side circuit, 36 Diffusion layer, 40 Level shift circuit, 50, 50u, 50v, 50w Output side circuit, 51 Diffusion layer, 60 Switch circuit, 61u, 61v, 61w, 62u, 62v, 62w Switching element, 64 Signal generation circuit, 70 Switch control circuit, 71 Shot pulse generation circuit, 72 SRFF, 80 Package, 100 Semiconductor device, 200 Semiconductor device, 218, 218u, 218v, 218w Sense terminal, 300 semiconductor device, 330 low-side IC, 800 semiconductor device, 830 low-side IC, BSD bootstrap diode, C1, C2, C3, C4 capacitor, D1 diode, Eu, Ev, Ew emitter wiring, GND', GND'u second ground terminal, IN input terminal, OUT output terminal, Rs shunt resistor, VN1 first power terminal, VNC first ground terminal, VP1 power terminal

Claims

1. An inverter circuit in which the upper arm and the lower arm are connected in series with each other, A high-side IC configured to control the on / off state of the upper arm, A low-side IC configured to control the on / off state of the lower arm, Equipped with, The aforementioned low-side IC is A first grounding terminal is connected via a shunt resistor to the main terminal on the lower arm opposite to the upper arm, A first power supply terminal configured such that a first power supply is supplied with reference to the first grounding terminal, A second grounding terminal connected to the connection point between the main terminal and the shunt resistor, A second power supply terminal configured to supply a second power supply with reference to the second grounding terminal, A diode having its anode connected to the first power supply terminal and its cathode connected to the second power supply terminal, An input circuit configured to receive power from the first power supply terminal, An output circuit configured to apply the voltage of the second power supply terminal to the gate terminal of the lower arm in response to an input signal for turning the lower arm on and off, It has, The semiconductor device is characterized in that the second power supply is generated by supplying current from the first power supply terminal via the diode.

2. The semiconductor device according to claim 1, characterized in that the diffusion layer forming the output circuit and the diffusion layer forming the input circuit are formed independently in the low-side IC.

3. The semiconductor device according to claim 1 or 2, characterized in that the low-side IC includes a level shift circuit configured to transmit the input signal from the input circuit to the output circuit.

4. The package of the semiconductor device includes a sense terminal connected to the main terminal, The semiconductor device according to claim 1 or 2, characterized in that the second power terminal is connected to the connection point via the sense terminal.

5. The inverter circuit comprises multiple inverter circuits, The aforementioned low-side IC is One of the aforementioned second power terminals, A plurality of output circuits are provided to correspond to the plurality of inverter circuits and are configured to apply the voltage of the second power supply terminal to the gate terminal of the lower arm of the plurality of inverter circuits in accordance with the plurality of input signals corresponding to the plurality of inverter circuits, A switch circuit configured to connect the connection point of any of the plurality of inverter circuits to the second power supply terminal in accordance with the plurality of input signals, A semiconductor device according to claim 1 or 2, characterized by having the following features.

6. The semiconductor device according to claim 5, characterized in that the switch circuit connects the connection point of the inverter circuit among the plurality of inverter circuits to which an ON signal for turning on the lower arm is input as the corresponding input signal, to the second power terminal.

7. The switch circuit connects the connection point of one of the plurality of inverter circuits, in which the ON signal is input as the corresponding input signal and the voltage of the corresponding first grounding terminal is lower than a predetermined reference voltage, to the second power supply terminal. The semiconductor device according to claim 5, characterized in that the reference voltage is set so as not to connect the corresponding connection point and the second power supply terminal when the inverter circuit is in freewheeling operation.

8. The low-side IC has a switch control circuit, The aforementioned switch control circuit is When an ON signal that turns on the corresponding lower arm is input as one of the plurality of input signals, the switch circuit is given an ON output that connects the connection point of the inverter circuit corresponding to the one of the plurality of inverter circuits to the second power terminal. The semiconductor device according to claim 5, characterized in that when an ON signal that turns on the corresponding lower arm is input as an input signal other than the one input signal among the plurality of input signals, the ON output is stopped.

9. The semiconductor device according to claim 1 or 2, characterized in that at least one of the upper arm and the lower arm is formed of a wide bandgap semiconductor.

10. The semiconductor device according to claim 9, characterized in that the wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

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