Semiconductor equipment

Abstract

The present invention provides a semiconductor device that allows the advantages of multiple resistive field plates, each with different connection destinations, to coexist. [Solution] The semiconductor device comprises a substrate 1 of a first conductivity type, a first well region 2 of a second conductivity type provided on the upper surface side of the substrate 1 on which a high-side circuit 102 is formed, a withstand voltage structure (3,8) provided so as to surround the first well region 2, a level shifter 20a provided on the withstand voltage structure (3,8), and first and second resistive field plates (10,50),40 provided above the withstand voltage structure (3,8) via insulating films 71,72, with one end of each plate electrically connected to different semiconductor regions 2a,5 which are electrically connected to the high-side circuit 102.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a configuration in which a resistive field plate (RFP) is formed by a plurality of meandering resistance elements. Patent Document 2 discloses a configuration in which a part of a spiral resistance is formed of a metal layer, and the RFP is divided into two by forming a meandering resistance under the metal layer. Patent Document 3 discloses a configuration in which a plurality of high-side potentials are detected by two or more sense resistances that also function as an RFP.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In conventional semiconductor devices, sufficient consideration has not been given to coexisting the advantages of a plurality of RFPs having different connection destinations.

[0005] An object of this disclosure is to provide a semiconductor device capable of coexisting the advantages of a plurality of RFPs having different connection destinations.

Means for Solving the Problems

[0006] One aspect of the present disclosure is a semiconductor device comprising: a substrate of a first conductivity type; a first well region of a second conductivity type provided on the upper surface side of the substrate, on which a high-side circuit is formed; a breakdown structure provided so as to surround the first well region; a level shifter provided on the breakdown structure; and first and second RFPs provided above the breakdown structure via an insulating film, each having one end electrically connected to a different semiconductor region electrically connected to the high-side circuit. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a semiconductor device that can combine the advantages of multiple RFPs with different destinations. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram of a semiconductor device according to the first embodiment. [Figure 2] This is a plan view of a semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view taken along line AA' in Figure 2. [Figure 4] This is an enlarged plan view of a part of the semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view taken along line BB' in Figure 4. [Figure 6] This is a cross-sectional view taken along the CC' line in Figure 4. [Figure 7] This is a plan view of a semiconductor device according to the second embodiment. [Figure 8] This is an enlarged plan view of a part of the semiconductor device according to the second embodiment. [Figure 9] This is a cross-sectional view taken along line AA' in Figure 8. [Figure 10] This is a cross-sectional view taken along line BB' in Figure 8. [Figure 11] This is a plan view of a semiconductor device according to the third embodiment. [Figure 12] This is a plan view of the semiconductor device according to the fourth embodiment. [Figure 13] This is a plan view of a semiconductor device according to the fifth embodiment. [Figure 14] This is a plan view of a semiconductor device according to the sixth embodiment. [Figure 15] This is a plan view of the semiconductor device according to the seventh embodiment. [Figure 16] This is a plan view of the semiconductor device according to the eighth embodiment. [Figure 17] This is a cross-sectional view of a semiconductor device according to the ninth embodiment. [Figure 18] This is a cross-sectional view of a semiconductor device according to the tenth embodiment. [Figure 19] This is a plan view of a resistive field plate according to another embodiment. [Figure 20] This is a plan view of a resistive field plate according to another embodiment. [Figure 21] This is a plan view of a resistive field plate according to another embodiment. [Modes for carrying out the invention]

[0009] The first to tenth embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first to tenth embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0010] In this specification, "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or electrostatic induction transistor (SIT), or the emitter region of an insulated-gate bipolar transistor (IGBT). In diodes, electrostatic induction (SI) thyristors, or gate turn-off (GTO) thyristors, the anode region serves as the carrier supply region. Furthermore, "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of an FET or SIT, or the collector region of an IGBT. In diodes, SI thyristors, or GTO thyristors, the cathode region functions as the carrier receiving region.

[0011] Furthermore, in this specification, the definitions of directions such as up and down are merely for explanatory convenience and do not limit the technical ideas of this disclosure. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0012] Furthermore, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type will be explained exemplarily. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Also, the "+" and "-" attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without "+" and "-" attached. However, even if two semiconductor regions are marked with the same "n," this does not mean that the impurity concentrations of each semiconductor region are exactly the same. Moreover, in the following explanation, the components and regions specified as "first conductivity type" and "second conductivity type" refer to components and regions made of semiconductor material, even without explicit limitation.

[0013] (First Embodiment) <Semiconductor device circuit> As an example of a semiconductor device according to the first embodiment, a high-voltage integrated circuit (HVIC) 100 is shown in Figure 1. The HVIC 100 drives, for example, a power conversion unit 200 which is one phase of a power conversion bridge circuit. The power conversion unit 200 is configured as a half-bridge circuit by connecting a high-potential side switching element T3 and a low-potential side switching element T4 in series. In Figure 1, IGBTs are shown as the high-potential side switching element T3 and the low-potential side switching element T4, but other power switching elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) may be used.

[0014] The collector of the high-potential switching element T3 is connected to the high-potential HV potential. The emitter of the low-potential switching element T4 is connected to the low-potential ground potential (GND potential). The connection point 105 between the emitter of the high-potential switching element T3 and the collector of the low-potential switching element T4 is connected to the VS potential of the negative terminal of the high-potential power supply (high-potential power supply) 104. The VS potential is the midpoint potential of the half-bridge circuit composed of the high-potential switching element T3 and the low-potential switching element T4. A load (not shown), such as a motor, can be connected to the connection point 105.

[0015] The HVIC100 applies a drive signal to the gate of the high-potential switching element T3 to drive it by turning its gate on and off in response to an input signal IN from an external microcontroller or the like. The HVIC100 includes a low-potential circuit (low-side circuit) 101, a high-potential circuit (high-side circuit) 102, a level shift circuit 111, a voltage divider resistor 113, and a resistor R7. The low-side circuit 101 is connected to the VCC potential on the positive side of the low-potential power supply (low-potential power supply) 103 and the GND potential on the negative side of the low-potential power supply 103. Furthermore, the gates of the level shift elements (level shifters) T1 and T2 of the level shift circuit 111 are connected to the low-side circuit 101.

[0016] The low-side circuit 101 operates with the GND potential as the reference potential and the VCC potential, which is approximately 15V higher than the GND potential, as the power supply potential. In response to an input signal IN from an external microcontroller or the like, which is based on the GND potential, the low-side circuit 101 generates an on / off signal based on the GND potential and outputs it to the gates of the level shifters T1 and T2.

[0017] The level shift circuit 111 includes level shifters T1 and T2 and level shift resistors R1 and R2. The level shifters T1 and T2 transmit signals between the low-side circuit 101 and the high-side circuit 102. The level shifters T1 and T2 convert the on / off signal from the low-side circuit 101, which is referenced to the GND potential, into an on / off signal referenced to the VS potential, and output the converted on / off signal to the high-side circuit 102. The level shifters T1 and T2 are composed of, for example, high-voltage n-channel MOSFETs (HVNMOS).

[0018] The source of level shifter T1 is connected to the GND potential. The drain of level shifter T1 is connected to the high-side circuit 102 and one end of level shift resistor R1. The other end of level shift resistor R1 is connected to the positive terminal VB potential of the high-potential side power supply 104. The drain of level shifter T1 and one end of level shift resistor R1 are connected to the cathode of diode D1. The anode of diode D1 is connected to the negative terminal VS potential of the high-side circuit 102 and high-potential side power supply 104. Diode D1 has the function of preventing an excessive drop in the drain potential (Dr potential) of level shifter T1.

[0019] The source of level shifter T2 is connected to the GND potential. The drain of level shifter T2 is connected to the high-side circuit 102 and one end of level shift resistor R2. The other end of level shift resistor R2 is connected to the positive terminal VB potential of the high-potential power supply 104. The drain of level shifter T2 and one end of level shift resistor R2 are connected to the cathode of diode D2. The anode of diode D2 is connected to the negative terminal VS potential of the high-side circuit 102 and high-potential power supply 104. Diode D2 has the function of preventing an excessive drop in the drain potential (Dr potential) of level shifter T2.

[0020] The cathode of a high-voltage diode D0, called a high-voltage junction termination (HVJT), is connected to the VB potential on the positive side of the high-voltage power supply 104. The anode of diode D0 is connected to the GND potential.

[0021] The high-side circuit 102 operates with the VS potential, which is the midpoint potential of the half-bridge circuit, as its reference potential, and the VB potential, which is higher than the VS potential, as its power supply potential. In response to the on / off signals from the level shifters T1 and T2, the high-side circuit 102 outputs a drive signal referenced to the VS potential to the gate of the high-potential side switching element T3, thereby driving the gate of the high-potential side switching element T3. The high-side circuit 102 includes, for example, CMOS circuits of n-channel MOSFETs and p-channel MOSFETs in its output stage.

[0022] The voltage divider resistor 113 has resistors R3 and R4. One end of resistor R3 is connected to the high-side circuit 102 and the VS potential. One end of resistor R4 is connected to the other end of resistor R3. The other end of resistor R4 is connected to the GND potential. The connection point of resistors R3 and R4 is connected to the low-side circuit 101. One end of resistor R7 is connected to the VB potential and the other end is connected to the GND potential.

[0023] The VB potential is the highest potential applied to the HVIC100, and under normal conditions unaffected by noise, it is maintained approximately 15V higher than the VS potential. The VS potential fluctuates between 0V and several hundred V as the high-potential HV potential (for example, between approximately 100V and 400V) and the low-potential GND potential are switched on and off complementaryly by the high-potential switching element T3 and the low-potential switching element T4. Note that the VS potential can also be negative.

[0024] <Structure of a semiconductor device> Figure 2 shows a planar layout of the semiconductor device according to the first embodiment, corresponding to the HVIC100 shown in Figure 1. The semiconductor device according to the first embodiment has a first conductivity type (p - The device comprises a substrate (semiconductor chip) 1 of type p. The substrate 1 is composed of, for example, a silicon (Si) substrate. The substrate 1 may also be composed of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), or diamond. Furthermore, the substrate 1 is p - A semiconductor substrate of type and p provided on the semiconductor substrate - It may also consist of an epitaxial layer of a certain type.

[0025] The substrate 1 may be fixed at GND potential. A well region 2, which is a semiconductor region of the second conductivity type (n-type), is provided on the upper side (top) of the substrate 1. The well region 2 has a substantially rectangular planar pattern. A high-side circuit (high-side circuit region) 102 is formed in the well region 2. In Figure 2, the various elements included in the high-side circuit 102 are not shown.

[0026] A contact region (pickup region) 2a, which is an n-type semiconductor region, is provided on the upper side (top) of well region 2. A VB potential is applied to the contact region 2a. A p-type well region 5 is provided on the upper side (top) of well region 2. A VS potential is applied to well region 5.

[0027] Surrounding well region 2, adjacent to well region 2, is n with a lower impurity concentration than well region 2. - A breakdown voltage region 8, which is a semiconductor region of a certain type, is provided. The breakdown voltage region 8 is annular and has a planar pattern with an outer shape that is approximately rectangular.

[0028] A voltage-bearing region 3, which is a p-type semiconductor region, is provided adjacent to the voltage-bearing region 8, surrounding its outer periphery. The voltage-bearing region 3 is annular and has a planar pattern with a substantially rectangular outer shape. A GND potential is applied to the voltage-bearing region 3. The outer periphery of the voltage-bearing region 3 is surrounded by the substrate 1.

[0029] p-type withstand voltage regions 3 and n - A pn junction in the voltage-resistant region 8 of the type constitutes a voltage-resistant structure (3,8) called a high-voltage junction termination (HVJT). The voltage-resistant structure (3,8) corresponds to the high-voltage diode D0 shown in Figure 1. The voltage-resistant structure (3,8) is annular and has a roughly rectangular planar pattern. The voltage-resistant structure (3,8) electrically isolates the high-side circuit 102 on the inner circumference side of the voltage-resistant structure (3,8) from the low-side circuit (low-side circuit region) 101 formed on the substrate 1 on the outer circumference side of the voltage-resistant structure (3,8). The voltage-resistant structure (3,8) ensures that the device operates normally even when the potential of the high-side circuit 102 is several hundred volts higher than the potential of the low-side circuit 101.

[0030] In the plan view of Figure 2, the low-side circuit 101 is provided below the high-side circuit 102 via a voltage-resistant structure (3,8). In Figure 2, the various elements constituting the low-side circuit 101 are not shown.

[0031] As shown in Figure 2, a level shift element (level shifter) 20a is provided in the pressure-resistant structure (3,8). The level shifter 20a is provided including a part of the pressure-resistant region 8. The level shifter 20a corresponds to the level shifter T1 shown in Figure 1. Note that in Figure 2, the level shifter corresponding to the level shifter T2 shown in Figure 1 is not shown.

[0032] The level shifter 20a is composed of high-voltage-resistant n-channel MOSFETs (HVNMOS). The level shifter 20a has an n + -type carrier supply region (source region) 21a, a gate electrode 22a, and an n + -type carrier receiving region (drain region) 23a. The source region 21a, the gate electrode 22a, and the drain region 23a have a linear planar pattern that extends parallel to each other. A part of the high-voltage region 8 sandwiched between the source region 21a and the drain region 23a constitutes the drift region of the level shifter 20a.

[0033] A separation region (slit region) 6a, which is a p - -type semiconductor region, is provided so as to surround the periphery of the level shifter 20a. The slit region 6a has a substantially U-shaped planar pattern that has a bottom on the high-side circuit 102 side and an opening on the low-side circuit 101 side. Each end of a pair (two) of straight portions connected to the substantially U-shaped bottom of the slit region 6a is in contact with the high-voltage region 3. That is, the semiconductor device according to the first embodiment has a structure (divided RESURF structure) in which the level shifter 20a is surrounded by the slit region 6a and electrically separated from the high-voltage structure portions (3, 8).

[0034] FIG. 3 shows a cross section taken along the line A-A' passing through the level shifter 20a in FIG. 2. As shown in FIG. 3, an n-type well region 2 is provided on the upper part of the p - -type substrate 1. The well region 2 is composed of a diffusion layer into which n-type impurities are ion-implanted. The high-side circuit 102 is formed in the well region 2.

[0035] An n - -type high-voltage region 8 is provided on the upper part of the substrate 1 in contact with the well region 2. The high-voltage region 8 is composed of a diffusion layer into which n-type impurities are ion-implanted. The depth of the high-voltage region 8 is shallower than the depth of the well region 2. On the upper part of the substrate 1, a p -A slit region 6a of a certain type is provided. The slit region 6a is composed of a diffusion layer in which p-type impurities are ion-implanted. The depth of the slit region 6a is greater than the depth of the pressure-bearing region 8.

[0036] As shown in Figure 3, the level shifter 20a is p - It is separated from the n-type well region 2 by the slit region 6a. - A portion of the pressure-bearing region 8, separated from the n-type well region 2 by the slit region 6a, constitutes the drift region of the level shifter 20a. Above the pressure-bearing region 8 that constitutes the drift region of the level shifter 20a, + A drain region 23a of type n is provided. The drain region 23a is composed of a diffusion layer in which n-type impurities are ion-implanted.

[0037] Insulating films 71 and 72 are provided on the upper surface of the drain region 23a. Insulating films 71 and 72 are not shown in Figure 1. A drain electrode 32 is connected to the drain region 23a via vias 32a made of metal or the like, provided in the openings (contact holes) of the insulating films 71 and 72. The drain electrode 32 may be made of a metal mainly composed of aluminum (Al) or copper (Cu), for example.

[0038] As the insulating film 71, a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film thereof can be used. The insulating film 71 may also be an insulating film produced by chemical vapor deposition (CVD) using a gas of an organosilicon compound such as tetraethoxysilane (TEOS).

[0039] As the insulating film 72, silicon oxide films without impurities, referred to as "NSG films" (SiO2 films), silicon oxide films with added phosphorus (PSG films), and silicon oxide films with added boron (BSG films) can be used. Furthermore, single-layer films of silicon oxide films with added phosphorus and boron (BPSG films) or silicon nitride films (Si3N4 films), or composite films combining multiple types of these, can also be used as the insulating film 72.

[0040] A p-type pressure-bearing region 3 is provided on the upper part of the substrate 1, in contact with the pressure-bearing region 8 on the opposite side of the well region 2. The pressure-bearing region 3 is composed of a diffusion layer in which p-type impurities are ion-implanted. A portion of the pressure-bearing region 3 that is in contact with the pressure-bearing region 8, which constitutes the drift region of the level shifter 20a, functions as the base region of the level shifter 20a.

[0041] The upper part of the pressure-bearing region 3, which functions as the base region of the level shifter 20a, is n + A source region 21a of type n is provided. The source region 21a is composed of a diffusion layer in which n-type impurities are ion-implanted. Above the breakdown region 3, which functions as the base region of the level shifter 20a, a p-type source region with a higher impurity concentration than the breakdown region 3 is provided in contact with the source region 21a. + A type contact region 4 is provided. The contact region 4 consists of a diffusion layer in which p-type impurities are ion-implanted.

[0042] The source electrode 31 is connected to the source region 21a and the contact region 4 via vias 31a made of metal or the like, which are provided in the openings (contact holes) of the insulating film 71 and the insulating film 72. The source electrode 31 may be made of a metal mainly composed of, for example, aluminum (Al) or copper (Cu).

[0043] A gate electrode 22a is provided on the upper surface of the breakdown region 3, which is sandwiched between the source region 21a and the breakdown region 8, via a gate insulating film 25. The gate insulating film 25 can be a single layer of any one of the following: silicon oxide (SiO2), silicon oxynitride (SiON), strontium oxide (SrO), silicon nitride (Si3N4), aluminum oxide (Al2O3), magnesium oxide (MgO), yttrium oxide (Y2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or bismuth oxide (Bi2O3), or a composite film made by stacking multiple of these. As the material for the gate electrode 22a, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0044] In semiconductor devices such as HVICs, a field plate may be provided above the HVJT and HVNMOS to ensure stable breakdown voltage. Resistive field plates (RFPs) formed in a spiral or meandering pattern are particularly useful for ensuring high breakdown voltage because they exert a stronger potential forcing than concentrically formed capacitively coupled field plates (MFFPs). Typically, one end of the RFP is connected to a potential such as the VB or VS potential in the high-side circuit, and the other end is connected to a potential such as the GND potential in the low-side circuit. The preferred potential for connecting one end of the RFP to within the high-side circuit varies depending on the purpose.

[0045] For example, if the RFP is used as a voltage divider resistor and has the function of detecting the midpoint potential of a half-bridge circuit, it is preferable to connect the RFP directly to the VS potential rather than to connect it to the VB potential. Also, the p that separates the HVNMOS and HVJT -When a slit region of a certain type is formed, the RFP provided above the slit region should be at a low potential to prevent field inversion in the slit region, so it is preferable to connect it to a VS potential or the like, which is lower than the VB potential. On the other hand, in order to prevent the drain potential of the HVNMOS from unexpectedly dropping due to noise, the RFP capacitively coupled to the drain region of the HVNMOS should be at a high potential, so it is preferable to connect it to a VB potential or the like, which is higher than the VS potential. Therefore, in the semiconductor device according to the first embodiment, the RFP is divided into multiple parts, and the potential of the high-side circuit connected to each region is changed so that the advantages of each potential connection can coexist.

[0046] As shown in Figure 2, the semiconductor device according to the first embodiment includes two independent RFPs, RFP(10,50) and RFP40, above the breakdown structure (3,8) via insulating films 71,72 (see Figure 3). RFP(10,50) and RFP40 have the function of ensuring stable breakdown voltage by creating a uniform potential distribution with a small current for the high voltage applied within the HVIC. Although not shown, level shift resistors R1 and R2, composed of polysilicon layers, may be provided above the well region 2 via the insulating film 71.

[0047] The RFP(10,50) constitutes the resistor R7 shown in Figure 1 and has a spiral-shaped planar pattern surrounding the well region 2 in which the high-side circuit 102 is formed. The width of the RFP(10,50) in the direction perpendicular to the direction in which the spiral extends is, for example, about 1 μm, but is not particularly limited. The spacing between adjacent spiral lines of the RFP(10,50) in the direction perpendicular to the direction in which the spiral extends is, for example, about 1 μm, but is not particularly limited.

[0048] Figure 2 illustrates a case where the RFP(10,50) is wound approximately 5 times, but the number of turns (windings) of the RFP(10,50) is not particularly limited. The number of turns of the RFP(10,50) can be appropriately set according to the width of the pressure-bearing region 8 in the direction perpendicular to the direction in which the spiral of the RFP(10,50) extends.

[0049] Figure 2 illustrates the case where RFP(10,50) is left-handed, rotating counterclockwise from the inner circumference (higher potential) to the outer circumference (lower potential). However, it may also be right-handed, rotating clockwise. Furthermore, Figure 2 illustrates the case where the outer shape of RFP(10,50) is approximately rectangular. However, the outer shape of RFP(10,50) is not limited to this. The outer shape of RFP(10,50) may be, for example, approximately elliptical or approximately racetrack-shaped.

[0050] The inner end 10a of RFP(10,50) is electrically connected to the high-side circuit 102. + It is electrically connected to the contact region 2a, which is a semiconductor region of type . A VB potential is applied to the contact region 2a. The outer end 10b of RFP(10,50) is p + It is electrically connected to the contact region 4, which is a semiconductor region of the type. The ground potential (GND potential) is applied to the contact region 4. The inner end 10a of RFP(10,50) is the high-potential side, and the outer end 10b of RFP(10,50) is the low-potential side.

[0051] RFP(10,50) is positioned closest to the drain region 23a of the level shifter 20a among all the RFPs provided by the semiconductor device according to the first embodiment. RFP(10,50) is positioned closer to the drain region 23a of the level shifter 20a than RFP40. In the plan view of Figure 2, RFP(10,50) is separated from the drain region 23a of the level shifter 20a by a predetermined distance d1. In the region where RFP(10,50) and the drain region 23a face each other, the predetermined distance d1 may be constant or may vary.

[0052] The RFP(10,50) has a resistive section 10 and a connecting section 50 located above the resistive section 10. The resistive section 10 constitutes the majority of the RFP(10,50) and includes the portion closest to the drain region 23a of the level shifter 20a. At each turn of the RFP(10,50), a portion of the resistive section 10 is divided, and a connecting section 50 is provided at the divided position. The multiple connecting sections 50 have a linear planar pattern extending parallel to each other. Both ends of each of the multiple connecting sections 50 are electrically connected to the divided ends of the resistive section 10. In Figure 1, the connecting sections 50 are schematically shown with solid lines, and the connections of the connecting sections 50 to the resistive section 10 are shown with black circles.

[0053] The RFP40 is positioned to overlap with the connection portion 50. The RFP40 has a meandering planar pattern that crosses the pressure-resistant structure portion (3,8). In Figure 2, the folded portion of the RFP40 faces the divided end of the resistance portion 10, but it may be positioned offset from the divided end of the resistance portion 10. The number of folded portions of the RFP40 is not particularly limited.

[0054] RFP40 constitutes the voltage divider resistor 113 shown in Figure 1 and has the function of detecting the VS potential, which is the midpoint potential of the half-bridge circuit. A p-type well region 5 is electrically connected to the inner end 40a of RFP40, and the VS potential is applied to it. A contact region 4 is electrically connected to the outer end 40b of RFP40, and the GND potential is applied to it. The inner end 40a of RFP40 is the high potential side, and the outer end 40b of RFP40 is the low potential side.

[0055] A voltage divider point 40c is provided between the inner end 40a and the outer end 40b of the RFP40. The voltage divider point 40c is electrically connected to the low-side circuit 101. The portion of the RFP40 inside the voltage divider point 40c corresponds to the resistor R3 shown in Figure 1, and the portion of the RFP40 outside the voltage divider point 40c corresponds to the resistor R4 shown in Figure 1. The low-side circuit 101 monitors the potential at the voltage divider point 40c and may stop driving the power conversion unit 200 or output an alarm if the potential at the voltage divider point 40c becomes above or below a predetermined threshold.

[0056] Figure 4 shows an enlarged plan view of the overlapping portion between RFP(10,50) connection 50 and RFP40 in Figure 2. In Figure 4, connection 50 is schematically shown with a solid line, and the connection portion of connection 50 to the resistor 10 is shown with a black circle. Figure 5 shows a cross-section cut along line BB' in Figure 4, and Figure 6 shows a cross-section cut along line CC' in Figure 4.

[0057] As shown in Figure 5, a p-type well region 5 is provided on the upper side of the n-type well region 2. On the upper side of well region 5 is a p-type well region with a higher impurity concentration than well region 5. + A type of contact region (pickup region) 5a is provided. Note that the contact region 5a is not shown in Figures 1 and 4. A VS electrode 33 to which a VS potential is applied is electrically connected to the contact region 5a via vias 33a made of metal or the like, which are provided in the openings (contact holes) of the insulating film 71 and insulating film 72.

[0058] On the upper side of the n-type well region 2, there is an n-type well region with a higher impurity concentration than well region 2. + A type contact region (pickup region) 2a is provided. A VB electrode 34 to which a VB potential is applied is electrically connected to the contact region 2a via vias 34a made of metal or the like, which are provided in the openings (contact holes) of the insulating film 71 and the insulating film 72.

[0059] On the upper side of the p-type breakdown region 3, there is a p-type with a higher impurity concentration than the breakdown region 3. + A type of contact region (pickup region) 4 is provided. A GND electrode 35 to which a GND potential is applied is electrically connected to the contact region 4 via a via 35a made of metal or the like, which is provided in the openings (contact holes) of the insulating film 71 and the insulating film 72.

[0060] As shown in Figures 5 and 6, the RFP40 is located above the breakdown region 8 and on the upper surface side of the insulating film 71. The RFP40 is composed of a thin-film resistive layer of polysilicon to which, for example, p-type or n-type impurities are added. The impurity concentration of the RFP40 is, for example, 1 × 10⁻⁶ 17 cm -3 The above is 1 x 10 20 cm -3 The sheet resistance of RFP40 is approximately 1 kΩ / sq or more and 10 kΩ / sq or less.

[0061] As shown in Figure 6, the resistive portion 10 of RFP(10,50) is located above the breakdown voltage region 8, in the same layer as RFP40 on the upper surface side of the insulating film 71, and separated from RFP40. The resistive portion 10 may be made of the same material as RFP40, in which case it can be formed in the same process as the process for forming RFP40. The resistive portion 10 is made of, for example, a thin film resistive layer of polysilicon to which p-type or n-type impurities are added. The impurity concentration of the resistive portion 10 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 20 cm -3 The sheet resistance value of the resistor section 10 is, for example, approximately 1 kΩ / sq or more and 10 kΩ / sq or less.

[0062] As shown in Figures 5 and 6, the connection portion 50 of RFP(10,50) is located above the withstand voltage region 8 and on the upper surface side of the insulating film 72. The connection portion 50 may also be located on the upper surface side of an insulating film (not shown) further above the insulating film 72. The connection portion 50 is made of a metal mainly composed of aluminum (Al) or copper (Cu), for example. The connection portion 50 may be made of the same material as the source electrode 31 and drain electrode 32 of the level shifter 20a, in which case it can be formed in the same process as the process for forming the source electrode 31 and drain electrode 32. The connection portion 50 may be made of a different material from the source electrode 31 and drain electrode 32, such as polysilicon.

[0063] As shown in Figure 6, both ends of the connection portion 50 are provided so as to overlap with the separated ends of the resistor portion 10. Both ends of the connection portion 50 are electrically connected to the separated ends of the resistor portion 10 via vias 50a and 50b made of metal or the like, which are provided in the openings (contact holes) of the insulating film 72. In other words, the resistor portion 10 and the connection portion 50 are connected in series.

[0064] According to the semiconductor device of the first embodiment, the field plate on the withstand voltage structure (3,8) is composed of two independent RFPs, RFP(10,50) and RFP40. The ends 10a and 40a of RFP(10,50) and RFP40, respectively, are electrically connected to different semiconductor regions electrically connected to the high-side circuit 102. For example, the inner end 10a of RFP(10,50) is electrically connected to the n-type well region 2 and the VB potential, while the inner end 40a of RFP40 is electrically connected to the p-type well region 5 and the VS potential. This makes it possible to combine (achieve) the advantages of RFP(10,50) and RFP40, which have different connection destinations.

[0065] For example, an RFP(10,50) having an n-type well region 2 and an end 10a electrically connected to the VB potential is placed closer to the drain region 23a of the level shifter 20a than the RFP40, and capacitively coupled. This effectively prevents the drain potential of the level shifter 20a from unexpectedly dropping due to noise.

[0066] Furthermore, an RFP40 having an end 40a electrically connected to the p-type well region 5 and the VS potential is used as a voltage divider resistor 113 (sense resistor) to detect the potential of the high-side circuit 102. This makes it possible to directly detect the VS potential, which is the midpoint potential of the half-bridge circuit.

[0067] (Second Embodiment) Figure 7 is a plan view of the semiconductor device according to the second embodiment. As shown in Figure 7, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that it includes two independent RFPs, RFP(10,51) and RFP60.

[0068] RFP(10,51) and RFP60 are provided above the withstand voltage structure (3,8) via insulating films 71 and 72 (see Figures 9 and 10). RFP(10,51) and RFP60 have the function of ensuring stable withstand voltage by creating a uniform potential distribution with a small current for the high voltage applied within the HVIC.

[0069] The RFP(10,51) has a spiral-shaped planar pattern surrounding the well region 2 in which the high-side circuit 102 is formed. The width of the RFP(10,51) in the direction perpendicular to the direction in which the spiral extends is, for example, about 1 μm, but is not particularly limited. The spacing between adjacent spiral lines of the RFP(10,51) in the direction perpendicular to the direction in which the spiral extends is, for example, about 1 μm, but is not particularly limited.

[0070] Figure 7 illustrates a case where RFP(10,51) is wound approximately 5 times, but the number of turns (windings) of RFP(10,51) is not particularly limited. The number of turns of RFP(10,51) can be appropriately set according to the width of the pressure-bearing region 8 in the direction perpendicular to the direction in which the spiral of RFP(10,51) extends.

[0071] Figure 7 illustrates the case where RFP(10,51) is left-handed, rotating counterclockwise toward the outer circumference, but it may also be right-handed, rotating clockwise. Furthermore, Figure 7 illustrates the case where the outer shape of RFP(10,51) is approximately rectangular, but the outer shape of RFP(10,51) is not limited to this. The outer shape of RFP(10,51) may be, for example, approximately elliptical, or approximately racetrack-shaped.

[0072] A well region 5, which is a p-type semiconductor region, is electrically connected to the inner end 10a of RFP(10,51), and a VS potential is applied. A p + The contact region 4, which is a semiconductor region of the type, is electrically connected, and the ground potential (GND potential) is applied.

[0073] The RFP(10,51) has a resistor 10 and a connection 51 provided above the resistor 10. The resistor 10 constitutes the majority of the RFP(10,51). The resistor 10 surrounds the level shifter 20a. - It includes a portion that overlaps with the slit region 6a of the mold and passes over (straddles) the slit region 6a. In the plan view of Figure 7, at the position where it overlaps with the level shifter 20a, a portion of the resistive section 10 is divided at each rotation of RFP(10,50), and a connection portion 51 is provided at the divided position. The multiple connection portions 51 have a linear planar pattern that extends parallel to each other. Both ends of each of the multiple connection portions 51 are electrically connected to the divided ends of the resistive section 10. In Figure 7, the connection portions 51 are schematically shown with solid lines, and the connections of the connection portions 51 to the resistive section 10 are shown with black circles.

[0074] RFP60 is p - It is provided in the inner region surrounded by the slit region 6a of the type, at a position overlapping with the level shifter 20a, and traversing the pressure-resistant structure (3,8). RFP60 has a meandering planar pattern. At the inner end 60a of RFP60, n + The contact area 2a of the type is electrically connected and the VB potential is applied. The contact area 4 is electrically connected to the outer end 60b of RFP60 and the GND potential is applied.

[0075] RFP60 is positioned closest to the drain region 23a of the level shifter 20a among all the RFPs provided in the semiconductor device according to the second embodiment. RFP60 is positioned closer to the drain region 23a of the level shifter 20a than RFP(10,51). In the plan view of Figure 7, RFP(10,51) is separated from the drain region 23a of the level shifter 20a by a predetermined distance d2. In the region where RFP(10,51) and the drain region 23a face each other, the predetermined distance d2 may vary depending on the shape of the meandering planar pattern of RFP60. It is even more desirable that RFP60 be positioned closer to the drain electrode 32 of the level shifter 20a than RFP(10,51). By capacitively coupling RFP60 with the drain electrode 32, the effect of preventing the drain potential of the level shifter 20a from unexpectedly dropping due to noise can be further enhanced.

[0076] Figure 8 shows an enlarged plan view of the area where the connection point 51 of RFP(10,51) in Figure 7 and RFP60 overlap. In Figure 8, the connection point 51 is schematically shown with a solid line, and the connection point of the connection point 51 to the resistor 10 is shown with a black circle.

[0077] Figure 9 shows a cross-section taken along line AA' in Figure 8, and Figure 10 shows a cross-section taken along line BB' in Figure 8. As shown in Figures 9 and 10, the RFP60 is located above the breakdown region 8 and on the upper surface side of the insulating film 71. The RFP60 is composed of a thin-film resistive layer of polysilicon to which, for example, p-type or n-type impurities are added. The impurity concentration of the RFP60 is, for example, 1 × 10⁻⁶ 17 cm -3 The above is 1 x 10 20 cm -3 The sheet resistance of RFP60 is approximately 1 kΩ / sq or more and 10 kΩ / sq or less.

[0078] As shown in Figure 10, the resistive portion 10 of RFP(10,51) is located above the breakdown voltage region 8, in the same layer as RFP60 on the upper surface side of the insulating film 71, and separated from RFP60. The resistive portion 10 may be made of the same material as RFP60, in which case it can be formed in the same process as the process for forming RFP60. The resistive portion 10 is made of, for example, a thin-film resistive layer of polysilicon to which p-type or n-type impurities are added. The impurity concentration of the resistive portion 10 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 20 cm -3 The sheet resistance value of the resistor section 10 is, for example, approximately 1 kΩ / sq or more and 10 kΩ / sq or less.

[0079] As shown in Figures 9 and 10, the connection portion 51 of RFP(10,51) is located above the withstand voltage region 8 and on the upper surface side of the insulating film 72. The connection portion 51 may also be located on the upper surface side of an insulating film (not shown) further above the insulating film 72. The connection portion 51 is made of a metal mainly composed of aluminum (Al) or copper (Cu), for example. The connection portion 51 may be made of the same material as the source electrode 31 and drain electrode 32 of the level shifter 20a, in which case it can be formed in the same process as the process for forming the source electrode 31 and drain electrode 32. The connection portion 51 may be made of a different material from the source electrode 31 and drain electrode 32, such as polysilicon.

[0080] As shown in Figure 10, both ends of the connection portion 51 are provided so as to overlap with the separated ends of the resistor portion 10. Both ends of the connection portion 51 are electrically connected to the separated ends of the resistor portion 10 via vias 51a and 51b made of metal or the like, which are provided in the openings (contact holes) of the insulating film 72. That is, the resistor portion 10 and the connection portion 51 are connected in series. The other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0081] According to the semiconductor device of the second embodiment, the field plate on the withstand voltage structure (3,8) is composed of two independent RFPs, RFP(10,51) and RFP60. The ends 10a and 60a of RFP(10,51) and RFP60 are electrically connected to different semiconductor regions. For example, the end 10a of RFP(10,51) is electrically connected to the p-type well region 5 and the VS potential, while the end 60a of RFP60 is electrically connected to the n-type well region 2 and the VB potential. This makes it possible to combine (achieve) the advantages of RFP(10,51) and RFP60, which have different connection destinations.

[0082] For example, an RFP60 having an n-type well region 2 and an end 60a electrically connected to the VB potential is placed closer to the drain region 23a of the level shifter 20a than to the RFP(10,51) and capacitively coupled. This effectively prevents the drain potential of the level shifter 20a from unexpectedly dropping due to noise.

[0083] Also, p - When the slit region 6a of the type is field-reversed, a parasitic n-type MOSFET operates with the slit region 6a as the channel and the breakdown region 8 flanking the slit region 6a as the source and drain. In contrast, an RFP(10,51) having a p-type well region 5 and an end 10a electrically connected to the VS potential is p - By providing it so as to overlap the slit region 6a of the mold, field inversion of the slit region 6a can be prevented.

[0084] (Third embodiment) Figure 11 is a plan view of the semiconductor device according to the third embodiment. As shown in Figure 11, the semiconductor device according to the third embodiment is similar to the semiconductor device according to the first embodiment in that it has two independent RFPs, RFP(10,50) and RFP40. However, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that the resistive portion 10 of RFP(10,50) has a resistive portion (low resistance portion) 10x and a resistive portion (high resistance portion) 10y with a higher resistance than the low resistance portion 10x. In Figure 11, the low resistance portion 10x is schematically hatched with diagonal lines.

[0085] In the plan view of Figure 11, the low-resistance portion 10x includes the portion from the inner end 10a of RFP(10,50) to a position that passes over (straddles) the pair of slit regions 6a that sandwich the level shifter 20a in the extending direction of the low-resistance portion 10x. The low-resistance portion 10x includes the portion closest to the drain region 23a of the level shifter 20a. The low-resistance portion 10x is located closer to the drain region 23a of the level shifter 20a than the high-resistance portion 10y.

[0086] The sheet resistance of the low-resistance section 10x is, for example, approximately 100 Ω / sq or more and 1 kΩ / sq or less. The impurity concentration of the low-resistance section 10x is higher than that of the high-resistance section 10y. The impurity concentration of the low-resistance section 10x may be the same as that of the contact area of ​​the inner end 10a of RFP(10,50) and the contact area of ​​the outer end 10b of RFP(10,50). The low-resistance section 10x can be formed by ion implanting p-type or n-type impurities with a higher total dose than that of the high-resistance section 10y.

[0087] The high-resistance section 10y includes the portion from the boundary position 10c with the low-resistance section 10x to the outer end 10b of the RFP(10,50). The sheet resistance value of the high-resistance section 10y is, for example, approximately 1 kΩ / sq or more and 10 kΩ / sq or less. The other configurations of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0088] According to the semiconductor device of the third embodiment, similar to the first embodiment, the advantages of RFP(10,50) and RFP40, which have different connection destinations, can be combined (matched). Furthermore, RFP(10,50) has a low-resistance section 10x and a high-resistance section 10y, and the low-resistance section 10x, which has a small voltage drop from the VB potential, is closest to the drain region 23a of the level shifter 20a. This makes it possible to more effectively prevent a decrease in the drain potential of the level shifter 20a.

[0089] (Fourth Embodiment) Figure 12 is a plan view of the semiconductor device according to the fourth embodiment. As shown in Figure 12, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in that it includes three independent RFPs, RFP(10, 50, 51), RFP40 and RFP60, as field plates on the pressure-resistant structure (3, 8).

[0090] The RFP(10,50,51) has the same configuration as the RFP(10,51) of the semiconductor device according to the second embodiment shown in Figure 7, except that it further includes a connection part 50. The RFP(10,50,51) has a spiral planar pattern. A p-type well region 5 is electrically connected to the inner end 10a of the RFP(10,50,51), and a VS potential is applied. At the outer end 10b of the RFP(10,50,51), a p + The contact area 4 of the type is electrically connected, and the GND potential is applied.

[0091] RFP(10,50,51) comprises a resistor 10 and connection parts 50,51 provided above the resistor 10. The resistor 10 is p - It is positioned to pass above the slit region 6a of the mold. The connecting portion 50 is positioned to overlap with the RFP 40. The connecting portion 51 is positioned to overlap with the RFP 60 in the inner region surrounded by the slit region 6a.

[0092] RFP40 has the same configuration as RFP40 of the semiconductor device according to the first embodiment shown in Figure 2. RFP40 constitutes a voltage divider resistor 113 and has the function of detecting the VS potential. The inner end 40a of RFP40 is electrically connected to the well region 5 and the VS potential is applied to it. The outer end 40b of RFP40 is electrically connected to the contact region 4 and the GND potential is applied to it. The voltage divider point 40c of RFP60 is electrically connected to the low-side circuit 101.

[0093] The RFP60 has the same configuration as the RFP60 of the semiconductor device according to the second embodiment shown in Figure 7. The inner end 60a of the RFP60 is electrically connected to the contact area 2a and the VB potential is applied to it. The outer end 60b of the RFP60 is electrically connected to the contact area 4 and the GND potential is applied to it. The RFP60 is closest to the drain area 23a of the level shifter 20a. The other configurations of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0094] According to the semiconductor device of the fourth embodiment, the field plate on the withstand voltage structure (3,8) is composed of three independent RFPs: RFP(10,50,51), RFP40, and RFP60. The ends 10a and 40a of RFP(10,50,51) and RFP40, and the end 60a of RFP60 are electrically connected to different semiconductor regions. For example, the ends 10a and 40a of RFP(10,50,51) and RFP40 are electrically connected to the p-type well region 5 and the VS potential, while the end 60a of RFP60 is electrically connected to the n-type well region 2 and the VB potential. This allows the advantages of each of the three independent RFPs, RFP(10,50,51), RFP40, and RFP60, to coexist.

[0095] For example, by having an end 60a electrically connected to the n-type well region 2 and the VB potential, and positioning the RFP60 closest to the drain region 23a of the level shifter 20a, a decrease in the drain potential of the level shifter 20a can be effectively prevented. Furthermore, by using an RFP40 having an end 40a electrically connected to the p-type well region 5 and the VS potential as a voltage divider resistor 113, the midpoint potential of the half-bridge circuit can be detected, thereby directly detecting the VS potential, which is the midpoint potential of the half-bridge circuit. While a voltage divider resistor 113 can be used by setting voltage divider points on RFP(10, 50, 51), the resistance value and area are set to obtain the field plate effect of the entire voltage-resistant structure, resulting in a large parasitic capacitance and a long detection time. By providing an RFP40 connected to the VS potential separately from RFP(10, 50, 51) connected to the VS potential, a voltage divider resistor with an optimal resistance value and parasitic capacitance considering detection time and current consumption can be arranged. Furthermore, RFP(10,50,51) can obtain the field plate effect of the entire pressure-resistant structure, and furthermore p - By providing it so as to overlap the slit region 6a of the mold, field inversion of the slit region 6a can be prevented.

[0096] (Fifth embodiment) Figure 13 is a plan view of the semiconductor device according to the fifth embodiment. As shown in Figure 13, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 2 in that it includes four independent RFPs, RFP(10, 50, 52, 53), RFP40, RFP81, and RFP82, as field plates on the pressure-resistant structure (3, 8).

[0097] RFP(10,50,52,53) has the same configuration as RFP(10,50) of the semiconductor device according to the first embodiment shown in Figure 2, except that it further includes connection parts 52,53. RFP(10,50,52,53) has a spiral planar pattern. The inner end 10a of RFP(10,50,52,53) has n +The contact area 2a of type is electrically connected and the VB potential is applied. At the outer end 10b of RFP(10,50,52,53), p + The contact area 4 of the type is electrically connected and the GND potential is applied. Of the four RFPs, RFP(10, 50, 52, 53) is closest to the drain area 23a of the level shifter 20a.

[0098] RFP(10,50,52,53) comprises a resistor 10 and connection parts 50,52,53 located above the resistor 10. In Figure 13, the connection parts 50,52,53 are schematically shown with solid lines, and the connections between the connection parts 50,52,53 and the resistor 10 are shown with black circles. The resistor 10 includes the portion closest to the drain region 23a of the level shifter 20a. The resistor 10 is p - It is not provided above the slit region 6a of the mold. The connecting parts 52 and 53 are provided so as to pass above the slit region 6a. Connecting part 50 is provided in a position that overlaps with RFP 40. Connecting part 52 is provided in a position that overlaps with RFP 81. Connecting part 53 is provided in a position that overlaps with RFP 82.

[0099] The RFP40 has the same configuration as the RFP40 of the semiconductor device according to the first embodiment shown in Figure 2. The RFP40 constitutes a voltage divider resistor 113 and has the function of detecting the VS potential. The RFP40 is located below the connection portion 50, at a position where the resistance portion 10 is divided. The inner end portion 40a of the RFP40 is electrically connected to the well region 5, to which the VS potential is applied. The outer end portion 40b of the RFP40 is electrically connected to the contact region 4, to which the GND potential is applied. The voltage divider point 40c of the RFP40 is electrically connected to the low-side circuit 101.

[0100] RFP81 is located below the connection portion 52, at a position where the resistive portion 10 is interrupted. RFP81 has a meandering planar pattern that traverses the withstand voltage structure portion (3,8). RFP81 is positioned to pass above the slit region 6a. RFP81 is on the same layer as the resistive portion 10, but spaced apart from it. The inner end 81a of RFP81 is electrically connected to the well region 5, to which the VS potential is applied. The outer end 81b of RFP81 is electrically connected to the contact region 4, to which the GND potential is applied.

[0101] RFP82 is located below the connection portion 53, at a position where the resistive portion 10 is interrupted. RFP82 has a meandering planar pattern that crosses the withstand voltage structure portion (3,8). RFP82 is positioned to pass above the slit region 6a. RFP82 is on the same layer as the resistive portion 10, but spaced apart from it. The inner end 82a of RFP82 is electrically connected to the well region 5, to which a VS potential is applied. The outer end 82b of RFP82 is electrically connected to the contact region 4, to which a GND potential is applied. Other configurations of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0102] According to the semiconductor device of the fifth embodiment, the field plate on the withstand voltage structure (3,8) is composed of four independent RFPs: RFP(10, 50, 52, 53), RFP40, RFP81, and RFP82. The end 10a of RFP(10, 50, 52, 53) and the ends 40a, 81a, and 82a of RFP40, RFP81, and RFP82 are electrically connected to different semiconductor regions. For example, the ends 40a, 81a, and 82a of RFP40, RFP81, and RFP82 are electrically connected to the p-type well region 5 and the VS potential, while the end 10a of RFP(10, 50, 52, 53) is electrically connected to the n-type well region 2 and the VB potential. This allows the advantages of each of the four independent RFPs—RFP(10,50,51), RFP(10,50,52,53), RFP40, RFP81, and RFP82—to coexist.

[0103] For example, by having an n-type well region 2 and an end 10a electrically connected to the VB potential, RFPs (10, 50, 52, 53) are closest to the drain region 23a of the level shifter 20a, a decrease in the drain potential of the level shifter 20a can be effectively prevented. Furthermore, by using RFP40, which has a p-type well region 5 and an end 40a electrically connected to the VS potential, as a voltage divider resistor 113, the midpoint potential of the half-bridge circuit can be detected, thereby directly detecting the VS potential, which is the midpoint potential of the half-bridge circuit. Also, by using RFP81 and RFP82, which have p-type well regions 5 and an end 81a, 82a electrically connected to the VS potential, - By positioning it so as to pass above the slit region 6a of the mold, field inversion of the slit region 6a can be prevented.

[0104] (Sixth Embodiment) Figure 14 is a plan view of the semiconductor device according to the sixth embodiment. As shown in Figure 14, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 2 in that the RFP11 connected to the well region 2 and the VB potential has a meandering planar pattern surrounding the well region 2, rather than a spiral pattern.

[0105] The inner end 11a of RFP11 is electrically connected to the well region 2 and the VB potential. The outer end 11b of RFP11 is electrically connected to the contact region 4 and the GND potential. RFP40 is provided between the folded portions of the meandering planar pattern of RFP11. Although Figure 14 illustrates the case where RFP11 has one meandering planar pattern, it may be divided into multiple meandering planar patterns. The other configurations of the semiconductor device according to the sixth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0106] According to the semiconductor device of the sixth embodiment, even if the RFP11 connected to the well region 2 and the VB potential has a meandering planar pattern rather than a spiral pattern, the same effects as the semiconductor device of the first embodiment can be achieved.

[0107] (Seventh Embodiment) Figure 15 is a plan view of the semiconductor device according to the seventh embodiment. As shown in Figure 15, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the second embodiment shown in Figure 7 in that the RFP12 connected to the well region 5 and the VS potential has a meandering planar pattern surrounding the well region 2, rather than a spiral pattern.

[0108] The inner end 12a of RFP12 is electrically connected to the well area 5 and the VS potential. The outer end 12b of RFP12 is electrically connected to the contact area 4 and the GND potential. The folded portion of the meandering planar pattern of RFP12 is p - It is provided so as to pass above the slit region 6a of the mold. RFP60 is provided between the folded portions of the meandering planar pattern of RFP12. Although Figure 15 illustrates the case where RFP12 has one meandering planar pattern, it may be divided into multiple meandering planar patterns. The other configurations of the semiconductor device according to the seventh embodiment are the same as those of the semiconductor device according to the second embodiment, so redundant explanations are omitted.

[0109] According to the semiconductor device of the seventh embodiment, even if the RFP12 connected to the well region 5 and the VS potential has a meandering planar pattern rather than a spiral pattern, the same effects as the semiconductor device of the first embodiment can be achieved.

[0110] (Eighth embodiment) Figure 16 is a plan view of a semiconductor device according to the eighth embodiment. The semiconductor device according to the eighth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 2 in that, as shown in Figure 16, a plurality (two) of level shifters 20a and 20b are integrally formed on a part of the pressure-resistant structure (3,8). The level shifters 20a and 20b are provided adjacent to each other on one side of the rectangle formed by the planar pattern of the pressure-resistant structure (3,8). Note that the arrangement position of the level shifters 20a and 20b is not limited to this. For example, the level shifters 20a and 20b may be provided on opposite sides of the rectangle formed by the planar pattern of the pressure-resistant structure (3,8).

[0111] Level shifter 20b has the same configuration as level shifter 20a. Level shifter 20b has n + Source region 21b, gate electrode 22b and n + It includes a drain region 23b of a certain type. The source region 21b, gate electrode 22b, and drain region 23b have linear planar patterns that extend parallel to each other. A portion of the withstand voltage region 8 sandwiched between the source region 21b and the drain region 23b constitutes the drift region of the level shifter 20b.

[0112] p - A slit region 6b of the type is provided. The slit region 6b electrically isolates the level shifter 20b from the well region 2. The other configurations of the semiconductor device according to the eighth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0113] According to the semiconductor device of the eighth embodiment, even when a plurality of level shifters 20a, 20b are provided, the same effects as the semiconductor device of the first embodiment can be achieved. In the case where the semiconductor device of the seventh embodiment shown in Figure 15 is provided with two level shifters 20a, 20b, an RFP similar to the RFP 60 may be provided at a position overlapping with the level shifters 20b.

[0114] (Ninth Embodiment) Figure 17 is a cross-sectional view of the semiconductor device according to the ninth embodiment, and corresponds to the position of the cross-section of the semiconductor device according to the first embodiment shown in Figure 3. As shown in Figure 17, in the semiconductor device according to the ninth embodiment, the substrate 1 is p - A semiconductor substrate 1a of a certain type, and p provided on the semiconductor substrate 1a - The semiconductor device according to the first embodiment shown in Figure 3 differs in that it is composed of an epitaxial layer 1b of a certain type.

[0115] Furthermore, the semiconductor device according to the 9th embodiment has a higher impurity concentration n in contact with the lower surface of the well region 2. + The semiconductor device according to the ninth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 3 in that it is provided with a molded embedding layer 9. The other configurations of the semiconductor device according to the ninth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0116] According to the semiconductor device of the 9th embodiment, the substrate 1 is p - A semiconductor substrate 1a of a certain type, and p provided on the semiconductor substrate 1a - Even when composed of an epitaxial layer 1b of type , the same effects as the semiconductor device according to the first embodiment can be achieved. Furthermore, in contact with the lower surface of the well region 2, n with a higher impurity concentration than the well region 2 is present. + Even when a molded embedding layer 9 is provided, the same effects as those of the semiconductor device according to the first embodiment can be achieved. Furthermore, the configuration of the epitaxial substrate of the semiconductor device according to the ninth embodiment is also applicable to the semiconductor devices according to the second to eighth embodiments.

[0117] (Tenth embodiment) Figure 18 is a cross-sectional view of the semiconductor device according to the 10th embodiment, and corresponds to the position of the cross-section of the semiconductor device according to the 1st embodiment shown in Figure 3. The semiconductor device according to the 10th embodiment differs from the semiconductor device according to the 1st embodiment shown in Figure 3 in that it is made of an SOI (Silicon on Insulator) substrate, as shown in Figure 18.

[0118] The semiconductor device according to the 10th embodiment is n -type or p - It is equipped with a support substrate 400 of a certain type. An insulating film 401 such as an oxide film is provided on the upper side of the support substrate 400. - A molded substrate 1 is provided. The other configurations of the semiconductor device according to the 10th embodiment are the same as those of the semiconductor device according to the 1st embodiment, so redundant explanations are omitted.

[0119] According to the semiconductor device of the 10th embodiment, even when it is composed of an SOI substrate, it can achieve the same effects as the semiconductor device of the first embodiment. The configuration of the SOI substrate in the semiconductor device of the 10th embodiment is also applicable to the semiconductor devices of the second to eighth embodiments.

[0120] (Other embodiments) As described above, this disclosure is based on embodiments 1 through 10, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0121] For example, in the semiconductor device according to the first to tenth embodiments, the case in which RFP40, 60, 81, and 82 have a meandering planar pattern is illustrated, but the meandering shape is not particularly limited and any shape that can be substantially considered meandering is acceptable. For example, RFP40 may have a meandering planar pattern as shown in Figures 19 to 21. RFP60, 81, and 82 may also have a meandering planar pattern similar to RFP40 shown in Figures 19 to 21.

[0122] Furthermore, while the semiconductor devices according to the first to tenth embodiments exemplified a case where one end of each RFP 10, 11, 12, 40, 60, 81, 82, (10, 50), (10, 51), (10, 50, 51), (10, 50, 52, 53) is connected to the VB potential or VS potential, the invention is not limited to this, and it is sufficient if the RFPs are connected to the potential used in the high-side circuit 102. For example, one end of each RFP 10, 11, 12, 40, 60, 81, 82, (10, 50), (10, 51), (10, 50, 51), (10, 50, 52, 53) may be connected to the drain potential of the level shifter 20a. The drain potential of the level shifter 20a is a potential between the VB potential and the VS potential. Also, when a field plate is configured with three or more independent RFPs, three or more RFPs may be connected to three or more different semiconductor regions and different potentials. For example, one end of each of the three RFPs may be connected to the VB potential, VS potential, and Dr potential, respectively. Furthermore, the field plate may consist of at least two independent RFPs, and the number of RFPs is not particularly limited.

[0123] Furthermore, while the semiconductor device according to the first embodiment is exemplified as having a high-side circuit 102 for one phase on one chip, it is not limited to this, and a configuration having high-side circuits for multiple phases (for example, three phases) on one chip is also possible. The same applies to the semiconductor devices according to the second to tenth embodiments.

[0124] Furthermore, although the semiconductor device according to the first to tenth embodiments is exemplified as being HVIC, the method is also applicable to semiconductor devices other than HVIC.

[0125] Furthermore, the configurations disclosed in each of the first to tenth embodiments can be combined as appropriate, provided that they do not create any contradictions. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of Symbols]

[0126] 1...Base 1a... Semiconductor substrate 1b…Epitaxial layer 2... Well area 2a... Contact area 3…Pressure resistance range 4… Contact area 5... Well area 5a... Contact area 6a, 6b... Slit regions 8…Pressure resistance range 9…Buried layer 10...Resistance part 10a,10b...end 10c…Boundary position 10x…Low resistance part 10y...High resistance part 11,12… Resistant field plate 11a, 11b, 12a, 12b...ends 20a, 20b... Level Shifter 21a, 21b… Source area 22a, 22b… Grid gate 23a, 23b... Drain region 25…Gate insulating film 31…Source electrode 31a... Beer 32...Drain electrode 32a... Beer 33…VS electrode 33a... Beer 34…VB electrode 34a... Beer 35...GND electrode 35a... Beer 40… Resistive field plate 40a,40b...end 40°C...partial pressure point 50-53...Connection part 50a, 50b, 51a, 51b... Beer 60… Resistive field plate 60a, 60b... Ends 71, 72… insulating film 81, 82… Resistant field plate 81a, 81b, 82a, 82b... Ends 101... Low-side circuit 102... High-side circuit 103,104…Power supply 105...Connection point 111... Level shift circuit 113... Voltage divider resistor 200... Power conversion unit 400...Support board 401… Insulating film D0, D1, D2... Diodes IN…Input signal R1, R2... Level shift resistors R3,R4,R7…Resistance T1, T2... Level Shifter T3... High-potential switching element T4... Low-voltage switching element d1,d2…distance

Claims

1. A first-type conductive substrate and A first well region of a second conductivity type is provided on the upper surface side of the substrate, where a high-side circuit is formed, A pressure-resistant structure is provided so as to surround the first well region, A level shifter provided in the pressure-resistant structure, A first and second resistive field plate are provided above the pressure-resistant structure via an insulating film, with one end of each plate electrically connected to a different semiconductor region electrically connected to the high-side circuit. A semiconductor device equipped with a semiconductor device.

2. One end of the first resistive field plate is electrically connected to the first well region. The semiconductor device according to claim 1.

3. The first well region further comprises a second well region of a first conductivity type provided on the upper surface side of the first well region, One end of the second resistive field plate is electrically connected to the second well region. The semiconductor device according to claim 1 or 2.

4. The level shifter has a carrier receiving region, The first resistive field plate is located closer to the carrier receiving region than the second resistive field plate. The semiconductor device according to claim 1 or 2.

5. The first resistant field plate has a spiral or meandering planar pattern surrounding the first well region. The semiconductor device according to claim 4.

6. The first resistance field plate has a meandering planar pattern that traverses the pressure-resistant structure. The semiconductor device according to claim 4.

7. The first resistive field plate has a first resistive portion on one end of the first resistive field plate and a second resistive portion on the other end of the first resistive field plate that has a higher resistance than the first resistive portion. The first resistor is located closer to the carrier receiving region than the second resistor. The semiconductor device according to claim 4.

8. The second resistive field plate constitutes a voltage divider resistor and detects the potential of the high-side circuit. The semiconductor device according to claim 1 or 2.

9. The second resistance field plate has a meandering planar pattern that traverses the pressure-resistant structure. The semiconductor device according to claim 8.

10. The first resistant field plate has a spiral planar pattern surrounding the first well region, The first resistive portion has a resistive portion in the same layer as the second resistive field plate and a connecting portion in a layer above the resistive portion. The second resistive field plate is provided below the connection portion. The semiconductor device according to claim 9.

11. The first resistant field plate has a meandering planar pattern surrounding the first well region, The second resistive field plate is provided between the folded portions of the first resistive field plate. The semiconductor device according to claim 9.

12. The pressure-resistant structure has a first conductivity type slit region provided so as to surround the level shifter. The semiconductor device according to claim 1 or 2.

13. The first resistive field plate is provided above the region enclosed by the slit region. The semiconductor device according to claim 12.

14. A portion of the second resistive field plate is provided above the slit region. The semiconductor device according to claim 12.

15. The second resistant field plate has a spiral or meandering planar pattern surrounding the first well region. The semiconductor device according to claim 14.

16. The second resistance field plate has a meandering planar pattern that traverses the pressure-resistant structure. The semiconductor device according to claim 14.

17. The facility further comprises a third resistive field plate, provided above the pressure-resistant structure via an insulating film, with one end electrically connected to a semiconductor region electrically connected to the high-side circuit. The semiconductor device according to claim 1 or 2.

18. One end of each of the first and second resistive field plates is on the high-potential side, and the other end of each of the first and second resistive field plates is on the low-potential side. The semiconductor device according to claim 1 or 2.

19. The potential connected to one end of the first resistive field plate is higher than the potential connected to one end of the second resistive field plate. The semiconductor device according to claim 1 or 2.

20. The pressure-resistant structure has a second conductivity type pressure-resistant region that surrounds the first well region and is in contact with the first well region. The semiconductor device according to claim 1 or 2.

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