Semiconductor equipment

Abstract

To improve yield. [Solution] According to the embodiment, the semiconductor device includes a first chip 10 and a second chip 20. The first chip includes a first wiring layer M1 extending in a first direction and a first electrode 108 including a first contact plug VB and a first pad MB provided on the first wiring layer. The second chip includes a second wiring layer D2 extending in a second direction intersecting the first direction and a second electrode 210 including a second contact plug CB provided on the second wiring layer and a second pad DB bonded to the first pad. The length of the first contact plug in the first direction is longer than the length of the first contact plug in the second direction. The length of the second contact plug in the second direction is longer than the length of the second contact plug in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] As one type of semiconductor device, a NAND type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, a semiconductor device capable of improving the yield is provided.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first chip and a second chip. The first chip includes a first wiring layer extending in a first direction, and a first electrode including a first contact plug provided on the first wiring layer and a first pad provided on the first contact plug. The second chip includes a second wiring layer extending in a second direction intersecting the first direction, and a second electrode including a second contact plug provided on the second wiring layer and a second pad provided on the second contact plug and bonded to the first pad. The length in the first direction of the upper surface of the first contact plug is longer than the length in the second direction of the upper surface of the first contact plug. The length in the second direction of the upper surface of the second contact plug is longer than the length in the first direction of the upper surface of the second contact plug.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing the overall configuration of the semiconductor device according to the first embodiment. [Figure 2] Circuit diagram of a memory cell array included in a semiconductor device according to the first embodiment. [Figure 3] A perspective view showing an overview of the bonding structure of a semiconductor device according to the first embodiment. [Figure 4] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor device according to the first embodiment. [Figure 5] A cross-sectional view showing an example of the cross-sectional structure of a semiconductor device along the IV-IV line in Figure 4. [Figure 6] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a semiconductor device according to the first embodiment. [Figure 7] Cross-sectional view along line VV in Figure 6. [Figure 8] A perspective view showing an example of the structure of the M1 wiring layer, electrodes 108 and 210, and D2 wiring layer included in the semiconductor device according to the first embodiment. [Figure 9] A diagram showing an example of the planes of the electrode 108 and the M1 wiring layer, as well as the plane of the insulating layer 127, included in the semiconductor device according to the first embodiment. [Figure 10] A diagram showing an example of the planes of the electrode 210 and D2 wiring layer, and the insulating layer 214, included in the semiconductor device according to the first embodiment. [Figure 11] Cross-sectional views along the line VI-VI in Figures 9 and 10. [Figure 12] Cross-sectional views along line VII-VII in Figures 9 and 10. [Figure 13] This figure shows an example of the positional relationship between the opening region of the insulating layer 214 included in the semiconductor device according to the first embodiment and the electrode 210 (bonding pad DB). [Figure 14] This diagram shows the bonding of wafer WF1, on which multiple array chips are formed, and wafer WF2, on which multiple circuit chips are formed. [Figure 15] A schematic perspective view showing the warpage of wafer WF1 on which multiple array chips are formed. [Figure 16]A diagram schematically showing the misalignment direction of array chips in wafer WF1. [Figure 17] In the semiconductor device according to the first embodiment, a plan view of the M1 wiring layer and the electrode 108 showing an example of the misalignment correction of the electrode 108 corresponding to the misalignment in the X direction. [Figure 18] In the semiconductor device according to the first embodiment, a plan view of the D2 wiring layer and the electrode 210 showing an example of the misalignment correction of the electrode 210 corresponding to the misalignment in the Y direction. [Figure 19] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the first embodiment. [Figure 20] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the first embodiment. [Figure 21] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the first embodiment. [Figure 22] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the first embodiment. [Figure 23] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the first embodiment. [Figure 24] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the first embodiment. [Figure 25] A diagram showing an example of the plan view of the electrode 108 and the M1 wiring layer and the plan view of the insulating layer 127 included in the semiconductor device according to the second embodiment. [Figure 26] A diagram showing an example of the plan view of the electrode 210 and the D2 wiring layer and the plan view of the insulating layer 214 included in the semiconductor device according to the second embodiment. [Figure 27] A cross-sectional view taken along line VI-VI of FIGS. 25 and 26. [Figure 28] A cross-sectional view taken along line VII-VII of FIGS. 25 and 26. [Figure 29] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the second embodiment. [Figure 30] A diagram showing the manufacturing process of the electrode 210 included in the semiconductor device according to the second embodiment. [Figure 31]A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the second embodiment. [Figure 32] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the second embodiment. [Figure 33] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the second embodiment. [Figure 34] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the second embodiment. [Figure 35] A cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the third embodiment. [Figure 36] A perspective view showing an example of the structure of the M1 wiring layer, electrodes 108 and 210, and D2 wiring layer included in the semiconductor device according to the third embodiment. [Figure 37] A diagram showing an example of the planar configuration of the electrode 108 and the M1 wiring layer included in the semiconductor device according to the third embodiment. [Figure 38] A diagram showing an example of the planar configuration of the electrode 210 and the D2 wiring layer included in the semiconductor device according to the third embodiment. [Figure 39] Cross-sectional views along the line VI-VI in Figures 37 and 38. [Figure 40] Cross-sectional views along line VII-VII in Figures 37 and 38. [Figure 41] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the third embodiment. [Figure 42] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the third embodiment. [Figure 43] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the third embodiment. [Figure 44] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the third embodiment. [Figure 45] A diagram showing the manufacturing process of an electrode 210 included in a semiconductor device according to the third embodiment. [Figure 46] A cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the fourth embodiment. [Figure 47]A perspective view showing an example of the structure of the M1 wiring layer, electrodes 108 and 210, and D2 wiring layer included in the semiconductor device according to the fourth embodiment. [Figure 48] A diagram showing an example of the planar configuration of the electrode 108 and the M1 wiring layer included in the semiconductor device according to the fourth embodiment. [Figure 49] A diagram showing an example of the planar configuration of the electrode 210 and the D2 wiring layer included in the semiconductor device according to the fourth embodiment. [Figure 50] Cross-sectional views along the line VI-VI in Figures 48 and 49. [Figure 51] Cross-sectional views along line VII-VII in Figures 48 and 49. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be given a common reference numeral. When multiple components having a common reference numeral need to be distinguished, a subscript will be added to the common reference numeral to distinguish them. When there is no particular need to distinguish between multiple components, only the common reference numeral will be assigned to those components, and no subscript will be added. Here, the subscript is not limited to subscripts or superscripts, but also includes, for example, lowercase alphabet letters added to the end of the reference numeral, and indices indicating arrangement.

[0008] 1. First Embodiment A semiconductor device according to the first embodiment will be described below. In the following description, a three-dimensional stacked NAND flash memory formed by bonding multiple chips together will be used as an example of the semiconductor device. However, the semiconductor device is not limited to a NAND flash memory. This embodiment can be applied to any semiconductor device having a bonded structure formed by bonding multiple chips together.

[0009] 1.1 Configuration 1.1.1 Overall configuration of semiconductor device First, an example of the overall configuration of semiconductor device 1 will be described with reference to Figure 1. Figure 1 is a block diagram showing the overall configuration of semiconductor device 1. Note that in Figure 1, some of the connections between each component are shown by arrow lines, but the connections between components are not limited to these.

[0010] The semiconductor device 1 is, for example, a three-dimensional stacked NAND flash memory. The three-dimensional stacked NAND flash memory includes a plurality of non-volatile memory cell transistors arranged three-dimensionally on a semiconductor substrate.

[0011] As shown in Figure 1, the semiconductor device 1 includes an array chip 10 and a circuit chip 20.

[0012] The array chip 10 is a chip on which a memory cell array 11 including non-volatile memory cell transistors is provided. The circuit chip 20 is a chip on which a circuit for controlling the array chip 10 is provided. The semiconductor device 1 of this embodiment has a structure in which the array chip 10 and the circuit chip 20 are bonded together (hereinafter referred to as the "bonded structure"). Hereinafter, unless limited to either the array chip 10 or the circuit chip 20, it will simply be referred to as "chip". The semiconductor device 1 may include a plurality of array chips 10 or a plurality of circuit chips 20.

[0013] The array chip 10 includes one or more memory cell arrays 11. The memory cell array 11 is a region in which non-volatile memory cell transistors (hereinafter also referred to as "memory cells") are arranged in three dimensions. In the example shown in Figure 1, the array chip 10 includes one memory cell array 11.

[0014] The circuit chip 20 includes a sequencer 21, a voltage generation circuit 22, a low decoder 23, and a sense amplifier 24.

[0015] The PLC 21 is the control circuit of the semiconductor device 1. For example, the PLC 21 is connected to the voltage generation circuit 22, the row decoder 23, and the sense amplifier 24. The PLC 21 controls the voltage generation circuit 22, the row decoder 23, and the sense amplifier 24. The PLC 21 also controls the overall operation of the semiconductor device 1 based on the control of an external controller. More specifically, the PLC 21 performs write operations, read operations, erase operations, etc.

[0016] The voltage generation circuit 22 is a circuit that generates voltages used for writing, reading, and erasing operations. For example, the voltage generation circuit 22 is connected to the row decoder 23 and the sense amplifier 24. The voltage generation circuit 22 supplies the generated voltage to the row decoder 23 and the sense amplifier 24, etc.

[0017] The row decoder 23 is a circuit that decodes row addresses. A row address is an address signal that specifies the row-direction wiring of the memory cell array 11. Based on the decoding result of the row address, the row decoder 23 supplies the voltage applied from the voltage generation circuit 22 to the memory cell array 11.

[0018] The sense amplifier 24 is a circuit that performs data writing and reading. During a read operation, the sense amplifier 24 senses the data read from the memory cell array 11. During a write operation, the sense amplifier 24 supplies a voltage to the memory cell array 11 corresponding to the data to be written.

[0019] Next, the internal structure of the memory cell array 11 will be described. The memory cell array 11 has multiple block BLKs. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased all at once. The multiple memory cell transistors within a block BLK are mapped to rows and columns. In the example shown in Figure 1, the memory cell array 11 includes blocks BLK0, BLK1, BLK2, and BLK3.

[0020] A block BLK contains multiple string units SU. A string unit SU is a collection of multiple NAND strings that are selected together, for example, during a write or read operation. A NAND string contains a collection of multiple memory cell transistors connected in series. In the example shown in Figure 1, each block BLK contains five string units SU0 to SU4. The number of block BLKs in the memory cell array 11 and the number of string units SU within each block BLK are arbitrary.

[0021] 1.1.2 Circuit configuration of memory cell array Next, an example of the circuit configuration of the memory cell array 11 will be described with reference to Figure 2. Figure 2 is a circuit diagram of the memory cell array 11. Note that the example shown in Figure 2 shows the circuit configuration of one block BLK.

[0022] As shown in Figure 2, the string unit SU includes multiple NAND strings NS.

[0023] The NAND string NS includes multiple memory cell transistors MC and selection transistors ST1 and ST2. In the example shown in Figure 2, the NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0024] A memory cell transistor (MC) is a memory element that stores data non-volatilely. The MC includes a control gate and a charge storage film. The MC may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or the FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage film. The FG type uses a conductor for the charge storage film. The following description will focus on the case where the memory cell transistor (MC) is of the MONOS type.

[0025] The selection transistors ST1 and ST2 are switching elements. They are used to select the string unit SU during various operations. The number of selection transistors ST1 and ST2 in the NAND string NS is arbitrary; it is sufficient to have at least one ST1 and one ST2 in the NAND string NS.

[0026] The current paths of the selection transistor ST2, memory cell transistors MC0~MC7, and selection transistor ST1 within the NAND string NS are connected in series. The drain of selection transistor ST1 is connected to the bit line BL. The source of selection transistor ST2 is connected to the source line SL.

[0027] The control gates of memory cell transistors MC0 to MC7 within the same block BLK are connected in common to word lines WL0 to WL7. More specifically, for example, block BLK contains five string units SU0 to SU4, and each string unit SU contains multiple memory cell transistors MC0. The control gates of multiple memory cell transistors MC0 within block BLK are connected in common to a single word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0028] The gates of multiple selection transistors ST1 within a string unit SU are connected in common to a single selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 within a string unit SU0 are connected in common to selection gate line SGD0. The gates of multiple selection transistors ST1 within a string unit SU1 are connected in common to selection gate line SGD1. The gates of multiple selection transistors ST1 within a string unit SU2 are connected in common to selection gate line SGD2. The gates of multiple selection transistors ST1 within a string unit SU3 are connected in common to selection gate line SGD3. The gates of multiple selection transistors ST1 within a string unit SU4 are connected in common to selection gate line SGD4.

[0029] The gates of multiple selection transistors ST2 within block BLK are connected in common to the selection gate line SGS. Note that, similar to the selection gate line SGD, a different selection gate line SGS may be provided for each string unit SU.

[0030] Word lines WL0 to WL7, selection gate lines SGD0 to SGD4, and selection gate line SGS are connected to the row decoder 23, respectively.

[0031] Each bit line BL is connected in common to one NAND string NS within each string unit SU of each block BLK. Multiple NAND strings NS connected to a single bit line BL are assigned the same column address. Each bit line BL is connected to the sense amplifier 24.

[0032] Source lines SL are shared, for example, between multiple block lines BLK.

[0033] A collection of multiple memory cell transistors MC connected to a common word line WL within a single string unit SU is denoted, for example, as a "cell unit CU". For example, write and read operations are performed on a cell unit CU basis.

[0034] 1.1.3 Bonding structure of semiconductor device Next, an overview of the bonding structure of the semiconductor device 1 will be described with reference to Figure 3. Figure 3 is a perspective view showing an overview of the bonding structure of the semiconductor device 1.

[0035] As shown in Figure 3, the array chip 10 includes a plurality of bonding pads MB provided on the surface facing the circuit chip 20. The circuit chip 20 also includes a plurality of bonding pads DB provided on the surface facing the array chip 10 so as to face the bonding pads MB. In the bonding structure, the bonding pads MB of the array chip 10 and the bonding pads DB of the circuit chip 20 are bonded together to form a single bonding pad BP. In other words, the electrodes (conductors) constituting the bonding pads MB provided on the array chip 10 and the electrodes (conductors) constituting the bonding pads DB provided on the circuit chip 20 are bonded together to form a bonding pad BP.

[0036] In the following, the surface on which the array chip 10 and the circuit chip 20 are bonded together (hereinafter referred to as the "bonding surface") is defined as the XY plane. The directions that are orthogonal to each other in the XY plane are defined as the X direction and the Y direction. The direction that is approximately perpendicular to the XY plane and moves from the array chip 10 toward the circuit chip 20 is defined as the Z1 direction. The direction that is approximately perpendicular to the XY plane and moves from the circuit chip 20 toward the array chip 10 is defined as the Z2 direction. If neither the Z1 direction nor the Z2 direction is specified, it will be referred to as the Z direction. Furthermore, in the array chip 10, the Z1 direction is defined as "up" and the Z2 direction is defined as "down". Conversely, in the circuit chip 20, the Z2 direction is defined as "up" and the Z1 direction is defined as "down".

[0037] 1.1.4 Planar layout of memory cell array Next, an example of a planar layout of the memory cell array 11 will be described with reference to Figure 4. Figure 4 is a plan view showing an example of a planar layout of the memory cell array 11. The example shown in Figure 4 shows the regions corresponding to the four blocks BLK0 to BLK3 included in the memory cell array 11. Note that the interlayer insulating film is omitted in the example shown in Figure 4.

[0038] As shown in Figure 4, the memory cell array 11 includes a WL area WR1, a cell area CR, and a WL area WR2. Hereafter, unless it is specifically limited to either WL area WR1 or WR2, it will be referred to as "WL area WR".

[0039] The cell region CR is the area where the memory cell transistor MC is located.

[0040] The WL region WR is the connection region between the word line WL, the selection gate lines SGD and SGS, and the corresponding multiple contact plugs. WL regions WR1 and WR2 are provided at both ends of the cell region CR in the X direction, respectively. Note that the WL region WR may also be provided within the cell region CR. In the WL region WR, both ends of the word line WL and the selection gate lines SGD and SGS extending in the X direction are drawn out in a stepped manner. Note that in the WL region WR, the word line WL and the selection gate lines SGD and SGS do not necessarily have to be drawn out in a stepped manner. Even in this case, contact plugs that are electrically connected to the target wiring layer but not to other wiring layers can be formed.

[0041] Furthermore, the memory cell array 11 includes, for example, a plurality of slits SLT and a plurality of slits SHE.

[0042] The slit SLT extends in the X direction and crosses the WL region WR1, the cell region CR, and the WL region WR2. Multiple slit SLTs are aligned in the Y direction. The slit SLT has a structure in which an insulator is embedded, for example. The slit SLT may also include a conductor connected to the source line SL. The slit SLT separates adjacent wiring (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) through the slit SLT. In the memory cell array 11, each region separated by the slit SLT corresponds to one block BLK.

[0043] The slit SHE extends in the X direction and crosses the cell region CR. Multiple slit SHEs are aligned in the Y direction. In this embodiment, four slit SHEs are located between each of two adjacent slits SLT in the Y direction. Each slit SHE has a structure, for example, an embedded insulator. Each slit SHE separates adjacent wiring (at least the selected gate line SGD) through it. In the memory cell array 11, each region separated by the slits SLT and SHEs corresponds to one string unit SU.

[0044] The number of slits SHE placed between two adjacent slits SLT can be designed to be any number. The number of string units SU in each block BLK can be changed based on the number of slits SHE placed between two adjacent slits SLT.

[0045] 1.1.5 Cross-sectional structure of semiconductor device Next, an example of the cross-sectional structure of the semiconductor device 1 will be described with reference to Figure 5. Figure 5 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 along the line IV-IV in Figure 4. In the following, we will focus on the cross-section of the region in the array chip 10 where the memory cell array 11 is provided (hereinafter also referred to as the "memory cell array region"). Furthermore, we will focus on the WL region WR2 in the explanation, but the structure of the WL region WR1 is similar.

[0046] As shown in Figure 5, the semiconductor device 1 has a bonded structure in which an array chip 10 and a circuit chip 20 are bonded together.

[0047] The array chip 10 includes a semiconductor layer 101, a wiring layer 102, conductors 103 and 104, an M0 wiring layer 105, a conductor 106, an M1 wiring layer 107, an electrode 108, a conductor 109, insulating layers 121 to 128, and a memory pillar MP. Conductor 103 functions as a contact plug CH, conductor 104 functions as a contact plug VY, conductor 106 functions as a contact plug V0, electrode 108 functions as a contact plug VB and bonding pad MB, and conductor 109 functions as a contact plug CC. The number of wiring layers 102 and the multilayer wiring structure on the wiring layers 102 provided on the array chip 10 can be designed arbitrarily.

[0048] The circuit chip 20 includes a semiconductor substrate 201, a transistor TR, a gate insulating film 202, a gate electrode 203, a conductor 204, a D0 wiring layer 205, a conductor 206, a D1 wiring layer 207, a conductor 208, a D2 wiring layer 209, an electrode 210, and insulating layers 211 to 215. Conductor 204 functions as a contact plug CS. Conductor 206 functions as a contact plug C0. Conductor 208 functions as a contact plug C1. Electrode 210 functions as a contact plug CB and a bonding pad DB. The number of layers in the multilayer wiring structure provided on the circuit chip 20 can be designed arbitrarily.

[0049] 1.1.5.1 Cross-sectional structure of array chip Next, we will describe the cross-sectional structure of the array chip 10 with reference to Figure 5.

[0050] As shown in Figure 5, a semiconductor layer 101 is provided on the upper surface of the insulating layer 121 facing the Z1 direction. The semiconductor layer 101 is stretched in the X and Y directions. The semiconductor layer 101 in the memory cell array region functions as a source line SL. For example, the insulating layer 121 contains silicon oxide (SiO) as an insulating material. For example, the semiconductor layer 101 contains silicon.

[0051] In the cell region CR, multiple insulating layers 122 and multiple wiring layers 102 are alternately stacked one layer at a time on the upper surface of the semiconductor layer 101 facing the Z1 direction. In the example shown in Figure 5, 10 insulating layers 122 and 10 wiring layers 102 are alternately stacked one layer at a time. In other words, multiple wiring layers 102 are provided between the semiconductor layer 101 and the circuit chip 20, spaced apart in the Z direction. The wiring layers 102 and insulating layers 122 are stretched in the X direction. The insulating layer 122 contains, for example, silicon oxide. The wiring layer 102 contains, for example, tungsten (W) as a conductive material. In the example shown in Figure 5, the 10 wiring layers 102 function, in order from the side closest to the semiconductor layer 101, as a selectable gate line SGS, word lines WL0 to WL7, and a selectable gate line SGD.

[0052] In the WL region WR, multiple wiring layers 102 and multiple insulating layers 122 are drawn out in a stepped manner. The length of the multiple wiring layers 102 in the X direction gradually decreases from the semiconductor layer 101 side toward the circuit chip 20 side.

[0053] Multiple memory pillars MP are provided in the cell region CR. Each memory pillar MP corresponds to one NAND string NS. The memory pillar MP has, for example, a cylindrical shape extending in the Z direction. The memory pillar MP penetrates (passes through) multiple insulating layers 122 and multiple wiring layers 102. The Z2 end (bottom surface) of the memory pillar MP reaches into the semiconductor layer 101. Details of the structure of the memory pillar MP will be described later.

[0054] The insulating layer 123 is provided so as to cover the insulating layer 122, the wiring layer 102, and the memory pillar MP.

[0055] Multiple conductors 109 are provided in the WL region WR. The conductors 109 function as contact plugs CC. The conductors 109 have, for example, a cylindrical shape extending in the Z direction. The conductors 109 contain, for example, tungsten as a conductive material. The conductors 109 are connected to one of the wiring layers 102 and are not electrically connected to the other wiring layers 102. For example, the length of the conductor 109 in the Z direction varies depending on the wiring layer 102 to which it is connected. For example, the length of the multiple conductors 109 in the Z direction (plug height) is longest for the conductor 109 connected to the wiring layer 102 that functions as a selective gate line SGS, and shortest for the conductor 109 connected to the wiring layer 102 that functions as a selective gate line SGD.

[0056] A conductor 103, which functions as a contact plug CH, is provided on the upper surface of the memory pillar MP facing in the Z1 direction. The conductor 103 has, for example, a cylindrical shape extending in the Z direction. The conductor 103 contains, for example, tungsten as a conductive material.

[0057] A conductor 104, which functions as a contact plug VY, is provided on the upper surfaces of the conductor 103 in the cell region CR and the conductor 109 in the WL region WR, facing in the Z1 direction. The conductor 104 has, for example, a cylindrical shape extending in the Z direction. The conductor 104 contains, for example, tungsten as a conductive material.

[0058] An M0 wiring layer 105 is provided on the upper surface of the conductor 104 facing in the Z1 direction. For example, multiple M0 wiring layers 105 of a cell region CR are arranged in a line in the X direction, each extending in the Y direction. Each of the multiple memory pillars MP is electrically connected to one of the multiple M0 wiring layers 105 via a conductor 103 (contact plug CH) and a conductor 104 (contact plug VY). The M0 wiring layer 105 to which the memory pillar MP is connected functions as a bit line BL. The M0 wiring layer 105 contains, for example, copper (Cu) as a conductive material.

[0059] A conductor 106, which functions as a contact plug V0, is provided on the upper surface of the M0 wiring layer 105 facing in the Z1 direction. The conductor 106 has, for example, a cylindrical shape extending in the Z direction. The conductor 106 contains, for example, copper or tungsten as a conductive material.

[0060] An M1 wiring layer 107 is provided on the upper surface of the conductor 106 facing the Z1 direction. In this embodiment, at least a portion of the M1 wiring layer 107 extends in the X direction. An electrode 108 is connected to the portion of the M1 wiring layer 107 that extends in the X direction. The M1 wiring layer 107 contains, for example, copper as a conductive material. The conductor 106 and the M1 wiring layer 107 may be formed by the dual damascene method. In the case of the dual damascene method, the patterns of the conductor 106 (contact plug V0) and the M1 wiring layer 107 are processed separately. The conductor 106 and the M1 wiring layer 107 are then embedded together with a conductive material (for example, copper).

[0061] An insulating layer 124 is provided on the upper surface of the insulating layer 123 facing in the Z1 direction. The insulating layer 124 covers the conductors 103 and 104, the M0 wiring layer 105, the conductor 106, and the M1 wiring layer 107. For example, the insulating layer 124 contains silicon oxide.

[0062] An insulating layer 125 is provided on the upper surfaces of the insulating layer 124 and the M1 wiring layer 107 facing in the Z1 direction. The insulating layer 125 functions as a cap insulating layer (oxidation prevention layer) for the M1 wiring layer 107. The insulating layer 125 contains silicon (Si) and at least one of nitrogen or carbon. More specifically, the insulating layer 125 includes, for example, silicon nitride (SiN), silicon carbonitride (SiCN), or silicon carbide (SiC). For example, if the M1 wiring layer 107 is formed of a material that does not require an oxidation prevention layer, the insulating layer 125 may be omitted.

[0063] An insulating layer 126, made of a different material from insulating layer 125, is provided on the upper surface of insulating layer 125 facing in the Z1 direction. Insulating layer 126 contains, for example, silicon oxide.

[0064] An insulating layer 127 made of a different material from insulating layer 126 is provided on the upper surface of insulating layer 126 facing in the Z1 direction. Insulating layer 127 functions as an etching stopper VSP when forming electrode 108 by the dual damascene method. Insulating layer 127 includes, for example, silicon nitride (SiN), silicon carbonitride (SiCN), or silicon carbide (SiC). Insulating layer 127 can be any insulating material that provides a sufficient etching selectivity ratio with insulating layers 126 and 128 in the etching process of the dual damascene method.

[0065] An insulating layer 128, made of a different material from insulating layer 127, is provided on the upper surface of insulating layer 127 facing in the Z1 direction. Insulating layer 128 contains, for example, silicon oxide. The upper surface of insulating layer 128 facing in the Z1 direction and the upper surface of electrode 108 facing in the Z1 direction are flattened. The upper surface of insulating layer 128 is in contact with insulating layer 215 of circuit chip 20. The surface where insulating layer 128 and insulating layer 215 are in contact is the bonding surface BS.

[0066] An electrode 108 is provided on the upper surface of the M1 wiring layer 107 facing in the Z1 direction. The electrode 108 contains, for example, copper as a conductive material. The electrode 108 includes a bonding pad MB and a contact plug VB that connects the bonding pad MB and the M1 wiring layer 107. The contact plug VB is provided on the upper surface of the M1 wiring layer 107. The bonding pad MB is provided on the upper surface of the contact plug VB facing in the Z1 direction. The upper surface of the bonding pad MB facing in the Z1 direction is in contact with the bonding pad DB provided on the circuit chip 20 at the bonding surface BS.

[0067] The electrode 108 is formed, for example, by the dual damascene method. When the electrode 108 is formed by the dual damascene method, the insulating layer 127 functions as an etching stopper VSP for the bonded pad MB. By using the insulating layer 127, the controllability of the height between the bonded pad MB and the contact plug VB is improved. Details of the structure of the electrode 108 will be described later.

[0068] 1.1.5.2 Cross-sectional structure of a circuit chip Next, we will describe the cross-sectional structure of the circuit chip 20 with reference to Figure 5.

[0069] As shown in Figure 5, a plurality of transistors TR are provided on the upper surface of the semiconductor substrate 201 facing the Z2 direction. Each transistor TR includes a gate insulating film 202, a gate electrode 203, and a source and drain (not shown) formed on the semiconductor substrate 201. The gate insulating film 202 is provided on the upper surface of the semiconductor substrate 201. The gate electrode 203 is provided on the upper surface of the gate insulating film 202 facing the Z2 direction. For example, a row decoder 23 or a sense amplifier 24 can be formed by the plurality of transistors TR. The row decoder 23 is electrically connected to the wiring layer 102 of the array chip 10 via a bonding pad BP. The sense amplifier 24 is electrically connected to the memory pillar MP of the array chip 10 via a bonding pad BP.

[0070] A conductor 204, which functions as a contact plug CS, is provided on the gate electrode 203 and on the upper surface of the semiconductor substrate 201. The conductor 204 includes, for example, tungsten. The conductor 204 has, for example, a cylindrical shape extending in the Z direction.

[0071] A D0 wiring layer 205 is provided on the upper surface of the conductor 204 facing in the Z2 direction. The D0 wiring layer 205 contains, for example, tungsten as a conductive material.

[0072] A conductor 206, which functions as a contact plug C0, is provided on the upper surface of the D0 wiring layer 205 facing the Z2 direction. The conductor 206 contains, for example, tungsten or copper as a conductive material. The conductor 206 has, for example, a cylindrical shape extending in the Z direction.

[0073] A D1 wiring layer 207 is provided on the upper surface of the conductor 206 facing the Z2 direction. The D1 wiring layer 207 contains, for example, tungsten or copper as a conductive material. The D1 wiring layer 207 and the conductor 206 may be formed together by a dual damascene method.

[0074] A conductor 208, which functions as a contact plug C1, is provided on the upper surface of the D1 wiring layer 207 facing in the Z2 direction. The conductor 208 contains, for example, copper as a conductive material. The conductor 208 has, for example, a cylindrical shape extending in the Z direction.

[0075] A D2 wiring layer 209 is provided on the upper surface of the conductor 208 facing the Z2 direction. In this embodiment, at least a portion of the D2 wiring layer 209 extends in the Y direction. The portion of the D2 wiring layer 209 that extends in the Y direction is connected to the electrode 210. The D2 wiring layer 209 contains, for example, copper as a conductive material. The D2 wiring layer 209 and the conductor 208 may be formed together by a dual damascene method.

[0076] An insulating layer 211 is provided on the upper surface of the semiconductor substrate 201. The insulating layer 211 covers the transistor TR, conductor 204, D0 wiring layer 205, conductor 206, D1 wiring layer 207, conductor 208, and D2 wiring layer 209. The insulating layer 211 contains, for example, silicon oxide.

[0077] An insulating layer 212 is provided on the upper surfaces of the insulating layer 211 and the D2 wiring layer 209 facing in the Z2 direction. The insulating layer 212 functions as a cap insulating layer (oxidation prevention layer) for the D2 wiring layer 209. The insulating layer 212 includes, for example, silicon nitride (SiN), silicon carbonitride (SiCN), or silicon carbide (SiC).

[0078] An insulating layer 213 made of a different material from insulating layer 212 is provided on the upper surface of insulating layer 212 facing in the Z2 direction. Insulating layer 213 contains, for example, silicon oxide.

[0079] An insulating layer 214 made of a different material from insulating layer 213 is provided on the upper surface of insulating layer 213 facing in the Z2 direction. Insulating layer 214 functions as an etching stopper CSP when forming the electrode 210 by the dual damascene method. Insulating layer 214 includes, for example, silicon nitride (SiN), silicon carbonitride (SiCN), or silicon carbide (SiC). Insulating layer 214 can be any insulating material that provides a sufficient etching selectivity ratio with insulating layers 213 and 215 in the etching process of the dual damascene method.

[0080] An insulating layer 215 made of a different material from insulating layer 214 is provided on the upper surface of insulating layer 214 facing in the Z2 direction. The insulating layer 215 contains, for example, silicon oxide. The surface of insulating layer 215 facing in the Z2 direction and the surface of electrode 210 facing in the Z2 direction are flattened. The upper surface of insulating layer 215 facing in the Z2 direction is in contact with the insulating layer 128 of array chip 10.

[0081] An electrode 210 is provided on the upper surface of the D2 wiring layer 209. The electrode 210 contains, for example, copper as a conductive material. The electrode 210 includes a bonding pad DB and a contact plug CB that connects the bonding pad DB and the D2 wiring layer 209. The bonding pad DB is in contact with a bonding pad MB provided on the array chip 10 at the bonding surface BS.

[0082] The electrode 210 is formed, for example, by the dual damascene method. When the electrode 210 is formed by the dual damascene method, the insulating layer 214 functions as an etching stopper CSP for the bonded pad DB. By using the insulating layer 214, the controllability of the height between the bonded pad DB and the contact plug CB is improved. Details of the structure of the electrode 210 will be described later.

[0083] The number of layers in the multilayer wiring structure provided between the transistor TR and the electrode 210 is arbitrary.

[0084] 1.1.6 Cross-sectional structure of memory cell array Next, the cross-sectional structure of the memory cell array 11 will be described with reference to Figure 6. Figure 6 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 11. Figure 6 shows two memory pillars MP included in the memory cell array 11.

[0085] As shown in Figure 6, the semiconductor layer 101 includes, for example, three semiconductor layers 101a, 101b, and 101c. Semiconductor layer 101b is provided on the upper surface of semiconductor layer 101a facing the Z1 direction. Semiconductor layer 101c is provided on the upper surface of semiconductor layer 101b facing the Z1 direction. Semiconductor layer 101b is formed, for example, by replacing the sacrificial layer provided between semiconductor layer 101a and semiconductor layer 101c. Semiconductor layers 101a to 101c include, for example, silicon. Semiconductor layers 101a to 101c also include, for example, phosphorus (P) as a semiconductor impurity.

[0086] On the upper surface of the semiconductor layer 101 facing the Z1 direction, 10 layers of insulating layer 122 and 10 layers of wiring layer 102 are alternately stacked one layer at a time. In the example shown in Figure 6, the 10 layers of wiring layer 102 function as, in order from the side closest to the semiconductor layer 101, as a selectable gate line SGS, word lines WL0 to WL7, and selectable gate line SGD, respectively. Note that multiple wiring layers 102 functioning as selectable gate lines SGS and SGD may be provided. As the conductive material for the wiring layer 102, for example, a laminated structure of titanium nitride (TiN) / tungsten (W) can be used. In this case, the titanium nitride is formed to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of tungsten or as an adhesion layer to improve the adhesion of tungsten when forming a tungsten film by, for example, CVD (chemical vapor deposition). The wiring layer 102 may also contain a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed to cover the conductive material. For example, in each of the wiring layers 102, the high dielectric constant material is provided so as to be in contact with the insulating layer 122 provided above and below the wiring layer 102 and the side surface of the memory pillar MP. Titanium nitride is provided so as to be in contact with the high dielectric constant material. Tungsten is provided so as to be in contact with the titanium nitride and to fill the interior of the titanium nitride. For example, when aluminum oxide is provided as the high dielectric constant material, the memory cell transistor MC is also referred to as the MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type.

[0087] An insulating layer 123 is provided on the upper surface of the wiring layer 102, which functions as a select gate wire SGD, facing in the Z1 direction.

[0088] Multiple memory pillars MP are provided within the memory cell array 11. For example, the memory pillars MP have a substantially cylindrical shape extending in the Z direction. The memory pillars MP penetrate the 10 wiring layers 102. The bottom surface of the memory pillars MP reaches the semiconductor layer 101. The memory pillars MP may also have a structure in which multiple pillars are connected in the Z direction.

[0089] Next, the internal structure of the memory pillar MP will be described. The memory pillar MP includes a block insulating film 140, a charge storage film 141, a tunnel insulating film 142, a semiconductor film 143, a core film 144, and a cap film 145.

[0090] A block insulating film 140, a charge storage film 141, and a tunnel insulating film 142 are stacked on a portion of the side surface of the memory pillar MP and on the bottom surface facing the Z2 direction, in order from the outside. More specifically, the block insulating film 140, charge storage film 141, and tunnel insulating film 142 on the side surface of the memory pillar MP are removed in the same layer as and near the semiconductor layer 101b. A semiconductor film 143 is provided so as to be in contact with the side surface and bottom surface of the tunnel insulating film 142 and the semiconductor layer 101b. The semiconductor film 143 is the region where the channels of the memory cell transistor MC and the selection transistors ST1 and ST2 are formed. The interior of the semiconductor film 143 is filled with a core film 144. At the top of the memory pillar MP in the Z1 direction, a cap film 145 is provided on the upper ends of the semiconductor film 143 and the core film 144. The side surface of the cap film 145 is in contact with the tunnel insulating film 142. The cap film 145 contains, for example, silicon. A conductor 103 is provided on the surface of the cap film 145 facing the Z1 direction. A conductor 104 is provided on the surface of the conductor 103 facing the Z1 direction. The conductor 104 is connected to the M0 wiring layer 105 which functions as a bit line BL.

[0091] Memory cell transistors MC0 to MC7 are formed by combining memory pillar MP with wiring layer 102 that functions as word lines WL0 to WL7. Similarly, selection transistor ST1 is formed by combining memory pillar MP with wiring layer 102 that functions as a selection gate line SGD. Selection transistor ST2 is formed by combining memory pillar MP with wiring layer 102 that functions as a selection gate line SGS. Thus, each memory pillar MP can function as a single NAND string NS.

[0092] Refer to Figure 7 to see an example of the cross-sectional structure of the memory pillar MP along the XY plane. Figure 7 is a cross-sectional view along the VV line in Figure 6. More specifically, Figure 7 shows the cross-sectional structure of the memory pillar MP in a layer including the wiring layer 102.

[0093] In a cross-section including the wiring layer 102, the core film 144 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 143 surrounds the sides of the core film 144. The tunnel insulating film 142 surrounds the sides of the semiconductor film 143. The charge storage film 141 surrounds the sides of the tunnel insulating film 142. The block insulating film 140 surrounds the sides of the charge storage film 141. The wiring layer 102 surrounds the sides of the block insulating film 140.

[0094] The semiconductor film 143 is used as the channel (current path) for the memory cell transistors MC0 to MC7 and the selection transistors ST1 and ST2. The tunnel insulating film 142 and the block insulating film 140 each contain, for example, silicon oxide. The charge storage film 141 has the function of storing charge. The charge storage film 141 contains, for example, silicon nitride (SiN).

[0095] 1.1.7 Structure of adhesive pads Next, the structure of the bonded pad BP will be described with reference to Figures 8 to 12. Figure 8 is a perspective view showing an example of the structure of the M1 wiring layer 107, electrodes 108 and 210, and D2 wiring layer 209. Figure 9 is a diagram showing an example of the plan view of electrodes 108 and M1 wiring layer 107, and an example of the plan view of the insulating layer 127. Figure 10 is a diagram showing an example of the plan view of electrodes 210 and D2 wiring layer 209, and an example of the plan view of the insulating layer 214. Figure 11 is a cross-sectional view along the line VI-VI in Figures 9 and 10. Figure 12 is a cross-sectional view along the line VII-VII in Figures 9 and 10.

[0096] Note that the insulating layer is omitted in the perspective view of Figure 8, the plan view of electrode 108 and M1 wiring layer 107 in Figure 9, and the plan view of electrode 210 and D2 wiring layer 209 in Figure 10. Other conductors and insulating layers are omitted in the plan view of insulating layer 127 in Figure 9 and the plan view of insulating layer 214 in Figure 10. Also, in Figure 8, the contact surface between the bonded pad MB and bonded pad DB is shown with hatching to make it easier to see.

[0097] As shown in Figure 8, the M1 wiring layer 107 of the array chip 10 has a portion that extends in the X direction. An electrode 108 is provided on the upper surface of the portion of the M1 wiring layer 107 that extends in the X direction, facing in the Z1 direction. In other words, a contact plug VB is provided on the upper surface of the M1 wiring layer 107. Then, a bonding pad MB is provided on the upper surface of the contact plug VB, facing in the Z1 direction.

[0098] The length of the upper surface of the contact plug VB in the X direction is the same as the length of the lower surface of the adhesive pad MB facing the Z2 direction in the X direction. The side surface of the contact plug VB facing the X direction and the side surface of the adhesive pad MB facing the X direction are located on the same plane. Also, the length of the upper surface of the contact plug VB in the Y direction is shorter than the length of the lower surface of the adhesive pad MB in the Y direction.

[0099] The D2 wiring layer 209 of the circuit chip 20 has a portion that extends in the Y direction. An electrode 210 is provided on the upper surface of the portion of the D2 wiring layer 209 that extends in the Y direction, facing in the Z2 direction. In other words, a contact plug CB is provided on the upper surface of the D2 wiring layer 209. And a bonding pad DB is provided on the upper surface of the contact plug CB, facing in the Z2 direction.

[0100] The length of the upper surface of the contact plug CB in the Y direction is the same as the length of the lower surface of the adhesive pad DB facing the Z1 direction in the Y direction. The side surface of the contact plug CB facing the Y direction and the side surface of the adhesive pad MB facing the Y direction are located on the same plane. Also, the length of the upper surface of the contact plug CB in the X direction is shorter than the length of the lower surface of the adhesive pad DB in the X direction.

[0101] For example, if there is no misalignment between the bonding pad MB and the bonding pad DB, and the shapes of the bonding pads MB and DB on the bonding surface BS are both square and of the same size, then the entire upper surface of the bonding pad MB facing in the Z1 direction will be in contact with the entire upper surface of the bonding pad DB facing in the Z2 direction.

[0102] As shown in Figure 9, in a plan view from the Z direction, the M1 wiring layer 107, the contact plug VB, and a portion of the bonding pad MB overlap. The contact plug VB is provided on the upper surface of the M1 wiring layer 107. The bonding pad MB is provided on the upper surface of the contact plug VB. The shape of the bonding pad MB on the upper surface of the bonding pad MB, i.e., on the bonding surface BS, is, for example, approximately square. In this case, let Lmb be the length of one side of the upper surface of the bonding pad MB. Also, let Lm1y be the length in the Y direction of the upper surface of the M1 wiring layer 107, i.e., the wiring width. Length Lmb is longer than length Lm1y.

[0103] For example, the upper surface of the contact plug VB (the contact surface with the bonding pad MB) has a roughly rectangular shape that is longer in the X direction (the stretching direction of the M1 wiring layer 107). The length Lvbx of the upper surface of the contact plug VB in the X direction is the same as the length of the lower surface of the bonding pad MB in the X direction. Also, the length Lvby of the upper surface of the contact plug VB in the Y direction is shorter than the wiring width Lm1y of the M1 wiring layer 107.

[0104] In this embodiment, the contact plug VB and the bonding pad MB are formed (processed) together by a dual damascene method using an insulating layer 127, which functions as an etching stopper VSP, as a mask. By using the insulating layer 127 as a mask, the contact plug VB is processed to be self-aligned with the bonding pad MB.

[0105] For example, the opening region ROvsp of the insulating layer 127 includes regions Rm1, Rmb1, and Rmb2. Region Rm1 overlaps with the M1 wiring layer 107, the contact plug VB, and a portion of the bonding pad MB in a plan view from the Z direction. Regions Rmb1 and Rmb2 overlap with the bonding pad MB and do not overlap with the contact plug VB in a plan view from the Z direction. Regions Rmb1 and Rmb2 are provided adjacent to region Rm1 in the Y direction. Region Rm1 is provided between region Rmb1 and region Rmb2 in the Y direction. Region Rm1 corresponds to the contact plug VB. Region Rm1 is the region where the insulating layer 127 is removed when the insulating layer 127 is processed to form the mask pattern of the contact plug VB. Regions Rmb1 and Rmb2 are areas where the insulating layer 127 is removed when the insulating layers 125-128 are processed to form the hole pattern of the electrode 108.

[0106] Let Lvspx be the length of region Rm1 in the X direction and Lvspy be its length in the Y direction. Length Lvspx is longer than length Lmb. Both ends of region Rm1 in the X direction protrude in the X direction from both ends of the bonded pad MB in the X direction, respectively, when viewed from the Z direction in a plan view. In other words, both ends of region Rm1 in the X direction protrude in the X direction from both ends of region Rmb1 and region Rmb2 in the X direction, respectively. At the X-direction ends of region Rm1 (i.e., the protruding portions), the insulating layer 127 is not in contact with the bonded pad MB. In contrast, in regions Rmb1 and Rmb2, the insulating layer 127 is in contact with the bonded pad MB. For example, it is preferable that the difference between length Lvspx and length Lmb is greater than or equal to the amount of alignment deviation between the photolithography corresponding to the processing of region Rm1 of the insulating layer 127 and the photolithography corresponding to the processing of the electrode 108. As a result, even if an alignment misalignment occurs between the Rm1 region of the opening region ROvsp and the electrode 108 (bonded pad MB), the length of the contact plug VB in the X direction, formed by self-alignment, remains unchanged. The length Lvbx of the upper surface of the contact plug VB in the X direction is approximately the same as the length Lmb of the upper surface of the bonded pad MB. "Approximately the same" means that errors due to the processing shape of the dual damascene, such as a tapered shape, may be included.

[0107] The length Lvspy of region Rm1 is shorter than the wiring width Lm1y of the M1 wiring layer 107. Also, the length Lvspy is approximately the same as the length Lvby of the upper surface of the contact plug VB in the Y direction. For example, it is preferable that the length Lvspy be less than or equal to the length obtained by subtracting the photolithography alignment margin (e.g., 200 nm) corresponding to the processing of the insulating layer 127 from the wiring width Lm1y of the M1 wiring layer 107. This prevents the contact plug VB from deviating from the M1 wiring layer 107 in the Y direction when viewed from the Z direction in a plan view.

[0108] In this embodiment, in order to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB, the arrangement of the opening region ROvsp of the insulating layer 127 and the electrode 108 can be shifted in the X direction relative to the M1 wiring layer 107 which extends in the X direction. By shifting the opening region ROvsp of the insulating layer 127 and the electrode 108 in the X direction, the X-direction misalignment between the bonded pad MB and the bonded pad DB can be corrected.

[0109] As shown in Figure 10, in a plan view from the Z direction, the D2 wiring layer 209, the contact plug CB, and the bonding pad DB overlap. The contact plug CB is provided on the upper surface of the D2 wiring layer 209. The bonding pad DB is provided on the upper surface of the contact plug CB. The shape of the top surface of the bonding pad DB, i.e., the bonding surface BS, is, for example, approximately square. In this case, the length of one side of the top surface of the bonding pad DB is Ldb. Also, the length in the X direction of the top surface of the D2 wiring layer 209, i.e., the wiring width, is Ld2x. The length Ldb is longer than the wiring width Ld2x.

[0110] For example, the upper surface of the contact plug CB (the contact surface with the bonding pad DB) has a roughly rectangular shape that is longer in the Y direction (the direction of extension of the D2 wiring layer 209). The length Lcby of the upper surface of the contact plug CB in the Y direction is the same as the length Lcby of the lower surface of the bonding pad DB in the Y direction. Also, the length Lcbx of the upper surface of the contact plug CB in the X direction is shorter than the wiring width Ld2x of the D2 wiring layer 209.

[0111] In this embodiment, the contact plug CB and the bonding pad DB are formed (processed) together by a dual damascene method using an insulating layer 214, which functions as an etching stopper CSP, as a mask. By using the insulating layer 214 as a mask, the contact plug CB is processed to be self-aligned with the bonding pad DB.

[0112] For example, the opening region ROcsp of the insulating layer 214 includes regions Rd2, Rdb1, and Rdb2. Region Rd2 overlaps with the D2 wiring layer 209, the contact plug CB, and part of the bonding pad DB in a plan view from the Z direction. Regions Rdb1 and Rdb2 overlap with the bonding pad DB and do not overlap with the contact plug CB in a plan view from the Z direction. Regions Rdb1 and Rdb2 are provided adjacent to region Rd2 in the X direction. Region Rd2 is provided between region Rdb1 and region Rdb2 in the X direction. Region Rd2 corresponds to the contact plug CB. Region Rd2 is the region where the insulating layer 214 is removed when the insulating layer 214 is processed to form the mask pattern of the contact plug CB. Regions Rdb1 and Rdb2 are the regions where the insulating layer 214 is removed when the insulating layers 212 to 215 are processed to form the hole pattern of the electrode 210.

[0113] Let Lcspx be the length of region Rd2 in the X direction, and Lcspy be its length in the Y direction. Length Lcspy is longer than length Ldb. In a plan view from the Z direction, both ends of region Rd2 in the Y direction protrude in the Y direction from both ends of the bonded pad DB. In other words, both ends of region Rd2 in the Y direction protrude in the Y direction from both ends of region Rdb1 and region Rdb2. At the Y-direction ends of region Rd2 (i.e., the protruding portions), the insulating layer 214 is not in contact with the bonded pad DB. In contrast, in regions Rdb1 and Rdb2, the insulating layer 214 is in contact with the bonded pad DB. For example, it is preferable that the difference between length Lcspy and length Ldb is greater than or equal to the amount of alignment deviation between the photolithography corresponding to the processing of region Rd2 of the insulating layer 214 and the photolithography corresponding to the processing of the electrode 210. As a result, even if an alignment misalignment occurs between region Rd2 of the opening region ROcsp and electrode 210 (bonded pad DB), the Y-direction length of the contact plug CB formed by self-alignment remains unchanged. The Y-direction length Lcby of the upper surface of the contact plug CB is approximately the same as the length Ldb of the bonded pad DB.

[0114] The length Lcspx of region Rd2 is shorter than the wiring width Ld2x of the D2 wiring layer 209. Also, the length Lcspx is approximately the same as the length Lcbx in the X direction of the upper surface of the contact plug CB. For example, it is preferable that the length Lcspx be less than or equal to the length obtained by subtracting the photolithography alignment margin (e.g., 200 nm) corresponding to the processing of the insulating layer 214 from the wiring width Ld2x of the D2 wiring layer 209. This prevents the contact plug CB from deviating from the D2 wiring layer 209 in the X direction when viewed from the Z direction in a plan view.

[0115] In this embodiment, in order to correct the misalignment in the Y direction between the bonded pad MB and the bonded pad DB, the arrangement of the opening region ROcsp of the insulating layer 214 and the electrode 210 can be shifted in the Y direction relative to the D2 wiring layer 209 which extends in the Y direction. By shifting the opening region ROcsp of the insulating layer 214 and the electrode 210 in the Y direction, the misalignment in the Y direction between the bonded pad MB and the bonded pad DB can be corrected.

[0116] Furthermore, the M1 wiring layer 107 may be extended in the Y direction, and the D2 wiring layer 209 may be extended in the X direction. In this case, the opening region ROvsp and electrode 108 are shifted in the Y direction, and the opening region ROcsp and electrode 210 are shifted in the X direction. This corrects the misalignment between the bonded pad MB and the bonded pad DB.

[0117] Next, the cross-sectional shapes of the adhesive pads MB and DB will be described.

[0118] As shown in Figures 11 and 12, the M1 wiring layer 107 includes a barrier metal 107_1 and a conductor 107_2. The barrier metal 107_1 functions as an oxidation prevention layer, a diffusion prevention layer, and an adhesion layer for the conductor 107_2. The barrier metal 107_1 is formed to cover the side surface and the bottom surface facing the Z2 direction of the M1 wiring layer 107. The barrier metal 107_1 is in contact with the insulating layer 124. The conductor 107_2 is provided within the barrier metal 107_1 in contact with the barrier metal 107_1. The conductor 107_2 is embedded within the barrier metal 107_1 so as to form the core portion of the M1 wiring layer 107. The barrier metal 107_1 includes, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier metal 107_1 may be a laminate of these materials. The conductor 107_2 includes, for example, copper as a conductive material.

[0119] The electrode 108 has a bonding pad MB and a contact plug VB.

[0120] As shown in Figure 11, for example, the cross-section of electrode 108 in the X direction has a trapezoidal shape in which the length Lmb in the X direction of the upper surface of electrode 108 facing the Z1 direction (upper surface of the bonding pad MB) is longer than the length in the X direction of the lower surface facing the Z2 direction (lower surface of the contact plug VB) that is in contact with the M1 wiring layer 107. The side surface of electrode 108 facing the X direction has a tapered shape. The side surfaces of the bonding pad MB and the contact plug VB facing the X direction are aligned in a straight line. The length Lvbx in the X direction of the upper surface of contact plug VB is the same as the length in the X direction of the lower surface of the bonding pad MB.

[0121] As shown in Figure 12, for example, in the cross-section of electrode 108 in the Y direction, a trapezoidal contact plug VB smaller than the adhesive pad MB is provided so as to be connected to the adhesive pad MB in the Z2 direction relative to the adhesive pad MB, which has a trapezoidal shape. The sides of the adhesive pad MB and the contact plug VB each have a tapered shape. The sides of the adhesive pad MB and the contact plug VB facing in the Y direction are not connected in a straight line. The length Lmb in the Y direction of the upper surface of the adhesive pad MB is longer than the length in the Y direction of the lower surface that is in contact with the contact plug VB. The length Lvby in the Y direction of the upper surface of the contact plug VB is shorter than the length in the Y direction of the lower surface of the adhesive pad MB and longer than the length in the Y direction of the lower surface that is in contact with the M1 wiring layer 107 of the contact plug VB.

[0122] As shown in Figures 11 and 12, the adhesive pad MB is provided in the same layer as the insulating layers 127 and 128. The lower surface of the adhesive pad MB reaches the insulating layer 126. The contact plug VB is provided within the insulating layers 125 and 126. That is, the adhesive pad MB and the contact plug VB are in contact in the same layer as the insulating layer 126. The lower surface of the contact plug VB reaches the M1 wiring layer 107.

[0123] The X-shaped side of electrode 108 is not in contact with the insulating layer 127 located at the X-direction end of region Rm1. However, the X-shaped side of electrode 108 is in contact with the insulating layer 127 located at the X-direction ends of regions Rmb1 and Rmb2. The Y-shaped side of electrode 108 is in contact with the insulating layer 127.

[0124] The electrode 108 includes a barrier metal (conductor) 108_1 and a conductor 108_2. The barrier metal 108_1 functions as an oxidation prevention layer, a diffusion prevention layer, and an adhesion layer for the conductor 108_2. The barrier metal 108_1 is formed to cover the side and bottom surfaces of the electrode 108. The barrier metal 108_1 is in contact with the M1 wiring layer 107 and the insulating layers 125-128. The conductor 108_2 is provided within the barrier metal 108_1 in contact with it. The conductor 108_2 is embedded within the barrier metal 108_1 to form the core portion of the electrode 108 (bonding pad MB and contact plug VB). The barrier metal 108_1 includes, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier metal 108_1 may be a laminated film of these materials. The conductor 108_2 includes, for example, copper as a conductive material.

[0125] The electrode 210 has a bonding pad DB and a contact plug CB.

[0126] As shown in Figure 11, for example, in the cross-section of electrode 210 in the X direction, a trapezoidal contact plug CB smaller than the adhesive pad DB is provided so as to be connected to the adhesive pad DB in the Z1 direction relative to the adhesive pad DB, which has a trapezoidal shape. The sides of the adhesive pad DB and the contact plug CB each have a tapered shape. The sides of the adhesive pad DB and the contact plug CB facing the X direction are not connected in a straight line. The length Ldb in the X direction of the upper surface of the adhesive pad DB is longer than the length in the X direction of the lower surface that contacts the contact plug CB. The length in the X direction of the upper surface of the contact plug CB is shorter than the length in the X direction of the lower surface of the adhesive pad DB, and longer than the length in the X direction of the lower surface that contacts the D2 wiring layer 209 of the contact plug CB.

[0127] As shown in Figure 12, for example, the cross-section of the electrode 210 in the Y direction has a trapezoidal shape in which the length Ldb in the Y direction of the upper surface of the electrode 210 facing the Z2 direction (upper surface of the bonding pad DB) is longer than the length in the Y direction of the lower surface facing the Z1 direction (lower surface of the contact plug CB) that is in contact with the D2 wiring layer 209. The side surface of the electrode 210 facing the Y direction has a tapered shape. The side surfaces of the bonding pad DB and the contact plug CB facing the Y direction are aligned in a straight line. The length Lcby in the Y direction of the upper surface of the contact plug CB is the same as the length in the Y direction of the lower surface of the bonding pad DB.

[0128] As shown in Figures 11 and 12, the adhesive pad DB is provided in the same layer as the insulating layers 214 and 215. The lower surface of the adhesive pad DB reaches the insulating layer 213. The contact plug CB is provided within the insulating layers 212 and 213. That is, the adhesive pad DB and the contact plug CB are in contact in the same layer as the insulating layer 213. The lower surface of the contact plug CB reaches the D2 wiring layer 209.

[0129] The side of electrode 210 facing the X direction is in contact with the insulating layer 214. The side of electrode 210 facing the Y direction is not in contact with the insulating layer 214 located at the Y-direction end of region Rd2. However, the side of electrode 210 facing the Y direction is in contact with the insulating layer 214 located at the Y-direction ends of regions Rdb1 and Rdb2.

[0130] The electrode 210 includes a barrier metal (conductor) 210_1 and a conductor 210_2. The barrier metal 210_1 functions as an oxidation prevention layer, a diffusion prevention layer, and an adhesion layer for the conductor 210_2. The barrier metal 210_1 is formed to cover the side and bottom surfaces of the electrode 210. The barrier metal 210_1 is in contact with the D2 wiring layer 209 and the insulating layers 212-215. The conductor 210_2 is provided within the barrier metal 210_1 in contact with it. The conductor 210_2 is embedded within the barrier metal 210_1 to form the core portion of the electrode 210 (bonding pad DB and contact plug CB). The barrier metal 210_1 includes, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier metal 210_1 may be a laminated film of these materials. The conductor 210_2 includes, for example, copper as a conductive material.

[0131] The D2 wiring layer 209 includes a barrier metal 209_1 and a conductor 209_2. The barrier metal 209_1 functions as an oxidation prevention layer, a diffusion prevention layer, and an adhesion layer for the conductor 209_2. The barrier metal 209_1 is formed to cover the side surface and the bottom surface facing the Z1 direction of the D2 wiring layer 209. The barrier metal 209_1 is in contact with the insulating layer 211. The conductor 209_2 is provided within the barrier metal 209_1 in contact with it. The conductor 209_2 is embedded within the barrier metal 209_1 to form the core portion of the D2 wiring layer 209. The barrier metal 209_1 includes, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier metal 209_1 may also be a laminated film of these materials. The conductor 209_2 includes, for example, copper as a conductive material.

[0132] For example, if copper is used for conductors 108_2 and 210_2, the copper of conductor 108_2 and the copper of conductor 210_2 may become integrated, making it difficult to confirm the boundary between the copper. However, the bonding can be confirmed by the distortion of the shape of the bonded electrodes 108 and 210 due to misalignment during bonding, and by the misalignment of barrier metal 108_1 and barrier metal 210_1 (occurrence of discontinuities on the side).

[0133] Furthermore, when electrodes 108 and 210 are formed by the dual damascene method, their respective sides have a tapered shape. As a result, the cross-sectional shape along the Z-direction at the point where electrodes 108 and 210 are bonded together is not a straight side wall, but rather a non-rectangular shape.

[0134] Furthermore, when electrodes 108 and 210 are bonded together, the bottom, side, and top surfaces of the copper forming them are covered by barrier metals 108_1 and 210_1. In contrast, in a typical wiring layer using copper, a cap insulating layer (SiN or SiCN, etc.) with an anti-oxidation function for copper is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0135] 1.2 Specific examples of alignment misalignment between region Rd2 and adhesive pad DB Next, with reference to Figure 13, a specific example of alignment misalignment between region Rd2 of the opening region ROcsp of the insulating layer 214 and the bonding pad DB will be described. Figure 13 is a diagram showing an example of the positional relationship between the opening region ROcsp of the insulating layer 214 and the electrode 210 (bonding pad DB). Figure 13(a) shows an example of a planar and Y-direction cross-section when no alignment misalignment occurs between the photolithography corresponding to the processing of region Rd2 of the insulating layer 214 and the photolithography corresponding to the processing of the electrode 210. Figure 13(b) shows an example of a planar and Y-direction cross-section when an alignment misalignment occurs between the photolithography corresponding to the processing of region Rd2 of the insulating layer 214 and the photolithography corresponding to the processing of the electrode 210. Furthermore, the relationship between region Rm1 of the opening region ROvsp of the insulating layer 127 and electrode 108 (bonded pad MB) exhibits a similar trend to that between region Rd2 of the opening region ROcsp of the insulating layer 214 and electrode 210 (bonded pad DB), by swapping the X and Y directions.

[0136] The etching stopper CSP (insulating layer 214) functions as a mask when processing the contact plug CB (insulating layer 213). For example, in photolithography for processing region Rd2 of the aperture region ROcsp of the insulating layer 214, which corresponds to the contact plug CB, alignment is performed with respect to the alignment pattern of the D2 wiring layer 209. For example, in photolithography for processing the electrode 210 (forming the hole pattern of the electrode 210), alignment is performed with respect to the alignment pattern formed by processing the insulating layer 214 or the alignment pattern of the D2 wiring layer 209. In this case, a positional shift due to alignment errors may occur between region Rd2 of the aperture region ROcsp and the electrode 210. In photolithography for processing the electrode 210, if the alignment pattern formed by processing the insulating layer 214 is used, the hole pattern of the electrode 210 is directly aligned with respect to the mask pattern (region Rd2) of the insulating layer 214. In contrast, when using the alignment pattern of the D2 wiring layer 209 in photolithography for processing the electrode 210, the hole pattern of the electrode 210 is indirectly aligned with respect to the mask pattern of the insulating layer 214. Therefore, when using the alignment pattern of the D2 wiring layer 209 in photolithography for processing the electrode 210, the positional displacement due to alignment errors between the region Rd2 of the aperture region ROcsp and the electrode 210 tends to be larger than when using the alignment pattern formed by processing the insulating layer 214.

[0137] In the example shown in Figure 13(a), no alignment misalignment occurs between the photolithography used to process region Rd2 of the aperture region ROcsp of the insulating layer 214 and the photolithography used to process the electrode 210. That is, no positional misalignment occurs between region Rd2 of the aperture region ROcsp and the electrode 210. In a plan view from the Z direction, region Rd2 of the aperture region ROcsp protrudes in the Y direction from the Y-direction end of the bonding pad DB (electrode 210). When no alignment misalignment occurs, the Y-direction length of the protrusion on the right side of the paper of region Rd2 is equal to the Y-direction length of the protrusion on the left side of the paper. For example, let that length be Ly. In this case, the Y-direction length Lcspy of region Rd2 of the aperture region ROcsp can be expressed as Lcspy = 2Ly + Ldb.

[0138] In the example shown in Figure 13(b), an alignment misalignment occurs between the photolithography used to process region Rd2 of the aperture region ROcsp of the insulating layer 214 and the photolithography used to process the electrode 210. That is, a positional misalignment occurs between region Rd2 of the aperture region ROcsp and the bonding pad DB. In the example shown in Figure 13(b), the electrode 210 is shifted to the right of the plane relative to region Rd2 of the aperture region ROcsp. Let the amount of alignment misalignment at this time be Δ. The length in the Y direction of the protrusion of region Rd2 on the right side of the plane is Ly-Δ. The length in the Y direction of the protrusion of region Rd2 on the left side of the plane is Ly+Δ. When the relationship between the length of the protrusion Ly and the misalignment Δ is Ly>Δ, the bonding pad DB does not protrude from region Rd2 in the Y direction. Therefore, the length Lcby in the Y direction of the upper surface of the contact plug CB is constant regardless of the misalignment Δ.

[0139] 1.3 Specific Examples of Positional Misalignment Correction Between Bonding Pad MB and Bonding Pad DB Next, with reference to Figures 14 to 18, specific examples of misalignment correction between the bonding pad MB and the bonding pad DB will be described. Figure 14 is a diagram showing the bonding of a wafer WF1 on which multiple array chips 10 are formed and a wafer WF2 on which multiple circuit chips 20 are formed. Figure 15 is a schematic perspective view showing the warpage of the wafer WF1 on which the multiple array chips 10 are formed. Figure 16 is a diagram schematically showing the direction of misalignment of the array chips 10 on the wafer WF1. Figure 17 is a plan view of the M1 wiring layer 107 and electrode 108, showing an example of misalignment correction of electrode 108 corresponding to the misalignment of electrode 108 in the X direction. Figure 18 is a plan view of the D2 wiring layer 209 and electrode 210, showing an example of misalignment correction of electrode 210 corresponding to the misalignment of electrode 108 in the Y direction.

[0140] As shown in Figure 14, multiple array chips 10 are formed on wafer WF1. Multiple circuit chips 20 are formed on wafer WF2. In the assembly process of the semiconductor device 1, wafer WF1 on which the multiple array chips 10 are formed and wafer WF2 on which the multiple circuit chips 20 are formed are bonded together. Subsequently, the bonded wafers WF1 and WF2 are separated into individual pieces by dicing, thereby forming a bonded semiconductor device 1.

[0141] As shown in Figure 15, for example, a wafer WF1 on which multiple array chips 10 are formed may have different warping directions along the X direction and along the Y direction due to the influence of film stress on the wiring layer 102 (word lines WL and selected gate lines SGD and SGS) that extends in the X direction. In the example shown in Figure 15, when looking at the cross-section in the X direction (cross-section along the X direction at the position Y=0 in the figure) along the extension direction of the word line WL passing through the center of the wafer WF1, the wafer WF1 has a convex shape downwards due to tensile stress. In contrast, when looking at the cross-section in the Y direction (cross-section along the Y direction at the position X=0 in the figure) passing through the center of the wafer WF1, the wafer WF1 has a convex shape upwards due to compressive stress.

[0142] As shown in Figure 16, if, for example, a warp occurs in wafer WF1 as explained using Figure 15, the actual chip position shown by the solid line will be offset from the design chip position shown by the dashed line. Specifically, for example, the array chip 10_c located at the center of wafer WF1 has the same chip position as the design chip. In contrast, with wafer WF1 with the notch facing downwards, the array chip 10_ue located at the 12 o'clock edge of wafer WF1 (upper side of the paper in Figure 16) has its actual chip position shifted in the Y direction toward the outer edge of wafer WF1 (upper side of the paper in Figure 16) relative to the design chip position.

[0143] The array chip 10_re, located at the 3 o'clock edge of wafer WF1 (right side of Figure 16), is actually misaligned in the X direction relative to its design chip position, towards the center of wafer WF1 (left side of Figure 16). Similarly, for example, the array chip 10_rm, located between array chip 10_c and array chip 10_re, is actually misaligned in the X direction relative to its design chip position, towards the center of wafer WF1 (left side of Figure 16). For example, as shown in Figure 15, the amount of warping in the X direction of wafer WF1 increases from the center of wafer WF1 towards the edge in the X direction. Therefore, the amount of misalignment in the X direction of array chip 10_re is greater than the amount of misalignment in the X direction of array chip 10_rm.

[0144] The array chip 10_be, located at the 6 o'clock edge of wafer WF1 (bottom of the page in Figure 16), is actually misaligned in the Y direction relative to its design chip position, towards the outer edge of wafer WF1 (bottom of the page in Figure 16). Similarly, for example, the array chip 10_bm, located between array chip 10_c and array chip 10_be, is actually misaligned in the Y direction relative to its design chip position, towards the outer edge of wafer WF1 (bottom of the page in Figure 16). For example, as shown in Figure 15, the amount of warping in the Y direction of wafer WF1 increases from the center of wafer WF1 towards the edge in the Y direction. Therefore, the amount of misalignment in the Y direction of array chip 10_be is greater than the amount of misalignment in the Y direction of array chip 10_bm.

[0145] The array chip 10_le located at the 9 o'clock edge of wafer WF1 (left side of Figure 16) is actually shifted in the X direction toward the center of wafer WF1 (right side of Figure 16) relative to its design chip position. Thus, the direction and amount of the shift of the array chip 10 differ depending on its position on wafer WF1.

[0146] The X-direction misalignment of the array chip 10 is corrected by shifting the electrodes 108 (bonding pad MB and contact plug VB) of the array chip 10 in the X direction. The Y-direction misalignment of the array chip 10 is corrected by shifting the electrodes 210 (bonding pad DB and contact plug CB) of the corresponding (bonded) circuit chip 20 in the Y direction. Therefore, the direction of misalignment correction and the amount of misalignment correction differ between semiconductor device 1_c including array chip 10_c, semiconductor device 1_ue including array chip 10_ue, semiconductor device 1_rm including array chip 10_rm, semiconductor device 1_re including array chip 10_re, semiconductor device 1_bm including array chip 10_bm, semiconductor device 1_be including array chip 10_be, and semiconductor device 1_le including array chip 10_le.

[0147] Next, we will explain how to correct the positional misalignment in the X direction. The example shown in Figure 17 illustrates the correction of the positional misalignment in the X direction for array chips 10_rm and 10_re, which are located at the 3 o'clock position from the center of wafer WF1 (right side of the page in Figure 16). Note that array chip 10_le, which is located at the 9 o'clock position from the center of wafer WF1 (left side of the page in Figure 16), has a positional misalignment in the opposite direction to array chip 10_re. Therefore, the positional misalignment in the X direction for array chip 10_le is corrected in the opposite direction to array chip 10_re.

[0148] As explained using Figure 16, for example, the array chip 10_c of semiconductor device 1_c is not misaligned in the X direction. Therefore, when bonding the bonding pad MB and bonding pad DB, there is almost no misalignment in the X direction between the bonding pad MB and bonding pad DB. Note that this may include misalignment due to manufacturing variations. In this case, as shown in Figure 17, in array chip 10_c, the electrodes 108 (bonding pad MB and contact plug VB) are formed on the M1 wiring layer 107 without correction for misalignment in the X direction. Array chips 10_ue and 10_be, which are not misaligned in the X direction, are the same as array chip 10_c.

[0149] For example, the array chip 10_rm of semiconductor device 1_rm and the array chip 10_re of semiconductor device 1_re are misaligned in the X direction toward the center of wafer WF1 (left side of the page in Figure 17), similar to the explanation using Figure 16. Therefore, if the bonding pad MB and bonding pad DB are bonded together without misalignment correction, the bonding pad MB will be misaligned in the X direction toward the left side of the page in Figure 17 relative to the bonding pad DB. For this reason, in array chips 10_rm and 10_re, the position of the bonding pad MB is corrected toward the outer edge of wafer WF1 (right side of the page in Figure 17), which is in the opposite direction to the misalignment. This corrects the misalignment in the X direction.

[0150] The amount of warping in the X direction of wafer WF1 differs depending on the position of wafer WF1 on which the array chip 10 is installed. Therefore, the amount of X-direction displacement of the bonding pad MB differs depending on the position of wafer WF1 on which the array chip 10 is installed. Consequently, the amount of correction for the X-direction displacement of the bonding pad MB differs between array chip 10_rm and array chip 10_re. The amount of X-direction displacement of array chip 10_re is greater than that of array chip 10_rm. Therefore, the amount of correction for the X-direction displacement of electrode 108 (bonding pad MB) of array chip 10_re is greater than that of array chip 10_rm. For example, in array chip 10_c, let La1 be the distance from the right edge of the M1 wiring layer 107 on the paper to electrode 108 (bonding pad MB). In array chip 10_rm, the distance from the right-hand edge of the M1 wiring layer 107 to the electrode 108 is defined as La2. In array chip 10_re, the distance from the right-hand edge of the M1 wiring layer 107 to the electrode 108 is defined as La3. Due to the X-direction positional shift correction in array chips 10_rm and 10_re, the distances La1, La2, and La3 have the relationship La1 > La2 > La3.

[0151] Therefore, in order to correct the positional misalignment in the X direction, the positional relationship between the M1 wiring layer 107 and the electrode 108 may differ for each array chip 10.

[0152] Next, we will explain how to correct the misalignment in the Y direction. The example shown in Figure 18 illustrates the correction of the misalignment in the Y direction for circuit chips 20_bm and 20_be, which correspond to array chips 10_bm and 10_be, respectively, located at the 6 o'clock position from the center of wafer WF1 (bottom of the page in Figure 16). Note that array chip 10_ue, located at the 12 o'clock position from the center of wafer WF1 (top of the page in Figure 16), is misaligned in the opposite direction to array chip 10_be. Therefore, in circuit chip 20, which corresponds to array chip 10_ue located at the 12 o'clock position from the center of wafer WF1 (top of the page in Figure 16), the misalignment in the Y direction is corrected in the opposite direction to circuit chip 20_be.

[0153] As explained using Figure 16, for example, the array chip 10_c of semiconductor device 1_c is not misaligned in the Y direction. Therefore, when bonding the bonding pad MB and bonding pad DB, there is almost no misalignment in the Y direction between the bonding pad MB and bonding pad DB. However, this may include misalignment due to manufacturing variations. In this case, as shown in Figure 18, in the circuit chip 20_c corresponding to the array chip 10_c, the electrodes 210 (bonding pad DB and contact plug CB) are formed on the D2 wiring layer 209 without correction for misalignment in the Y direction. Note that the array chips 10_rm, 10_re, and 10_le are also not misaligned in the Y direction. Therefore, the circuit chips 20 corresponding to the array chips 10_rm, 10_re, and 10_le are the same as the circuit chip 20_c.

[0154] For example, the array chip 10_bm of semiconductor device 1_bm and the array chip 10_be of semiconductor device 1_be are misaligned in the Y direction toward the outer edge of wafer WF1 (the bottom side of the paper in Figure 18), similar to the explanation using Figure 16. Therefore, if the bonding pad MB and bonding pad DB are bonded together without misalignment correction, the bonding pad MB will be misaligned in the Y direction toward the bottom side of the paper in Figure 18 relative to the bonding pad DB. For this reason, the circuit chip 20_bm corresponding to array chip 10_bm and the circuit chip 20_be corresponding to array chip 10_be are corrected in the same direction as the misalignment of the bonding pad MB, i.e., toward the outer edge of wafer WF2 (the bottom side of the paper in Figure 18). This corrects the misalignment in the Y direction.

[0155] Depending on the position of the wafer WF1 provided with the array chip 10, the amount of displacement in the Y direction of the bonding pad MB varies. Therefore, the correction amount of the displacement in the Y direction of the bonding pad DB varies depending on the circuit chip 20. The amount of displacement in the Y direction of the array chip 10_be is larger than the amount of displacement in the Y direction of the array chip 10_bm. For this reason, the correction amount of the displacement in the Y direction of the electrode 210 (bonding pad DB) of the circuit chip 20_be corresponding to the array chip 10_be is larger than the correction amount of the displacement in the Y direction of the electrode 210 (bonding pad DB) of the circuit chip 20_bm corresponding to the array chip 10_bm. For example, in the circuit chip 20_c, let the distance from the upper end on the paper surface of the D2 wiring layer 209 to the bonding pad DB be Lb1. In the circuit chip 20_bm, let the distance from the upper end on the paper surface of the D2 wiring layer 209 to the bonding pad DB be Lb2. In the circuit chip 20_be, let the distance from the upper end on the paper surface of the D2 wiring layer 209 to the bonding pad DB be Lb3. Due to the correction of the displacement in the Y direction in the circuit chips 20_bm and 20_be, the distances Lb1, Lb2, and Lb3 are in the relationship of Lb1 < Lb2 < Lb3.

[0156] Therefore, in order to correct the displacement in the Y direction, the positional relationship between the D2 wiring layer 209 and the electrode 210 can be different for each circuit chip 20.

[0157] In addition, in the array chip 10 and the circuit chip 20 not shown, which are arranged in directions other than 12 o'clock, 3 o'clock, 6 o'clock, and 9 o'clock from the centers of the wafers WF1 and WF2, the electrode 108 of the array chip 10 may be shifted in the X direction, and the electrode 210 of the circuit chip 20 may be shifted in the Y direction. Thereby, in the semiconductor device 1 in which the corresponding array chip 10 and circuit chip 20 are bonded together, the displacement between the bonding pad MB and the bonding pad DB can be corrected.

[0158] 1.4 Method for manufacturing an electrode Next, an example of a manufacturing method for the electrode 210 will be described with reference to Figures 19 to 24. Figures 19 to 24 are diagrams showing the manufacturing process of the electrode 210. In each of Figures 19 to 24, (a) the XY plane, (b) a cross-section in the X direction, and (c) a cross-section in the Y direction are shown, respectively. Note that the manufacturing method for the electrode 108 is the same as that for the electrode 210.

[0159] As shown in Figure 19, first, an insulating layer 211 is provided on top of the semiconductor substrate 201 (not shown). Next, a D2 wiring layer 209 is formed. More specifically, a groove pattern for the D2 wiring layer 209 is formed within the insulating layer 211. When the contact plug C1 and the D2 wiring layer 209 are formed by the dual damascene method, the groove pattern for the D2 wiring layer 209 and the hole pattern (not shown) for the contact plug C1 are formed. Next, barrier metal 209_1 and conductor 209_2 are sequentially deposited to fill the groove pattern for the D2 wiring layer 209. Then, for example, excess barrier metal 209_1 and conductor 209_2 on the insulating layer 211 are removed by CMP (Chemical Mechanical Polishing). This forms the D2 wiring layer 209.

[0160] As shown in Figure 20, an insulating layer 212 is deposited on the insulating layer 211 and the D2 wiring layer 209. An insulating layer 213 and an insulating layer 214 (etching stopper CSP) are sequentially deposited on the insulating layer 212. Next, an opening pattern 400 of the resist 302 corresponding to region Rd2 (contact plug CB) is formed above the D2 wiring layer 209 by photolithography. The pattern 400 has a roughly rectangular shape with a length Lcspx in the X direction and a length Lcspy in the Y direction. More specifically, first, a component 301 is deposited on the insulating layer 214. For example, the component 301 functions as an anti-reflective film for photolithography. After applying the resist 302 on the component 301, the pattern 400 is formed by photolithography. Note that in order to correct the Y-direction misalignment between the bonding pad MB and the bonding pad DB, the pattern 400 may be shifted in the Y direction relative to the reference position (the design position when no misalignment occurs).

[0161] As shown in Figure 21, the insulating layer 214 is processed using the resist 302 as a mask. This forms the region Rd2 of the opening region ROcsp. After processing the insulating layer 214, the resist 302 and the component 301 are removed.

[0162] As shown in Figure 22, an insulating layer 215 is deposited on insulating layers 213 and 214. Next, an aperture pattern 401 of the resist 312 corresponding to the bonding pad DB (electrode 210) is formed by photolithography above region Rd2 of the aperture region ROcsp. The pattern 401 has a substantially square shape with side length Ldb. More specifically, first, a component 311 is deposited on the insulating layer 215. For example, component 311 functions as an anti-reflective film in photolithography. After coating the resist 312 on component 311, the pattern 401 is formed by photolithography. If pattern 400 is shifted in the Y direction, pattern 401 is shifted in the Y direction similarly to pattern 400.

[0163] As shown in Figure 23, the insulating layers 212-215 are processed using the resist 312 as a mask to form the hole pattern for the electrode 210. That is, the hole patterns corresponding to the bonded pad DB and the contact plug CB are formed simultaneously. More specifically, first, the insulating layer 215 is processed using the resist 312 as a mask. Once the insulating layer 215 is processed and the insulating layer 214 is exposed, the insulating layer 213 is processed using the resist 312 and the insulating layer 214 as masks. That is, the pattern for the contact plug CB is formed self-aligned using the insulating layer 214 as a mask. Next, the exposed insulating layer 214 (the insulating layer 214 in regions Rdb1 and Rdb2) and the insulating layer 212 exposed at the bottom of the contact plug CB pattern are removed to form the hole pattern for the electrode 210. At this time, the opening region ROcsp of the insulating layer 214 has the shape described using Figure 10.

[0164] As shown in Figure 24, the electrode 210 (bonding pad DB and contact plug CB) is formed. More specifically, barrier metal 210_1 and conductor 210_2 are sequentially deposited to fill the hole pattern of the electrode 210. Next, for example, excess barrier metal 210_1 and conductor 210_2 on the insulating layer 215 are removed by CMP. This forms the electrode 210.

[0165] 1.5 Effects of this embodiment In the configuration according to this embodiment, the semiconductor device 1 includes a bonded array chip 10 and a circuit chip 20. The array chip 10 and the circuit chip 20 are electrically connected by bonding the bonding pad MB of the array chip 10 and the bonding pad DB of the circuit chip 20. To correct the X-direction misalignment between the bonding pad MB and the bonding pad DB, the semiconductor device 1 can shift the arrangement of the opening region ROvsp of the insulating layer 127 and the electrode 108 in the X-direction relative to the M1 wiring layer 107 which extends in the X-direction. By shifting the opening region ROvsp of the insulating layer 127 and the electrode 108 in the X-direction, the semiconductor device 1 can correct the X-direction misalignment between the bonding pad MB and the bonding pad DB. Furthermore, to correct the Y-direction misalignment between the bonding pad MB and the bonding pad DB, the semiconductor device 1 can shift the arrangement of the opening region ROcsp of the insulating layer 214 and the electrode 210 in the Y-direction relative to the D2 wiring layer 209 which extends in the Y-direction. By shifting the opening region ROcsp of the insulating layer 214 and the electrode 210 in the Y direction, the semiconductor device 1 can correct the Y-direction misalignment between the bonded pad MB and the bonded pad DB. This reduces connection failures between the bonded pad MB and the bonded pad DB caused by the misalignment. Therefore, the yield of the semiconductor device 1 can be improved.

[0166] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can make the length Lvspx in the X direction of region Rm1 of the opening region ROvsp of the insulating layer 127, which functions as an etching stopper VSP, longer than the length Lmb of the upper surface of the bonding pad MB. That is, the semiconductor device 1 can make the length Lvspx in the X direction of the mask pattern corresponding to the contact plug VB longer than the length Lmb of the upper surface of the bonding pad MB. As a result, even if an alignment misalignment occurs between region Rm1 of the opening region ROvsp and the bonding pad MB, the length in the X direction of the contact plug VB formed by self-alignment will not vary. That is, the semiconductor device 1 can make the resistance value of the contact plug VB approximately constant. By making the resistance value of the contact plug VB approximately constant, the semiconductor device 1 can reduce connection failures between the M1 wiring layer 107 and the bonding pad MB. Similarly, the semiconductor device 1 can make the length Lcspy in the Y direction of region Rd2 of the opening region ROcsp of the insulating layer 214, which functions as an etching stopper CSP, longer than the length Ldb of the bonding pad DB. In other words, the semiconductor device 1 can make the Y-direction length Lcspy of the mask pattern corresponding to the contact plug CB longer than the Y-direction length Ldb of the bonding pad DB. As a result, even if an alignment misalignment occurs between the region R2d of the aperture region ROcsp and the bonding pad DB, the Y-direction length of the contact plug CB formed by self-alignment will not vary. In other words, the semiconductor device 1 can make the resistance value of the contact plug CB approximately constant. By making the resistance value of the contact plug CB approximately constant, the semiconductor device 1 can reduce connection failures between the D2 wiring layer 209 and the bonding pad DB. Therefore, the yield of the semiconductor device 1 can be improved.

[0167] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, the shape of the etching stopper will differ from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0168] 2.1 Structure of adhesive pads First, the structure of the bonded pad BP will be described with reference to Figures 25 to 28. Figure 25 shows an example of a plan view of the electrode 108 and the M1 wiring layer 107, as well as a plan view of the insulating layer 127. Figure 26 shows an example of a plan view of the electrode 210 and the D2 wiring layer 209, as well as a plan view of the insulating layer 214. Figure 27 is a cross-sectional view along the line VI-VI in Figures 25 and 26. Figure 28 is a cross-sectional view along the line VII-VII in Figures 25 and 26.

[0169] Note that the insulating layer is omitted in the plan view of electrode 108 and M1 wiring layer 107 in Figure 25, and in the plan view of electrode 210 and D2 wiring layer 209 in Figure 26. Other conductors and insulating layers are omitted in the plan view of insulating layer 127 in Figure 25 and the plan view of insulating layer 214 in Figure 26.

[0170] In this embodiment, the shapes of the contact plug VB, bonding pad MB, bonding pad DB, and contact plug CB are the same as in Figure 8 of the first embodiment. The shapes of the opening region ROvsp of the insulating layer 127 and the opening region ROcsp of the insulating layer 214 differ from those of the first embodiment. The following description will focus on the insulating layers 127 and 214.

[0171] As shown in Figure 25, for example, the opening region ROvsp of the insulating layer 127 includes regions Rm1, Rmb1, and Rmb2. In this embodiment, the length Lvspx of region Rm1 in the X direction is different from that of the first embodiment. In this embodiment, in a plan view from the Z direction, region Rm1 overlaps with almost the entire surface of the M1 wiring layer 107. That is, the size of the top surface of the M1 wiring layer 107 and the size of region Rm1 are approximately the same. The length Lvspx of region Rm1 in the X direction is approximately the same as the length Lm1x of the M1 wiring layer 107 in the X direction. For example, the distance from the X-direction end of the M1 wiring layer 107 to the X-direction end of region Rm1 of the opening region ROvsp of the insulating layer 127 is 200 nm or less. More specifically, for example, it is preferable to define length Lvspx as the length Lm1x minus the photolithography alignment margin corresponding to the processing of the opening region ROvsp of the insulating layer 127. This prevents region Rm1 from deviating from the M1 wiring layer 107 in the X direction in a plan view from the Z direction.

[0172] By making the X-direction length Lvspx of region Rm1 approximately the same as the X-direction length Lm1x of the M1 wiring layer 107, the X-direction length of the contact plug VB formed by self-alignment remains unchanged even when the position of the electrode 108 (bonded pad MB) is shifted in the X direction. The X-direction length Lvbx of the upper surface of the contact plug VB is approximately the same as the length Lmb of the upper surface of the bonded pad MB.

[0173] In this embodiment, in order to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB, the arrangement of the electrodes 108 can be shifted in the X-direction without shifting the region Rm1 of the opening region ROvsp relative to the M1 wiring layer 107 that extends in the X-direction. This makes it possible to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB.

[0174] As shown in Figure 26, for example, the opening region ROcsp of the insulating layer 214 includes regions Rd2, Rdb1, and Rdb2. In this embodiment, the length Lcspy in the Y direction of region Rd2 is different from that of the first embodiment. In this embodiment, in a plan view from the Z direction, region Rd2 overlaps with almost the entire surface of the D2 wiring layer 209. That is, the size of the top surface of the D2 wiring layer 209 and the size of region Rd2 are approximately the same. The length Lcspy in the Y direction of region Rd2 is approximately the same as the length Ld2y in the Y direction of the D2 wiring layer 209. For example, the distance from the Y-direction end of the D2 wiring layer 209 to the Y-direction end of region Rd2 of the opening region ROcsp of the insulating layer 214 is 200 nm or less. More specifically, for example, it is preferable to define length Lcspy as the length Ld2y minus the photolithography alignment margin corresponding to the processing of the opening region ROcsp of the insulating layer 214. This prevents region Rd2 from deviating from the D2 wiring layer 209 in the Y direction in a plan view from the Z direction.

[0175] By making the Y-direction length Lcspy of region Rd2 approximately the same as the Y-direction length Ld2y of the D2 wiring layer 209, the Y-direction length of the contact plug CB formed by self-alignment remains unchanged even when the position of the electrode 210 (bonded pad DB) is shifted in the Y-direction. The Y-direction length Lcby of the upper surface of the contact plug CB is approximately the same as the length Ldb of the bonded pad DB.

[0176] In this embodiment, in order to correct the positional misalignment in the Y direction between the bonded pad MB and the bonded pad DB, the arrangement of the electrodes 210 can be shifted in the Y direction without shifting the region Rd2 of the opening region ROcsp relative to the D2 wiring layer 209 that extends in the Y direction. This makes it possible to correct the positional misalignment in the Y direction between the bonded pad MB and the bonded pad DB.

[0177] As shown in Figures 27 and 28, the shapes of electrodes 108 and 210, i.e., the shapes of the bonding pads MB and DB, are the same as those described using Figures 11 and 12 in the first embodiment. In this embodiment, the length Lvspx in the X direction of the opening region ROvsp of the insulating layer 127 and the length Lcspy in the Y direction of the opening region ROcsp of the insulating layer 214 are longer than the lengths Lvspx and Lcspy described in the first embodiment.

[0178] 2.2 Method for manufacturing electrodes Next, an example of a manufacturing method for the electrode 210 will be described with reference to Figures 29 to 34. Figures 29 to 34 are diagrams showing the manufacturing process of the electrode 210. In each of Figures 29 to 34, (a) the XY plane, (b) a cross-section in the X direction, and (c) a cross-section in the Y direction are shown, respectively. The manufacturing method for the electrode 108 is the same as that for the electrode 210.

[0179] As shown in Figure 29, first, an insulating layer 211 is provided on top of the semiconductor substrate 201 (not shown), similar to the explanation using Figure 19 of the first embodiment. Next, a D2 wiring layer 209 is formed.

[0180] As shown in Figure 30, an insulating layer 212 is deposited on the insulating layer 211 and the D2 wiring layer 209, similar to the explanation using Figure 20 of the first embodiment. An insulating layer 213 and an insulating layer 214 (etching stopper CSP) are sequentially deposited on the insulating layer 212. Next, an opening pattern 400 of the resist 302 corresponding to region Rd2 is formed above the D2 wiring layer 209 by photolithography. The pattern 400 has a substantially rectangular shape with a length Lcspx in the X direction and a length Lcspy in the Y direction. In this embodiment, the pattern 400 is not shifted in the Y direction from the reference position (the design position when no positional displacement occurs).

[0181] As shown in Figure 31, the insulating layer 214 is processed using the resist 302 as a mask, similar to the explanation using Figure 21 of the first embodiment. This forms the region Rd2 of the opening region ROcsp. After processing the insulating layer 214, the resist 302 and member 301 are removed.

[0182] As shown in Figure 32, an insulating layer 215 is deposited on insulating layers 213 and 214, similar to the description using Figure 22 of the first embodiment. Next, an opening pattern 401 of the resist 312 corresponding to the bonding pad DB is formed above region Rd2 of the opening region ROcsp by photolithography. The pattern 401 has a substantially square shape with a side length of Ldb. In order to correct the positional misalignment in the Y direction between the bonding pad MB and the bonding pad DB, the pattern 401 may be shifted in the Y direction relative to the reference position.

[0183] As shown in Figure 33, similar to the explanation using Figure 23 of the first embodiment, the insulating layers 213 to 215 are processed using the resist 312 as a mask to form the hole pattern of the electrode 210. That is, the hole patterns corresponding to the bonding pad DB and the contact plug CB are formed at the same time. At this time, the opening region ROcsp of the insulating layer 214 has the shape explained using Figure 26.

[0184] As shown in Figure 34, the electrode 210 (bonding pad DB and contact plug CB) is formed in the same manner as described using Figure 24 of the first embodiment.

[0185] 2.3 Effects according to this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained. More specifically, the semiconductor device 1 can make the size of the upper surface of the M1 wiring layer 107 and the size of region Rm1 approximately the same. As a result, the semiconductor device 1 can shift the arrangement of the electrodes 108 in the X direction without shifting the region Rm1 of the opening region ROvsp relative to the M1 wiring layer 107 that extends in the X direction. Therefore, the semiconductor device 1 can correct the X-direction misalignment between the bonded pad MB and the bonded pad DB. In addition, the semiconductor device 1 can make the size of the upper surface of the D2 wiring layer 209 and the size of region Rd2 approximately the same. As a result, the semiconductor device 1 can shift the arrangement of the electrodes 210 in the Y direction without shifting the region Rd2 of the opening region ROcsp relative to the D2 wiring layer 209 that extends in the Y direction. Therefore, the semiconductor device 1 can correct the Y-direction misalignment between the bonded pad MB and the bonded pad DB.

[0186] Furthermore, with the configuration according to this embodiment, the semiconductor device 1, like the first embodiment, does not have variations in the length in the X direction of the contact plug VB formed by self-alignment. That is, the semiconductor device 1 can maintain a substantially constant resistance value of the contact plug VB. Also, the semiconductor device 1 does not have variations in the length in the Y direction of the contact plug CB formed by self-alignment. That is, the semiconductor device 1 can maintain a substantially constant resistance value of the contact plug CB. Therefore, the yield of the semiconductor device 1 can be improved.

[0187] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, the shape of the bonding pad BP and the dual damascene method, which differ from those of the first and second embodiments, will be described. The following description will focus on the differences from the first and second embodiments.

[0188] 3.1 Cross-sectional structure of semiconductor device First, an example of the cross-sectional structure of the semiconductor device 1 will be described with reference to Figure 35. Figure 35 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 according to the third embodiment, along the line IV-IV in Figure 4.

[0189] As shown in Figure 35, the semiconductor device 1 of this embodiment has a structure in which the insulating layers 127 and 128 of the array chip 10 and the insulating layers 214 and 215 of the circuit chip 20 are eliminated compared to the semiconductor device 1 shown in Figure 5 of the first embodiment. In other words, in this embodiment, the insulating layer 127 that functions as an etching stopper VSP and the insulating layer 214 that functions as an etching stopper CSP are eliminated.

[0190] An electrode 108 is provided within the insulating layer 126. An electrode 210 is also provided within the insulating layer 213. The length of electrode 108 in the X direction is longer than the length of electrode 210 in the X direction. Furthermore, the length of electrode 210 in the Y direction, as described later, is longer than the length of electrode 108 in the Y direction.

[0191] The surface where the insulating layer 126 and the insulating layer 213 are in contact is the bonding surface BS. The other structures are the same as in Figure 5 of the first embodiment.

[0192] 3.2 Structure of adhesive pads First, the structure of the bonded pad BP will be described with reference to Figures 36 to 40. Figure 36 is a perspective view showing an example of the structure of the M1 wiring layer 107, electrodes 108 and 210, and D2 wiring layer 209. Figure 37 is a diagram showing an example of a plan view of the electrode 108 and the M1 wiring layer 107. Figure 38 is a diagram showing an example of a plan view of the electrode 210 and the D2 wiring layer 209. Figure 39 is a cross-sectional view along the line VI-VI in Figures 37 and 38. Figure 40 is a cross-sectional view along the line VII-VII in Figures 37 and 38.

[0193] Note that the insulating layer is omitted in Figures 36 to 38. Also, in Figure 36, the contact surface between the adhesive pad MB and the adhesive pad DB is indicated by hatching to make it easier to see.

[0194] As shown in Figure 36, in this embodiment, the electrode 108, compared to the electrode 108 shown in Figure 8 of the first embodiment, has a portion of the electrode 108 located on the M1 wiring layer 107 that extends (protrudes) in the X direction.

[0195] In this embodiment, the electrode 210, compared to the electrode 210 shown in Figure 8 of the first embodiment, has a portion of the electrode 210 located on the D2 wiring layer 209 that extends (protrudes) in the Y direction.

[0196] For example, if there is no misalignment between the bonding pad MB and the bonding pad DB, and the length Lmb in the Y direction of the upper surface of the bonding pad MB and the length Ldb in the X direction of the upper surface of the bonding pad DB are approximately the same, then the shape of the contact surface between the bonding pad MB and the bonding pad DB is approximately square, as shown in Figure 8.

[0197] As shown in Figure 37, the electrode 108 includes a first part 108_vb, a second part 108_mb1, and a third part 108_mb2.

[0198] In this embodiment, a dual damascene method is used to process the electrode 108, in which a hole pattern corresponding to the contact plug VB is processed first, and then a hole pattern corresponding to the bonding pad MB is processed. Alternatively, a dual damascene method may be used to process the electrode 108, in which a hole pattern corresponding to the bonding pad MB is processed first, and then a hole pattern corresponding to the contact plug VB is processed.

[0199] The first part 108_vb is the region where the insulating layer 126 is processed when processing the hole pattern corresponding to the contact plug VB. The second part 108_mb1 and the third part 108_mb2 are the regions where the insulating layer 126 is processed when processing the hole pattern corresponding to the bonded pad MB.

[0200] The first part 108_vb overlaps with the M1 wiring layer 107 in a plan view from the Z direction. The first part 108_vb has a roughly rectangular shape, longer in the X direction than in the Y direction. The first part 108_vb includes a contact plug VB and a portion of the bonding pad MB located on the contact plug VB.

[0201] The second part 108_mb1 is in contact with one side of the first part 108_vb facing the Y direction. The second part 108_mb1 has a roughly rectangular shape, longer in the X direction than in the Y direction. The second part 108_mb1 includes a portion of the bonding pad MB but does not include the contact plug VB.

[0202] The third portion 108_mb2 is in contact with the other side of the first portion 108_vb facing the Y direction. In the Y direction, the first portion 108_vb is provided between the second portion 108_mb1 and the third portion 108_mb2. That is, the second portion 108_mb1 and the third portion 108_mb2 are adjacent in the Y direction with the first portion 108_vb in between. The third portion 108_mb2 has a substantially rectangular shape that is longer in the X direction than in the Y direction. The third portion 108_mb2 includes a part of the bonding pad MB but does not include the contact plug VB.

[0203] The length of the first part 108_vb in the X direction is approximately the same as the length Lvbx of the upper surface of contact plug VB in the X direction. Also, the length of the first part 108_vb in the Y direction is approximately the same as the length Lvby of the upper surface of contact plug VB in the Y direction. The length Lvbx of the first part 108_vb in the X direction is longer than the length Lmb of the second part 108_mb1 and the third part 108_mb2 in the X direction.

[0204] The first part 108_vb, in a plan view from the Z direction, includes a central portion sandwiched between the second part 108_mb1 and the third part 108_mb2, and two protrusions projecting in the X direction from the X-direction ends of the second part 108_mb1 and the third part 108_mb2. That is, the central portion is provided between the two protrusions. For example, in a plan view from the Z direction, the combined shape of the central portion of the first part 108_vb, the second part 108_mb1, and the third part 108_mb2 is approximately square. In this case, the combined length in the Y direction of the central portion of the first part 108_vb, the second part 108_mb1, and the third part 108_mb2 is approximately the same as the X-direction length Lmb of the second part 108_mb1 and the third part 108_mb2. This length is also the Y-direction length Lmb of the upper surface of electrode 108. The protruding portion of the first part 108_vb is the part that does not come into contact with the electrode 210. When there is no misalignment between the electrode 108 and the electrode 210, the upper surfaces of the central part of the first part 108_vb, the second part 108_mb1, and the third part 108_mb2 each come into contact with the electrode 210. For example, it is preferable that the difference between length Lvbx and length Lmb is greater than or equal to the amount of alignment misalignment between the photolithography corresponding to the processing of the contact plug VB and the photolithography corresponding to the processing of the bonded pad MB. As a result, even if an alignment misalignment occurs between the first part 108_vb (contact plug VB) and the second part 108_mb1 and the third part 108_mb2 (bonded pad MB), the length Lvbx in the X direction of the upper surface of the contact plug VB remains unchanged.

[0205] In this embodiment, in order to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB, the arrangement of the contact plug VB and the bonded pad MB can be shifted in the X direction relative to the M1 wiring layer 107 which extends in the X direction. By shifting the contact plug VB and the bonded pad MB in the X direction, the X-direction misalignment between the bonded pad MB and the bonded pad DB can be corrected.

[0206] As shown in Figure 38, the electrode 210 includes a first portion 210_cb, a second portion 210_db1, and a third portion 210_db2.

[0207] In this embodiment, a dual damascene method is used to process the electrode 210, in which a hole pattern corresponding to the contact plug CB is processed first, and then a hole pattern corresponding to the bonding pad DB is processed. Alternatively, a dual damascene method may be used to process the electrode 210, in which a hole pattern corresponding to the bonding pad DB is processed first, and then a hole pattern corresponding to the contact plug CB is processed.

[0208] The first part 210_cb is the region where the insulating layer 213 is processed when processing the hole pattern corresponding to the contact plug CB. The second part 210_db1 and the third part 210_db2 are the regions where the insulating layer 213 is processed when processing the hole pattern corresponding to the bonded pad DB.

[0209] The first portion 210_cb overlaps with the D2 wiring layer 209 in a plan view from the Z direction. The first portion 210_cb has a roughly rectangular shape, longer in the Y direction than in the X direction. The first portion 210_cb includes a contact plug CB and a portion of the bonding pad DB located on the contact plug CB.

[0210] The second part 210_db1 is in contact with one side of the first part 210_cb facing the X direction. The second part 210_db1 has a roughly rectangular shape, longer in the Y direction than in the X direction. The second part 210_db1 includes a portion of the bonding pad DB but does not include the contact plug CB.

[0211] The third portion 210_db2 is in contact with the other side of the first portion 210_cb facing the X direction. In the X direction, the first portion 210_cb is provided between the second portion 210_db1 and the third portion 210_db2. That is, the second portion 210_db1 and the third portion 210_db2 are adjacent in the X direction with the first portion 210_cb in between. The third portion 210_db2 has a substantially rectangular shape that is longer in the Y direction than in the X direction. The third portion 210_db2 includes a part of the bonding pad DB but does not include the contact plug CB.

[0212] The length of the first part 210_cb in the X direction is approximately the same as the length Lcbx of the upper surface of the contact plug CB in the X direction. Also, the length of the first part 210_cb in the Y direction is approximately the same as the length Lcby of the upper surface of the contact plug CB in the Y direction. The length Lcby of the first part 210_cb in the Y direction is longer than the length Ldb of the second part 210_db1 and the third part 210_db2 in the Y direction.

[0213] The first part 210_cb, in a plan view from the Z direction, includes a central portion sandwiched between the second part 210_db1 and the third part 210_db2, and two protrusions projecting in the Y direction from the Y-direction ends of the second part 210_db1 and the third part 210_db2. That is, the central portion is provided between the two protrusions. For example, in a plan view from the Z direction, the combined shape of the central portion of the first part 210_cb, the second part 210_db1, and the third part 210_db2 is approximately square. In this case, the combined length in the X direction of the central portion of the first part 210_cb, the second part 210_db1, and the third part 210_db2 is approximately the same as the Y-direction length Ldb of the second part 210_db1 and the third part 210_db2. This length is also the X-direction length Ldb of the upper surface of the electrode 210. The protruding portion of the first part 210_cb is the part that does not come into contact with the electrode 108. When there is no misalignment between the electrode 108 and the electrode 210, the upper surfaces of the central part of the first part 210_cb, the second part 210_db1, and the third part 210_db2 each come into contact with the electrode 108. For example, it is preferable that the difference between length Lcby and length Ldb is greater than or equal to the amount of alignment misalignment between the photolithography corresponding to the processing of the contact plug CB and the photolithography corresponding to the processing of the bonding pad DB. As a result, even if an alignment misalignment occurs between the first part 210_cb (contact plug CB) and the second part 210_db1 and third part 210_db2 (bonding pad DB), the length Lcby of the contact plug CB in the Y direction remains unchanged.

[0214] In this embodiment, in order to correct the misalignment of the bonded pad MB and bonded pad DB in the Y direction, the arrangement of the contact plug CB and bonded pad DB can be shifted in the Y direction relative to the D2 wiring layer 209 which extends in the Y direction. By shifting the contact plug CB and bonded pad DB in the Y direction, the misalignment of the bonded pad MB and bonded pad DB in the Y direction can be corrected.

[0215] Next, the cross-sectional shapes of the adhesive pads MB and DB will be described.

[0216] As shown in Figure 39, for example, the cross-section of the first portion 108_vb of electrode 108 in the X direction has a trapezoidal shape in which the length Lvbx of the upper surface of the first portion 108_vb of electrode 108 facing the Z1 direction in the X direction is longer than the length Ldb of the lower surface facing the Z2 direction which is in contact with the M1 wiring layer 107. The length Lvbx of the upper surface of the first portion 108_vb in the X direction is longer than the length Ldb of the upper surface of the bonded pad DB in the X direction. In the first portion 108_vb, the surface of the contact plug VB facing the X direction is provided on the same plane as the surface of the bonded pad MB facing the X direction.

[0217] The cross-section of electrode 210 in the X direction is the same as in Figure 11 of the first embodiment. The length of the first portion 210_cb in the Z direction is longer than the lengths of the second portion 210_db1 and the third portion 210_db2 in the Z direction.

[0218] As shown in Figure 40, for example, the cross-section of the first portion 210_cb of the electrode 210 in the Y direction has a trapezoidal shape in which the length Lcby of the upper surface of the first portion 210_cb of the electrode 210 facing the Z2 direction is longer than the length Lmb of the lower surface facing the Z1 direction which is in contact with the D2 wiring layer 209. The length Lcby of the upper surface of the first portion 210_cb in the Y direction is longer than the length Lmb of the upper surface of the bonding pad MB in the Y direction. In the first portion 210_cb, the surface of the contact plug CB facing the Y direction is provided on the same plane as the surface of the bonding pad DB facing the Y direction.

[0219] The cross-section of electrode 108 in the Y direction is the same as in Figure 12 of the first embodiment. The length of the first part 108_vb in the Z direction is longer than the lengths of the second part 108_mb1 and the third part 108_mb2 in the Z direction.

[0220] In this embodiment, the bonded pads MB and DB have discontinuous areas at the bonding location where the barrier metal 108_1 and barrier metal 210_1 are bonded, so the bonding can be confirmed.

[0221] 3.3 Method for manufacturing electrodes Next, an example of a method for manufacturing the electrode 210 will be described with reference to Figures 41 to 45. Figures 41 to 45 are diagrams showing the manufacturing process of the electrode 210. In each of Figures 41 to 45, (a) the XY plane, (b) a cross-section in the X direction, and (c) a cross-section in the Y direction are shown, respectively. The method for manufacturing the electrode 108 is the same as the method for manufacturing the electrode 210.

[0222] As shown in Figure 41, first, an insulating layer 211 is provided on top of the semiconductor substrate 201 (not shown). Next, a D2 wiring layer 209 is formed in the same manner as described using Figure 19 of the first embodiment. Next, an insulating layer 212 is deposited on top of the insulating layer 211 and the D2 wiring layer 209. An insulating layer 213 is deposited on top of the insulating layer 212. Next, an opening pattern 400 of the resist 302 corresponding to the contact plug CB (first portion 210_cb of the electrode 210) is formed on top of the D2 wiring layer 209 by photolithography. More specifically, first, a component 301 is deposited on top of the insulating layer 213. After coating the component 301 with resist 302, the pattern 400 is formed by photolithography. Note that in order to correct the positional misalignment in the Y direction between the bonding pad MB and the bonding pad DB, the pattern 400 may be shifted in the Y direction relative to the reference position (the design position when no positional misalignment occurs).

[0223] As shown in Figure 42, the insulating layer 213 is processed using the resist 302 as a mask. This forms the hole pattern of the contact plug CB. After processing the insulating layer 213, the resist 302 and component 301 are removed.

[0224] As shown in Figure 43, sacrificial material 313 is embedded in the hole pattern of the contact plug CB. Next, an opening pattern 401 of the resist 312 corresponding to the bonding pad DB is formed by photolithography. The pattern 401 has a substantially square shape with a side length of Ldb. More specifically, first, a component 311 is deposited on the sacrificial material 313. After coating the resist 312 on the component 311, the pattern 401 is formed by photolithography. If the pattern 400 is shifted in the Y direction, the pattern 401 is shifted in the Y direction similarly to the pattern 400.

[0225] As shown in Figure 44, the insulating layer 213 is processed using the resist 312 as a mask to form the hole pattern of the bonded pad DB. After removing the resist 312, member 311, and sacrificial material 313, the exposed insulating layer 212 is removed. This forms the hole pattern of the electrode 210.

[0226] As shown in Figure 45, the electrode 210 (bonding pad DB and contact plug CB) is formed in the same manner as described using Figure 24 of the first embodiment.

[0227] 3.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained. More specifically, the semiconductor device 1 can shift the arrangement of the contact plug VB and the bonded pad MB in the X direction relative to the M1 wiring layer 107 extending in the X direction in order to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB. By shifting the contact plug VB and the bonded pad MB in the X direction, the semiconductor device 1 can correct the X-direction misalignment between the bonded pad MB and the bonded pad DB. Furthermore, the semiconductor device 1 can shift the arrangement of the contact plug CB and the bonded pad DB in the Y direction relative to the D2 wiring layer 209 extending in the Y direction in order to correct the Y-direction misalignment between the bonded pad MB and the bonded pad DB. By shifting the contact plug CB and the bonded pad DB in the Y direction, the semiconductor device 1 can correct the Y-direction misalignment between the bonded pad MB and the bonded pad DB. As a result, the semiconductor device 1 can reduce connection failures between the bonded pad MB and the bonded pad DB due to misalignment. Therefore, the yield of the semiconductor device 1 can be improved.

[0228] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can make the length Lvbx in the X direction of the first portion 108_vb of the electrode 108 longer than the length Lmb in the X direction of the second portion 108_mb1 and the third portion 108_mb2. That is, the contact plug VB can be formed to be longer in the X direction than the hole pattern when processing the bonding pad MB. As a result, even if an alignment misalignment occurs between the contact plug VB and the bonding pad MB, the length Lvbx in the X direction of the upper surface of the contact plug VB will not vary. That is, the semiconductor device 1 can make the resistance value of the contact plug VB approximately constant. By making the resistance value of the contact plug VB approximately constant, the semiconductor device 1 can reduce connection failures between the M1 wiring layer 107 and the bonding pad MB. Similarly, the semiconductor device 1 can make the length Lcby in the Y direction of the first portion 210_cb of the electrode 210 longer than the length Ldb in the Y direction of the second portion 210_db1 and the third portion 210_db2. In other words, the contact plug CB can be formed to be longer in the Y direction than the hole pattern when processing the bonding pad DB. As a result, even if alignment misalignment occurs between the contact plug CB and the bonding pad DB of the semiconductor device 1, the Y-direction length Lcby of the upper surface of the contact plug CB will not vary. In other words, the semiconductor device 1 can maintain a nearly constant resistance value of the contact plug CB. By maintaining a nearly constant resistance value of the contact plug CB, the semiconductor device 1 can reduce connection failures between the D2 wiring layer 209 and the bonding pad DB. Therefore, the yield of the semiconductor device 1 can be improved.

[0229] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can have the contact plug VB formed to be longer in the X direction. This reduces the contact resistance between the M1 wiring layer 107 and the contact plug VB. Similarly, the semiconductor device 1 can have the contact plug CB formed to be longer in the Y direction. This reduces the contact resistance between the D2 wiring layer 209 and the contact plug CB.

[0230] 4. Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, the shapes of electrodes 108 and 210, which differ from those in the third embodiment, will be described. The following description will focus on the differences from the third embodiment.

[0231] 4.1 Cross-sectional structure of semiconductor device First, an example of the cross-sectional structure of the semiconductor device 1 will be described with reference to Figure 46. Figure 46 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 according to the fourth embodiment, along the line IV-IV in Figure 4.

[0232] As shown in Figure 46, the semiconductor device 1 of this embodiment has a structure in which the insulating layers 127 and 128 of the array chip 10 and 214 and 215 of the circuit chip 20 are eliminated, similar to the third embodiment. The length of the electrode 108 in the X direction of this embodiment is approximately the same as the length of the M1 wiring layer 107 in the X direction. Also, the length of the electrode 210, which will be described later, in the Y direction is approximately the same as the length of the D2 wiring layer 209 in the Y direction. The other structures are the same as in Figure 35 of the third embodiment.

[0233] 4.2 Structure of adhesive pads The structure of the bonded pad BP will be described with reference to Figures 47 to 51. Figure 47 is a perspective view showing an example of the structure of the M1 wiring layer 107, electrodes 108 and 210, and D2 wiring layer 209. Figure 48 is a diagram showing an example of a plan view of the electrode 108 and the M1 wiring layer 107. Figure 49 is a diagram showing an example of a plan view of the electrode 210 and the D2 wiring layer 209. Figure 50 is a cross-sectional view along the line VI-VI in Figures 48 and 49. Figure 51 is a cross-sectional view along the line VII-VII in Figures 48 and 49.

[0234] Note that the insulating layer is omitted in Figures 47 to 49. Also, in Figure 47, the contact surface between the adhesive pad MB and the adhesive pad DB is indicated by hatching to make it easier to see.

[0235] As shown in Figures 47 and 48, the length Lvbx in the X direction of the first portion 108_vb of the electrode 108 in this embodiment is approximately the same as the length Lm1x in the X direction of the M1 wiring layer 107. That is, the size of the upper surface of the first portion 108_vb is approximately the same as the size of the upper surface of the M1 wiring layer 107. For example, the distance from the X-direction end of the M1 wiring layer 107 to the X-direction end of the first portion 108_vb is 200 nm or less. More specifically, it is preferable that the length Lvbx be the length obtained by subtracting the photolithography alignment margin corresponding to the processing of the contact plug VB (first portion 108_vb) from the length Lm1x. The shapes of the second portion 108_mb1 and the third portion 108_mb2 of the electrode 108 are the same as in the third embodiment.

[0236] In this embodiment, in order to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB, the arrangement of the bonded pad MB (the second portion 108_mb1 and the third portion 108_mb2 of the electrode 108) can be shifted in the X direction relative to the M1 wiring layer 107 which extends in the X direction, without shifting the contact plug VB. This makes it possible to correct the X-direction misalignment between the bonded pad MB and the bonded pad DB.

[0237] As shown in Figures 47 and 49, the length Lcby in the Y direction of the first portion 210_cb of the electrode 210 in this embodiment is approximately the same as the length Ld2y in the Y direction of the D2 wiring layer 209. That is, the size of the upper surface of the first portion 210_cb is approximately the same as the size of the upper surface of the D2 wiring layer 209. For example, the distance from the Y-direction end of the D2 wiring layer 209 to the Y-direction end of the first portion 210_cb is 200 nm or less. More specifically, it is preferable that the length Lcby be the length obtained by subtracting the photolithography alignment margin corresponding to the processing of the contact plug CB (first portion 210_cb) from the length Ld2y. The shapes of the second portion 210_db1 and the third portion 210_db2 of the electrode 210 are the same as in the third embodiment.

[0238] In this embodiment, in order to correct the misalignment in the Y direction between the bonded pad MB and the bonded pad DB, the arrangement of the bonded pad DB (the second portion 210_db1 and the third portion 210_db2 of the electrode 210) can be shifted in the Y direction relative to the D2 wiring layer 209 which extends in the Y direction, without shifting the contact plug CB. This makes it possible to correct the misalignment in the Y direction between the bonded pad MB and the bonded pad DB.

[0239] For example, if there is no misalignment between the bonding pad MB and the bonding pad DB, and the length Lmb in the Y direction of the upper surface of the bonding pad MB and the length Ldb in the X direction of the upper surface of the bonding pad DB are approximately the same, then the shape of the contact surface between the upper surface of the bonding pad MB and the upper surface of the bonding pad DB is approximately square, as shown in Figure 8.

[0240] Next, the cross-sectional shapes of the adhesive pads MB and DB will be described.

[0241] As shown in Figure 50, for example, the cross-section in the X direction of the first portion 108_vb of electrode 108 has a trapezoidal shape in which the length Lvbx in the X direction of the upper surface of the first portion 108_vb facing the Z1 direction is longer than the length in the X direction of the lower surface of the first portion 108_vb facing the Z2 direction. The length Lvbx in the X direction of the upper surface of the first portion 108_vb is approximately the same as the length Lm1x in the X direction of the M1 wiring layer 107. The cross-section in the X direction of electrode 210 is the same as in Figure 11 of the first embodiment.

[0242] As shown in Figure 51, for example, the cross-section in the Y direction of the first portion 210_cb of electrode 210 has a trapezoidal shape in which the Y-direction length Lcby of the upper surface of the first portion 210_cb facing the Z2 direction is longer than the Y-direction length of the lower surface of the first portion 210_cb facing the Z1 direction. The Y-direction length Lcby of the upper surface of the first portion 210_cb is approximately the same as the Y-direction length Ld2y of the D2 wiring layer 209. The Y-direction cross-section of electrode 108 is the same as in Figure 12 of the first embodiment.

[0243] In this embodiment, the bonded pads MB and DB have discontinuous areas at the bonding location where the barrier metal 108_1 and barrier metal 210_1 are bonded, so the bonding can be confirmed.

[0244] 4.3 Effects according to this embodiment With the configuration according to this embodiment, the same effects as in the second embodiment can be obtained. More specifically, the semiconductor device 1 can make the size of the upper surface of the M1 wiring layer 107 and the size of the upper surface of the contact plug VB (first portion 108_vb) approximately the same. As a result, the semiconductor device 1 can shift the arrangement of the bonding pad MB (second portion 108_mb1 and third portion 108_mb2 of the electrode 108) in the X direction without shifting the contact plug VB with respect to the M1 wiring layer 107 which extends in the X direction. Therefore, the semiconductor device 1 can correct the X-direction misalignment between the bonding pad MB and the bonding pad DB. In addition, the semiconductor device 1 can make the size of the upper surface of the D2 wiring layer 209 and the size of the upper surface of the contact plug CB (first portion 210_cb) approximately the same. As a result, the semiconductor device 1 can shift the arrangement of the bonding pad DB (the second portion 210_db1 and the third portion 210_db2 of the electrode 210) in the Y direction without shifting the contact plug CB relative to the D2 wiring layer 209 which extends in the Y direction. Therefore, the semiconductor device 1 can correct the misalignment in the Y direction between the bonding pad MB and the bonding pad DB.

[0245] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can form the contact plug VB to be longer in the X direction than the hole pattern when processing the bonding pad MB, similar to the third embodiment. As a result, even if an alignment misalignment occurs between the contact plug VB and the bonding pad MB, the length Lvbx in the X direction of the upper surface of the contact plug VB will not vary. In other words, the semiconductor device 1 can make the resistance value of the contact plug VB approximately constant. By making the resistance value of the contact plug VB approximately constant, the semiconductor device 1 can reduce connection failures between the M1 wiring layer 107 and the bonding pad MB. In addition, the semiconductor device 1 can form the contact plug CB to be longer in the Y direction than the hole pattern when processing the bonding pad DB. As a result, even if an alignment misalignment occurs between the contact plug CB and the bonding pad DB, the length Lcby in the Y direction of the upper surface of the contact plug CB will not vary. In other words, the semiconductor device 1 can make the resistance value of the contact plug CB approximately constant. By keeping the resistance value of the contact plug CB approximately constant, the semiconductor device 1 can reduce connection failures between the D2 wiring layer 209 and the adhesive pad DB. Therefore, the yield of the semiconductor device 1 can be improved.

[0246] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can have the contact plug VB formed to be longer in the X direction. This reduces the contact resistance between the M1 wiring layer 107 and the contact plug VB. Similarly, the semiconductor device 1 can have the contact plug CB formed to be longer in the Y direction. This reduces the contact resistance between the D2 wiring layer 209 and the contact plug CB.

[0247] 5. Variations, etc. The semiconductor device according to the above embodiment includes a first chip (10) and a second chip (20). The first chip includes a first wiring layer (M1) extending in a first direction (X direction), and a first electrode (108) including a first contact plug (VB) provided on the first wiring layer and a first pad (MB) provided on the first contact plug. The second chip includes a second wiring layer (D2) extending in a second direction (Y direction) intersecting the first direction, and a second electrode (210) including a second contact plug (CB) provided on the second wiring layer and a second pad (DB) provided on the second contact plug and bonded to the first pad. The length (Lvbx) in the first direction of the upper surface of the first contact plug is longer than the length (Lvby) in the second direction of the upper surface of the first contact plug. The length (Lcby) in the second direction of the upper surface of the second contact plug is longer than the length (Lcbx) in the first direction of the upper surface of the second contact plug.

[0248] With the configuration according to the above embodiment, the semiconductor device 1 can improve the yield.

[0249] Note that various modifications can be applied, not limited to the above-described embodiment. For example, when wafer warpage occurs only along one of the X direction and the Y direction, in order to correct the positional deviation of the bonding pads in the direction due to the wafer warpage, the arrangement of the bonding pads may be shifted from the designed position only for one side of the wafers to be bonded.

[0250] In the above embodiment, "connection" includes a state where, for example, a transistor or a resistor or the like is interposed therebetween and indirectly connected.

[0251] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0252] 1... semiconductor device, 10... array chip, 11... memory cell array, 20... circuit chip, 21... sequencer, 22... voltage generation circuit, 23... row decoder, 24... sense amplifier, 101, 101a - 101c... semiconductor layer, 102, 105, 107, 205, 207, 209... wiring layer, 103, 104, 106, 107_2, 108_2, 109, 204, 206, 208, 209_1, 210_1... conductor, 107_1, 108_1, 209_1, 210_1... barrier metal, 108, 210... electrode, 121 - 128, 211 - 215... insulating layer, 140... block insulating film, 141... charge storage film, 142... tunnel insulating film, 143... semiconductor film, 144... core film, 145... cap film, 201... semiconductor substrate, 202... gate insulating film, 203... gate electrode, 301, 311... member, 302, 312... resist, 313... sacrificial material, BLK, BLK0 - BLK3... block, BP, DB, MB... bonding pad, CB, C0, C1, CC, CH, CS, V0, VB... contact plug, MC, MC0 - MC7... memory cell transistor, MP... memory pillar, NS... NAND string, SGD, SGD0 - SGD4... selection gate line, ST1, ST2... selection transistor, SU, SU0 - SU4... string unit, WF1, WF2... wafer, WL, WL0 - WL7... word line

Claims

1. A first wiring layer extending in the first direction, A first electrode including a first contact plug provided on the first wiring layer and a first pad provided on the first contact plug. A first chip including, A second wiring layer extending in a second direction intersecting the first direction, A second contact plug provided on the second wiring layer and a second electrode including a second pad provided on the second contact plug and bonded to the first pad, and The second chip includes Equipped with, The length of the upper surface of the first contact plug in the first direction is longer than the length of the upper surface of the first contact plug in the second direction. The length of the upper surface of the second contact plug in the second direction is longer than the length of the upper surface of the second contact plug in the first direction. Semiconductor equipment.

2. The length of the upper surface of the first contact plug in the first direction is the same as the length of the lower surface of the first pad that contacts the first contact plug in the first direction. The length of the upper surface of the second contact plug in the second direction is the same as the length of the lower surface of the second pad that contacts the second contact plug in the second direction. The semiconductor device according to claim 1.

3. The first electrode is A first portion provided on the first wiring layer, including the first contact plug and the portion of the first pad provided on the first contact plug, A second portion that is in contact with one side of the first portion facing the second direction, includes the portion of the first pad that is not included in the first portion, and does not include the first contact plug, A third portion that is in contact with the other side of the first portion facing the second direction, includes the portion of the first pad not included in the first and second portions, and does not include the first contact plug. including, The semiconductor device according to claim 1.

4. The first chip is A first insulating layer provided on the first wiring layer, through which the first contact plug passes, A second insulating layer is provided on the first insulating layer, in which the first contact plug and the first pad are connected, and which is made of a different material from the first insulating layer. A third insulating layer is provided on the second insulating layer, has an opening region through which the first pad passes, and is made of a different material from the second insulating layer. A fourth insulating layer is provided on the third insulating layer, through which the first pad passes, in contact with the second chip, and made of a different material from the third insulating layer. It further includes, One and the other side of the first pad facing the second direction are in contact with the third insulating layer, and at least one of the one and the other side facing the first direction is not in contact with the third insulating layer. The semiconductor device according to claim 1.

5. A first wiring layer extending in the first direction, A first electrode including a first contact plug provided on the first wiring layer and a first pad provided on the first contact plug. A first chip including, A second wiring layer extending in a second direction intersecting the first direction, A second contact plug provided on the second wiring layer and a second electrode including a second pad provided on the second contact plug and bonded to the first pad, and The second chip includes Equipped with, The first electrode is A first portion provided on the first wiring layer, including the first contact plug and the portion of the first pad provided on the first contact plug, A second portion that is in contact with one side of the first portion facing the second direction, includes the portion of the first pad that is not included in the first portion, and does not include the first contact plug, A third portion that is in contact with the other side of the first portion facing the second direction, includes the portion of the first pad not included in the first and second portions, and does not include the first contact plug. Includes, The first portion includes a central portion sandwiched between the second and third portions, and protruding portions projecting from both ends of the second and third portions in the first direction to one side and the other side in the first direction, respectively. Semiconductor equipment.

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