Semiconductor equipment
The semiconductor device addresses high reverse current peaks and recovery charge amounts by employing tailored semiconductor regions and grooves, achieving reduced Irp and Qrr without degrading RRSOA.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SANKEN ELECTRIC CO LTD
- Filing Date
- 2025-01-08
- Publication Date
- 2026-07-21
AI Technical Summary
Existing semiconductor devices with IGBT and FWD in antiparallel connection exhibit high reverse current peaks (Irp) and reverse recovery charge amounts (Qrr), which are not effectively addressed by existing technologies.
A semiconductor device design with specific semiconductor regions and grooves, including wider and narrower trenches, and impurity concentration variations, to manage current flow and reduce reverse current peaks and recovery charge without compromising the Reverse Recovery Safe Operating Area (RRSOA).
The design effectively reduces reverse current peaks and recovery charge amounts while maintaining or enhancing the RRSOA, improving operational efficiency.
Smart Images
Figure 2026120053000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device in which an IGBT and an FWD are connected in antiparallel, and in which the peak of the reverse current (Irp) and the reverse recovery charge amount (Qrr) are reduced.
Background Art
[0002] As a switching element for driving a motor or the like, a semiconductor device in which an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode) are connected in antiparallel is known. The FWD connected in antiparallel to the IGBT serves to protect the IGBT from the reflux current caused by the back electromotive force generated in the coil of the motor or the like.
[0003] A reverse conducting IGBT (RC-IGBT) in which an IGBT region and an FWD region are formed on the same semiconductor substrate and miniaturization and bonding wires are reduced is known. In order to improve the operating characteristics of the reverse conducting IGBT, it is necessary to improve the respective operating characteristics of the IGBT region and the FWD region formed on the same semiconductor substrate. In the reverse conducting IGBT of Patent Document 1, an example in which the depth of the anode region 17 is formed deeper than the diode trench 19 in the FWD region is disclosed. It is described that the RRSOA (Reverse Recovery Safe Operating Area) can be improved in the reverse conducting IGBT.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] However, the semiconductor device described in Patent Document 1 exhibited high reverse current peaks (Irp) and reverse recovery charge amounts (Qrr).
[0006] Therefore, this disclosure has been made in view of the above problems, and aims to provide a semiconductor device that can reduce the reverse current peak (Irp) and reverse recovery charge amount (Qrr) without reducing RRSOA. [Means for solving the problem]
[0007] To achieve the above objective, this disclosure provides a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region and having a conductivity type opposite to the first conductivity type, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a fourth semiconductor region of the second conductivity type located on the first semiconductor region and on the opposite side from the second semiconductor region, a first groove penetrating the second semiconductor region, a control electrode disposed within the first groove via an insulating film facing the second semiconductor region, and electrically connected to the third semiconductor region. The present invention provides a semiconductor device comprising: a first element region including a first main electrode and a second main electrode electrically connected to the fourth semiconductor region; a fifth semiconductor region of a second conductivity type located on the first semiconductor region and electrically connected to the first main electrode; a sixth semiconductor region of a first conductivity type located on the first semiconductor region and on the opposite side from the fifth semiconductor region, and electrically connected to the second main electrode; and a second element region including a second groove that is wider than the first groove and has its bottom located within the fifth semiconductor region. Furthermore, it is preferable that the width of the fifth semiconductor region adjacent to the second groove is narrower than the width of the second semiconductor region adjacent to the first groove. Furthermore, it is preferable that the ratio of the width of the second groove to the width of the fifth semiconductor region sandwiched between adjacent second grooves is greater than the ratio of the width of the first groove to the width of the second semiconductor region sandwiched between adjacent second grooves. Furthermore, it is preferable that a seventh semiconductor region of a first conductivity type is included between the first semiconductor region and the second semiconductor region, which is deeper than the bottom of the first groove and has a higher impurity concentration than the first semiconductor region, and that the fifth semiconductor region is formed to be deeper than the second semiconductor region and shallower than the seventh semiconductor region. Furthermore, it is preferable that the seventh semiconductor region extends to the area between the fifth semiconductor region and the first semiconductor region on the first device region side. [Effects of the Invention]
[0008] As described above, the semiconductor device of this disclosure can reduce the reverse current peak (Irp) and reverse recovery charge amount (Qrr) without reducing RRSOA. [Brief explanation of the drawing]
[0009] [Figure 1] This is a cross-sectional view illustrating an embodiment of a semiconductor device in the present disclosure. [Figure 2] This is a cross-sectional view showing a conventional semiconductor device. [Modes for carrying out the invention]
[0010] The following describes the embodiments for implementing the semiconductor device described herein. However, the semiconductor device described herein is not limited in any way to the following description.
[0011] Embodiments of the semiconductor device of this disclosure will be described in detail with reference to the drawings. The drawings are schematic, and the relationships between thickness and dimensions, as well as the thickness and ratios of each layer, are examples only and do not limit the technical concept of the invention. Furthermore, the relationships between dimensions and ratios may differ between drawings. In the following description, when describing the positional relationships of components, terms such as "top," "bottom," "right," and "left" will be used as necessary based on the orientation of the referenced drawing, but do not limit the technical concept of the invention. Also, terms such as "top," "bottom," "right," and "left" may be used even if the components are not in contact. Furthermore, "impurity concentration" refers to the effective concentration of impurity elements that contribute to the conductivity of the semiconductor. For example, if a semiconductor contains an n-type impurity element that acts as a donor and a p-type impurity element that acts as an acceptor, the concentration of one impurity element after subtracting the amount that is offset by the other element is defined as the "impurity concentration." Furthermore, unless otherwise specified, the impurity concentration of a semiconductor layer or semiconductor region refers to the maximum impurity concentration in each semiconductor layer or semiconductor region.
[0012] A semiconductor device 40 according to an embodiment of the present disclosure will be described. Figure 1 is a diagram showing a semiconductor device 40 in an embodiment of the present disclosure. The semiconductor device 40 is provided with an IGBT region (first element region) 20 and an FWD diode region (second element region) 30. The IGBT region 20 and the diode region 30 may be arranged alternately, or the IGBT region 20 and the diode region 30 may be arranged such that, when the semiconductor device 40 is viewed in plan, at least a part of the IGBT region 20 is surrounded from the outside by the diode region 30.
[0013] The IGBT region 20 comprises a drift region 1 of the first conductivity type (N-type), a base region 2 of the second conductivity type (P-type) on the drift region 1, and an emitter region 3 of the first conductivity type (N-type) on the base region 2. A first trench 9 is formed to penetrate the base region 2, and the emitter region 3 is formed on the side wall of the first trench 9. A collector region 4 of the second conductivity type (P-type) is provided below the drift region 1, and a field stop (FS) layer 7 of the first conductivity type (N-type) with a higher impurity concentration than that of the drift region 1 is provided between the drift region 1 and the collector region 4. A carrier storage layer (FN layer) 8 of the first conductivity type (N-type) with a higher impurity concentration than that of the drift region 1 is provided between the drift region 1 and the base region 2. In Figure 1, the first trench 9 does not penetrate the carrier storage layer 8, but it may penetrate the carrier storage layer 8. The first trench 9 contains a control electrode 10 made of conductive polysilicon via an insulating film. Above the control electrode 10, a first main electrode 5 is provided via an interlayer insulating film 11. The first main electrode 5 is electrically connected to the emitter region 3 with low resistance, and the second main electrode 6 is electrically connected to the collector region 4 with low resistance.
[0014] The diode region 30 comprises a drift region 1, a second conductivity type (P-type) anode region 12 and a second trench 14 on the drift region 1. The anode region 12 is electrically connected to the first main electrode 5 with low resistance. A cathode region 13 is provided on the opposite side of the drift region 1 from the anode region 12. The cathode region 13 is electrically connected to the second main electrode 6. In the diode region 30, a field stop layer 7 extending from the IGBT region 20 may also be provided between the cathode region 13 and the drift region 1.
[0015] The anode region 12 is formed deeper than the base region 2 and shallower than the carrier storage layer 8. This makes it difficult for holes that have moved from the collector region 4 into the drift region 1 to move to the anode region 12, and instead accumulate in the drift region 1 directly beneath the carrier storage layer 8, thereby reducing on-resistance. Furthermore, the impurity concentration in the anode region 12 may be lower than that in the base region 2. This can reduce the peak (Irp) of the reverse current. Furthermore, it is desirable that the carrier storage layer 8 provided in the IGBT region 20 extends to the anode region 12 on the IGBT region 20 side (the diode region 30 on the IGBT region 20 side) and covers the corner portion of the anode region 12. However, it is desirable that the carrier storage layer 8 is not provided between the anode region 12 and the drift region 1 of the diode region 30. By not providing the carrier storage layer 8, the depletion layer spreading from the interface between the anode region 12 and the drift region 1 can be further widened, thereby ensuring the breakdown voltage of the diode region 30.
[0016] The second trench 14 does not penetrate the anode region 12, and the bottom of the second trench 14 is covered by the anode region 12. An auxiliary electrode 15 made of conductive polysilicon is provided at the bottom and side walls of the second trench 14 via an insulating film. The auxiliary electrode 15 is electrically connected to the first electrode 5. The depth of the bottom of the second trench 14 may be the same as the depth of the bottom of the first trench 9. Alternatively, the first electrode 5 may not be provided in the second trench 14, and the inside of the second trench 14 may be filled with an insulating film. Also, the auxiliary electrode 15 may not be electrically connected to the first electrode 5, but may be electrically connected to the control electrode 10.
[0017] Here, the width t3 of the second trench 14 provided in the diode region 30 is wider than the width t1 of the first trench 9 provided in the IGBT region 20. Furthermore, it is desirable that the width t3 of the second trench 14 is wider than the width t4 of the semiconductor region sandwiched between the second trenches 14. Also, it is desirable that the ratio of the width t3 of the second trench 14 to the width t4 of the semiconductor region sandwiched between the second trenches 14 is greater than the ratio of the width t1 of the first trench 9 to the width t2 of the semiconductor region sandwiched between the first trenches 9. In other words, it is desirable that (t1 / t2) < (t3 / t4).
[0018] As a result, the width t4 of the semiconductor region sandwiched between the second trenches 14 becomes narrow, the holes moving from the first main electrode 5 through the space between the second trenches 14 to the drift region 1 decrease, and the peak of the reverse current (Irp) and the reverse recovery charge amount (Qrr) can be reduced. By preventing the diode region 30 from decreasing, the peak of the reverse current (Irp) and the reverse recovery charge amount (Qrr) can be reduced without degrading the RRSOA.
[0019] Note that other layers can be appropriately added or deleted to the matters described in the semiconductor device 40 according to the present disclosure. Also, it is clear that the same configuration can be applied even when all of the p-type and n-type in the semiconductor are reversed in the above example.
[0020] This specification includes the following aspects. [1]: A first element region including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type that is on the first semiconductor region and has a conductivity type opposite to the first conductivity type, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a fourth semiconductor region of the second conductivity type that is on the first semiconductor region and provided on the opposite side of the second semiconductor region, a first groove penetrating the second semiconductor region, a control electrode disposed via an insulating film facing the second semiconductor region in the first groove, a first main electrode electrically connected to the third semiconductor region, and a second main electrode electrically connected to the fourth semiconductor region; a fifth semiconductor region of the second conductivity type that is on the first semiconductor region and electrically connected to the first main electrode; a sixth semiconductor region of the first conductivity type that is on the first semiconductor region, provided on the opposite side of the fifth semiconductor region, and electrically connected to the second main electrode; and a second groove that is wider than the first groove and has a bottom in the fifth semiconductor region. [[ID=
[13] ] [2]: The semiconductor device according to [1] above, wherein the width of the fifth semiconductor region adjacent to the second groove is narrower than the width of the second semiconductor region adjacent to the first groove. [3]: The semiconductor device of [1] wherein the ratio of the width of the second groove to the width of the fifth semiconductor region sandwiched between adjacent second grooves is greater than the ratio of the width of the first groove to the width of the second semiconductor region sandwiched between adjacent second grooves. [4]: The semiconductor device according to [1], [2], or [3], wherein a seventh semiconductor region of a first conductivity type is located between the first semiconductor region and the second semiconductor region, the seventh semiconductor region being deeper than the bottom of the first groove and having a higher impurity concentration than the first semiconductor region, and the fifth semiconductor region is formed to be deeper than the second semiconductor region and shallower than the seventh semiconductor region. [5]: The semiconductor device of [4] wherein the seventh semiconductor region extends to the space between the fifth semiconductor region and the first semiconductor region on the first element region side. [Explanation of symbols]
[0021] 1. Drift region 2 Base area 3. Emitter region 4. Collector area 5. First main electrode 6. Second main electrode 7 Field Stop Layer 8. Carrier storage layer 9. The first trench 10 Control electrodes 11 Interlayer insulating film 12 Anode Region 13. First main electrode 14. The Second Trench 15 Auxiliary electrode 20 IGBT region (first device region) 30 Diode region (second element region) 40 Semiconductor Equipment
Claims
1. The first semiconductor region of the first conductivity type, A second semiconductor region having a second conductivity type opposite to the first conductivity type, located on the first semiconductor region, A third semiconductor region of the first conductivity type is provided on the second semiconductor region, A fourth semiconductor region of second conductivity type is provided on the first semiconductor region, on the side opposite to the second semiconductor region, A first groove that penetrates the second semiconductor region, A control electrode is disposed within the first groove, with an insulating film facing the second semiconductor region, The first main electrode is electrically connected to the third semiconductor region, A second main electrode electrically connected to the fourth semiconductor region, A first element region including, A fifth semiconductor region of second conductivity type located on the first semiconductor region and electrically connected to the first main electrode, A sixth semiconductor region of first conductivity type is provided on the first semiconductor region on the side opposite to the fifth semiconductor region and is electrically connected to the second main electrode, A second groove that is wider than the first groove and has its bottom within the fifth semiconductor region, A semiconductor device comprising a second element region including a ...
2. The semiconductor device according to claim 1, characterized in that the width of the fifth semiconductor region adjacent to the second groove is narrower than the width of the second semiconductor region adjacent to the first groove.
3. The semiconductor device according to claim 1, characterized in that the ratio of the width of the second groove to the width of the fifth semiconductor region sandwiched between adjacent second grooves is greater than the ratio of the width of the first groove to the width of the second semiconductor region sandwiched between adjacent second grooves.
4. Between the first semiconductor region and the second semiconductor region, there is a seventh semiconductor region of a first conductivity type which is deeper than the bottom of the first groove and has a higher impurity concentration than the first semiconductor region. The semiconductor device according to any one of claims 1 to 3, characterized in that the fifth semiconductor region is formed to be deeper than the second semiconductor region and shallower than the seventh semiconductor region.
5. The semiconductor device according to claim 4, characterized in that the seventh semiconductor region extends to the area between the fifth semiconductor region and the first semiconductor region on the first element region side.