Transistor with vertical structure including gate insulating layer and method for manufacturing the same

Abstract

This provides a method for manufacturing a vertically structured semiconductor device. [Solution] A method for manufacturing a vertically structured GAA semiconductor element 1, comprising the steps of: forming a first insulator 210 on a substrate, a source 110 on the first insulator, a second insulator 220 placed on the source, a gate 120 on the second insulator, a third insulator 230 on the gate, and a drain 130 on the third insulator; forming a hole V penetrating the drain, the third insulator, the gate, the second insulator, and the source; and forming an insulating layer on the inner surface of the gate by growing a shielding material on the remaining inner surface excluding the inner surface of the gate formed by the hole.

Description

[Technical Field]

[0001] This disclosure relates to a vertical structure transistor including a gate insulating layer and a method for manufacturing the same, and provides a vertical structure transistor including a gate insulating layer formed by selectively depositing a shielding material. [Background technology]

[0002] To overcome the short-channel effect by developing 3D semiconductor devices, various 3D structures such as FinFETs, Gate-All-Around (GAA), and Channel-All-Around (CAA) are currently being researched. Among these, there is a growing demand for vertically structured three-dimensional field-effect transistors, which offer advantages in terms of integration density and channel control. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] In existing vertically structured three-dimensional field-effect transistors, conventional processes form an insulating film between the source, drain, and channel, and process limitations place a significant burden on the electrical connection between the source, drain, and channel. Research is also being conducted on using wet etching to form a trench structure on the gate in order to form an insulating film only between the gate and channel, but there are limitations to process control, making it difficult to realize transistors on the nanometer (nm) scale.

[0004] Therefore, in order to overcome the conventional process limitations, the semiconductor element with a vertical structure including a gate insulating layer according to multiple embodiments and the method for manufacturing the same can provide a manufacturing method in which an insulating layer is formed only between the gate and channel of a vertical structure transistor, based on an AS-ALD process utilizing self-assembled monolayers (SAMs).

[0005] Furthermore, the vertical structure semiconductor elements including a gate insulating layer according to multiple embodiments and the method for manufacturing the same can provide memory semiconductor structures including transistors of various structures such as CAA and GAA, which allow control of the overall channel characteristics (e.g., conductivity) of the implemented vertical structure transistors.

[0006] The problems that this application seeks to solve are not limited to those described above, and any problems not mentioned should be clearly understood by those skilled in the art from this specification and the drawings. [Means for solving the problem]

[0007] According to several embodiments, a method for manufacturing a vertically structured semiconductor element is described below. The steps include forming a first insulator on a substrate, a first conductor on the first insulator, a second insulator placed on the first conductor, a gate on the second insulator, a third insulator on the gate, and a second conductor on the third insulator, The steps include forming a hole that penetrates the second conductor, the third insulator, the gate, the second insulator, and the first conductor, The steps include forming an insulating layer on the inner surface of the gate by growing SAM on the remaining inner surface excluding the inner surface of the gate formed by the hole, A manufacturing method is provided, which includes the step of forming a channel layer along the same plane in which the inner surface of the second conductor, the inner surface of the third insulator, the inner surface of the insulating layer, the inner surface of the second insulator, and the inner surface of the first conductor are formed.

[0008] According to several embodiments, the semiconductor device is The first conductor and, A first insulator disposed on the first conductor, A gate placed on the first insulator, A second insulator is placed on the gate, A second conductor disposed on the second insulator, A channel layer formed along the inner surface formed by holes that penetrate vertically through the second conductor, the second insulator, the gate, and the first insulator, The channel layer and the gate are disposed between the channel layer and the gate, A semiconductor device is provided in which, of the first conductor and the second conductor, one is a source and the other is a drain, and the inner surface of the second conductor, the inner surface of the second insulator, the inner surface of the insulating layer, and the inner surface of the first insulator, formed by the hole, form a coplanar plane, and the channel layer is formed along the coplanar plane.

[0009] The means of solving the problem are not limited to those described above, and any means of solving that are not mentioned should be clearly understood by those skilled in the art from this specification and the drawings. [Effects of the Invention]

[0010] According to several examples, a manufacturing method is provided in which an insulating layer is formed only between the gate and channel of a vertically structured transistor, based on an AS-ALD process utilizing self-assembled monolayers (SAMs).

[0011] Furthermore, according to several embodiments, a memory semiconductor structure is provided that includes transistors in the embodied vertical structure that allow control of the overall channel characteristics (e.g., conductivity). [Brief explanation of the drawing]

[0012] [Figure 1] This is a perspective view illustrating the general structure of a GAA semiconductor device. [Figure 2] Figure 1 is a perspective view showing the inside of the GAA semiconductor device. [Figure 3] Figures 1 and 2 show a cross-sectional view of the GAA semiconductor device shown, cut in the xz plane with respect to axis (c), along with a comparison of the two devices. [Figure 4]This is a diagram for explaining an example of a method for manufacturing a GAA semiconductor device according to multiple embodiments. [Figure 5] This is a diagram for explaining an example of a method for selectively removing a SAM to form an insulating layer only between a gate and a channel layer according to multiple embodiments. [Figure 6] This is a diagram for explaining an example of a method for selectively attaching a SAM to form an insulating layer only between a gate and a channel layer according to multiple embodiments. [Figure 7] This is a diagram showing an example of a SAM according to multiple embodiments. [Figure 8] This is a diagram showing a structure in which multiple GAA semiconductor devices with a vertical structure are connected according to multiple embodiments. [Figure 9a] This is a diagram showing a manufacturing method of a structure in which multiple GAA semiconductor devices with a vertical structure are connected according to multiple embodiments. [Figure 9b] This is a diagram showing a manufacturing method of a structure in which multiple GAA semiconductor devices with a vertical structure are connected according to multiple embodiments. [Figure 10a] This is a diagram showing an example of a structure in which a GAA semiconductor device and a CAA semiconductor device are combined according to multiple embodiments. [Figure 10b] This is a diagram for explaining an example of the operation of a structure according to multiple embodiments. [Figure 11] This is a diagram showing an example of a structure in which a GAA semiconductor device and a CAA semiconductor device are combined according to multiple embodiments. [Figure 12] This is a diagram for explaining an example of the operation of a structure according to multiple embodiments. [Figure 13] This is a diagram for explaining an example of a structure in which an oxygen tunnel is formed according to multiple embodiments.

Modes for Carrying Out the Invention

[0013] The specific structural and functional descriptions for some embodiments are merely illustrative for the purpose of illustrating those embodiments, and the embodiments may be carried out in multiple forms and should not be construed as being limited to the embodiments described herein or in this application.

[0014] Multiple embodiments can be modified and take on various forms; therefore, multiple embodiments are illustrated in the drawings and described in detail with respect to this specification or this application. However, it should be understood that the matters disclosed in the drawings are not intended to specify or limit the multiple embodiments, but rather to include all modifications, equivalents, and substitutes that fall within the concept and technical scope of the multiple embodiments.

[0015] The terms "First" and / or "Second," etc., are used to describe multiple components, but the components are not limited by such terms. The terms are for the sole purpose of distinguishing one component from another; for example, provided that this does not deviate from the scope of rights under the concepts of this disclosure, a first component may be named as a second component, and a similar second component may be named as a first component.

[0016] When any component is referred to as being "linked" or "connected" to another component, it can be understood that it may be directly linked or connected to the other component, but there may also be other components in between. Conversely, when any component is referred to as being "directly linked" or "directly connected" to another component, it must be understood that there are no other components in between. Other expressions describing the relationship between components, such as "between," "just between," "adjacent to," and "directly adjacent to," should be interpreted in the same way.

[0017] The terms used herein are used solely to describe specific embodiments and do not limit any embodiments. A singular expression includes plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “includes” or “having” specify the presence of a particular feature, figure, stage, operation, component, part, or combination thereof, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, stages, operations, components, parts, or combinations thereof.

[0018] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as those commonly understood by those skilled in the art. Terms that are commonly used and predefined should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as ideal or overly formal unless explicitly defined herein.

[0019] The present disclosure will be described in detail below by referring to the drawings to describe preferred embodiments thereof. The same reference numerals in each drawing indicate the same component.

[0020] According to several embodiments, the semiconductor device is The first conductor and, A first insulator disposed on the first conductor, A gate placed on the first insulator, A second insulator is placed on the gate, A second conductor disposed on the second insulator, A channel layer formed along the inner surface formed by holes that penetrate vertically through the second conductor, the second insulator, the gate, and the first insulator, The channel layer and the gate are disposed between the channel layer and the gate, A semiconductor device is provided in which, of the first conductor and the second conductor, one is a source and the other is a drain, and the inner surface of the second conductor, the inner surface of the second insulator, the inner surface of the insulating layer, and the inner surface of the first insulator, formed by the hole, form a coplane, and the channel layer is formed along the coplane.

[0021] According to several embodiments, a semiconductor device is provided in which the insulating layer is formed between the inner surface of the gate and the channel layer.

[0022] According to several embodiments, a semiconductor device is provided in which the insulating layer is formed on the inner surface of the gate as the insulating layer material is deposited while the SAM is grown on the remaining portion other than the gate.

[0023] According to several embodiments, a semiconductor device is provided in which the functional groups of the SAM are configured to prevent the deposition of the insulating layer material.

[0024] According to several embodiments, a semiconductor device is provided in which an additional insulating layer and an additional gate are formed in the hole, and the conductivity of the channel layer can be adjusted by the additional gate.

[0025] According to several embodiments, a method for manufacturing a vertically structured semiconductor element is described below. The steps include forming a first insulator on a substrate, a first conductor on the first insulator, a second insulator placed on the first conductor, a gate on the second insulator, a third insulator on the gate, and a second conductor on the third insulator, The steps include forming a hole that penetrates the second conductor, the third insulator, the gate, the second insulator, and the first conductor, The steps include forming an insulating layer on the inner surface of the gate by growing SAM on the remaining inner surface excluding the inner surface of the gate formed by the hole, A manufacturing method is provided, which includes the step of forming a channel layer along the same plane formed by the inner surface of the second conductor, the inner surface of the third insulator, the inner surface of the insulating layer, the inner surface of the second insulator, and the inner surface of the first conductor.

[0026] According to several embodiments, a manufacturing method is provided in which the functional groups of the SAM are configured to prevent the deposition of the insulating layer material.

[0027] According to several embodiments, the step of forming an insulating layer on the inner surface of the gate is: The steps include growing the SAM on the inner surface formed by the hole, The steps include selectively etching only the aforementioned gate for a predetermined time, A manufacturing method is provided, which includes the step of depositing the insulating layer onto a trench structure formed on the gate, with the SAM grown on the remaining portion excluding the gate.

[0028] According to several embodiments, a manufacturing method is provided in which the etching time is ~.

[0029] According to several embodiments, the step of forming an insulating layer on the inner surface of the gate is: The step of making the inner surface formed by the aforementioned hole hydrophilic, The steps include selectively etching only the aforementioned gate for a predetermined time, The step of growing the SAM only on the remaining portion, with the gate removed, in a state where the remaining portion is hydrophilic, A manufacturing method is provided, which includes the step of depositing the insulating layer onto a trench structure formed on the gate, with the SAM grown on the remaining portion excluding the gate.

[0030] Figure 1 is a schematic perspective view showing the structure of the GAA semiconductor device (1). Figures 2 and 3 will be used to further explain Figure 1.

[0031] Figure 2 is a perspective view showing the interior of the GAA semiconductor device (1) shown in Figure 1. Figure 3 shows a cross-sectional view of the GAA semiconductor device (1) shown in Figures 1 and 2, cut in the xz plane with respect to axis (c), along with a comparative example.

[0032] According to several embodiments, as shown in Figures 1 to 2, the GAA semiconductor device (1) may include a first insulator (210), a source (110) disposed on the first insulator (210), a second insulator (220) disposed on the source (110), a gate (120) disposed on the second insulator (220), a third insulator (230) disposed on the gate (120), a drain (130) disposed on the third insulator (230), a channel layer (300), and an insulating layer (400) formed between the gate (120) and the channel layer (300).

[0033] Referring to Figures 1 and 2, the GAA semiconductor element (1) may include holes (V) (or grooves) penetrating a portion (220, 230) of the insulator (210, 220, 230), the source (110), the gate (120), and the drain (130). However, other transistors may be further formed in the holes (V), for example, channel all-around (CAA) transistors may be formed.

[0034] Without limiting to the examples described and / or shown in the figures, the source (110) may be embodied in the drain (210), and the drain (210) may be embodied in the source (110).

[0035] According to several embodiments, the source (110), the gate (120), and the drain (130) may be conductors. The source (110), the gate (120), and the drain (130) can be composed of TiN, TaN, WN, TiSiN, WSiN, ITO, IZO, ZTO, Poly-Si, Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, Pt, Rh, Re, Ru, Sb, Ta, Te, Ti, V, W, Zr, Zn, Mxene, or PEDOT:PSS, or a combination thereof. A void space can be formed in the central region of the source (110), the gate (120), and the drain (130) by the hole (300).

[0036] According to several embodiments, the insulators (210, 220, 230) and the insulating layer (400) may include, for example, SiNx, SiO2, SiCN, SiBN, SiON, SiCN, SiBCN, SiOC, or combinations thereof. Each of the insulators (210, 220, 230) is positioned between the source (110), the gate (120), and the drain (130) to provide electrical insulation between them. The insulating layer (400) is positioned between the channel layer (300) and the gate (120) to provide electrical insulation between them.

[0037] According to several embodiments, the channel layer (300) can be composed of a material that allows electron movement. For example, the channel layer (300) can be IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, CNT, Graphene, Transition Metal Dichalcogenide (MoSe2, WSe2) MoS2, WS2), InSe, Silicon, SiC, GaN, AIN, Ge, SiGe, GaAs, InGaAs, Poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), polypyrrole, polythiophene, polyphenylene, polyphenylene vinylene, Poly(3,4-ethylenedioxythiophene):tosylate (PEDOT:TOS), poly(6-(thiophen-3-yl)hexane-1-sulfonate)tetrabutylammonium (PTHS), poly(4-(2,3-dihydrothieno[3,4-b][1,4]dioxin-2-yl-methoxy)-1-butanesulfonic acid) (PEDOT-S), poly(2-(3,3'bis(2-(2-(2-(methoxyethoxy)ethoxy) The semiconductor may be ethoxy))-[2,2'bithiophene]-5-yl)thieno[3,2-B]thiophene)(p(g2T-TT)), and poly((ethoxy)ethyl 2-(2-(2-methoxyethoxy)ethoxy)acetate)-naphthalene-1,4,5,8-tetracarboxyl-diimide-co-3,3'bis(2-(2-(2-methoxyethoxy)ethoxy)ethoxy)-(bithiophene)(p(gNDI-g2T)), or a combination thereof. Preferably, the semiconductor layer (330) may be composed of IGZO (InGaZnO) which has low leakage current and excellent electron mobility.

[0038] According to several embodiments, the channel layer (300) may be formed on the drain (130), on the side surface of the empty space between the drain (130), the third insulator (230), the insulating layer (400), the second insulator (220), and the source (110), and on top of the first insulator (210). That is, the inner surface of the empty space of the GAA semiconductor element (1) formed by the hole (V) can be covered by the channel (300). Accordingly, the channel layer (300) may be formed in the vertical direction (e.g., the z-axis), which can be defined as the semiconductor element having a vertical structure. The channel layer (300) may also be surrounded by the source (110), the gate (120), and the drain (130).

[0039] The channel layer (300) allows the source (110) and the drain (210) to be electrically connected. The current flow in the channel layer (300) can be controlled by the voltage (VG) applied to the gate (120) surrounding the channel layer (300). Figure 3(b) shows a cross-section of the gate (120) of the semiconductor element (1) cut in the xy plane. Referring to Figure 3(b), the outer surface of the channel layer (300) is surrounded by the gate (120), which allows the influence of the voltage (VG) applied to the gate (120) on the channel layer (300) to be greatly increased. This can be defined as having a high degree of control over the channel layer (300). At this time, the insulating layer (400) can improve electrical stability by electrically insulating the channel layer (300) and the gate (120) from each other.

[0040] Figure 3(a) shows a GAA semiconductor element (1) on which the AS-ALD substrate insulating layer (400) proposed by the present invention is formed, and Figure 3(b) shows a semiconductor element on which the insulating layer (400) is formed by a general process. In the case of Figure 3(b), according to the general process, the source (110) and drain (210) are not electrically connected to the channel layer (300) by the insulating layer (400), making it difficult for the transistor element to operate. Therefore, as will be explained later with reference to Figures 4 to 7, a method is needed in which the insulating layer (400) is formed only between the gate (120) and the channel layer (300) by the manufacturing method of the present invention.

[0041] The channel layer (300) can be formed flat without any portions protruding and / or recessed into the internal space formed by the holes (V). For example, the inner surfaces of the third insulator (230), the drain (130), the second insulator (220), the insulating layer (400), and the source (110) can form the same plane. In other words, the distances from the central axis (c) to the inner surfaces of the third insulator (230), the drain (130), the second insulator (220), the insulating layer (400), and the source (110) can correspond to each other. By forming the channel layer (300) on the formed plane, the shortest distance channel can be formed, thereby improving the performance of the semiconductor device (1).

[0042] However, the examples described are not limited to those described, and the inner surface of the insulating layer (400) may be formed at a greater distance from the central axis (c) than the other parts, and the region of the channel layer (300) located on the inner surface of the insulating layer (400) may be embodied in a recessed manner.

[0043] Figure 4 is a diagram illustrating examples of methods for manufacturing a semiconductor device (1) according to multiple embodiments. Figures 5 to 7 will be used to further explain Figure 4 below.

[0044] Figure 5 illustrates an example of a method for selectively removing SAM and forming an insulating layer (400) only between the gate (120) and the channel layer (300), according to multiple embodiments. Figure 6 illustrates an example of a method for selectively adhering SAM and forming an insulating layer (400) only between the gate (120) and the channel layer (300), according to multiple embodiments. Figure 7 shows an example of SAM according to multiple embodiments.

[0045] Referring to Figure 4(a), the manufacturing method may include the steps of forming a first insulator (210) on a substrate (not shown), a source (110) on the first insulator (210), a second insulator (220) placed on the source (110), a gate (120) on the second insulator (220), a third insulator (230) on the gate (120), and a drain (130) on the third insulator (230).

[0046] Referring to Figure 4(b), the manufacturing method may include the step of forming a hole (V) that penetrates the drain (130), the third insulator (230), the gate (120), the second insulator (220), and the source (110). The hole (V) may expose a portion of the surface of the first insulator (210) to the outside.

[0047] Referring to Figure 4(c), the manufacturing method may include the step of forming an insulating layer (400) from the inner surface of the gate (120) into the hole (V) with a predetermined thickness, extending from the central axis (c) in the direction of the gate (120).

[0048] Referring to Figures 5 to 6, in order to form the insulating layer (400), the inner surface of the gate (120) may be etched to a predetermined thickness, and the insulating layer (400) may be formed on the etched portion, based on forming a shielding material in the remaining area of ​​the hole (V) other than the inner surface of the gate (120) (for example, the inner surface of the source (130), insulating layers (220, 230), drain (110), and the area exposed by the groove (V) of the first insulating layer (210)).

[0049] For example, the shielding material may include self-assembled monolayers (SAM(500)) and precursors, as described later, as materials (or substances) for preventing (or suppressing) the formation of the insulating layer (400). Specific examples of the shielding material are described below.

[0050] In one embodiment, an AS-ALD process can be performed in which self-assembled monolayers (SAM(500)) are grown on the inner surface formed by the holes (V), the inner surface of the gate (120) is etched to a predetermined thickness, and an insulating layer (400) is formed on the etched portion of the gate (120).

[0051] According to several embodiments, the SAM(500) may be embodied in such a way as to prevent the adhesion of material for forming the insulating layer (400). For example, the SAM(500) may have a hydrophilic end and an outward-facing hydrophobic end. The hydrophobic end can prevent the formation of material for the insulating layer (400).

[0052] For example, Figure 7(a) shows one example of SAM(500). Referring to Figure 7(a), the SAM(500) may include a functional group (710), a spacer (720), and a reactor (730).

[0053] The reactor (710) may have water-repellent properties to prevent the formation of the insulating layer (400) material.

[0054] The spacer (720) may be a long-chain molecule. It may be polar, nonpolar, positively charged, negatively charged, or uncharged. For example, saturated, unsaturated, linear, or branched hydrocarbon or halogenated hydrocarbon-containing groups can be used. The term hydrocarbon as used herein may refer to linear, branched, and ring-shaped fatty and aromatic groups, and may typically include alkyl, alkenyl, alkynyl, cycloalkyl, cycloalkylalkyl, aryl, arylalkyl, arylalkenyl, and arylalkynyl groups. The term "hydrocarbon-containing group" also permits the presence of atoms other than carbon and hydrogen, usually, for example, oxygen and / or nitrogen. For example, one or more methylene oxides, ethylene oxides, or moieties may be present in the hydrocarbon-containing group, and alkylated amino groups can also be useful. Appropriately, a hydrocarbon group may contain up to 35 carbon atoms, usually up to 30 carbon atoms, and more typically up to 20 carbon atoms. Corresponding halogenated hydrocarbons, especially fluorinated hydrocarbons, can also be used. These fluorinated hydrocarbons have the general formula (F(CF2) k (CH2) l ) is shown as such, where k is an integer typically between 1 and 30, and l is an integer typically between 0 and 6. More preferably, k is an integer between 5 and 20, particularly between 8 and 18. Of course, the foregoing provides a preferred range for the values ​​of k and l, but it is recognized that the specific selection of k and l may be modified according to the principles of the present invention. It is further recognized that the term “hydrocarbon-containing group” also allows for the presence of atoms other than carbon and hydrogen, typically O or N, as described above. The hydrocarbon spacer groups described above also include C 1-6 Alkyl, phenyl, C 1-6 Haloalkyl, hydroxy, C 1-6 Alcoxy, C 1-6 Alcoxialkyl, C 1-6 Alcoccine C 1-6 Alcoccine, aryloxy, keto, C2-6 Alkoxycarbonyl, C 2-6 Alkoxycarbonyl C 1-6 Alkyl, C 2-6 Alkylcarbonyloxy, arylcarbonyloxy, reelcarbonyl, amino, mono- or di-(C 1-6 ) alkylamino and other well-known alternatives in the art, or can be additionally substituted with any other suitable alternatives known in the art.

[0055] The functional group (730) can have hydrophilicity. Referring to FIG. 7(b), the functional group (710) is configured to contain a hydroxyl group (OH-) through hydrolysis and can be bonded by a dehydration reaction with the hydroxyl group (OH-) on the hydrophilic surface.

[0056] According to several embodiments, Figure 5 shows a manufacturing method in which an insulating layer (400) is formed by placing SAM(500) as an example of the shielding material described above, and then removing the SAM(500) corresponding to the side surface of the gate (120). For example, referring to Figure 5(a), the manufacturing method allows the SAM(500) to grow with holes (V) formed, as shown in Figure 4(b). The SAM(500) can be formed over the entire area of ​​the inner surface formed by the holes (V). At this time, a layer that enables the growth of the shielding material can be formed over the entire area of ​​the inner surface. For example, in order to form the SAM(500), a step can be performed to provide O2 plasma over the entire area for hydrophilization. In one example, the growth of the SAM(500) can be performed by immersing a structure with holes (V) formed in it in a solution containing the SAM(500), as shown in Figure 4(b). Furthermore, for example, as shown in Figure 5(b), the manufacturing method may include providing an etchant for etching only the material of the gate (120), selectively etching (e.g., wet etching) only the inner surface of the gate (120) to remove the SAM (500) grown on the inner surface of the gate (120) and to form a groove (SE) (or trench structure) of a predetermined thickness from the inner surface. Furthermore, as shown in Figure 5(c), the manufacturing method may include a step of forming an insulating layer (400) in the remaining area other than the inner surface of the gate (120) (e.g., the inner surface of the source (130), insulating layers (220, 230), and drain (110), and the area exposed by the groove (V) of the first insulating layer (210)) in which the SAM (500) has grown and a groove (SE) has been formed on the gate (120). The remaining areas (for example, the inner surfaces of the source (130), insulating layers (220, 230), and drain (110), and the areas exposed by the groove (V) of the first insulating layer (210)) are prevented from forming the insulating layer (400) material by the functional groups (710) of the formed SAM (500), so that the insulating layer (400) can be formed only in the groove (SE).On the other hand, since the groove depth is determined in proportion to the etching time, the thickness of the insulating layer (400) varies depending on the etching time. If the thickness of the insulating layer (400) must be greater than or equal to the upper limit, a problem arises in which the insulating layer (400) is deposited in other areas. If the thickness of the insulating layer (400) must be less than the lower limit, a leakage current problem occurs. Therefore, the etching time must be optimally designed. For example, the etching time may range from a few seconds to several tens of minutes. Preferably, the etching time is 2 to 10 minutes, and more preferably, 4 to 6 minutes. If the etching time is 6 minutes or more, etching may occur in areas other than the gate (120), reducing the selectivity of the etching. If the etching time is less than 4 minutes, the gate (120) may not be etched as the thickness of the insulating layer (400) grows sufficiently, potentially causing leakage current.

[0057] According to several embodiments, Figure 6 shows a manufacturing method for forming an insulating layer (400) based on selectively forming SAM (500) as a shielding material only in the remaining area excluding the side of the gate (120) (for example, the inner surface of the source (130), insulating layers (220, 230), and drain (110), and the area exposed by the groove (V) of the first insulating layer (210)).

[0058] For example, as shown in Figure 6(a), the manufacturing method allows for the growth of SAM(500) in the remaining region of the gate (120) excluding the region (610) corresponding to the inner surface, as shown in Figure 4(b), while the hole (V) is formed. In one example, while the hole (V) is formed, the internal space created by the hole (V) may be made hydrophilic, and only the inner surface of the gate (120) may be partially etched before growing SAM(500) so that SAM(500) grows only in the remaining region other than the inner surface of the gate (120). In another example, UDA, (CH3(CH2)9CHO), and BA(C6H5CHO), which bond only to NH-functional groups, can be used as SAM(500).

[0059] Furthermore, for example, the manufacturing method may include the step of forming an insulating layer (400) with the SAM (500) grown in the remaining area and a groove (SE) formed in the gate (120), as shown in Figure 6(b).

[0060] On the other hand, instead of the SAM(500), a precursor may be used that selectively binds to the remaining region excluding the region corresponding to the gate(120) (for example, the inner surface of the source(130), insulating layers(220, 230), and drain(110), and the region exposed by the groove(V) of the first insulating layer(210)). For example, a precursor having a functional group that is chemically adsorbed to a hydrophilic hydroxide group(-OH) to prevent the formation of the insulating material(400) can be used. As one example, the precursor may include aminosilane and BDIPADS. Alternatively, for example, the precursor may include FeOx.

[0061] As shown in Figure 4(d), the manufacturing method may include a step of forming the channel layer (300) with the insulating layer (400) already formed. As previously mentioned, for example, the inner surfaces of the third insulator (230), the drain (130), the second insulator (220), the insulating layer (400), and the source (110) can form the same plane. This allows the channel layer (300) to be formed flat without any protruding and / or recessed portions in the internal space formed by the hole (V).

[0062] Figure 8 shows a structure in which multiple vertically structured GAA semiconductor elements (1a, 1b) are connected, according to multiple embodiments. Figures 9a to 9b show a manufacturing method for a structure in which multiple vertically structured GAA semiconductor elements (1a, 1b) are connected, according to multiple embodiments.

[0063] According to several embodiments, as shown in Figure 8, a structure can be manufactured that includes multiple GAA semiconductor elements (1a, 1b) including the above-mentioned insulators (210a, 210b, 220a, 220b, 230a, 230b), sources (110a, 110b), gates (120a, 120b), drains (130a, 130b), a channel layer (800), and insulating layers (400a, 400b). The configuration included in the structure is the same as that of the GAA semiconductor element (1) described above, so redundant explanations are omitted. The holes (V) are formed through all remaining parts of the insulators (210a, 210b, 220a, 220b, 230a, 230b), sources (110a, 110b), gates (120a, 120b), drains (130a, 130b), channel layer (800), and insulating layers (400a, 400b), except for the bottommost insulator (210a), and the channel layer (800) can be formed along the inner surface formed thereby. The structure can function as a NAND or AND circuit. For example, the structure can function as a NAND or AND circuit, and a charge trap layer based on AS-ALD can be selectively grown on at least a portion of the channel layer (800).

[0064] Referring to Figure 9a(a), the manufacturing method may include as many repeating steps as there are semiconductor elements to be formed from the process shown in Figure 4(a) above. This allows for the formation of insulators (210a, 210b, 220a, 220b, 230a, 230b), sources (110a, 110b), gates (120a, 120b), and drains (130a, 130b).

[0065] Referring to Figure 9a(b), the manufacturing method may include the step of forming holes (V) that penetrate the insulators (210b, 220a, 220b, 230a, 230b), sources (110a, 110b), gates (120a, 120b), and drains (130a, 130b). The holes (V) allow a portion of the surface of the 1-1 insulator (210a) to be exposed to the outside.

[0066] Referring to Figure 9b(c), the manufacturing method may include a step of forming an insulating layer (400) from the inner surface of the gate (120) into the hole (V) with a predetermined thickness, extending from the central axis (c) in the direction of the gates (120a, 120bb). As mentioned above, the step of forming the insulating layer (400) is performed by the formation of the SAM (500), so a redundant explanation will be omitted.

[0067] Referring to Figure 9B=b(d), the manufacturing method may include a step of forming the channel layer (300) with the insulating layer (400) already formed. As previously mentioned, for example, the inner surfaces of the third insulator (230), the drain (130), the second insulator (220), the insulating layer (400), and the source (110) can form the same plane. This allows the channel layer (300) to be formed flat without any portions protruding into and / or recessed into the internal space formed by the hole (V).

[0068] Figure 10a shows one example of a structure (1000) in which a GAA semiconductor element (1) and a CAA semiconductor element (2) are coupled, according to multiple embodiments. Figure 10 will be further explained below with reference to Figure 10b.

[0069] Figure 10b is a diagram illustrating examples of the operation of structure (1000) in multiple embodiments.

[0070] As shown in several embodiments, with reference to Figure 10a, the structure (1000) can include a semiconductor element (2) in addition to the configuration of the semiconductor element (1) described above (for example, source (110), gate (120), drain (130), insulators (210, 220, 230), and insulating layer (400)).

[0071] According to several embodiments, the CAA semiconductor element (2) may include a source (1011), an insulator (1021) placed on the source (1011), a drain (1012) placed on the insulator (1021), a channel layer (1013) formed perpendicular to a hole penetrating the drain (1012), the insulator (1021), and a portion of the source (1011), an insulating layer (1022), a gate (1013), and a dielectric layer (1040). Based on the configuration in which the channel layer (1033) and the gate (1013) are arranged perpendicularly and the gate (1013) is surrounded by the channel layer (1033), the semiconductor element can be defined as a channel all-around semiconductor element (2). On the other hand, the source (1011) and the drain (1012) may be opposite to each other.

[0072] According to several embodiments, the source (1011), the drain (1012), and the gate (1013) may be conductors. The flow of current between the source (1011) and the drain (1012) can be controlled via a channel layer (1030) that functions as a channel controlled by the gate (1013) extending vertically.

[0073] According to several embodiments, an insulating layer (1022) can be formed in such a manner that it is positioned between the gate (1013) and the channel layer (1030) and is in contact with each of them, thereby providing electrical insulation between the gate (1013) and the channel layer (1030). The insulating layer (1022) has an electrical insulating function and at the same time provides oxygen atoms (O) to the channel layer (1030). 2- ) can be supplied. For example, the insulating layer (1022) can be embodied in Al2O3.

[0074] According to several embodiments, the channel layer (1030) can electrically connect the source (1011) and the drain (1012). With a channel formed in the channel layer (1030) by a voltage (VG) applied to the gate (1013), a current can be formed in the channel layer (1030) by a voltage applied to the drain (1012) (or the source (1011)). Accordingly, as shown in Figure 10b, when a voltage is first applied to the gate (130) of the GAA semiconductor element (1), providing a current (or voltage) toward the source (110), a voltage is then applied to the gate (1013) of the CAA semiconductor element (1), and when a channel is formed in the channel layer (1030) by the gate (1013) and a current is applied to the drain (1012), a current can flow in the channel layer (1030).

[0075] According to several embodiments, the channel layer (1030) may consist of IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, CNT, Graphene, Si, TMD, 2D material, organic semiconductor material, or a combination thereof. Preferably, the channel layer (1030) can be embodied in IGZO (InGaZnO), which has low leakage current and excellent electron mobility. However, oxygen vacancies may form inside the IGZO (InGaZnO) constituting the channel layer (1030), and free electrons (2e-) for charge compensation due to the oxygen vacancies may be formed, which can reduce the resistance of the channel layer (1030). However, the formation of migration paths by free electrons can reduce the stability of the device, making it difficult to control the channel characteristics based on the voltage (VG) applied to the gate (1013).

[0076] According to several embodiments, the insulator (1021) may be an oxide film insulator containing oxygen atoms that is in contact with a portion of the channel layer (1030). For example, the insulator (1021) can be embodied in SiO2. The oxygen atoms contained in the insulator (1021) can be provided by the remaining portion of the channel layer (1030). Accordingly, the generation of oxygen vacancies in the remaining portion of the channel layer (1030) is suppressed, and channel control by the voltage (VG) applied to the gate (1013) can be made smoother.

[0077] According to several embodiments, the method for manufacturing the structure (1000) can be implemented in a manner that involves manufacturing the CAA semiconductor element (2) first, followed by manufacturing the GAA semiconductor element (1) described above.

[0078] A method for manufacturing the CAA semiconductor device (2) may first include the steps of forming a source (1011), an insulator (1021) on the source (1011), and a drain (1013) on the insulator (1021), then including the step of forming a hole, forming the channel layer (1030) through the hole, forming an insulating layer (1022) on the channel layer (1030), and forming a gate (1013) on the insulating layer (1022), then including the step of forming an insulator (1040), and then discharging a portion of the insulator (1040) to expose the upper surface of the gate (1013) and manufacturing the aforementioned GAA semiconductor device (1).

[0079] Figure 11 shows other examples of structures (1100) in which a GAA semiconductor element (1) and a CAA semiconductor element are coupled, according to multiple embodiments. Figure 10 will be further explained below with reference to Figure 12.

[0080] Figure 12 is a diagram illustrating examples of the operation of the structure (1100) in multiple embodiments.

[0081] According to several embodiments, with reference to Figure 11, the structure (1100) can be an additional structure including an additional insulating layer (1120) and an additional gate (1110) in addition to the configuration of the GAA semiconductor element (1) described above (e.g., source (110), gate (120), drain (130), insulators (210, 220, 230), insulating layer (400)). For example, the additional gate (1110) is positioned inside the hole (V) in the vertical direction, and the additional insulating layer (1120) surrounds (or covers) the additional gate (1110) in a manner that contacts the additional gate (1110), and the additional insulating layer (1120) can be in contact with the channel layer (300).

[0082] According to several embodiments, the additional structure can be formed to penetrate the holes (V) of the GAA semiconductor element (1). By forming the additional structure vertically (e.g., in the z-axis direction), the characteristics (e.g., conductivity) of the channel (300) connecting the source (110) and the drain (130) can be controlled by the voltage applied to the additional gate (1110), as shown in Figure 11(a), which can be defined as the vertical structure CAA transistor (2) described above.

[0083] The conductivity of the channel (300) is controlled by the voltage applied to the additional gate (1110), thereby setting a threshold voltage for the voltage applied to the additional gate (1110). With the threshold voltage set, the activated state of the channel (300) can be determined by the voltage applied to the gate (120), as shown in Figure 11(b), as described above. That is, when the channel (300) is activated, current flows between the source (110) and the drain (130), and when the channel (300) is deactivated, the flow of current can be restricted.

[0084] According to several embodiments, the additional gate (1110) can be made of the same material as the aforementioned source (110), gate (120), and drain (130).

[0085] According to several embodiments, an additional insulating layer (1120) can be formed in a manner that is positioned between the additional gate (1110) and the channel layer (300) and is in contact with each of them, thereby electrically insulating the additional gate (1110) and the channel layer (300). The additional insulating layer (1120) can be embodied in HfO2, SiO2, Al2O3, ZrO2, HZO, Ta2O5, La2O3, and Y2O3.

[0086] Figure 13 is a diagram illustrating examples of structures (1100) in which oxygen tunnels are formed, according to multiple embodiments.

[0087] According to several embodiments, Figure 13(a) shows an additional embodiment of a structure (1000) in which the aforementioned GAA semiconductor (1) and CAA semiconductor (2) are connected, and Figure 13(b) shows an additional embodiment of a structure (1100) in which the CAA semiconductor is embodied in the GAA semiconductor (1).

[0088] According to several embodiments, preferably, the channel layer (1030, 300) of the CAA semiconductor (2) of the structure (1000, 1100) can be embodied in IGZO (InGaZnO), which has low leakage current and excellent electron mobility. However, oxygen vacancies may occur inside the IGZO (InGaZnO) constituting the channel layer (1030, 300), and free electrons (2e-) for charge compensation by the oxygen vacancies may be formed, which can reduce the resistance of the channel layer (300). However, the formation of migration paths by free electrons may reduce the stability of the device and make it difficult to control the channel characteristics based on the voltage (VG) applied to the gate (1013, 1110). Therefore, in order to improve the stability of the CAA semiconductor device described above, the structure (1000, 1100) can be further embodied to include an oxygen tunnel structure in the channel (1030, 300) that concentrates the flow of oxygen atoms to prevent the induction of oxygen vacancies.

[0089] For example, referring to Figure 13, in order to reduce the contact resistance with the channel layers (1030, 300), the sources (1011, 110) and drains (1012, 130) may each further include contact layers (e.g., a first contact layer (110a), a second contact layer (130a)). The contact layers (110a, 130a) may be embodied in the same material as the channels (1030, 300), preferably in IGZO (InGaZnO), but are not limited to the examples described in the specification.

[0090] For example, referring to Figure 12, the structure (1000, 1100) may further include insulating layers (e.g., a first insulating layer (110b), a second insulating layer (130b)) between the contact layers (110a, 130a) and insulators (1021, 220, 230) of the source (1011, 110) and drain (1012, 130), respectively. The permeability of oxygen atoms in the insulating layers (e.g., a first insulating layer (110b), a second insulating layer (130b)) may be lower than the permeability of oxygen atoms in the insulating layer (1022, 1120) that is in contact with the gate (1013, 1110) and the channel layer (1030, 300). That is, the insulating layers (for example, the first insulating layer (110b), the second insulating layer (130b)) can form an oxygen tunnel structure such that oxygen atoms contained in the insulator (1021, 220, 230) are concentrated in a part of the channel layer (1030, 300) that is in contact with the insulator (1021, 220, 230) (for example, the region in contact with the insulator (1021, 220, 230)). Furthermore, by preventing the flow of oxygen atoms in the remaining portion of the channel layer (1030, 300) connected to the contact layer (110a, 130a), the source (1011, 110), and the drain (1012, 130), and inducing the generation of oxygen vacancies, the resistance of the contact layer (110a, 110b) and the remaining portion of the channel layer (1030, 300) can be made relatively lower compared to the resistance of a portion of the channel layer (1030, 300) (for example, the region in contact with the insulator (1021, 220, 230)). Consequently, the contact resistance between the source (1011, 110) (or the drain (1012, 130)) and the channel layer (1030, 300) can be made lower.

Claims

1. A method for manufacturing a semiconductor device with a vertical channel structure, The steps include forming a first insulator on a substrate, a first conductor on the first insulator, a second insulator placed on the first conductor, a gate on the second insulator, a third insulator on the gate, and a second conductor on the third insulator, The steps include forming a hole that penetrates the second conductor, the third insulator, the gate, the second insulator, and the first conductor, The steps include forming an insulating layer on the inner surface of the gate by growing a shielding material on the remaining inner surface excluding the inner surface of the gate formed by the hole, A manufacturing method comprising the step of forming a channel layer that electrically connects the first conductor and the second conductor.

2. The manufacturing method according to claim 1, wherein the functional groups of the shielding material are embodied in such a way as to prevent the deposition of the insulating layer material.

3. The step of forming an insulating layer on the inner surface of the gate is: The steps include growing the shielding material on the inner surface formed by the hole, The steps include selectively etching only the aforementioned gate for a predetermined time, The manufacturing method according to claim 2, comprising the step of depositing the insulating layer onto a trench structure formed on the gate while the shielding material has grown on the remaining portion excluding the gate.

4. The manufacturing method according to claim 3, wherein the insulating layer of the gate electrically separates the gate from the channel layer.

5. The step of forming an insulating layer on the inner surface of the gate is: The steps include forming a layer on the inner surface formed by the aforementioned hole that allows for the growth of a shielding material, A step of selectively etching only the gate for a predetermined time, The steps include: growing the shielding material only on the remaining portion, with the remaining portion excluding the gate being made hydrophilic; The manufacturing method according to claim 2, comprising the step of depositing the insulating layer onto a trench structure formed in the gate, with the shielding material grown on the remaining portion excluding the gate.

6. A semiconductor device, The first conductor and, A first insulator disposed on the first conductor, A gate placed on the first insulator, A second insulator is placed on the gate, A second conductor disposed on the second insulator, A channel layer formed along the inner surface formed by holes that penetrate vertically through the second conductor, the second insulator, the gate, and the first insulator, The channel layer and the gate are disposed between the channel layer and the gate, Of the first conductor and the second conductor, one is the source and the other is the drain. A semiconductor element with a vertical channel structure, wherein the insulating layer is formed based on the formation of a shielding material inside the hole that prevents the growth of the insulating layer.

7. The semiconductor element having a vertical channel structure according to claim 6, wherein the insulating layer is formed between the inner surface of the gate and the channel layer.

8. A semiconductor element with a vertical channel structure according to claim 7, wherein the insulating layer is formed on the inner surface of the gate by depositing the insulating layer material while a layer that inhibits the growth of the insulating film is grown on the remaining portion other than the gate.

9. The semiconductor element having a vertical channel structure according to claim 8, wherein the functional groups of the shielding material are embodied in such a way as to prevent the deposition of the insulating layer material.

10. An additional insulating layer and an additional gate are formed in the aforementioned hole. The semiconductor element having a vertical channel structure according to claim 6, wherein the conductivity of the channel layer can be adjusted by the additional gate.

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