Power detector

Abstract

To provide a power detector capable of more accurately measuring the power of the detected signal. [Solution] The system includes a rectifier that generates a detection signal indicating the power of a signal to be detected by rectifying the signal to be detected based on a predetermined threshold voltage, and a bias adjuster that adjusts the bias voltage of the rectifier to suppress temperature fluctuations of the detection signal.

Description

Technical Field

[0001] The present invention relates to a power detector.

Background Art

[0002] Non-Patent Document 1 below discloses a power detector including a rectifier composed of an n-type MOSFET, a p-type MOS current mirror composed of a p-type MOSFET and having a low-pass filter, a current amplifier composed of an n-type MOSFET, a second p-type MOS current mirror composed of a p-type MOSFET, and a resistor (see FIG. 4).

[0003] In this power detector, a bias voltage is superimposed on an RF signal and input to the gate of the n-type MOSFET of the rectifier, so that the n-type MOSFET operates as a half-wave rectifier. That is, the rectifier in the power detector converts only the positive voltage of the RF signal into current, generates a half-wave rectified current that blocks the negative voltage of the RF signal, and outputs it to the p-type MOS current mirror. The p-type MOS current mirror converts the half-wave rectified current into voltage and converts it into a DC voltage by passing it through a low-pass filter.

[0004] This DC voltage is a detection signal indicating the magnitude of the RF signal. The detection signal is input from the p-type MOS current mirror to the current amplifier, amplified in current, and converted into a detection current. This detection current is folded back by the second p-type MOS current mirror, converted into a voltage (detection voltage) by a resistor, and output to the outside.

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

[0006] Incidentally, as is well known, the threshold voltage of an n-type MOSFET is subject to temperature fluctuations. In the above-mentioned background technology, an external bias voltage is applied to the gate of the n-type MOSFET in the rectifier. When the half-wave rectified current output from the rectifier is converted into a voltage, this voltage is the sum of the voltage based on the bias voltage and the half-wave rectified current, and therefore fluctuates with temperature due to the influence of the threshold voltage. Consequently, it is difficult to accurately detect the power of the RF signal in the above-mentioned background technology.

[0007] This invention has been made in view of the circumstances described above, and aims to provide a power detector that can more accurately measure the power of a signal to be detected. [Means for solving the problem]

[0008] To achieve the above objective, the present invention employs a first solution relating to a power detector, which includes a rectifier that generates a detection signal indicating the power of the detected signal by rectifying the detected signal based on a predetermined threshold voltage, and a bias adjuster that adjusts the bias voltage of the rectifier to suppress temperature fluctuations of the detection signal.

[0009] In the present invention, as a second solution relating to the power detector, the bias adjuster, in the first solution described above, adjusts the bias voltage by adjusting the first current flowing into the rectifier based on the detection signal.

[0010] In the present invention, as a third solution relating to the power detector, the method adopted is that, in the second solution described above, the bias adjuster is a current mirror that adjusts the first current by subtracting a second current from a reference current.

[0011] In the present invention, as a fourth solution relating to a power detector, in the second or third solution described above, the rectifier is provided with a first current mirror circuit consisting of an input circuit and an output circuit, the input circuit generates the bias voltage by converting the first current into a current / voltage, and the output circuit generates a rectified current by rectifying the signal to be detected by the bias.

[0012] In the present invention, as a fifth solution relating to the power detector, in the solution of the fourth above, the rectifier is provided with a second current mirror circuit and a third current mirror circuit that individually generate detection currents based on the rectified current, the second current mirror circuit outputs the detection current as the detection signal to the bias adjuster, and the third current mirror circuit outputs the detection current to a current / voltage converter.

[0013] In the present invention, as a sixth solution relating to the power detector, the fifth solution described above employs the means that the second current mirror circuit and the third current mirror circuit are equipped with a smoothing circuit for smoothing the rectified current. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a power detector that can more accurately measure the power of a signal to be detected. [Brief explanation of the drawing]

[0015] [Figure 1] This is a circuit diagram showing the configuration of a power detector related to one embodiment of the present invention. [Figure 2] This is a block diagram showing the basic configuration of a power detector according to one embodiment of the present invention. [Figure 3] This waveform diagram shows the rectification operation of a power detector according to one embodiment of the present invention. [Figure 4] This is a characteristic diagram showing the performance of a power detector according to one embodiment of the present invention.

Best Mode for Carrying Out the Invention

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the power detector A according to this embodiment includes an input terminal Tin, a bias current input terminal Trin, a power supply terminal Td, a rectifier 1, a current mirror 2, a current / voltage converter 3, and an output terminal Tout.

[0017] The rectifier 1 includes a first bias terminal Tb1, a second bias terminal Tb2, a third bias terminal Tb3, a fourth bias terminal Tb4, a first capacitor 1a, a first resistor 1b, a second capacitor 1c, a first transistor 1d, a second transistor 1e, a third transistor 1f, a fourth transistor 1g, a fifth transistor 1h, a sixth transistor 1i, a second resistor 1j, a third capacitor 1k, a seventh transistor 1m, an eighth transistor 1n, a ninth transistor 1p, and a tenth transistor 1q.

[0018] The current mirror 2 includes a fifth bias terminal Tb5, a sixth bias terminal Tb6, an eleventh transistor 2a, a twelfth transistor 2b, a thirteenth transistor 2c, and a fourteenth transistor 2d. The current / voltage converter 3 includes a seventh bias terminal Tb7, a fifteenth transistor 3a, and a sixteenth transistor 3b.

[0019] The input terminal Tin is connected to one end of the first capacitor 1a as shown in the figure. Although not shown, this input terminal Tin is connected to a high-frequency signal source outside the power detector A. A high-frequency signal of a predetermined frequency, for example, in the range of several to several tens of GHz, is input as an input signal Vin from the high-frequency signal source to such an input terminal Tin.

[0020] The bias current input terminal Trin is connected to the gate terminal of the first transistor 1d, the other end of the first resistor 1b, one end of the second capacitor 1c, the drain terminal of the second transistor 1e, and the first input terminal of the current mirror 2. This bias current input terminal Trin is connected to the output terminal of the reference current source outside the power detector A.

[0021] A predetermined reference current Iref is input from the reference current source to such a bias current input terminal Trin. This reference current Iref is shunted to the rectifier 1 and the current mirror 2 as shown in the figure. That is, the first current Ir flows into the rectifier 1, and the second current Ih flows into the current mirror 2.

[0022] The power supply terminal Td is connected to the source terminal of the fifth transistor 1h, the other end of the third capacitor 1k, the source terminal of the seventh transistor 1m, and the source terminal of the ninth transistor 1p. This power supply terminal Td is connected to the output terminal of the DC power supply outside the power detector A. The power supply voltage Vcc is supplied to such a power supply terminal Td from the DC power supply.

[0023] As shown in the figure, the output terminal Tout is connected to the drain terminal of the tenth transistor 1q, the drain terminal of the sixteenth transistor 3b, and the gate terminal of the fifteenth transistor 3a. This output terminal Tout is connected to the input terminal of the subsequent stage circuit outside the power detector A. Such an output terminal Tout outputs the output signal Vout of the power detector A to the subsequent stage circuit.

[0024] In the rectifier 1, the first bias terminal Tb1 is connected to the gate terminal of the second transistor 1e. Also, the first bias terminal Tb1 is connected to the first output terminal of the external bias circuit outside the power detector A. The first bias voltage V1 is supplied to such a first bias terminal Tb1 from the external bias circuit.

[0025] The second bias terminal Tb2 is connected to the gate terminal of the fourth transistor 1g. Furthermore, outside of power detector A, the second bias terminal Tb2 is connected to the first output terminal of an external bias circuit, similar to the first bias terminal Tb1. The first bias voltage V1 is supplied to this second bias terminal Tb2 from the external bias circuit.

[0026] The third bias terminal Tb3 is connected to the gate terminal of the sixth transistor 1i. Furthermore, the third bias terminal Tb3 is connected to the second output terminal of an external bias circuit outside of power detector A. The second bias voltage V2 is supplied to this third bias terminal Tb3 from the external bias circuit.

[0027] The fourth bias terminal Tb4 is connected to the gate terminal of the eighth transistor 1n and the gate terminal of the tenth transistor 1q. Furthermore, outside of power detector A, the fourth bias terminal Tb4 is connected to the second output terminal of an external bias circuit, similar to the third bias terminal Tb3. The second bias voltage V2 is supplied to this fourth bias terminal Tb4 from the external bias circuit.

[0028] The first capacitor 1a has one end connected to the input terminal Tin and the other end connected to one end of the first resistor 1b and the gate terminal of the third transistor 1f. This first capacitor 1a is a coupling capacitor having a predetermined capacitance (first capacitance). In other words, this first capacitor 1a allows only the AC component of the input signal Vin to be input to one end of the first resistor 1b and the gate terminal of the third transistor 1f.

[0029] The first resistor 1b has one end connected to the other end of the first capacitor 1a and the gate terminal of the third transistor 1f, and the other end connected to one end of the second capacitor 1c, the gate terminal of the first transistor 1d, the drain terminal of the second transistor 1e and the bias current input terminal Trin. This first resistor 1b has a predetermined resistance value (first resistance value) and together with the second capacitor 1c, it constitutes a low-pass filter.

[0030] This low-pass filter has a cutoff frequency determined by the value of the first resistor and the capacitance of the second capacitor 1c (second capacitance). This cutoff frequency is set to a frequency sufficiently lower than the frequency of the input signal Vin (high-frequency signal). The first resistor 1b, together with the second capacitor 1c, prevents the input signal Vin from being input to the gate terminal of the first transistor 1d.

[0031] The second capacitor 1c has one end connected to the other end of the first resistor 1b, the gate terminal of the third transistor 1f, the drain terminal of the second transistor 1e, and the bias current input terminal Trin, while the other end is grounded as shown in the figure. This second capacitor 1c has a predetermined capacitance (second capacitance) and, together with the first resistor 1b, constitutes a low-pass filter. This second capacitor 1c, together with the first resistor 1b, constitutes the low-pass filter described above and prevents the input signal Vin from being input to the gate terminal of the first transistor 1d.

[0032] The first transistor 1d is an n-type MOS (Metal Oxide Semiconductor) transistor, as shown in the figure. The gate terminal of this first transistor 1d is connected to the other end of the first resistor 1b, one end of the second capacitor 1c, the drain terminal of the second transistor 1e, and the bias current input terminal Trin, and the source terminal is grounded as shown in the figure.

[0033] Furthermore, the drain terminal of the first transistor 1d is connected to the source terminal of the second transistor 1e. Such a first transistor 1d has a structure in which its gate terminal and drain terminal are interconnected via the second transistor 1e, that is, a diode-connected structure via the second transistor 1e.

[0034] The second transistor 1e is an n-type MOS transistor, similar to the first transistor 1d. The gate terminal of this second transistor 1e is connected to the first bias terminal Tb1, and its source terminal is connected to the drain terminal of the first transistor 1d. Furthermore, the drain terminal of the second transistor 1e is connected to the other end of the first resistor 1b, one end of the second capacitor 1c, the gate terminal of the first transistor 1d, and the bias current input terminal Trin.

[0035] This second transistor 1e is an n-type MOS transistor, just like the first transistor 1d. Furthermore, this second transistor 1e is a cascode transistor connected in cascode mode to the first transistor 1d. In addition, together with the first transistor 1d, the second transistor 1e constitutes a signal conversion circuit that converts the first current Ir into a DC voltage.

[0036] In other words, the second transistor 1e functions as a gate bias circuit that generates a gate bias voltage together with the first transistor 1d. The gate bias voltage is the gate voltage (DC voltage) of the third transistor 1f based on the first current Ir input to the bias current input terminal Trin from an external source, and is the bias voltage in the half-wave rectification operation of the third transistor 1f.

[0037] Here, the first resistor 1b, second capacitor 1c, first transistor 1d, and second transistor 1e described above constitute a gate bias generation circuit that generates a gate bias voltage based on the first current Ir. Such a gate bias generation circuit functions as a bias adjuster that adjusts the gate voltage of the third transistor 1f (rectifier transistor).

[0038] In other words, the bias adjuster, consisting of a first resistor 1b, a second capacitor 1c, a first transistor 1d, and a second transistor 1e, sets the bias voltage of the third transistor 1f (rectifier transistor) in half-wave rectification operation by outputting a gate bias voltage generated based on the first current Ir to the gate terminal of the third transistor 1f (rectifier transistor).

[0039] The third transistor 1f is an n-type MOS transistor, as shown in the figure. The gate terminal of this third transistor 1f is connected to the other end of the first capacitor 1a and one end of the first resistor 1b, and the source terminal is grounded as shown in the figure. The drain terminal of the third transistor 1f is connected to the source terminal of the fourth transistor 1g.

[0040] Such a third transistor 1f performs half-wave rectification on the input signal Vin (high-frequency signal), which is the signal to be detected. That is, the third transistor 1f performs half-wave rectification on the input signal Vin (high-frequency signal) by using the gate bias voltage supplied from the bias adjuster in this embodiment as the bias voltage in half-wave rectification.

[0041] The third transistor 1f outputs a half-wave rectified current, generated by half-wave rectification of the input signal Vin (high-frequency signal), from its drain terminal to the source terminal of the fourth transistor 1g. This third transistor 1f is a rectifier transistor that performs half-wave rectification on the input signal Vin (high-frequency signal).

[0042] The third transistor 1f (rectifier transistor) has a threshold voltage Vt inherent to MOS transistors, which are semiconductor devices. This threshold voltage Vt has the property of fluctuating with temperature.

[0043] The fourth transistor, 1g, is an n-type MOS transistor, similar to the third transistor, 1f. The gate terminal of this fourth transistor, 1g, is connected to the second bias terminal Tb2, and its source terminal is connected to the drain terminal of the third transistor, 1f.

[0044] Furthermore, the drain terminal of the fourth transistor 1g is connected to the gate terminal of the fifth transistor 1h, the drain terminal of the sixth transistor 1i, and one end of the second resistor 1j. Thus, the fourth transistor 1g is a cascode transistor that is cascode-connected to the third transistor 1f.

[0045] Here, the diode-connected first transistor 1d and second transistor 1e, the first resistor 1b and second capacitor 1c that constitute a low-pass filter, and the cascode-connected third transistor 1f and fourth transistor 1g together constitute a first current mirror circuit.

[0046] The first transistor 1d, the second transistor 1e, the first resistor 1b, and the second capacitor 1c constitute the input circuit of the first current mirror circuit. The third transistor 1f and the fourth transistor 1g constitute the output circuit of the first current mirror circuit.

[0047] In this type of first current mirror circuit, the first transistor 1d and the second transistor 1e that constitute the input circuit and the third transistor 1f and the fourth transistor 1g that constitute the output circuit are configured to be of the same element size, so the Miller ratio is "1".

[0048] In other words, in the reference state where no input signal Vin (high-frequency signal) is input to input terminal Tin, the first current Ir flows through the output circuit of the first current mirror circuit. In the operating state where the input signal Vin (high-frequency signal) is input to input terminal Tin, the third transistor 1f half-wave rectifies the input signal Vin (high-frequency signal), so a superimposed current flows through the output circuit of the first current mirror circuit, which is the first current Ir superimposed with the half-wave rectified current representing the power of the input signal Vin (high-frequency signal).

[0049] Here, in the reference state, if a temperature fluctuation of the threshold voltage Vt occurs in the third transistor 1f (rectifier transistor), a composite superimposed current flows through the output circuit of the first current mirror circuit, in which the current drift component caused by the temperature fluctuation of the threshold voltage Vt is superimposed on the first current Ir. On the other hand, in the operating state, if a temperature fluctuation of the threshold voltage Vt occurs in the third transistor 1f (rectifier transistor), a composite superimposed current flows through the output circuit of the first current mirror circuit, in which the current drift component caused by the temperature fluctuation of the threshold voltage Vt is superimposed on the first current Ir and the half-wave rectified current.

[0050] The fifth transistor 1h is a p-type MOS transistor, as shown in the figure. The gate terminal of this fifth transistor 1h is connected to the drain terminal of the fourth transistor 1g, the drain terminal of the sixth transistor 1i, and one end of the second resistor 1j, while the drain terminal of this fifth transistor 1h is connected to the source terminal of the sixth transistor 1i.

[0051] Furthermore, the source terminal of this fifth transistor 1h is connected to the power supply terminal Td, the other end of the third capacitor 1k, the source terminal of the seventh transistor 1m, and the source terminal of the ninth transistor 1p. In other words, this fifth transistor 1h is connected in series with the third transistor 1f and the fourth transistor 1g via the sixth transistor 1i, and a drain current equal to the first current Ir flows through it in the reference state.

[0052] Furthermore, this fifth transistor 1h has a structure in which its gate terminal and drain terminal are interconnected via the sixth transistor 1i. In other words, this fifth transistor 1h has a structure in which it is diode-connected via the sixth transistor 1i.

[0053] The sixth transistor 1i is a p-type MOS transistor, similar to the fifth transistor 1h. Its gate terminal is connected to the third bias terminal Tb3, and its source terminal is connected to the drain terminal of the fifth transistor 1h. Furthermore, its drain terminal is connected to the drain terminal of the fourth transistor 1g, the gate terminal of the fifth transistor 1h, and one end of the second resistor 1j.

[0054] Such a sixth transistor 1i is a cascode transistor cascode-connected to the fifth transistor 1h. Furthermore, the sixth transistor 1i is connected in series with the third transistor 1f and the fourth transistor 1g together with the fifth transistor 1h, and a drain current equal to the first current Ir flows through it in the reference state.

[0055] The second resistor 1j has one end connected to the drain terminal of the fourth transistor 1g, the gate terminal of the fifth transistor 1h, and the drain terminal of the sixth transistor 1i, and the other end connected to one end of the third capacitor 1k, the gate terminal of the seventh transistor 1m, and the gate terminal of the ninth transistor 1p. This second resistor 1j has a predetermined resistance value (second resistance value) and together with the third capacitor 1m, it forms a smoothing circuit.

[0056] The time constant of this smoothing circuit is determined by the value of the second resistor and the capacitance of the third capacitor 1k (third capacitance). This time constant is set so as to sufficiently smooth the half-wave rectified current contained in the superimposed current input from the drain terminal of the fourth transistor 1g. Such a second resistor 1j applies the detected voltage Vs, which is the result of smoothing the superimposed current, to the gate terminals of the seventh transistor 1m and the ninth transistor 1p.

[0057] This detection voltage Vs is the smoothed superimposed current input from the drain terminal of the fourth transistor 1g, and is a DC voltage that indicates the power of the input signal Vin (high-frequency signal). This detection voltage Vs also sets the gate voltage of the seventh transistor 1m and the gate voltage of the ninth transistor 1p.

[0058] The third capacitor 1k has one end connected to the other end of the second resistor 1j, the gate terminal of the seventh transistor 1m, and the gate terminal of the ninth transistor 1p, and the other end connected to the power supply terminal Td, the source terminal of the fifth transistor 1h, the source terminal of the seventh transistor 1m, and the source terminal of the ninth transistor 1p.

[0059] This third capacitor 1k has a predetermined capacitance (third capacitance) and, together with the second resistor 1j described above, constitutes a smoothing circuit. That is, the third capacitor 1k, together with the second resistor 1j, generates a detection voltage Vs by smoothing the superimposed current and applies it to the gate terminal of the seventh transistor 1m and the gate terminal of the ninth transistor 1p.

[0060] The seventh transistor, 1m, is a p-type MOS transistor, as shown in the figure. The gate terminal of this seventh transistor, 1m, is connected to the other end of the second resistor, 1j, one end of the third capacitor, 1k, and the gate terminal of the ninth transistor, 1p, while its drain terminal is connected to the source terminal of the eighth transistor, 1n.

[0061] Furthermore, the source terminal of this seventh transistor 1m is connected to the power supply terminal Td, the source terminal of the fifth transistor 1h, the other end of the third capacitor 1k, and the source terminal of the ninth transistor 1p. In other words, the seventh transistor 1m is cascode-connected to the eighth transistor 1n, and is electrically connected to the second input terminal of the current mirror 2 via the eighth transistor 1n.

[0062] The eighth transistor, 1n, is a p-type MOS transistor, similar to the seventh transistor, 1m. The gate terminal of this eighth transistor, 1n, is connected to the fourth bias terminal Tb4 and the gate terminal of the tenth transistor, 1q, while its source terminal is connected to the drain terminal of the seventh transistor, 1m.

[0063] Furthermore, the drain terminal of this eighth transistor 1n is connected to the second input terminal of the current mirror 2. This eighth transistor 1n is a cascode transistor that is cascode-connected to the seventh transistor 1m.

[0064] Here, the diode-connected fifth transistor 1h and sixth transistor 1i, the second resistor 1j and third capacitor 1k that constitute the smoothing circuit, and the cascode-connected seventh transistor 1m and eighth transistor 1n together constitute a second current mirror circuit.

[0065] This second current mirror circuit is a current mirror circuit with a mirror ratio of "1" because the fifth transistor 1h and the sixth transistor 1i that constitute the input circuit and the seventh transistor 1m and the eighth transistor 1n that constitute the output circuit are made of the same element size.

[0066] In this type of second current mirror circuit, when an input signal Vin (high-frequency signal) is input to the input terminal Tin, the drain current (DC current) of the 7th transistor 1m and the 8th transistor 1n that constitute the output circuit is equal to the drain current, or superimposed current, of the 5th transistor 1h and the 6th transistor 1i that constitute the input circuit.

[0067] In this operating state, a detection current Is is output to the current mirror 2 from the output circuit of the second current mirror circuit based on the detection voltage Vs generated from the superimposed current in the smoothing circuit of the second current mirror circuit. In other words, the second current mirror circuit generates a detection current Is to be output to the current mirror 2 based on the half-wave rectified current input from the first current mirror circuit.

[0068] The detection current Is generated by the second current mirror circuit is a detection signal that indicates the power of the input signal Vin (high-frequency signal) which is the signal to be detected. Furthermore, as will be described in detail later, this detection current Is is obtained after the influence of the current drift component caused by temperature fluctuations of the threshold voltage Vt of the third transistor 1f (rectifier transistor) has been removed or suppressed.

[0069] The ninth transistor, 1p, is a p-type MOS transistor, as shown in the figure. The gate terminal of this ninth transistor, 1p, is connected to the other end of the second resistor, 1j, one end of the third capacitor, 1k, and the gate terminal of the seventh transistor, 1m, while its drain terminal is connected to the source terminal of the tenth transistor, 1q.

[0070] Furthermore, the source terminal of the ninth transistor 1p is connected to the power supply terminal Td, the source terminal of the fifth transistor 1h, the other end of the third capacitor 1k, and the source terminal of the seventh transistor 1m. In other words, the ninth transistor 1p is cascode-connected to the tenth transistor 1q, and is electrically connected to the input terminal of the current / voltage converter 3 via the tenth transistor 1q.

[0071] The 10th transistor 1q is a p-type MOS transistor, similar to the 9th transistor 1p. The gate terminal of this 10th transistor 1q is connected to the 4th bias terminal Tb4 and the gate terminal of the 8th transistor 1n, and the source terminal is connected to the drain terminal of the 9th transistor 1p.

[0072] Furthermore, the drain terminal of this 10th transistor 1q is connected to the input terminal of the current / voltage converter 3. This 10th transistor 1q is a cascode transistor that is cascode-connected to the 9th transistor 1p.

[0073] Here, the diode-connected fifth transistor 1h and sixth transistor 1i, the second resistor 1j and third capacitor 1k that constitute the smoothing circuit, and the cascode-connected ninth transistor 1p and tenth transistor 1q together constitute a third current mirror circuit.

[0074] This third current mirror circuit is a current mirror circuit with a mirror ratio of "1," similar to the second current mirror circuit described above, because the fifth transistor 1h and the sixth transistor 1i that constitute the input circuit and the ninth transistor 1p and the tenth transistor 1q that constitute the output circuit are all the same size.

[0075] In this type of third current mirror circuit, when an input signal Vin (high-frequency signal) is input to the input terminal Tin, the drain current (DC current) of the 9th transistor 1p and the 10th transistor 1q, which constitute the output circuit, is equal to the drain current, or superimposed current, of the 5th transistor 1h and the 6th transistor 1i, which constitute the input circuit.

[0076] In this operating state, the detected current Is is output from the output circuit of the third current mirror circuit to the current / voltage converter 3 based on the detected voltage Vs generated from the superimposed current in the smoothing circuit of the third current mirror circuit. In other words, the third current mirror circuit generates a detected current Is for external output based on the half-wave rectified current input from the first current mirror circuit.

[0077] The detected current Is generated by the third current mirror circuit is a detection signal that indicates the power of the input signal Vin (high-frequency signal). Furthermore, as will be described in detail later, this detected current Is is one in which the influence of the current drift component caused by temperature fluctuations of the threshold voltage Vt of the third transistor 1f (rectifier transistor) has been removed or suppressed.

[0078] In the current mirror 2, the fifth bias terminal Tb5 is connected to the gate terminal of the twelfth transistor 2b. Furthermore, this fifth bias terminal Tb5, like the first bias terminal Tb1 of the rectifier 1, is connected to the first output terminal of an external bias circuit outside of the power detector A. The first bias voltage V1 is supplied to this fifth bias terminal Tb5 from the external bias circuit.

[0079] The sixth bias terminal Tb6 is connected to the gate terminal of the 14th transistor 2d. Furthermore, like the fifth bias terminal Tb5, this sixth bias terminal Tb6 is connected to the first output terminal of the external bias circuit outside of power detector A. The first bias voltage V1 is supplied to this sixth bias terminal Tb6 from the external bias circuit.

[0080] Transistor 11 2a is an n-type MOS transistor, as shown in the figure. Transistor 11 2a has its gate terminal connected to the drain terminal of transistor 12 2b and the gate terminal of transistor 13 2c, and its source terminal is grounded as shown in the figure.

[0081] Furthermore, the drain terminal of this 11th transistor 2a is connected to the source terminal of the 12th transistor 2b. Such an 11th transistor 2a has a structure in which its gate terminal and drain terminal are interconnected via the 12th transistor 2b, that is, a structure in which it is diode-connected via the 12th transistor 2b.

[0082] The 12th transistor 2b is an n-type MOS transistor, similar to the 11th transistor 2a. Its gate terminal is connected to the 5th bias terminal Tb5, and its source terminal is connected to the drain terminal of the 11th transistor 2a. In other words, the 12th transistor 2b is a cascode transistor cascode-connected to the 11th transistor 2a.

[0083] The drain terminal of this 12th transistor 2b is connected to the gate terminal of the 11th transistor 2a, the gate terminal of the 13th transistor 2c, and the drain terminal of the 8th transistor 1n in rectifier 1, that is, the output terminal of the second current mirror circuit in rectifier 1. In other words, the drain terminal of the 12th transistor 2b is the second input terminal of current mirror 2.

[0084] In this configuration, when an input signal Vin (high-frequency signal) is input to the input terminal Tin of the 12th transistor 2b, a superimposed current flows in from the second current mirror circuit of the rectifier 1. This superimposed current is the first current Ir superimposed with a half-wave rectified current representing the power of the input signal Vin (high-frequency signal).

[0085] Furthermore, if a temperature fluctuation occurs in the threshold voltage Vt of the third transistor 1f (rectifier transistor) in this operating state, a detection current Is based on a composite superimposed current, in which the current drift component caused by the temperature fluctuation of the threshold voltage Vt is superimposed on the first current Ir and the half-wave rectified current, flows in from the second current mirror circuit of the rectifier 1.

[0086] The 13th transistor 2c is an n-type MOS transistor, similar to the 11th transistor 2a. The gate terminal of this 13th transistor 2c is connected to the gate terminal of the 11th transistor 2a, the drain terminal of the 12th transistor 2b, and the drain terminal of the 8th transistor 1n in the rectifier 1. In addition, the source terminal of this 13th transistor 2c is grounded as shown in the figure, and the drain terminal is connected to the source terminal of the 14th transistor 2d.

[0087] The 14th transistor 2d is an n-type MOS transistor, similar to the 13th transistor 2c. The gate terminal of this 14th transistor 2d is connected to the 6th bias terminal Tb6, and its source terminal is connected to the drain terminal of the 13th transistor 2c. Thus, the 14th transistor 2d is a cascode transistor cascode-connected to the 13th transistor 2c.

[0088] The drain terminal of such a 14th transistor 2d is the first input terminal of the current mirror 2, and a second current Ih flows in through the bias current input terminal Trin. This second current Ih is equal to the detection current Is that flows into the second input terminal of the current mirror 2, according to the circuit characteristics of a well-known current mirror circuit.

[0089] In other words, in a reference state where no input signal Vin (high-frequency signal) is input to the input terminal Tin, and in a reference temperature state where the operating temperature of the third transistor 1f, which functions as a rectifier transistor, does not fluctuate, the second current Ih flowing into the first input terminal of the current mirror 2 is equal to the detected current Is flowing into the second input terminal of the current mirror 2.

[0090] Such a current mirror 2 is a bias adjuster in this embodiment. That is, the current mirror 2 adjusts the gate bias voltage of the third transistor 1f (rectifier transistor) to suppress temperature fluctuations of the detected current Is by adjusting the first current Ir based on the rectified signal (detected current Is) in this embodiment.

[0091] More specifically, the current mirror 2 adjusts the first current Ir by subtracting the second current Ih from the reference current Iref based on the rectified signal (detected current Is). In other words, the current mirror 2 adjusts the first current Ir by adjusting the amount of subtraction from the reference current Iref, thereby adjusting the gate bias voltage.

[0092] In the current / voltage converter 3, the seventh bias terminal Tb7 is connected to the gate terminal of the sixteenth transistor 3b. Furthermore, this seventh bias terminal Tb7 is connected to the first output terminal of an external bias circuit outside the power detector A, similar to the first bias terminals Tb1 and Tb2 in the rectifier 1, and the fifth bias terminals Tb5 and Tb6 in the current mirror 2. As shown in the figure, the first bias voltage V1 is supplied to this seventh bias terminal Tb7 from the external bias circuit.

[0093] The 15th transistor 3a is an n-type MOS transistor, as shown in the figure. The gate terminal of the 15th transistor 3a is connected to the output terminal Tout, the drain terminal of the 16th transistor 3b, and the drain terminal of the 10th transistor 1q in the rectifier 1, that is, the output terminal of the third current mirror circuit in the rectifier 1.

[0094] Furthermore, the drain terminal of this 15th transistor 3a is connected to the source terminal of the 16th transistor 3b, and the source terminal is grounded as shown in the figure. Such a 15th transistor 3a has a structure in which the gate terminal and the drain terminal are interconnected via the 16th transistor 3b, that is, a structure in which it is diode-connected via the 16th transistor 3b.

[0095] The 16th transistor 3b is an n-type MOS transistor, similar to the 15th transistor 3a. Its gate terminal is connected to the 7th bias terminal Tb7, and its source terminal is connected to the drain terminal of the 15th transistor 3a. In other words, the 16th transistor 3b is a cascode transistor cascode-connected to the 15th transistor 3a.

[0096] The drain terminal of this 16th transistor 3b is connected to the output terminal Tout, the gate terminal of the 15th transistor 3a, and the drain terminal of the 10th transistor 1q in the rectifier 1, that is, the output terminal of the third current mirror circuit in the rectifier 1. The drain terminal of this 16th transistor 3b is the input terminal of the current / voltage converter 3.

[0097] The detected current Is flows into the input terminal of the current / voltage converter 3 from the third current mirror circuit of the rectifier 1. In other words, the detected current Is equivalent to that of the second input terminal of the current mirror 2 flows into the current / voltage converter 3. The current / voltage converter 3 converts this detected current Is into a voltage signal and outputs it as an output signal Vout to the output terminal Tout.

[0098] Such a power detector A has the basic configuration shown in Figure 2. Specifically, power detector A divides an externally supplied reference current Iref into a first current Ir and a second current Ih, supplies the first current Ir to rectifier 1, and supplies the second current Ih to the first input terminal of current mirror 2. Rectifier 1 generates a detection current Is from the first current Ir and the input signal Vin (high-frequency signal) and supplies it to the second input terminal of current mirror 2. Rectifier 1 also supplies the detection current Is to current / voltage converter 3.

[0099] The current mirror 2 adjusts the second current Ih flowing into the first input terminal to compensate for the effect of temperature fluctuations on the threshold voltage Vt of the third transistor 1f (rectifier transistor), based on the detected current Is input to the second input terminal. The current / voltage converter 3 converts the detected current Is into a voltage and outputs it externally as an output signal Vout.

[0100] Next, the operation of the power detector A according to this embodiment will be described in detail with reference to Figures 3 and 4.

[0101] The rectifier 1 of this power detector A operates based on the reference current Iref input to the bias current input terminal Trin from the reference current source when the input signal Vin (high frequency signal) is input to the input terminal Tin.

[0102] In other words, in this operating state, the third transistor 1f (rectifier transistor) of rectifier 1, as shown in Figure 3, half-wave rectifies the input signal Vin (high-frequency signal) with the gate bias voltage as the operating point. As a result, a superimposed current flows through the drain terminal of the third transistor 1f (rectifier transistor), i.e., the output circuit of the first current mirror circuit, where the half-wave rectified current representing the power of the input signal Vin (high-frequency signal) is superimposed on the first current Ir.

[0103] Here, Figure 3(a) shows the half-wave rectified current when an input signal Vin (high-frequency signal) is half-wave rectified with a gate bias voltage equal to the threshold voltage Vt of the n-type MOS transistor. Figure 3(b) shows the half-wave rectified current when an input signal Vin with the same amplitude as in Figure 3(a) is half-wave rectified with a gate bias voltage lower than the threshold voltage Vt of the n-type MOS transistor. Furthermore, Figure 3(c) shows the half-wave rectified current when an input signal Vin with the same amplitude as in Figure 3(a) is half-wave rectified with the same gate bias voltage as in Figure 3(b), for example, when the threshold voltage Vt of the n-type MOS transistor is lower than in Figure 3(b) due to temperature fluctuations.

[0104] This superimposed current is converted into a detection voltage Vs by the smoothing circuits of the second and third current mirror circuits, and output as a detection current Is from the output circuits of the second and third current mirror circuits to the second input terminal of the current mirror 2 and the input terminal of the current / voltage converter 3.

[0105] Here, when the operating temperature of the third transistor 1f (rectifier transistor) fluctuates, the threshold voltage Vt of the third transistor 1f (rectifier transistor) rises in accordance with the increase in operating temperature and falls in accordance with the decrease in operating temperature. As a result, a current drift component caused by the fluctuation in the threshold voltage Vt is superimposed on the detected current Is.

[0106] In current mirror 2, when the detection current Is input to the second input terminal fluctuates due to the current drift component, the second current Ih input to the first input terminal fluctuates similarly. This fluctuation in the second current Ih causes a fluctuation in the first current Ir flowing into rectifier 1. For example, when the detection current Is increases, the second current Ih increases similarly, and as a result, the first current Ir decreases by the amount of the increase in the second current Ih. Conversely, when the detection current Is decreases, the second current Ih decreases similarly, and as a result, the first current Ir increases by the amount of the decrease in the second current Ih.

[0107] In other words, current mirror 2 operates to provide feedback correction to the gate bias voltage of the third transistor 1f (rectifier transistor) set by the input circuit of the first current mirror circuit. Therefore, the effect of temperature fluctuations on the threshold voltage Vt of the third transistor 1f (rectifier transistor) in the detected current Is is eliminated or suppressed.

[0108] As shown in Figure 4, the power detector A according to this embodiment makes it possible to obtain a sufficiently stable output signal Vout (Voltage) with respect to temperature fluctuations of the third transistor 1f (rectifier transistor). That is, as can be seen by comparing Figure 4(a), which shows the input / output characteristics of the power detector A according to this embodiment, with Figure 4(b), which shows a comparative example without the current mirror 2, the input / output characteristics of the power detector A according to this embodiment are sufficiently stable with respect to temperature fluctuations of the third transistor 1f (rectifier transistor) over a range of 0 to 125 degrees C.

[0109] The power detector A according to this embodiment includes a rectifier 1 that generates a detection current Is (detection signal) indicating the power of the input signal Vin (detection signal) by half-wave rectifying the input signal Vin (detection signal) based on a predetermined gate bias voltage, and a current mirror 2 (bias adjuster) that adjusts the gate bias voltage to suppress temperature fluctuations of the detection current Is (detection signal). It is equipped with.

[0110] In this embodiment, the gate bias voltage of the rectifier 1 is adjusted by the current mirror 2 (bias adjuster) to suppress temperature fluctuations in the detected current Is (detection signal). Therefore, according to this embodiment, it is possible to provide a power detector A that can more accurately measure the power of the input signal Vin (signal to be detected).

[0111] Furthermore, in the power detector A according to this embodiment, the current mirror 2 (bias adjuster) adjusts the gate bias voltage by adjusting the first current Ir that flows into the rectifier 1 based on the detected current Is (detection signal). According to this embodiment, by adjusting the first current Ir, it is possible to easily suppress temperature fluctuations in the detected current Is (detection signal).

[0112] Furthermore, in the power detector A according to this embodiment, the bias adjuster is a current mirror 2 that adjusts the first current Ir by subtracting the second current Ih from the reference current Iref. According to this embodiment, the first current Ir can be easily adjusted by using the current mirror 2, thereby easily suppressing temperature fluctuations in the detected current Is (detection signal).

[0113] Furthermore, in the power detector A according to this embodiment, the rectifier 1 includes a first current mirror circuit consisting of an input circuit and an output circuit. The input circuit generates a gate bias voltage by converting a first current Ir into a current / voltage, and the output circuit rectifies the input signal Vin (detected signal) using the gate bias voltage.

[0114] According to this embodiment, by using the first current mirror circuit, it is possible to easily generate a gate bias voltage based on the first current Ir, thereby easily suppressing temperature fluctuations in the detected current Is (detection signal).

[0115] Furthermore, in the power detector A according to this embodiment, the rectifier 1 includes a second current mirror circuit and a third current mirror circuit that individually generate a detection current Is based on the half-wave rectified current. The second current mirror circuit outputs the detection current Is as a detection signal to the current mirror 2 (bias adjuster), and the third current mirror circuit outputs the detection current Is to the current / voltage converter 3.

[0116] According to this embodiment, the detection current Is for the current mirror 2 and the detection current Is for the output are generated separately by the second current mirror circuit and the third current mirror circuit. Therefore, it is possible to suppress the influence of the output circuit, i.e., the current / voltage converter 3, on the detection current Is supplied to the current mirror 2. Accordingly, according to this embodiment, it is possible to accurately suppress temperature fluctuations in the detection current Is (detection signal).

[0117] Furthermore, in the power detector A according to this embodiment, the second current mirror circuit and the third current mirror circuit are equipped with smoothing circuits for smoothing the half-wave rectified current. According to this invention, it is possible to obtain a stable detection current Is (detection signal).

[0118] The present invention is not limited to the embodiments described above, and for example, the following modifications are possible. (1) In the above embodiment, a high-frequency signal in the range of several to tens of GHz was used as the signal to be detected, but the present invention is not limited thereto. The present invention is applicable to power detection in signals of frequencies other than those mentioned above.

[0119] (2) In the above embodiment, the rectifier 1 is configured as shown in Figure 1, but the present invention is not limited thereto. Various other modifications to the circuit configuration of the rectifier 1 are possible.

[0120] (3) In the above embodiment, the bias adjuster of the present invention was configured as a current mirror 2, but the present invention is not limited thereto. Various circuit configurations other than a current mirror 2 are possible for the bias adjuster of the present invention.

[0121] (4) In the above embodiment, a MOS transistor (unipolar transistor) was used as the transistor, but the present invention is not limited thereto. A bipolar transistor may be used instead of a unipolar transistor. Also, a structure other than a MOS transistor may be used as the unipolar transistor.

[0122] (5) In the above embodiment, the mirror ratio of the first to third current mirror circuits was set to "1", but the present invention is not limited thereto. That is, the mirror ratio of the first to third current mirror circuits may be set as appropriate according to the requirements of the circuit design. For example, the mirror ratio of the first to third current mirror circuits may be set to a value of 1 or more. [Explanation of symbols]

[0123] A...Power detector, Tin...Input terminal, 1...Rectifier, Tb1...First bias terminal, Tb2...Second bias terminal, Tb3...Third bias terminal, Tb4...Fourth bias terminal, 1a...First capacitor, 1b...First resistor, 1c...Second capacitor, 1d...First transistor, 1e...Second transistor, 1f...Third transistor, 1g...Fourth transistor, 1h...Fifth transistor, 1i...Sixth transistor, 1j...Second resistor, 1k...Third capacitor, 1m...Seventh transistor ,1n…8th transistor,1p…9th transistor,1q…10th transistor,Trin…bias current input terminal,Td…power terminal,2…current mirror,Tb5…5th bias terminal,Tb6…6th bias terminal,2a…11th transistor,2b…12th transistor,2c…13th transistor,2d…14th transistor,3…current / voltage converter,Tb7…7th bias terminal,3a…15th transistor,3b…16th transistor,Tout…output terminal

Claims

1. A rectifier that generates a detection signal indicating the power of the detected signal by rectifying the detected signal based on a predetermined threshold voltage, A bias adjuster that adjusts the bias voltage of the rectifier to suppress temperature fluctuations of the detection signal, A power detector equipped with the following features.

2. The power detector according to claim 1, wherein the bias adjuster adjusts the bias voltage by adjusting the first current flowing into the rectifier based on the detection signal.

3. The power detector according to claim 2, wherein the bias adjuster is a current mirror that adjusts the first current by subtracting a second current from a reference current.

4. The rectifier includes a first current mirror circuit consisting of an input circuit and an output circuit. The input circuit generates the bias voltage by converting the first current into a current / voltage. The power detector according to claim 2 or 3, wherein the output circuit generates a rectified current by rectifying the signal to be detected with the bias voltage.

5. The rectifier includes a second current mirror circuit and a third current mirror circuit that individually generate detection currents based on the rectified current. The second current mirror circuit outputs the detected current as the detection signal to the bias adjuster. The third current mirror circuit outputs the detected current to a current / voltage converter, as described in claim 4.

6. The power detector according to claim 5, wherein the second current mirror circuit and the third current mirror circuit are each equipped with a smoothing circuit for smoothing the rectified current.

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