Imaging device

Abstract

The present invention provides an imaging device that can output the integrated value of multiple count values. [Solution] The imaging device includes a light receiving unit that receives light and generates a pulse signal, and a pixel that includes a counter for counting the pulse signal, a reading unit that reads the count value of the pulse signal in each of the N subframe periods when N is an integer of 2 or more and the frame period consists of N subframe periods, an integrating unit that integrates the count values, and an output unit that outputs a first integrated value of the N count values ​​and can output a second integrated value of a number of count values ​​less than N.

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] Conventionally, there has been an imaging device including pixels having an APD (avalanche photodiode) capable of detecting weak light at the single-photon level. The imaging device of Patent Document 1 includes pixels having a counter that counts signals from the APD during a frame period, and an external memory provided outside the pixels. The imaging device of Patent Document 1 increases the number of bits of the integrated value while suppressing the number of bits of the counter by storing the value obtained by integrating the count values from the counter in the external memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in Patent Document 1, it was not possible to output a plurality of integrated values from the count values during the frame period.

[0005] Therefore, an object of the present invention is to provide an imaging device capable of outputting a plurality of integrated values from the count values during the frame period.

Means for Solving the Problems

[0006] According to one disclosure of this specification, an imaging device is provided comprising: a pixel including a light receiving unit that receives light and generates a pulse signal, and a counter that counts the pulse signal; a reading unit that reads the count value of the pulse signal in each of the N subframe periods, where N is an integer of 2 or more and the frame period consists of N subframe periods; an integrating unit that integrates the count values; and an output unit that outputs a first integrated value of the N count values ​​and can output a second integrated value of fewer than N count values. [Effects of the Invention]

[0007] According to the present invention, an imaging device can be realized that can output multiple integrated values ​​from the count value of the frame period. [Brief explanation of the drawing]

[0008] [Figure 1] This is an exploded perspective view of the imaging device according to the first embodiment. [Figure 2] This is a block diagram of a circuit board according to the first embodiment. [Figure 3] This figure shows the configuration and operation of pixels according to the first embodiment. [Figure 4] This is a schematic diagram of the operating timing of the imaging device according to the first embodiment. [Figure 5] This diagram shows the operation of the reading unit according to the first embodiment. [Figure 6] This is a timing chart of the imaging device according to the first embodiment. [Figure 7] This is a block diagram of a circuit board according to the second embodiment. [Figure 8] This is a schematic diagram of the operating timing of the imaging device according to the second embodiment. [Figure 9] This is a block diagram of the circuit board according to the third embodiment. [Figure 10] This is a timing chart of the imaging device according to the third embodiment. [Figure 11] This is a circuit diagram of the memory and signal lines according to the fourth embodiment. [Figure 12] It is a diagram showing the operation of the reading unit according to the fourth embodiment. [Figure 13] It is a schematic diagram of the operation timing of the imaging device according to the fourth embodiment. [Figure 14] It is a block diagram of the device according to the fifth embodiment. [Figure 15] It is a block diagram of the device according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0009] [First Embodiment] FIG. 1 is an exploded perspective view of an imaging device 100 according to the present embodiment. The imaging device 100 includes a sensor substrate 101 and a circuit substrate 102. The sensor substrate 101 and the circuit substrate 102 are laminated and electrically connected. The imaging device 100 includes a plurality of pixels. The plurality of pixels typically form an image, but when used for TOF (Time of Flight), it is not necessarily required to form an image. Each pixel includes an APD (Avalanche Photodiode) 10 and a signal processing circuit 20.

[0010] In the pixel region 101a of the sensor substrate 101, a plurality of APDs 10 are provided two-dimensionally. The APD 10 is a photoelectric conversion element that converts light into an electrical signal.

[0011] In the circuit region 102a of the circuit substrate 102, a plurality of signal processing circuits 20 are provided. Each of the plurality of signal processing circuits 20 is electrically connected to each APD 10 via wiring. The signal processing circuit 20 converts the electrical signal from the APD 10 into a pulse signal and counts the pulse signal

[0012] [[ID=3३]]FIG. 2 is a block diagram of the circuit substrate 102 according to the present embodiment. The circuit substrate 102 includes a plurality of signal processing circuits 20, a vertical scanning circuit (not shown), a reading unit 30, an integrating unit 40, an output unit 50, and a control unit 60.

[0013] The signal processing circuit 20 includes a waveform shaping circuit 21, a counter 22, and a memory 23. The waveform shaping circuit 21 converts the electrical signal from the APD 10 into a pulse signal and outputs the pulse signal to the counter 22.

[0014] The counter 22 counts the pulse signal from the waveform shaping circuit 21 and outputs a multi-bit count value to the memory 23. The counter 22 can be composed of 4 bits, but is not limited to 4 bits and may be multiple bits. The counter 22 receives a reset signal from the vertical scanning circuit and resets all bits.

[0015] The memory 23 holds the count value from the counter 22. The memory 23 can be composed of a 4-bit latch circuit, but is not limited to this and other storage elements may also be used. The memory 23 is connected to the reading unit 30 via the signal line L1 and outputs the count value to the reading unit 30.

[0016] The vertical scanning circuit receives a control signal from the control unit 60 and outputs a driving control signal to the pixels. Logic circuits such as a shift register and an address decoder can be used for the vertical scanning circuit. The vertical scanning circuit sequentially scans the pixels in the circuit region 102a row by row and causes the count value of each pixel to be output to the reading unit 30 sequentially. The reading unit 30 receives a control signal from the control unit 60, reads out the count value from the memory 23 of the pixel row by row, and outputs it to the integration unit 40. Logic circuits such as a shift register and an address decoder can be used for the reading unit 30.

[0018] The integration unit 40 integrates the count values from the reading unit 30 pixel by pixel. The integration unit 40 includes an integration memory (not shown) that holds the integrated value of the count values. The integration unit 40 integrates the count value read from the integration memory with the count value from the reading unit 30 pixel by pixel and writes the integrated value into the integration memory. The integration unit 40 outputs the integrated value to the output unit 50.

[0019] <0000?109>The output unit 50 receives a control signal from the control unit 60 and outputs the integrated value from the integration unit 40 as a pixel value to the outside of the imaging device 100 via the signal line L2.

[0020] The control unit 60 generates control signals to control the operation and timing of the vertical scanning circuit, the readout unit 30, and the output unit 50, and outputs them to each functional block. At least a portion of the control signals may be output from outside the imaging device 100. The control unit 60 may be composed of various electronic components such as a CPU and memory.

[0021] Figure 3 shows the configuration and operation of a pixel according to this embodiment. Figure 3(a) is a diagram showing an APD10, a quench element 24, and a waveform shaping circuit 21 extracted from the pixel. The APD10, quench element 24, and waveform shaping circuit 21 are examples of light receiving units. The input side of the waveform shaping circuit 21 is node A, and the output side is node B. Figure 3(b) shows the waveform change of node A in Figure 3(a), and Figure 3(c) shows the waveform change of node B in Figure 3(a).

[0022] A voltage VL is applied to the anode of the APD10, and a voltage VH, higher than VL, is applied to the cathode of the APD10. A reverse bias voltage is applied to the anode and cathode to induce avalanche multiplication by the APD10. When a photon is incident on the APD10, the charge generated by the incident photon undergoes avalanche multiplication, generating an avalanche current. The APD10 has two operating modes: Geiger mode and linear mode. In Geiger mode, the reverse bias voltage applied between the anode and cathode is greater than the breakdown voltage of the APD10. In linear mode, the reverse bias voltage applied between the anode and cathode is near or below the breakdown voltage of the APD10. When operating in Geiger mode, the APD10 is called SPAD (Single Photon Avalanche Diode). The APD10 may be configured to operate in linear mode or in Geiger mode.

[0023] The quench element 24 is connected to a power supply that applies a voltage VH and to the cathode of the APD10. The quench element 24 converts the change in avalanche current generated in the APD10 into a voltage signal (electrical signal). The quench element 24 functions as a load circuit (quench circuit) when the signal is multiplied by avalanche multiplication, suppressing the voltage applied to the APD10 and thereby suppressing avalanche multiplication.

[0024] The waveform shaping circuit 21 includes an input node to which an electrical signal from the APD 10 is input, and an output node connected to the counter 22. The waveform shaping circuit 21 may be configured to include, for example, one inverter circuit. Alternatively, the waveform shaping circuit 21 may be configured as a circuit in which multiple inverter circuits are connected in series. Furthermore, the waveform shaping circuit 21 can be configured not only with NOT circuits, but also with other circuits that have a waveform shaping effect, such as logic circuits including NOR circuits and NAND circuits.

[0025] Between times t0 and t1, a voltage VH minus VL is applied to the APD10 in Figure 3(a). When a photon is incident at time t1, an avalanche multiplication current flows through the quench element 24, and the voltage at nodeA drops. As the voltage drop increases further and the potential difference applied to the APD10 decreases, the avalanche multiplication of the APD10 stops, and the voltage level at nodeA stops dropping below a certain value (time t2). Subsequently, a current flows from the voltage VL side to compensate for the voltage drop, and at time t3, nodeA settles to its original potential level. At this time, the portion of the output waveform at nodeA that exceeds the judgment threshold is waveform shaped by the waveform shaping circuit 21 and output as a pulse signal at nodeB.

[0026] Figure 4 is a schematic diagram of the operating timing of the imaging device 100 according to this embodiment. The frame period for generating a frame consists of N subframe periods. Each of the N subframe periods is of the same length, and a subframe is generated. N is an integer of 2 or more, for example, "4". The frame consists of the first to fourth subframes.

[0027] During the first counting period from time t1 to t2, the counter 22 counts pulse signals to generate the first subframe. The first counting period corresponds to the first subframe period. Memory 23 holds the count value from the counter 22. After the end of the first counting period, the counter 22 receives a reset signal from the vertical scanning circuit and resets all bits.

[0028] During the first readout period from time t2 to t3, the readout unit 30 reads the count values ​​of the first subframe from the memory 23 of multiple pixels row by row and outputs them to the integration unit 40. The first readout period is of a length equivalent to the subframe period. The second to fourth readout periods, described later, are also of a length equivalent to the subframe period.

[0029] During the first accumulation period from time t2 to t3, the accumulation unit 40 stores the count value from the first reading period in the accumulation memory.

[0030] During the second counting period from time t2 to t3, counter 22 counts pulse signals to generate the second subframe. The second counting period corresponds to the second subframe period. Memory 23 holds the count value from counter 22. After the end of the second counting period, counter 22 resets all bits.

[0031] During the second readout period from time t3 to t4, the readout unit 30 reads the count values ​​of the second subframe from the memory 23 of multiple pixels row by row and outputs them to the integration unit 40.

[0032] During the second integration period from time t3 to t4, the integration unit 40 integrates the count value from the second reading period with the count value in the integration memory for each pixel and stores the integrated value. The integrated value (second integrated value) is the value obtained by integrating the count values ​​of the first and second subframes.

[0033] During the third count period from time t3 to t4, counter 22 counts pulse signals to generate the third subframe. The third count period corresponds to the third subframe period. Memory 23 holds the count value from counter 22. After the end of the third count period, counter 22 resets all bits.

[0034] During the third readout period from time t4 to t5, the readout unit 30 reads the count values ​​of the third subframe from the memory 23 of multiple pixels row by row and outputs them to the integration unit 40.

[0035] During the third integration period from time t4 to t5, the integration unit 40 integrates the count value from the third reading period with the count value in the integration memory for each pixel and stores the integrated value. The integrated value is the sum of the count values ​​from the first to the third subframes.

[0036] During the fourth count period from time t4 to t5, counter 22 counts pulse signals to generate the fourth subframe. The fourth count period corresponds to the fourth subframe period. Memory 23 holds the count value from counter 22. After the end of the fourth count period, counter 22 resets all bits.

[0037] During the fourth readout period from time t5 to t6, the readout unit 30 reads the count values ​​of the fourth subframe from the memory 23 of multiple pixels row by row and outputs them to the integration unit 40. In this way, the readout unit 30 reads the count values ​​according to the time series of the first to fourth subframe periods.

[0038] During the fourth integration period from time t5 to t6, the integration unit 40 integrates the count values ​​from the fourth reading period with the count values ​​in the integration memory for each pixel and stores the integrated value. The integrated value (first integrated value) is the value obtained by integrating the count values ​​of each of the first to fourth subframes. That is, the integrated value for the fourth integration period is the pixel value of one frame. The integration unit 40 sequentially integrates the count values ​​in the order in which the reading unit 30 reads the count values.

[0039] During the fourth output period from time t5 to t6, as shown in Figure 4(A), the output unit 50 outputs the integrated value of each pixel during the fourth integration period as a pixel value to the outside of the imaging device 100. During the first to third output periods from time t2 to t5, the output unit 50 does not output integrated values ​​and is therefore stopped, entering a power-saving state. Each of the first to fourth output periods corresponds to a subframe period.

[0040] During the first counting period from time t5 to t6, counter 22 counts pulse signals to generate the first subframe of the K+1 frame, which is the frame following the K frame. The K+1 frame is processed in the same way as the K frame, so its explanation is omitted.

[0041] Figure 4(A) illustrates an example where the output unit 50 outputs only the accumulated value for the fourth accumulation period. Figure 4(B) illustrates an example where the output unit 50 outputs the accumulated values ​​for the second and fourth accumulation periods. Note that the counter 22, read unit 30, and accumulation unit 40 operate in the same way, so their explanation is omitted.

[0042] As shown in Figure 4(B), during the second output period from time t3 to t4, the output unit 50 can output the integrated value of each pixel during the second integration period to the outside of the imaging device 100. The integrated value during the second integration period is the sum of the count values ​​of the first and second subframes. That is, the integrated value during the second integration period does not include the count values ​​of the third and fourth subframes. During the first output period from time t2 to t3 and the third output period from time t4 to t5, the output unit 50 is stopped and in a power-saving state.

[0043] During the fourth output period from time t5 to t6, the output unit 50 outputs the integrated value of each pixel during the fourth integration period to the outside of the imaging device 100. The integrated value of the fourth integration period is the value obtained by integrating the count values ​​of the first to fourth subframes. In this way, the output unit 50 may also output the integrated values ​​of the second and fourth integration periods.

[0044] The cumulative value of the second integration period is a smaller number of counts than the cumulative value of the fourth integration period, thus reducing subject blur and making it suitable for subject recognition processing. The cumulative value of the fourth integration period is a larger number of counts than the cumulative value of the second integration period, thus increasing brightness and making it suitable for image display. Each cumulative value can be used differently depending on the application.

[0045] Figure 4(C) illustrates an example in which the output unit 50 outputs the accumulated values ​​for the first, second, and fourth accumulation periods. Note that the counter 22, read unit 30, and accumulation unit 40 operate in the same way, so their explanations are omitted.

[0046] As shown in Figure 4(C), during the first output period from time t2 to t3, the output unit 50 outputs the integrated value of each pixel during the first integration period to the outside of the imaging device 100. The integrated value during the first integration period is the same as the count value of the first subframe.

[0047] During the second output period from time t3 to t4, the output unit 50 outputs the integrated value of each pixel during the second integration period to the outside of the imaging device 100. The integrated value during the second integration period is the sum of the count values ​​of the first and second subframes. During the third output period from time t4 to t5, the output unit 50 is stopped and in a power-saving state.

[0048] During the fourth output period from time t5 to t6, the output unit 50 outputs the integrated value of each pixel during the fourth integration period to the outside of the imaging device 100. The integrated value of the fourth integration period is the value obtained by integrating the count values ​​of the first to fourth subframes. In this way, the output unit 50 may output the integrated values ​​of the first, second, and fourth integration periods.

[0049] Figure 5 shows the operation of the reading unit 30 according to this embodiment. In the first reading period, the reading unit 30 reads all bits (in this case, 4 bits) of the count value in the memory 23 row by row. Similarly, in the second to fourth reading periods, the reading unit 30 reads all bits of the count value in the memory 23 row by row. The integrating unit 40 integrates all bits of the count value.

[0050] Figure 6 is a timing chart of the imaging device 100 according to this embodiment. Figure 6 will explain in detail the operation of the imaging device 100 shown in Figure 4(B). Specifically, it will explain the operation of the output unit 50 to output the integrated values ​​of the second and fourth integration periods. In Figure 6, the operation of a single pixel will be explained to facilitate understanding of the explanation.

[0051] At time t1, counter 22 resets its count value and begins counting the pulse signal in the first subframe.

[0052] At time t2, counter 22 receives a pulse signal from waveform shaping circuit 21 and increments its count value. Thereafter, counter 22 increments its count value each time it receives a pulse signal.

[0053] At time t3, memory 23 receives a memory transfer signal from the vertical scanning circuit and holds the count value of the first subframe. Since the count value at time t3 is "9", memory 23 holds "9". Note that memory 23 holds the count value of the previous frame before time t3.

[0054] At time t4, counter 22 resets its count value and begins counting the pulse signal in the second subframe.

[0055] At time t5, the counter 22 receives a pulse signal from the waveform shaping circuit 21 and increments its count value. The count value is incremented to "1".

[0056] At time t6, the reading unit 30 receives a read signal from the control unit 60 and reads the count value from memory 23. Since the count value of memory 23 at time t6 is "9", the reading unit 30 reads the count value "9".

[0057] At time t7, the reading unit 30 outputs the count value "9" from memory 23 to the integrating unit 40. The integrating unit 40 stores the count value "9" in the integrating memory. The integrating unit 40 retains the accumulated value of the previous frame. After clearing the accumulated value of the previous frame period (first frame period), the integrating unit 40 stores the count value "9" of the Kth frame period (second frame period) in the integrating memory. Note that if the integrating unit 40 wants to obtain a count result for a longer period than the frame period, it may add the count value "9" to the accumulated value of the previous frame period without clearing the accumulated value of the previous frame period.

[0058] At time t8, memory 23 receives a memory transfer signal from the vertical scanning circuit and holds the count value of the second subframe. Since the count value at time t8 is "6", memory 23 holds "6".

[0059] At time t9, counter 22 resets its count value and begins counting the pulse signal in the third subframe.

[0060] At time t10, the reading unit 30 receives a read signal from the control unit 60 and reads the count value from memory 23. Since the count value of memory 23 at time t10 is "6", the reading unit 30 reads the count value "6".

[0061] At time t11, the reading unit 30 outputs the count value "6" from memory 23 to the integrating unit 40. The integrating unit 40 adds the count value "6" to the count value "9" in the integrating memory and stores the integrated value "15" in the integrating memory.

[0062] At time t12 (start time of the second output period), the output unit 50 outputs the integrated value "15" of the count values ​​of the first and second subframes as a pixel value to the outside of the imaging device 100.

[0063] The processes at times t13-t16 and t17-t20 are the same as those at times t8-t11, so their explanations are omitted.

[0064] At time t21 (start time of the fourth output period), the output unit 50 outputs the cumulative value "22" of the count values ​​of the first to fourth subframes in the K frame as a pixel value to the outside of the imaging device 100.

[0065] As described above, the imaging device 100 according to this embodiment can output pixel values ​​obtained by accumulating count values ​​up to a certain point in the frame period. In other words, the imaging device 100 can output pixel values ​​for count periods of different lengths. Pixel values ​​for short count periods are suitable for subject recognition processing because they can reduce subject blur. Pixel values ​​for long count periods are suitable for image display because they can increase brightness. The imaging device 100 can output multiple pixel values ​​that can be used depending on the application, based on the count values ​​for the frame period.

[0066] [Second Embodiment] Figure 7 is a block diagram of the circuit board 102A according to this embodiment. The circuit board 102A differs from the circuit board 102 according to the first embodiment in that it includes a storage unit 70 for adjusting the timing of outputting pixel values ​​from the output unit 50. The same reference numerals are used for components that are the same as those in the circuit board 102 according to the first embodiment, and detailed descriptions are omitted.

[0067] The integration unit 40 outputs the integrated count value to the storage unit 70. The storage unit 70 is a frame memory capable of storing the integrated value of all pixels and stores the integrated value from the integration unit 40. The output unit 50 outputs the integrated value from the storage unit 70 to the outside of the imaging device 100.

[0068] Figure 8 is a schematic diagram of the operating timing of the imaging device 100 according to this embodiment. The operation of the counter 22, readout unit 30, and integrator unit 40 at times t1 to t5 in Figure 8 is the same as the operation at times t1 to t5 in Figure 4, so an explanation is omitted.

[0069] During the fourth integration period from time t5 to t6, the integration unit 40 integrates the count values ​​from the fourth reading period with the count values ​​in the integration memory for each pixel and stores the integrated value. The integrated value is the sum of the count values ​​from the first to the fourth subframes. The integration unit 40 outputs the integrated value from the fourth integration period to the storage unit 70.

[0070] During the period from time t5 to t8, as shown in Figure 8(A), the storage unit 70 stores the accumulated value of the fourth accumulation period. The period from time t5 to t8 corresponds to the length of four subframe periods.

[0071] During the fourth output period from time t5 to t8, the output unit 50 outputs the integrated value of each pixel in the fourth integration period of the storage unit 70 as a pixel value to the outside of the imaging device 100. The fourth output period is longer than the subframe period and corresponds to the length of four subframe periods.

[0072] Figure 8(A) illustrates an example where the output unit 50 outputs only the integrated value for the fourth integration period. Figure 8(B) illustrates an example where the output unit 50 outputs the integrated values ​​for the second and fourth integration periods, respectively.

[0073] During the second integration period from time t3 to t4, the integration unit 40 integrates the count values ​​from the second reading period with the count values ​​in the integration memory for each pixel and stores the integrated value. The integrated value is the sum of the count values ​​from the first and second subframes. The integration unit 40 outputs the integrated value from the second integration period to the storage unit 70.

[0074] During the period from time t3 to t5, as shown in Figure 8(B), the storage unit 70 stores the accumulated value of the second accumulation period. The period from time t3 to t5 corresponds to the length of two subframe periods.

[0075] During the second output period from time t3 to t5, the output unit 50 outputs the integrated value of each pixel in the second integration period of the storage unit 70 as a pixel value to the outside of the imaging device 100. The second output period is longer than the subframe period and is equivalent in length to two subframe periods.

[0076] During the fourth integration period from time t5 to t6, the integration unit 40 integrates the count values ​​from the fourth reading period with the count values ​​in the integration memory for each pixel and stores the integrated value. The integrated value is the sum of the count values ​​from the first to the fourth subframes. The integration unit 40 outputs the integrated value from the fourth integration period to the storage unit 70.

[0077] During the period from time t5 to t7, as shown in Figure 8(B), the storage unit 70 stores the accumulated value of the fourth accumulation period. The period from time t5 to t7 corresponds to the length of two subframe periods.

[0078] During the fourth output period from time t5 to t7, the output unit 50 outputs the integrated value of each pixel in the fourth integration period of the storage unit 70 as a pixel value to the outside of the imaging device 100. The fourth output period is longer than the subframe period and is equivalent in length to two subframe periods.

[0079] As described above, according to the imaging device 100 of this embodiment, the output unit 50 can output pixel values ​​with an output period longer than the subframe period. This allows the imaging device 100 to flexibly adjust the timing of pixel value output.

[0080] [Third Embodiment] Figure 9 is a block diagram of the circuit board 102B according to this embodiment. The circuit board 102B differs from the circuit board 102 according to the first embodiment in that it integrates the higher bits of the count value and combines them with the lower bits. The same reference numerals are used for the same components as in the circuit board 102 according to the first embodiment, and detailed explanations are omitted.

[0081] Counter 22 counts pulse signals and outputs the count value to memory 23. Counter 22 also receives a first reset signal from the vertical scanning circuit, which resets all of its bits, and resets all of its bits. Counter 22 also receives a second reset signal, which resets only the most significant bit, and resets the most significant bit.

[0082] The reading unit 30B reads all bits of the count value from the memory 23 of multiple pixels row by row and outputs the most significant bit of the count value to the integration unit 40B via the signal line L3. The reading unit 30B also outputs the lower bits of the count value to the combining unit 80 via the signal line L4. The lower bits of the count value are the bits of the count value excluding the most significant bit. If the count value is 4 bits, the lower bits will be 3 bits.

[0083] The integration unit 40B integrates the most significant bit of the count value from the reading unit 30 for each pixel. The integration unit 40B includes an integration memory that holds the integrated value of the most significant bit of the count value. The integration unit 40B integrates the most significant bit of the count value read from the integration memory with the most significant bit of the count value from the reading unit 30 for each pixel, and writes the integrated value of the most significant bits to the integration memory. The integration unit 40B outputs the integrated value from the integration memory to the synthesis unit 80.

[0084] The combining unit 80 receives a control signal from the control unit 60, combines the integrated value of the most significant bit from the integrating unit 40B with the lower bits of the count value from the reading unit 30 to generate a pixel value, and outputs it to the output unit 50.

[0085] Figure 10 is a timing chart of the imaging device 100 according to this embodiment. Figure 10 illustrates the operation of the output unit 50, which outputs the integrated values ​​for the second and fourth integration periods. To facilitate understanding of the explanation, Figure 10 describes the operation of a single pixel.

[0086] At time t1, the counter 22 receives a first reset signal from the vertical scanning circuit, resets all bits of the count value, and begins counting the pulse signal in the first subframe.

[0087] At time t2, counter 22 receives a pulse signal from waveform shaping circuit 21 and increments its count value. Thereafter, counter 22 increments its count value each time it receives a pulse signal.

[0088] At time t3, memory 23 receives a memory transfer signal from the vertical scanning circuit and holds the count value of the first subframe. Since the count value at time t3 is "9", memory 23 holds "9". Note that memory 23 holds the count value of the previous frame before time t3.

[0089] At time t4, counter 22 receives a second reset signal from the vertical scanning circuit and resets the most significant bit of the count value. Since the count value is "1001" in binary ("9" in decimal), when the most significant bit of the count value is reset, the count value becomes "0001" in binary ("1" in decimal).

[0090] At time t5, counter 22 receives a pulse signal from waveform shaping circuit 21 and increments its count value. The count value is incremented to the decimal number "2".

[0091] At time t6, the reading unit 30 receives a read signal from the control unit 60 and reads the count value from memory 23. Since the count value of memory 23 at time t6 is "9", the reading unit 30 reads the count value "9".

[0092] At time t7, the read unit 30 outputs the most significant bit "1" of the count value "1001" (decimal "9") in memory 23 to the integrator unit 40B. The integrator unit 40B stores the most significant bit "1" in the integrator memory. The integrator unit 40 holds the accumulated value of the most significant bit of the previous frame. After clearing the accumulated value of the most significant bit of the previous frame, the integrator unit 40B stores the most significant bit "1" in the integrator memory. Note that if the integrator unit 40B wants to obtain a count result for a longer period than the frame duration, it may accumulate the most significant bit "1" to the accumulated value of the most significant bit of the previous frame without clearing the accumulated value of the most significant bit of the previous frame.

[0093] At time t8, memory 23 receives a memory transfer signal from the vertical scanning circuit and holds the count value of the second subframe. Since the count value at time t8 is "7", memory 23 holds "7".

[0094] At time t9, counter 22 receives a second reset signal from the vertical scanning circuit and resets the most significant bit of the count value. Since the count value is binary "0111" (decimal "7"), even if the most significant bit of the count value is reset, the count value remains unchanged as binary "0111" (decimal "7").

[0095] At time t10, the reading unit 30 receives a read signal from the control unit 60 and reads the count value from memory 23. Since the count value of memory 23 at time t10 is "7", the reading unit 30 reads the count value "7".

[0096] At time t11, the read unit 30 outputs the most significant bit "0" of the count value "0111" (decimal "7") in memory 23 to the integrator unit 40B. The integrator unit 40B accumulates the most significant bit "0" with the most significant bit "1" in the integrator memory and stores the accumulated value "1" in the integrator memory. The integrator unit 40B outputs the accumulated value "1" to the synthesizer unit 80. The accumulated value "1" indicates the number of most significant bits "1". That is, the accumulated value "1" indicates that the number of most significant bits "1" in the count value is 1. Since the count value is 4 bits, the accumulated value of the most significant bits "1" is the binary number "1000" (decimal "8"). Note that the accumulated value "1" is an example of the fourth accumulated value.

[0097] At time t12, the combining unit 80 combines the most significant bit value "1" (binary "1000") from the integrating unit 40B with the lower bit "111" (decimal "7") from the reading unit 30 to generate the integrated value of all bits (binary "1111", decimal "15"). The combining unit 80 outputs the integrated value of all bits to the output unit 50. The integrated value is the sum of the count values ​​of the first and second subframes. During the second output period, the output unit 50 outputs the integrated value (decimal "15") as a pixel value to the outside of the imaging device 100.

[0098] The processes at times t13-t16 and t17-t20 are the same as those at times t8-t11, so their explanations are omitted.

[0099] At time t21, the combining unit 80 combines the most significant bit value "2" (binary "10000") from the integrating unit 40B with the lower bit "110" (decimal "6") from the reading unit 30. The most significant bit value "2" is "10000" (decimal "16") in binary because there are two most significant bits "1" in the 4 bits. The combining unit 80 generates the integrated value of all bits (binary "10110", decimal "22") and outputs it to the output unit 50. The integrated value is the sum of the count values ​​of the first to fourth subframes. During the fourth output period, the output unit 50 outputs the integrated value (decimal "22") as a pixel value to the outside of the imaging device 100. Note that the most significant bit's cumulative value of "2" is an example of a third cumulative value.

[0100] As described above, the imaging device 100 according to this embodiment integrates the most significant bit of the count value and combines it with the lower bits, thus improving the processing speed compared to the imaging device 100 according to the first embodiment, which integrates all bits of the count value.

[0101] [Fourth Embodiment] Figure 11 is a circuit diagram of the memory 23 and signal lines L1a and L1b according to this embodiment. The imaging device 100 of this embodiment differs from the imaging device 100 of the third embodiment, which reads all bits of the count value from the memory 23, in that it reads the upper bits and lower bits of the count value separately from the memory 23.

[0102] Memory 23 is a 4-bit latch circuit (memory element) and is located in circuit region 102a. Signal lines L1a and L1b are wired in each column of circuit region 102a. In memory 23, the latch circuit for bit 0 is connected to signal line L1a via switch SW1, and the latch circuit for bit 1 is connected to signal line L1b via switch SW2. The latch circuit for bit 2 is connected to signal line L1a via switch SW3, and the latch circuit for bit 3 is connected to signal line L1b via switch SW4. Bits 0 and 1 are the lower bits, and bits 2 and 3 are the higher bits.

[0103] When the vertical scanning circuit switches SW1 to SW4 on or off, either the latch circuit for the higher bits or the latch circuit for the lower bits is electrically connected to the readout unit 30 via signal lines L1a and L1b. When the vertical scanning circuit turns on switches SW3 and SW4 and off switches SW1 and SW2, the latch circuit for the higher bits is connected to the readout unit 30 via signal lines L1a and L1b. When the vertical scanning circuit turns on switches SW1 and SW2 and off switches SW3 and SW4, the latch circuit for the lower bits is connected to the readout unit 30 via signal lines L1a and L1b. By switching each switch, the vertical scanning circuit can output 4 bits using two signal lines L1a and L1b. This reduces the number of signal lines compared to outputting 4 bits using four signal lines. Reducing the number of signal lines is effective when the area of ​​signal lines wired in the circuit region 102a is limited due to pixel miniaturization.

[0104] Figure 12 shows the operation of the read unit 30B according to this embodiment. As shown in Figure 12(A), the read unit 30B reads only the upper bits of the count value of the memory 23 row by row during the third read period. Specifically, with the latch circuit for the upper bits of the memory 23 connected to the read unit 30B via signal lines L1a and L1b, the read unit 30B reads the upper bits of the count value of the memory 23 at the pixels of the first row of the circuit area 102a. Similarly, the read unit 30B reads the upper bits of the count value at the pixels of the second row of the circuit area 102a. The read unit 30B similarly reads the upper bits of the count value at the pixels of the third to the Mth row of the circuit area 102a. The read unit 30B can read only the upper bits of the count value in a shorter time than it takes to read both the upper and lower bits of the count value during the third read period. The third read period is approximately half the length of the fourth read period, which reads all bits of the count value in memory 23. The read unit 30B stops and enters a power-saving state after it has finished reading only the upper bits of the count value until the start of the next read period.

[0105] As shown in Figure 12(B), during the fourth reading period, the read unit 30B reads the upper and lower bits of the count value from memory 23 row by row. Specifically, at the first row of pixels in circuit region 102a, with the latch circuit for the upper bits of memory 23 connected to the read unit 30B via signal lines L1a and L1b, the read unit 30B reads the upper bits of the count value from memory 23. With the latch circuit for the lower bits of memory 23 connected to the read unit 30B via signal lines L1a and L1b, the read unit 30B reads the lower bits of the count value from memory 23. Similarly, the read unit 30B reads the upper and lower bits of the count value from memory 23 at the pixels of the second to the Mth rows of circuit region 102a. Since the read unit 30B reads both the upper and lower bits, it does not stop reading during the fourth reading period.

[0106] Figure 13 is a schematic diagram of the operating timing of the imaging device 100 according to this embodiment. During the first counting period from time t1 to t2, the counter 22 counts pulse signals to generate the first subframe. The memory 23 holds the count value from the counter 22. After the end of the first counting period, the counter 22 resets its upper bits.

[0107] During the first readout period from time t2 to t3, the readout unit 30B reads the upper bits of the count value of the first subframe from the memory 23 of multiple pixels row by row. The readout unit 30B outputs the upper bits of the count value to the integration unit 40B.

[0108] During the first integration period from time t2 to t3, the integration unit 40B stores the higher bits of the count value from the first reading period in the integration memory.

[0109] During the second counting period from time t2 to t4, counter 22 counts pulse signals to generate the second subframe. Memory 23 holds the count value from counter 22. After the end of the second counting period, counter 22 resets its higher bits.

[0110] During the stop period from time t3 to t4, the read unit 30B stops because it does not read the lower bits of the count value of the first subframe, and enters a power-saving state.

[0111] During the stop period from time t3 to t4, the integrator 40B stops because it does not integrate the lower bits of the count value of the first subframe, and enters a power-saving state.

[0112] During the second readout period from time t4 to t5, the readout unit 30B reads the upper bits of the count value of the second subframe from the memory 23 of multiple pixels row by row. The readout unit 30B outputs the upper bits of the count value to the integration unit 40B.

[0113] During the second integration period from time t4 to t5, the integration unit 40B integrates the upper bits of the count value from the second reading period into the upper bits of the integration memory for each pixel and stores the integrated value. The integrated value is the value obtained by integrating the upper bits of the count values ​​of the first and second subframes.

[0114] During the third counting period from time t4 to t6, counter 22 counts pulse signals to generate the third subframe. Memory 23 holds the count value from counter 22. After the end of the third counting period, counter 22 resets its higher bits.

[0115] During the stop period from time t5 to t6, the read unit 30B stops because it does not read the lower bits of the count value of the second subframe, and enters a power-saving state.

[0116] During the stop period from time t5 to t6, the integrator 40B stops because it does not integrate the lower bits of the count value of the second subframe, and enters a power-saving state.

[0117] During the third readout period from time t6 to t7, the readout unit 30B reads the upper bits of the count value of the third subframe from the memory 23 of multiple pixels row by row. The readout unit 30B outputs the upper bits of the count value to the integration unit 40B.

[0118] During the third integration period from time t6 to t7, the integration unit 40B integrates the upper bits of the count value from the third reading period into the upper bits of the integration memory for each pixel and stores the integrated value. The integrated value is the value obtained by integrating the upper bits of the count values ​​of each of the first to third subframes.

[0119] During the fourth counting period from time t6 to t8, counter 22 counts pulse signals to generate the fourth subframe. Memory 23 holds the count value from counter 22. After the end of the fourth counting period, counter 22 resets all bits.

[0120] During the stop period from time t7 to t8, the read unit 30B stops because it does not read the lower bits of the count value of the third subframe, and enters a power-saving state.

[0121] During the stop period from time t7 to t8, the integrator 40B stops because it does not integrate the lower bits of the count value of the third subframe, and enters a power-saving state.

[0122] During the fourth readout period from time t8 to t9, the readout unit 30B reads the upper and lower bits of the count value of the fourth subframe from the memory 23 of multiple pixels row by row. The readout unit 30B outputs the upper bits to the integration unit 40B and the lower bits to the synthesis unit 80.

[0123] During the fourth integration period from time t8 to t9, the integration unit 40B integrates the upper bits of the count value from the fourth reading period into the upper bits of the integration memory for each pixel and stores the integrated value. The integrated value is the value obtained by integrating the upper bits of the count values ​​of each of the first to fourth subframes. The integration unit 40B outputs the integrated value of the upper bits to the synthesis unit 80.

[0124] During the fourth synthesis period from time t8 to t9, as shown in Figure 13(A), the synthesis unit 80 synthesizes the integrated value of the upper bits of the fourth integration period with the lower bits of the count value from the read unit 30B for each pixel to generate a pixel value, which is then output to the output unit 50.

[0125] During the fourth output period from time t8 to t9, the output unit 50 outputs the pixel values ​​of the fourth integration period from the combining unit 80 to the outside of the imaging device 100. During the period from time t2 to t8, the output unit 50 is stopped and enters a power-saving state. As shown in Figure 13(A), the output unit 50 outputs only the integrated value of the fourth integration period out of the first to fourth integration periods.

[0126] Figure 13(A) illustrates an example where the output unit 50 outputs only the accumulated value for the fourth accumulation period. Figure 13(B) illustrates an example where the output unit 50 outputs the accumulated values ​​for the second and fourth accumulation periods. Note that the counter 22 operates in the same way, so its explanation is omitted. Also, the operation at times t1 to t4 is the same as in Figure 13(A), so its explanation is omitted.

[0127] During the second readout period from time t4 to t6, the readout unit 30B reads the upper and lower bits of the count value of the second subframe from the memory 23 of multiple pixels row by row. The readout unit 30B outputs the upper bits to the integration unit 40B and the lower bits to the synthesis unit 80.

[0128] During the second integration period from time t4 to t6, the integration unit 40B integrates the upper bits of the count value from the second reading period into the upper bits of the integration memory for each pixel and stores the integrated value. The integrated value is the value obtained by integrating the upper bits of the count values ​​of the first and second subframes. The integration unit 40B outputs the integrated value of the upper bits to the synthesis unit 80.

[0129] During the second synthesis period from time t4 to t6, the synthesis unit 80 synthesizes the integrated value of the upper bits of the second integration period with the lower bits of the count value from the readout unit 30B for each pixel to generate the pixel value of the second integration period and outputs it to the output unit 50.

[0130] During the second output period from time t4 to t6, the output unit 50 outputs the pixel values ​​from the combining unit 80 for the second integration period to the outside of the imaging device 100. The operation from time t6 to t8 is the same as the operation in Figure 13(A), so the explanation is omitted.

[0131] During the fourth output period from time t8 to t9, the output unit 50 outputs the pixel values ​​for the fourth integration period from the combining unit 80 to the outside of the imaging device 100. In this way, the output unit 50 may output the pixel values ​​for the second and fourth integration periods, respectively.

[0132] Figure 13(C) illustrates an example in which the output unit 50 outputs the accumulated values ​​for the first, second, and fourth accumulation periods.

[0133] The operation at times t1 to t2 is the same as the operation described above, so the explanation is omitted. During the first readout period at times t2 to t4, the readout unit 30B reads the upper and lower bits of the count value of the first subframe from the memory 23 of multiple pixels row by row. The readout unit 30B outputs the upper bits to the integration unit 40B and the lower bits to the composition unit 80.

[0134] During the first integration period from time t2 to t4, the integration unit 40B stores the upper bits of the count value for each pixel in the integration memory. The integration unit 40B then outputs the upper bits of the count value to the synthesis unit 80.

[0135] During the first synthesis period from time t2 to t4, the synthesis unit 80 synthesizes the upper bits of the integrated value (count value) from the first integration period with the lower bits of the count value from the reading unit 30B for each pixel to generate the pixel value for the first integration period and outputs it to the output unit 50.

[0136] During the first output period from time t2 to t4, the output unit 50 outputs the pixel values ​​for the first integration period from the composite unit 80 to the outside of the imaging device 100.

[0137] During the second output period from time t4 to t6, the output unit 50 outputs the pixel values ​​from the combining unit 80 for the second integration period to the outside of the imaging device 100. The operation from time t6 to t8 is the same as the operation in Figure 13(A), so the explanation is omitted.

[0138] During the fourth output period from time t8 to t9, the output unit 50 outputs the pixel values ​​of the fourth integration period from the combining unit 80 to the outside of the imaging device 100. In this way, the output unit 50 may output the integrated values ​​of the first, second, and fourth integration periods, respectively.

[0139] As described above, according to the imaging device 100 of this embodiment, the reading unit 30B does not read the lower bits of the count value in the memory 23 during a predetermined reading period, so it can be stopped for part of the reading period and thus power saving is possible. In addition, the integrating unit 40B can be stopped in accordance with the stopping period of the reading unit 30B, thus also power saving is possible.

[0140] [Fifth Embodiment] The imaging device in the above-described embodiment is applicable to various devices. Examples of such devices include digital still cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 14 is a block diagram of a digital still camera.

[0141] Device 7 includes an imaging device 700, a lens 702, an aperture 704, and a barrier 706. Furthermore, Device 7 includes a signal processing unit (processing unit) 708, a memory unit (storage device) 710, an external I / F unit 712, a recording medium 714, a recording medium control I / F unit 716, an overall control / calculation unit (control device) 718, and a timing generation unit 720. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of the subject on the imaging device 700. The aperture 704 makes the amount of light passing through the lens 702 variable. The imaging device 700 is configured as in the above-described embodiment and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc., on the imaging data output from the imaging device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. Furthermore, the device 7 may also include a display device (monitor, electronic viewfinder, etc.) for displaying information obtained by the imaging device 700. The device 7 comprises at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the imaging device 700. The mechanical device is a movable part (for example, a robot arm) that operates in response to signals from the imaging device 700.

[0142] Each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated by the first photoelectric conversion unit and a pixel signal based on the charge generated by the second photoelectric conversion unit to acquire distance information from the imaging device 700 to the subject.

[0143] [Sixth Embodiment] Figures 15(a) and 15(b) are block diagrams of the equipment related to the in-vehicle camera in this embodiment. Equipment 8 includes the imaging device 800 of the above-described embodiment and a signal processing device (processing device) that processes signals from the imaging device 800. Equipment 8 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by Equipment 8. Equipment 8 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware or by a software module. Furthermore, it may be implemented using FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), or a combination thereof.

[0144] Device 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 8 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination unit 804 determines that there is a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 8 functions as a control means that controls the actions that control the vehicle.

[0145] In this embodiment, the equipment 8 images the area around the vehicle, for example, the front or rear. Figure 15(b) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the equipment 8 or imaging device 800 to perform the imaging operation. This configuration allows for further improvement of the accuracy of distance measurement.

[0146] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0147] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0148] For example, the signal processing circuit 20 does not have to include the memory 23. In this case, the counter 22 is connected to the reading unit 30 via the signal line L1 and outputs the count value to the reading unit 30.

[0149] The arrangement of pixels in the pixel region 101a may be one-dimensional. The signal processing circuit 20 does not necessarily need to be provided for every pixel; for example, one signal processing circuit 20 may be shared by multiple pixels, and signal processing may be performed sequentially.

[0150] Instead of the counter 22, a Time-to-Digital Converter (TDC) and memory may be used to acquire the pulse detection timing. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 21 is converted into a digital signal by the TDC. The TDC receives a control pulse (reference signal) from the vertical scanning circuit via a drive line to measure the timing of the pulse signal. The TDC uses the control pulse as a reference and acquires the signal as a digital signal when the input timing of the signal output from the waveform shaping circuit 21 is considered as a relative time.

[0151] The number of divisions in the frame period is not limited to "4". A larger number of divisions results in faster pixel readout speed, but on the other hand, it allows for obtaining a cumulative value with more bits relative to the number of bits in counter 22.

[0152] A pixel may have a memory that holds the carry bit of the count value. The reading unit 30B reads the carry bit from the memory. The integrating unit 40B integrates the carry bits. The combining unit 80 combines the integrated value of N carry bits (5th integrated value) with the count value to generate a first integrated value, and combines the integrated value of fewer than N carry bits (6th integrated value) with the count value to generate a second integrated value.

[0153] The counter 22 may change the number of bits of the count value to be held in memory 23 to the upper bits or all bits for each reading period.

[0154] The accumulating unit 40 may perform various calculations on the count value from the reading unit 30 and then accumulate the count value.

[0155] The above-disclosed embodiment includes the following configuration. (Composition 1) A pixel includes a light receiving unit that receives light and generates a pulse signal, and a counter that counts the pulse signal, When N is an integer greater than or equal to 2, and the frame period consists of N subframe periods, a readout unit reads the count value of the pulse signal in each of the N subframe periods, An integration unit that integrates the aforementioned count values, An imaging device characterized by comprising an output unit capable of outputting a first integrated value of N count values ​​and a second integrated value of fewer than N count values. (Configuration 2) The imaging apparatus according to configuration 1, characterized in that the output unit outputs the first integrated value or the second integrated value for an output period of a length corresponding to the subframe period. (Composition 3) The system further comprises a storage unit capable of storing the first integrated value and the second integrated value, The imaging apparatus according to configuration 1, characterized in that the output unit outputs the first integrated value or the second integrated value of the storage unit for an output period longer than the subframe period. (Composition 4) The imaging apparatus according to any one of configurations 1 to 3, characterized in that the output unit outputs the first integrated value after outputting the second integrated value. (Composition 5) The aforementioned count value is composed of multiple bits, The reading unit reads all bits of the count value, The imaging apparatus according to any one of configurations 1 to 4, characterized in that the integration unit generates a first integrated value by integrating all bits of N count values, and generates a second integrated value by integrating all bits of fewer than N count values. (Composition 6) It further includes a combining unit that combines multiple bits, The aforementioned count value is composed of multiple bits, The reading unit reads the upper bits of the count value, The integration unit integrates the higher bits, The imaging apparatus according to any one of configurations 1 to 4, characterized in that the combining unit generates the first integrated value by combining the third integrated value of N upper bits with the lower bits of the count value, and generates the second integrated value by combining the fourth integrated value of fewer than N upper bits with the lower bits of the count value. (Composition 7) The aforementioned pixel has a memory that stores the count value, The imaging apparatus according to any one of configurations 1 to 6, characterized in that the reading unit reads the count value from the memory. (Composition 8) The signal line connected to the reading unit, The system further includes a switch for switching the connection between the signal line and the memory, The memory has multiple memory elements, The imaging apparatus according to configuration 7, characterized in that the switch connects either the memory element of the upper bits or the memory element of the lower bits of the memory to the signal line. (Composition 9) The imaging apparatus according to configuration 8, characterized in that the reading unit reads out the upper and lower bits of the count value for a reading period corresponding to the subframe period. (Composition 10) The imaging apparatus according to configuration 9, characterized in that the reading unit reads only the upper bits of the count value in a time shorter than the time required to read the upper bits and lower bits of the count value during the reading period. (Composition 11) The imaging apparatus according to configuration 10, characterized in that the reading unit is in a power-saving state from the time it has finished reading only the upper bits of the count value until the start of the next reading period. (Composition 12) The imaging apparatus according to configuration 2, characterized in that the output unit is in a power-saving state when it does not output the first integrated value and the second integrated value during the output period. (Composition 13) The plurality of frame periods include a first frame period and a second frame period following the first frame period. The imaging apparatus according to any one of configurations 1 to 12, characterized in that the integration unit integrates the first integrated value of the first frame period with the count value of the second frame period. (Composition 14) The plurality of frame periods include a first frame period and a second frame period following the first frame period. The imaging apparatus according to any one of configurations 1 to 12, characterized in that the integration unit clears the first integrated value for the first frame period and then integrates the count value for the second frame period. (Composition 15) It further includes a combining unit that combines multiple bits, The aforementioned pixel has a memory that holds the carry bit of the count value, The reading unit reads the carry bit from the memory, The integration unit integrates the carry bits, The imaging apparatus according to any one of configurations 1 to 4, characterized in that the combining unit generates the first integrated value by combining the fifth integrated value of N carry bits with the count value, and generates the second integrated value by combining the sixth integrated value of fewer than N carry bits with the count value. (Composition 16) The reading unit reads the count value according to the time series of N subframe periods, The imaging apparatus according to any one of configurations 1 to 15, characterized in that the reading unit reads out the count values ​​in the order in which the integrating unit integrates the count values. (Composition 17) The aforementioned pixel has a memory that stores the count value, The imaging apparatus according to configuration 6, characterized in that the counter changes the number of bits of the count value to be held in the memory to the upper bits or all bits for each read period of a length corresponding to the subframe period. (Composition 18) An imaging device as described in any of configurations 1 to 17, An optical device corresponding to the aforementioned imaging device, Control device for controlling the imaging device, A processing unit that processes the signal output from the imaging device, A display device that displays information obtained by the aforementioned imaging device. A storage device for storing information obtained by the aforementioned imaging device, and The apparatus is characterized by comprising at least one of the following: a mechanical device that operates based on information obtained by the imaging device. (Composition 19) The apparatus according to configuration 18, characterized in that the processing device acquires distance information from the imaging device to the object. [Explanation of Symbols]

[0156] 10...APD (light receiving section) 20... Signal processing circuits 21...Waveform shaping circuit (light receiving section) 22... Counter 23…Memory 24... Quench element (light receiving part) 30, 30B...Reading part 40, 40B... Estimation Department 50…Output section 70...Storage section 80...Synthetic part 100... Imaging device L1a, L1b…Signal line SW1~SW4...Switches

Claims

1. A pixel includes a light receiving unit that receives light and generates a pulse signal, and a counter that counts the pulse signal, In a case where N is an integer of 2 or more, and the frame period consists of N subframe periods, a reading unit reads the count value of the pulse signal in each of the N subframe periods, An integration unit that integrates the aforementioned count values, An imaging device characterized by comprising an output unit capable of outputting a first integrated value of N count values ​​and a second integrated value of fewer than N count values.

2. The imaging apparatus according to claim 1, characterized in that the output unit outputs the first integrated value or the second integrated value for an output period of a length corresponding to the subframe period.

3. The system further comprises a storage unit capable of storing the first integrated value and the second integrated value, The imaging apparatus according to claim 1, characterized in that the output unit outputs the first integrated value or the second integrated value of the storage unit for an output period longer than the subframe period.

4. The imaging apparatus according to claim 1, characterized in that the output unit outputs the first integrated value after outputting the second integrated value.

5. The aforementioned count value is composed of multiple bits, The reading unit reads all bits of the count value, The imaging apparatus according to claim 1, characterized in that the integration unit generates a first integrated value by integrating all bits of N count values, and generates a second integrated value by integrating all bits of fewer than N count values.

6. It further includes a combining unit that combines multiple bits, The aforementioned count value is composed of multiple bits, The reading unit reads the upper bits of the count value, The integration unit integrates the higher bits, The imaging apparatus according to claim 1, characterized in that the combining unit generates a first integrated value by combining the third integrated value of N upper bits and the lower bits of the count value, and generates a second integrated value by combining a fourth integrated value of fewer than N upper bits and the lower bits of the count value.

7. The aforementioned pixel has a memory that stores the count value, The imaging apparatus according to claim 1, characterized in that the reading unit reads the count value from the memory.

8. The signal line connected to the reading unit, The system further includes a switch for switching the connection between the signal line and the memory, The memory has multiple memory elements, The imaging apparatus according to claim 7, characterized in that the switch connects either the memory element of the upper bits or the memory element of the lower bits of the memory to the signal line.

9. The imaging apparatus according to claim 8, characterized in that the reading unit reads out the upper and lower bits of the count value for a reading period of a length corresponding to the subframe period.

10. The imaging apparatus according to claim 9, characterized in that the reading unit reads only the upper bits of the count value in a time shorter than the time required to read the upper bits and lower bits of the count value during the reading period.

11. The imaging apparatus according to claim 10, characterized in that the reading unit is in a power-saving state from the time it has finished reading only the upper bits of the count value until the start of the next reading period.

12. The imaging apparatus according to claim 2, characterized in that the output unit is in a power-saving state when it does not output the first integrated value and the second integrated value during the output period.

13. The plurality of frame periods include a first frame period and a second frame period following the first frame period. The imaging apparatus according to claim 1, characterized in that the integration unit integrates the first integrated value of the first frame period with the count value of the second frame period.

14. The plurality of frame periods include a first frame period and a second frame period following the first frame period. The imaging apparatus according to claim 1, characterized in that the integration unit clears the first integrated value for the first frame period and then integrates the count value for the second frame period.

15. It further includes a combining unit that combines multiple bits, The aforementioned pixel has a memory that holds the carry bit of the count value, The reading unit reads the carry bit from the memory, The integration unit integrates the carry bits, The imaging apparatus according to claim 1, characterized in that the combining unit combines the fifth integrated value of N carry bits with the count value to generate the first integrated value, and combines the sixth integrated value of fewer than N carry bits with the count value to generate the second integrated value.

16. The reading unit reads the count value according to the time series of N subframe periods, The imaging apparatus according to claim 1, characterized in that the reading unit reads out the count values ​​in the order in which the integrating unit integrates the count values.

17. The aforementioned pixel has a memory that stores the count value, The imaging apparatus according to claim 6, characterized in that the counter changes the number of bits of the count value to be held in the memory to the upper bits or all bits for each read period of a length corresponding to the subframe period.

18. An imaging device according to any one of claims 1 to 17, An optical device corresponding to the aforementioned imaging device, Control device for controlling the imaging device, A processing unit that processes the signal output from the imaging device, A display device that displays information obtained by the aforementioned imaging device. A storage device for storing information obtained by the aforementioned imaging device, and The apparatus is characterized by comprising at least one of the following: a mechanical device that operates based on information obtained by the imaging device.

19. The apparatus according to claim 18, characterized in that the processing device acquires distance information from the imaging device to the object.

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