Amplifier

Abstract

The present invention provides an amplification device that does not interfere with assembly work or wire connections, and avoids increasing the number of component types. [Solution] The amplification device comprises a transistor element, a first capacitor, and a second capacitor. The first capacitor has a first conductive pattern provided on a dielectric substrate. The first conductive pattern is electrically connected to the signal output terminal of the transistor element. The second capacitor has a second conductive pattern provided on a dielectric substrate. The second conductive pattern is electrically connected to the signal output terminal of the transistor element. The capacitance of the second capacitor is smaller than that of the first capacitor. The second conductive pattern is divided into a plurality of parts that are aligned in a first direction and connected in parallel to each other with respect to the signal output terminal. The first capacitor and the second capacitor are arranged in a second direction that intersects the first direction with respect to the transistor element, and are also arranged in the second direction relative to each other.

Description

Technical Field

[0005] , , , ,

[0001] The present disclosure relates to an amplification device.

Background Art

[0002] Patent Document 1 discloses a high-frequency semiconductor device. This device includes a plurality of unit FETs, a matching circuit, and a plurality of low-frequency oscillation suppression circuits. The plurality of unit FETs are arranged in parallel. The matching circuit is formed by combining branch lines that divide one line into a plurality of lines in two or more stages. The plurality of low-frequency oscillation suppression circuits are connected to the plurality of branch lines constituting the n-th stage of the matching circuit.

[0003] Patent Document 2 discloses a packaged high-frequency power transistor including a circuit for high-frequency bypass or output matching.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a package housing a transistor element, there may be a case where a transistor element extending along a certain direction, a first capacitor, and a second capacitor are arranged side by side along a direction intersecting the said direction. The first capacitor is included in, for example, a shunt circuit, and the second capacitor is included in, for example, a fundamental wave matching circuit (low-pass filter circuit). A plurality of wires extend from the transistor element toward the first capacitor and the second capacitor. In such a configuration, the first capacitor and the second capacitor also extend along the extending direction of the transistor element.

[0006] Generally, the capacitance of the capacitor in a fundamental wave matching circuit is significantly smaller than that of the capacitor in a shunt circuit. If the capacitance of the second capacitor is smaller than that of the first capacitor, making the length of the second capacitor in the extending direction approximately the same as that of the first capacitor will result in the width of the second capacitor becoming too short, causing difficulties in mounting and wire connection of the second capacitor. To avoid shortening the width of the second capacitor, one could consider making the dielectric constant of the dielectric substrate material of the second capacitor lower than that of the dielectric substrate of the first capacitor, or making the dielectric substrate of the second capacitor thicker than that of the first capacitor. However, in these cases, a different dielectric substrate would be used for the second capacitor than for the first capacitor. Therefore, the number of component types increases, and manufacturing costs rise.

[0007] Furthermore, in amplifiers equipped with transistor elements, a fundamental wave matching circuit may be connected to the signal output terminal of the transistor element. Typically, a fundamental wave matching circuit has the configuration of a T-type low-pass filter circuit. In amplifiers with high output power, multiple transistors are arranged in parallel inside the transistor element. In this case, the size of the transistor element increases along the direction in which the multiple transistors are arranged, so a large number of wires arranged along that direction, which constitute a T-type low-pass filter circuit, are connected to the signal output terminal of the transistor element. As a result, the distance between the wires located at both ends of the wire array increases, and loop oscillation occurs through the electrodes of the capacitor in the T-type low-pass filter circuit. Loop oscillation degrades the operating characteristics of the amplifier.

[0008] This disclosure aims to provide an amplification device that does not interfere with assembly work and wire connections and avoids increasing the number of component types. Furthermore, this disclosure aims to provide an amplification device that can reduce loop oscillation. [Means for solving the problem]

[0009] An amplifier according to one embodiment of the present disclosure comprises a transistor element, a first capacitor, and a second capacitor. The transistor element is provided on a base and has a signal output terminal. The first capacitor has a dielectric substrate provided on a base and a first conductive pattern provided on the dielectric substrate. The first conductive pattern is electrically connected to the signal output terminal. The second capacitor has a dielectric substrate provided on a base and a second conductive pattern provided on the dielectric substrate. The second conductive pattern is electrically connected to the signal output terminal. The second capacitor has a capacitance smaller than that of the first capacitor. The second conductive pattern is divided into a plurality of parts. The plurality of parts are aligned in a first direction and connected in parallel to each other with respect to the signal output terminal. The first capacitor and the second capacitor are arranged in a second direction that intersects the first direction with respect to the transistor element, and are also arranged in the second direction with respect to each other. [Effects of the Invention]

[0010] This disclosure provides an amplifier that does not interfere with assembly work or wire connections and avoids increasing the number of component types. Furthermore, this disclosure provides an amplifier that can reduce loop oscillation. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a plan view showing an amplification device according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view along the line II-II in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing the circuit configuration of the amplifier after the transistor element. [Figure 4] Figure 4 is a schematic diagram showing a part of the amplification device. [Figure 5] Figure 5 is a plan view showing an amplification device according to the first modified example. [Figure 6] Figure 6 is a plan view showing an amplification device according to the second modified example. [Figure 7]Figure 7 is a plan view showing an amplification device according to the third modified example. [Figure 8] Figure 8 is a plan view showing an amplification device according to a comparative example. [Figure 9] Figure 9 is a circuit diagram showing the circuit configuration of the amplifier after the transistor element. [Modes for carrying out the invention]

[0012] [Description of Embodiments in this Disclosure] First, the contents of embodiments of the present disclosure will be listed and described. [1] An amplifier according to one embodiment of the present disclosure comprises a transistor element, a first capacitor, and a second capacitor. The transistor element is provided on a base and has a signal output terminal. The first capacitor has a dielectric substrate provided on a base and a first conductive pattern provided on the dielectric substrate. The first conductive pattern is electrically connected to the signal output terminal. The second capacitor has a dielectric substrate provided on a base and a second conductive pattern provided on the dielectric substrate. The second conductive pattern is electrically connected to the signal output terminal. The second capacitor has a capacitance smaller than that of the first capacitor. The second conductive pattern is divided into a plurality of parts. The plurality of parts are aligned in a first direction and are connected in parallel to each other with respect to the signal output terminal. The first capacitor and the second capacitor are arranged in a second direction that intersects the first direction with respect to the transistor element and are arranged in the second direction with respect to each other.

[0013] In the amplifier described in [1] above, the second conductive pattern of the second capacitor is divided into multiple parts that are connected in parallel to each other with respect to the signal output terminal. In this case, the capacitance of the second capacitor can be reduced without shortening the width of the second capacitor. Therefore, there is no problem with mounting the second capacitor or connecting the wires. In addition, in order to reduce the capacitance of the second capacitor, it is not necessary to use different materials and thicknesses for the dielectric substrate of the second capacitor than for the dielectric substrate of the first capacitor. Therefore, an increase in the number of component types can be avoided.

[0014] [2] In the amplifier device of [1] above, the dielectric substrate of the first capacitor may be integral with the dielectric substrate of the second capacitor. In this case, the mounting operation of the second capacitor can be made even easier.

[0015] [3] In the amplifier device of [2] above, the first conductive pattern may include a portion located between a plurality of portions of the second conductive pattern. In this case, the capacitance of the first capacitor can be increased while avoiding an increase in the mounting area of the first capacitor and the second capacitor combined.

[0016] [4] In the amplifier device of [2] above, the first conductive pattern may have a plurality of openings arranged in the first direction, and each of the plurality of portions of the second conductive pattern may be provided inside each of the plurality of openings of the first conductive pattern. In this case, the capacitance of the first capacitor can be increased while suppressing an increase in the mounting area of the first capacitor and the second capacitor combined.

[0017] [[ID=​​​​​​​[7] An amplifier according to one embodiment of the present disclosure comprises a transistor element and a fundamental wave matching circuit. The transistor element has a signal output terminal. The fundamental wave matching circuit is connected to the signal output terminal. The fundamental wave matching circuit has a plurality of circuit parts connected in parallel to each other with respect to the signal output terminal. Each of the plurality of circuit parts has a first wire, a second wire, and a capacitor. The second wire is connected in series between the first wire and the signal output terminal. The capacitor is connected between the node between the first wire and the second wire and a reference potential.

[0020] In the amplifier described in [7] above, the fundamental wave matching circuit has multiple circuit sections, and each circuit section constitutes a T-type low-pass filter circuit. As a result, the number of wires in the T-type low-pass filter circuit of each circuit section is reduced, and the distance between the wires at both ends of the wire arrangement is shortened. Therefore, loop oscillation can be reduced.

[0021] [Details of the embodiments of this disclosure] Specific examples of the present disclosure will be described below with reference to the drawings. However, the present invention is not limited to these examples, and is intended to include all modifications within the meaning and scope of the claims, as defined by the claims. In the following description, identical elements in the drawings are denoted by the same reference numerals, and redundant descriptions are omitted.

[0022] Figure 1 is a plan view showing an amplifier 1A according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view along the line II-II in Figure 1. The amplifier 1A is used, for example, as one or both of the main amplifier and / or peak amplifier of a Doherty amplifier. As shown in Figures 1 and 2, the amplifier 1A comprises a package 10, a capacitor 20, a transistor element 30, a capacitor 40 (first capacitor), a capacitor 50A (second capacitor), a resistor 60, a capacitor 70 (third capacitor), and wire groups 81 to 87.

[0023] Package 10 includes a base 11, a side wall 12, an input terminal 13, an output terminal 14, and a lid 15. The base 11 is a conductive plate-shaped member having a flat mounting surface. The mounting surface of the base 11 is made of, for example, only metal. The planar shape of the base 11, as viewed from the thickness direction, is, for example, rectangular. The base 11 is connected to an external reference potential line and set to a reference potential. Figure 1 shows a first direction D1 along the mounting surface of the base 11 and a second direction D2 intersecting the first direction D1. In one example, the second direction D2 is perpendicular to the first direction D1. The side wall 12 has a rectangular frame shape and is positioned on the mounting surface at the periphery of the base 11. The side wall 12 is insulating and made of only dielectric material. The constituent material of the side wall 12 is, for example, ceramic.

[0024] The input terminal 13 is located on a portion of the side wall 12 along one of its four sides. The output terminal 14 is located on a portion of the side wall 12 along the side opposite to the side on which the input terminal 13 is located. The input terminal 13 and the output terminal 14 are made of, for example, metal plates. The input terminal 13 receives the high-frequency signal before amplification from the external circuit of the amplifier 1A. The output terminal 14 outputs the amplified high-frequency signal to the external circuit of the amplifier 1A. The lid 15 is shown only in Figure 2 and is omitted from Figure 1. The lid 15 is a cover provided on the side wall 12, covering the components arranged inside the package 10 and sealing the inside of the package 10. The lid 15 is insulating and consists only of dielectric material. The constituent material of the lid 15 is, for example, ceramic.

[0025] The capacitor 20 is located inside the package 10. The capacitor 20 is positioned on the mounting surface of the base 11, closer to the input terminal 13. The capacitor 20 is located in a second direction D2 when viewed from the input terminal 13. The capacitor 20 has a dielectric substrate 21 and a conductive pattern 22. The back surface of the dielectric substrate 21 is fixed to the mounting surface of the base 11. The conductive pattern 22 is provided on the surface of the dielectric substrate 21. The capacitor 20 extends along a first direction D1. In other words, the planar shape of the capacitor 20 is a long rectangle in the first direction D1. The conductive pattern 22 also extends along the first direction D1. The conductive pattern 22 is electrically connected to the input terminal 13 by a wire group 81 consisting of multiple wires. The conductive pattern 22 is electrically connected to the signal input terminal 32 of the transistor element 30, which will be described later, by a wire group 82 consisting of multiple wires. The inductance of wire group 81, the capacitance of capacitor 20, and the inductance of wire group 82 constitute an input-side fundamental wave matching circuit (T-type low-pass filter circuit).

[0026] The transistor element 30 is located inside the package 10. The transistor element 30 is positioned on the mounting surface of the base 11, with the capacitor 20 in between it and the input terminal 13. In other words, the transistor element 30 is located in the second direction D2 when viewed from the capacitor 20. The transistor element 30 has a substrate 31, a signal input terminal 32, and a signal output terminal 33. The substrate 31 extends along the first direction D1, and its back surface is fixed to the mounting surface of the base 11. Multiple transistors are arranged in parallel inside the substrate 31. Each transistor is, for example, a field-effect transistor (FET). The signal input terminal 32 is located on the surface of the substrate 31 closer to the capacitor 20 and extends along the first direction D1. The signal output terminal 33 is located on the surface of the substrate 31 closer to the capacitor 40 (described later) and extends along the first direction D1. The signal input terminal 32 is connected to the control terminal (e.g., gate) of each transistor located inside the substrate 31. The signal output terminal 33 is connected to the first current terminal (e.g., drain) of each transistor located inside the circuit board 31. The second current terminal (e.g., source) of each transistor located inside the circuit board 31 is connected to the base 11 via the back surface of the circuit board 31.

[0027] The capacitor 40 is located inside the package 10. The capacitor 40 is positioned on the mounting surface of the base 11, closer to the output terminal 14. The capacitor 40 is located in a second direction D2 when viewed from the transistor element 30. In other words, the capacitor 40 is located between the transistor element 30 and the output terminal 14 in the second direction D2. The capacitor 40 is a parallel plate capacitor, in which a dielectric substrate 41 is sandwiched between a conductive pattern 42 and the base 11. The dielectric substrate 41 is provided on the mounting surface of the base 11, and its back surface is fixed to the mounting surface of the base 11. The size of the dielectric substrate 41 in the first direction D1 is, for example, 300 μm or more and 8000 μm or less, and is typically 6000 μm. The size of the dielectric substrate 41 in the second direction D2 is, for example, 200 μm or more and 3000 μm or less, and is typically 1000 μm. The conductive pattern 42 is provided on the surface of the dielectric substrate 41. The capacitor 40 extends along a first direction D1. In other words, the planar shape of the capacitor 40 is a long rectangle in the first direction D1. The conductive pattern 42 also extends along the first direction D1. The size of the conductive pattern 42 in the first direction D1 is, for example, between 200 μm and 7900 μm, and is typically 5900 μm. The size of the conductive pattern 42 in the second direction D2 is, for example, between 100 μm and 2900 μm, and is typically 900 μm. The conductive pattern 42 is a single metal film. The conductive pattern 42 is electrically connected to the signal output terminal 33 of the transistor element 30 by one or more wire groups 84, each consisting of multiple wires.

[0028] Capacitor 50A is located inside package 10. Capacitor 50A is located on the mounting surface of base 11, closer to output terminal 14. Capacitor 50A is located in the second direction D2 when viewed from transistor element 30. In other words, capacitor 50A is located between transistor element 30 and output terminal 14 in the second direction D2. Capacitor 50A is aligned with capacitor 40 in the second direction D2. Capacitor 50A is a parallel plate capacitor in which a dielectric substrate 51 is sandwiched between a conductive pattern 55 and base 11. The dielectric substrate 51 is provided on the mounting surface of base 11, and its back surface is fixed to the mounting surface of base 11. The conductive pattern 55 is provided on the surface of dielectric substrate 51.

[0029] The dielectric substrate 51 extends along a first direction D1. In other words, the planar shape of the dielectric substrate 51 is a long rectangle in the first direction D1. The dielectric substrate 51 is separated from the dielectric substrate 41. The constituent material and thickness of the dielectric substrate of capacitor 50A are the same as those of the dielectric substrate of capacitor 40. The size of the dielectric substrate 51 in the first direction D1 is, for example, between 300 μm and 8000 μm, and is typically 6000 μm. The size of the dielectric substrate 51 in the second direction D2 is, for example, between 200 μm and 1000 μm, and is typically 300 μm.

[0030] The conductive pattern 55 is divided into a plurality of parts 52. The plurality of parts 52 are provided on a common dielectric substrate 51. Each part 52 is a metal film. The plurality of parts 52 are arranged along a first direction D1 and are connected in parallel to each other to the signal output terminal 33. In one example, the planar shape of each part 52 is rectangular. Also in one example, the planar shapes of the plurality of parts 52 are identical to each other. Also in one example, the areas of the plurality of parts 52 are equal to each other. The spacing between the plurality of parts 52 in the first direction D1 may be shorter than the length of each part 52 in the same direction. The length of each part 52 in the first direction D1 may be longer than the width of each part 52 in the second direction D2. The size of each part 52 in the first direction D1 is, for example, 100 μm or more and 2000 μm or less, and is typically 1000 μm. The size of each part 52 in the second direction D2 is, for example, 100 μm or more and 900 μm or less, and is typically 200 μm.

[0031] Capacitor 50A has a capacitance smaller than that of capacitor 40. The capacitance of capacitor 50A here refers to the combined capacitance between the multiple parts 52 and the base 11. The capacitance between each part 52 and the base 11 is mainly determined by the area of ​​each part 52, the distance between each part 52 and the base 11 (in other words, the thickness of the dielectric substrate 51), and the dielectric constant of the dielectric substrate 51.

[0032] Each portion 52 of the conductive pattern 55 is electrically connected to the signal output terminal 33 of the transistor element 30 by a wire group 83 consisting of one or more wires. In addition, each portion 52 of the conductive pattern 55 is electrically connected to the output terminal 14 by a wire group 85 consisting of one or more wires. Each wire in wire group 83 and wire group 85 extends along the second direction D2. Wire group 83 extends parallel to wire group 84. Multiple wire groups 83 may be arranged alternately with multiple wire groups 84 in the first direction D1.

[0033] The constituent materials of the dielectric substrates 21, 41, and 51 are, for example, aluminum oxide (Al2O3) or barium titanate (BaTiO3). The constituent materials of the conductive patterns 22, 42, and 55 are, for example, gold, titanium, or copper. The constituent materials of each bonding wire constituting the wire groups 81 to 85 are, for example, gold, silver, copper, or aluminum.

[0034] The resistor 60 and the capacitor 70 are arranged inside the package 10. The resistor 60 is positioned on the mounting surface of the base 11 in a direction intersecting the second direction D2 as viewed from the capacitor 40. The resistor 60 is electrically connected to the conductive pattern 42 of the capacitor 40 by a wire group 86 consisting of one or more wires. The capacitor 70 is positioned on the mounting surface of the base 11 alongside the resistor 60. The capacitor 70 is electrically connected to the resistor 60 by a wire group 87 consisting of one or more wires. That is, the capacitor 70 is electrically connected to the conductive pattern 42 via the resistor 60.

[0035] Figure 3 is a circuit diagram showing the circuit configuration of the amplifier 1A according to this embodiment, specifically the stage after the transistor element 30. As shown in Figure 3, the amplifier 1A includes a shunt circuit 91, a low-frequency suppression circuit 92, and a fundamental wave matching circuit (T-type low-pass filter circuit) 93, all connected to the signal output terminal 33 of the transistor element 30. The shunt circuit 91 includes the aforementioned wire group 84 as an inductor and a capacitor 40, and short-circuits high-frequency components. The low-frequency suppression circuit 92 is also called a video-bandwidth (VBW) circuit. The low-frequency suppression circuit 92 short-circuits low-frequency components. The frequency range of the low-frequency components is, for example, 50 MHz to 800 MHz. The low-frequency suppression circuit 92 includes the aforementioned wire group 86 as an inductor, a resistor 60, and a capacitor 70. The fundamental wave matching circuit 93 adjusts the output impedance of the fundamental wave. The fundamental wave matching circuit 93 consists of multiple circuit sections 95, each including a T-type low-pass filter circuit, connected in parallel. Each circuit section 95 includes the aforementioned wire group 83 (first wire) as an inductor, a capacitor 56 formed by each section 52 of the conductive pattern 55, and another wire group 85 (second wire) as an inductor. The capacitance of the capacitor 50A is the combined capacitance of the multiple capacitors 56. The capacitor 56 is connected between the node between wire group 83 and wire group 85 and the reference potential (base 11).

[0036] The capacitance of capacitor 40, which constitutes the shunt circuit 91, is set to a large value, such as 100pF, in order to sufficiently short-circuit high-frequency signals. In contrast, the capacitance of capacitor 50A, which constitutes the fundamental wave matching circuit 93, is set to a small value, such as 15pF, due to impedance relationships. In other words, the capacitance of capacitor 40 is significantly larger than the capacitance of capacitor 50A. The ratio of the capacitance C1 of capacitor 40 to the capacitance C3 of capacitor 50A (C1 / C3) is, for example, 5 or more.

[0037] The effects obtained by the amplifier 1A of this embodiment described above will be explained along with the problems of the comparative example. Figure 8 is a plan view showing the amplifier 1E according to the comparative example. Figure 9 is a circuit diagram showing the circuit configuration of the amplifier 1E from the transistor element 30 onwards. The amplifier 1E differs from the amplifier 1A in that it is equipped with capacitor 50E instead of capacitor 50A, and is otherwise identical to the amplifier 1A.

[0038] Capacitor 50E has the same configuration as capacitor 50A, except for the configuration described below. That is, capacitor 50E has a conductive pattern 54 instead of a conductive pattern 55. The conductive pattern 54 is not divided into multiple parts, but is formed on the dielectric substrate 51 as a single metal film. The conductive pattern 54 extends along the first direction D1. The conductive pattern 54 is electrically connected to the signal output terminal 33 by a wire group 83 and to the output terminal 14 by a wire group 85. As shown in Figure 9, the inductance of the wire group 83, the capacitance of capacitor 50E, and the inductance of the wire group 85 constitute the fundamental wave matching circuit 94.

[0039] Generally, the capacitance of the capacitor 50E in the fundamental wave matching circuit 94 is significantly smaller than the capacitance of the capacitor 40 in the shunt circuit 91. If the capacitance of capacitor 50E is smaller than that of capacitor 40, and the length of capacitor 50E in the extending direction (first direction D1) is made approximately the same as the length of capacitor 40 in the extending direction (first direction D1), the width W of capacitor 50E in the second direction D2 becomes too short, causing problems with mounting and wire connection of capacitor 50E. To avoid shortening the width W of capacitor 50E, it is conceivable to either lower the dielectric constant of the constituent material of the dielectric substrate 51 of capacitor 50E to that of the dielectric substrate 41 of capacitor 40, or to make the dielectric substrate 51 of capacitor 50E thicker than that of the dielectric substrate 41 of capacitor 40. However, in these cases, a different material would be used for the dielectric substrate 51 of capacitor 50E than the dielectric substrate 41 of capacitor 40. Therefore, the number of component types increases, and manufacturing costs increase.

[0040] In view of the above problems, in the amplifier 1A of this embodiment, the conductive pattern 55 of the capacitor 50A is divided into a plurality of parts 52 that are connected in parallel to each other to the signal output terminal 33. In this case, the capacitance of the capacitor 50A can be reduced without shortening the width of the capacitor 50A (in other words, the width of the dielectric substrate 51). Therefore, there is no problem with the mounting work of the capacitor 50A or the wire connection. In addition, in order to reduce the capacitance of the capacitor 50A, it is not necessary to make the constituent material and thickness of the dielectric substrate 51 different from the constituent material and thickness of the dielectric substrate 41 of the capacitor 40. Therefore, an increase in the number of types of components can be avoided.

[0041] This explains that dividing the conductive pattern 55 into multiple parts 52 does not affect the operation of the amplifier 1A. Figure 4 is a schematic diagram showing a part of the amplifier 1A. As shown in Figure 4, the regions in the conductive pattern 42 where the three wire groups 84 are connected and the surrounding regions are considered to be nodes a1, b1, and c1, respectively. The three parts 52 of the conductive pattern 55 are considered to be nodes a2, b2, and c2, respectively. In this case, in the conductive pattern 42, it is necessary that both nodes b1 and c1 and node a1 are the same point on the baseband signal. Therefore, nodes a1, b1, and c1 must be on the same metal film. In contrast, the conductive pattern 55 performs the same function even if nodes a2, b2, and c2 are separated from each other, as it does when the three parallel circuits are not separated from each other. Therefore, it is not a problem even if the conductive pattern 55 is divided into multiple parts 52.

[0042] Furthermore, by dividing the conductive pattern 55 into multiple sections 52, the number of wires in the wire group 85 may be reduced compared to the comparative example. However, even if the inductance of the wire group 85 is large, it does not hinder the operation of the circuit, so it is acceptable to have fewer wires in the wire group 85.

[0043] As in this embodiment, capacitor 40 may be included in the shunt circuit 91, and capacitor 50A may be included in the fundamental wave matching circuit 93. By canceling the output capacitance of transistor element 30 with the shunt circuit 91 and then providing the fundamental wave matching circuit 93 in the subsequent stage, the load impedance characteristics of the amplifier 1A can be adjusted to bring the optimal load closer to the real axis (i.e., the imaginary component (reactance) of the load impedance is reduced and the real component (resistive component) is increased). Generally, the capacitance of the capacitor in the fundamental wave matching circuit is significantly smaller than that of the capacitor in the shunt circuit. Therefore, the configuration of the amplifier 1A in this embodiment is extremely effective.

[0044] As in this embodiment, the amplifier 1A may also include a low-frequency suppression circuit 92. In this case, an amplifier 1A capable of reducing low-frequency components included in the output signal can be provided.

[0045] Here, we will explain why the conductive pattern 42 is a single unit (not divided into multiple parts) in this embodiment. In an amplifier 1A with high output power, multiple transistors are arranged in parallel in the transistor element 30. In that case, the width of the transistor element 30 in the first direction D1 becomes longer, so it becomes impossible to consider the output nodes of all transistors as a single node. Therefore, for example, the multiple transistors are divided into two groups in the first direction D1, and the circuit is designed so that each transistor operates uniformly, or in other words, so that the impedance seen from the output node of each group is equal, while considering the inductance and resistance present between the two groups. In addition, the low-frequency suppression circuit 92 is often arranged asymmetrically with respect to the center line of the amplifier 1A for layout reasons, in order to set the value of the capacitor 70 to a large value, for example, on the order of nF.

[0046] Consider the case where the conductive pattern 42 of capacitor 40 is divided into multiple parts, namely nodes a1, b1, and c1 shown in Figure 4. In this case, near the operating frequency, the capacitance value of capacitor 40 is sufficiently large, so nodes a1, b1, and c1 are almost short-circuited with the base 11 (reference voltage), and no branching to the low-frequency suppression circuit 92 is visible. Therefore, the impedances of nodes a1, b1, and c1 at the operating frequency appear to be the same. On the other hand, near the baseband frequency, it is desirable that nodes a1, b1, and c1 be connected to the low-frequency suppression circuit 92 with the shortest possible inductance. However, nodes a1 and b1 are connected to node c1 via wiring within the transistor element 30 or via wiring within the side wall 12. Therefore, the inductance between nodes a1 and b1 and the low-frequency suppression circuit 92 becomes large, reducing the effectiveness of the low-frequency suppression circuit 92 and causing a memory effect when amplifying broadband signals.

[0047] Therefore, in this embodiment, the conductive pattern 42 is not divided into multiple parts but is a single unit. This allows nodes a1 and b1 to be connected to node c1 with a small inductance. Consequently, the impedances of nodes a1, b1, and c1 at the baseband frequency can also be made the same. Furthermore, even if the conductive pattern 42 is divided into multiple parts (nodes a1, b1, and c1), if these parts are connected to each other via extremely short wires, for example, with a height of 200 μm or less and a length of 500 μm or less, they can perform the same function as when the conductive pattern 42 is a single unit.

[0048] In the amplifier 1A of this embodiment, the fundamental wave matching circuit 93 has multiple circuit sections 95, and each circuit section 95 constitutes a T-type low-pass filter circuit. As a result, the number of wires in the T-type low-pass filter circuit of each circuit section 95 is reduced. Specifically, in the comparative example in Figure 8, three wire groups 83 are connected to the conductive pattern 54, but in this embodiment, only one wire group 83 is connected to each section 52 of the conductive pattern 55. As a result, the distance between wires located at both ends of the wire array is shortened. Therefore, loop oscillation can be reduced.

[0049] [First variation] Figure 5 is a plan view showing the amplifier 1B according to the first modified example. The amplifier 1B differs from the amplifier 1A of the above embodiment in that it is equipped with capacitor 50B instead of capacitors 40 and 50A, and is otherwise identical to the amplifier 1A.

[0050] Capacitor 50B is located inside package 10. Capacitor 50B is positioned on the mounting surface of base 11, closer to output terminal 14. Capacitor 50B is located in the second direction D2 when viewed from transistor element 30. In other words, capacitor 50B is located between transistor element 30 and output terminal 14 in the second direction D2.

[0051] The capacitor 50B includes a dielectric substrate 53, a conductive pattern 42, and a conductive pattern 55. The dielectric substrate 53 is provided on the mounting surface of the base 11, and its back surface is fixed to the mounting surface of the base 11. The dielectric substrate 53 extends along a first direction D1. In other words, the planar shape of the dielectric substrate 53 is a long rectangle in the first direction D1. The thickness and material of the dielectric substrate 53 are the same as those of the dielectric substrates 41 and 51 in the above embodiment. The size of the dielectric substrate 53 in the first direction D1 is, for example, 300 μm or more and 8000 μm or less, and is typically 6000 μm. The size of the dielectric substrate 53 in the second direction D2 is, for example, 700 μm or more and 3000 μm or less, and is typically 800 μm. The conductive patterns 42 and 55 are provided on the surface of the dielectric substrate 53. The configuration, shape, material, and connection relationship of the conductive patterns 42 and 55 are the same as those in the above embodiment.

[0052] In this modified example, the conductive pattern 42 and the conductive pattern 55 are provided on a common dielectric substrate 53. In other words, the dielectric substrate of the capacitor constituting the shunt circuit is integrated with the dielectric substrate of the capacitor constituting the fundamental wave matching circuit. In this case, the width of the dielectric substrate can be further increased, making the capacitor mounting work even easier.

[0053] [Second variation] Figure 6 is a plan view showing the amplifier 1C according to the second modified example. The amplifier 1C differs from the amplifier 1A of the above embodiment in that it is equipped with a capacitor 50C instead of capacitors 40 and 50A, and is otherwise identical to the amplifier 1A.

[0054] Capacitor 50C has the same configuration as capacitor 50B of the first modification, except for the configuration described below. That is, capacitor 50C has a conductive pattern 43 instead of conductive pattern 42. Conductive pattern 43 includes a main portion 431 and one or more protrusions 432. The main portion 431 has the same arrangement and the same planar shape as the conductive pattern 42 described above. Each protrusion 432 protrudes from the main portion 431 along a second direction D2 and is located between multiple portions 52 of the conductive pattern 55. That is, the protrusions 432 and the multiple portions 52 are arranged alternately in a first direction D1.

[0055] As shown in this modified example, the conductive pattern 43 may include one or more protrusions 432 located between multiple portions 52 of the conductive pattern 55. In this case, the capacitance of the shunt circuit capacitor can be increased while avoiding an increase in the combined mounting area of ​​the shunt circuit capacitor and the fundamental wave matching circuit capacitor.

[0056] [Third variation] Figure 7 is a plan view showing an amplifier 1D according to a third modified example. Amplifier 1D differs from amplifier 1A of the above embodiment in that it includes a capacitor 50D instead of capacitors 40 and 50A, and is otherwise identical to amplifier 1A.

[0057] Capacitor 50D has the same configuration as capacitor 50B of the first modification, except for the configuration described below. That is, capacitor 50D has a conductive pattern 44 instead of conductive pattern 42. The conductive pattern 44 extends on the dielectric substrate 53 across both sides in a second direction D2 relative to a plurality of portions 52 of conductive pattern 55. The size of the conductive pattern 44 in the first direction D1 is, for example, 200 μm to 8000 μm, and is typically 6000 μm. The size of the conductive pattern 44 in the second direction D2 is, for example, 300 μm to 3000 μm, and is typically 600 μm. In addition, the conductive pattern 44 has a plurality of openings 441 aligned in the first direction D1. The planar shape of each opening 441 is, for example, similar to each portion 52. Each of the plurality of portions 52 is provided inside each of the plurality of openings 441 of the conductive pattern 44. This configuration can also be described as the conductive pattern 44 including one or more portions located between a plurality of portions 52. The size of each opening 441 in the first direction D1 is, for example, 100 μm to 2000 μm, and is typically 1000 μm. The size of each opening 441 in the second direction D2 is, for example, 200 μm to 1000 μm, and is typically 300 μm.

[0058] According to this modified example, it is possible to increase the capacitance of the shunt circuit capacitor while avoiding an increase in the combined mounting area of ​​the shunt circuit capacitor and the fundamental wave matching circuit capacitor.

[0059] The amplification device according to this disclosure is not limited to the embodiments described above, and various other modifications are possible. For example, in the above embodiments and each of its modifications, an example is shown in which the conductive pattern 55 is divided into three parts 52, but the number of divisions of the conductive pattern 55 may be two, four or more, or more. Also, in the above embodiments and each of its modifications, an example is shown in which the conductive pattern 42 (or the main part 431 of the conductive pattern 43) is placed between the conductive pattern 55 and the transistor element 30, but the conductive pattern 55 may be placed between the conductive pattern 42 (or the main part 431 of the conductive pattern 43) and the transistor element 30. [Explanation of Symbols]

[0060] 1A, 1B, 1C, 1D, 1E… Amplifiers 10…Package 11…Bass 12…Side wall 13…Input terminals 14…Output terminals 15... Lid 20…Capacitor 21, 41, 51, 53… Dielectric substrates 22, 42, 43, 44, 54, 55… Conductive patterns 30…Transistor element 31... Circuit board 32…Signal input terminal 33... Signal output terminal 40…Capacitor (First Capacitor) 42, 43, 44… Conductive patterns 50A…Capacitor (Second Capacitor) 50B, 50C, 50D, 50E, 56… Capacitors 52...part 60... Resistance 70...Capacitor (Third Capacitor) 81, 82, 83, 84, 85, 86, 87… Wire group 91... Shunt circuit 92...Low-frequency suppression circuit 93,94...Fundamental wave matching circuit 431... Main part 432...Protruding part 441...Aperture a1, a2, b1, b2, c1, c2… nodes D1…first direction D2…Second direction W…width

Claims

1. A transistor element provided on a base and having a signal output terminal, A dielectric substrate provided on the base, and a first capacitor having a first conductive pattern provided on the dielectric substrate, wherein the first conductive pattern is electrically connected to the signal output terminal, A dielectric substrate provided on the base, and a second conductive pattern provided on the dielectric substrate, wherein the second conductive pattern is electrically connected to the signal output terminal, and the second capacitor has a capacitance smaller than that of the first capacitor, Equipped with, The second conductive pattern is divided into a plurality of parts that are aligned in the first direction and connected in parallel to each other with respect to the signal output terminals. An amplification device in which the first capacitor and the second capacitor are arranged side by side in a second direction intersecting the first direction with respect to the transistor element, and are also arranged side by side with respect to each other in the second direction.

2. The amplification device according to claim 1, wherein the dielectric substrate of the first capacitor is integrated with the dielectric substrate of the second capacitor.

3. The amplification device according to claim 2, wherein the first conductive pattern includes a portion located between the plurality of portions of the second conductive pattern.

4. The first conductive pattern has a plurality of openings aligned in the first direction, The amplification device according to claim 2, wherein each of the plurality of portions of the second conductive pattern is provided inside each of the plurality of openings of the first conductive pattern.

5. The first capacitor is included in the shunt circuit. The amplification device according to any one of claims 1 to 4, wherein the second capacitor is included in the fundamental wave matching circuit.

6. It also features a low-frequency suppression circuit, The low-frequency suppression circuit described above is A resistor electrically connected to the first conductive pattern, A third capacitor electrically connected to the resistor, An amplification device according to any one of claims 1 to 4, having the following features.

7. A transistor element having a signal output terminal, A fundamental wave matching circuit connected to the aforementioned signal output terminal, Equipped with, The aforementioned fundamental wave matching circuit has a plurality of circuit components connected in parallel to each other with respect to the signal output terminal, Each of the aforementioned multiple circuit components is: First wire and A second wire connected in series between the first wire and the signal output terminal, A capacitor connected between the node between the first wire and the second wire and the reference potential, An amplification device having

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