Photoelectric conversion element and photoelectric conversion device

Abstract

This reduces noise caused by carriers originating from carrier generation levels within the photoelectric conversion element. [Solution] A photoelectric conversion element provided in a semiconductor layer having a first surface and a second surface opposite to the first surface, comprising: a first semiconductor region of a first conductivity type arranged from the first surface to a first depth; a second semiconductor region of a second conductivity type arranged to surround the first semiconductor region in a plan view and having an impurity concentration peak at a second depth between the first surface and the first depth; and a third semiconductor region of a second conductivity type arranged closer to the second surface than the first semiconductor region and forming an avalanche photodiode between itself and the first semiconductor region.

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion element and a photoelectric conversion device. [Background technology]

[0002] A single-photon avalanche diode (SPAD) is known as a detector capable of detecting weak light at the single-photon level. SPADs utilize the avalanche multiplication phenomenon, which is generated by a strong electric field induced at the PN junction of a semiconductor, to amplify the signal charge excited by a photon by several to several million times. By converting the current generated by the avalanche multiplication phenomenon into a pulse signal and counting the number of these pulse signals, it becomes possible to directly measure the number of incident photons. Patent Document 1 describes a photodetection device and a photodetection system using an SPAD. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-057651 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Patent Document 1 discloses a configuration in which a semiconductor region with a low impurity concentration is placed between the cathode and anode to increase the cathode-anode electric field strength, from the viewpoint of reducing noise while suppressing an increase in operating voltage. However, while the configuration described in Patent Document 1 can suppress an increase in operating voltage by increasing the cathode-anode electric field strength, noise caused by carriers generated at the carrier generation level within the photoelectric conversion element sometimes occurs.

[0005] The object of the present invention is to provide a photoelectric conversion element and a photoelectric conversion device that can reduce noise caused by carriers arising from carrier generation levels within the photoelectric conversion element. [Means for solving the problem]

[0006] One disclosure of this specification provides a photoelectric conversion element provided in a semiconductor layer having a first surface and a second surface opposite to the first surface, the photoelectric conversion element comprising: a first semiconductor region of a first conductivity type disposed from the first surface to a first depth; a second semiconductor region of a second conductivity type disposed so as to surround the first semiconductor region in a plan view and having an impurity concentration peak at a second depth between the first surface and the first depth; and a third semiconductor region of the second conductivity type disposed closer to the second surface than the first semiconductor region and constituting an avalanche photodiode between itself and the first semiconductor region. [Effects of the Invention]

[0007] According to the present invention, it is possible to reduce noise caused by carriers originating from carrier generation levels within a photoelectric conversion element. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram (part 1) showing the schematic configuration of the photoelectric conversion device according to the first embodiment. [Figure 2] This is a block diagram (part 2) showing the schematic configuration of the photoelectric conversion device according to the first embodiment. [Figure 3] This is a block diagram showing an example of the pixel configuration of a photoelectric converter according to the first embodiment. [Figure 4] This is a diagram (part 1) illustrating the basic operation of the photoelectric conversion unit in the photoelectric conversion device according to the first embodiment. [Figure 5] This is a diagram (part 2) illustrating the basic operation of the photoelectric conversion unit in the photoelectric conversion device according to the first embodiment. [Figure 6] This is a perspective view showing an example of the configuration of a photoelectric conversion device according to the first embodiment. [Figure 7] It is a schematic cross-sectional view showing the structure of a photoelectric conversion device according to the first embodiment. [Figure 8] It is a plan view showing the structure of a photoelectric conversion element in a photoelectric conversion device according to the first embodiment. [Figure 9] It is a schematic cross-sectional view showing the structure of a photoelectric conversion element in a photoelectric conversion device according to the first embodiment. [Figure 10] It is a graph showing the depth direction distribution of impurities constituting the photoelectric conversion element of the photoelectric conversion device according to the first embodiment. [Figure 11] It is a schematic cross-sectional view showing the structure of a photoelectric conversion element in a photoelectric conversion device according to a reference example. [Figure 12] It is a schematic cross-sectional view showing the structure of a photoelectric conversion element in a photoelectric conversion device according to the second embodiment. [Figure 13] It is a graph showing the depth direction distribution of impurities constituting the photoelectric conversion element of the photoelectric conversion device according to the second embodiment. [Figure 14] It is a schematic cross-sectional view showing the structure of a photoelectric conversion element in a photoelectric conversion device according to a modification of the second embodiment. [Figure 15] It is a block diagram showing the schematic configuration of a photodetection system according to the third embodiment. [Figure 16] It is a block diagram showing the schematic configuration of a distance image sensor according to the fourth embodiment. [Figure 17] It is a schematic diagram showing a configuration example of an endoscopic surgery system according to the fifth embodiment. [Figure 18] It is a schematic diagram showing a configuration example of a moving body according to the sixth embodiment. [Figure 19] It is a block diagram showing the schematic configuration of a photodetection system according to the sixth embodiment. [Figure 20] It is a flowchart showing the operation of the photodetection system according to the sixth embodiment. [Figure 21] It is a schematic diagram showing the schematic configuration of a photodetection system according to the seventh embodiment. [Figure 22] It is a block diagram showing the schematic configuration of a device according to the eighth embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, the following description may use terms indicating specific directions or positions (e.g., "up," "down," "right," "left," and other terms including these) as needed. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention. Also, the size and positional relationships of the components shown in each drawing may be exaggerated for clarity in the explanation.

[0010] In the embodiments described below, the focus will be on photoelectric converters for imaging applications as examples of semiconductor devices. However, each embodiment is not limited to photoelectric converters for imaging applications and can be applied to other semiconductor devices. For example, other examples of semiconductor devices include distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight)) and photometric devices (devices for measuring the amount of incident light).

[0011] [First Embodiment] The schematic configuration of the photoelectric conversion device according to the first embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment.

[0012] As shown in Figure 1, the photoelectric conversion device 100 according to this embodiment includes a pixel area 10, a vertical scanning circuit section 40, a readout circuit section 50, a horizontal scanning circuit section 60, an output circuit section 70, and a control pulse generation section 80.

[0013] The pixel region 10 is provided with multiple pixels 12 arranged in an array such that they form multiple rows and multiple columns. Each pixel 12 may consist of a photoelectric conversion unit including a photoelectric conversion element and a signal processing unit that processes the signal output from the photoelectric conversion unit, as will be described later. The number of pixels 12 constituting the pixel region 10 is not particularly limited. For example, the pixel region 10 can be composed of multiple pixels 12 arranged in an array of several thousand rows x several thousand columns, as in a typical digital camera. Alternatively, the pixel region 10 may be composed of multiple pixels 12 arranged in one row or one column. Alternatively, the pixel region 10 may be composed of a single pixel 12.

[0014] Each row of the pixel array in the pixel region 10 has a control line 14 extending in a first direction (horizontal direction in Figure 1). The control line 14 is connected to each pixel 12 arranged in the first direction and forms a common signal line for these pixels 12. The first direction in which the control line 14 extends is sometimes called the row direction or horizontal direction. Each of the control lines 14 may include multiple signal lines for supplying multiple types of control signals to the pixels 12.

[0015] Furthermore, each column of the pixel array in the pixel region 10 has an output line 16 extending in a second direction (vertical direction in Figure 1) that intersects the first direction. The output line 16 is connected to each pixel 12 arranged in the second direction, forming a common signal line for these pixels 12. The second direction in which the output line 16 extends is sometimes called the column direction or the vertical direction. Each of the output lines 16 may contain multiple signal lines. For example, the output line 16 may contain multiple signal lines for transferring multi-bit digital signals output from the pixels 12 bit by bit.

[0016] Each row's control line 14 is connected to the vertical scanning circuit unit 40. The vertical scanning circuit unit 40 is a control circuit that receives control signals output from the control pulse generation unit 80, generates control signals to drive the pixels 12, and supplies them to the pixels 12 via the control lines 14. Logic circuits such as shift registers and address decoders may be used in the vertical scanning circuit unit 40. The vertical scanning circuit unit 40 sequentially scans the pixels 12 within the pixel area 10 row by row and outputs the pixel signal of each pixel 12 to the readout circuit unit 50 via the output line 16.

[0017] Each output line 16 of a column is connected to the readout circuit 50. The readout circuit 50 includes a plurality of holding units (not shown) corresponding to each column of the pixel array of the pixel region 10, and has the function of holding the pixel signals of the pixels 12 of each column, which are output row by row from the pixel region 10 via the output line 16, in the holding unit of the corresponding column.

[0018] The horizontal scanning circuit unit 60 is a control circuit that receives a control signal output from the control pulse generation unit 80, generates a control signal for reading pixel signals from the holding units of each column of the reading circuit unit 50, and supplies it to the reading circuit unit 50. Logic circuits such as shift registers and address decoders may be used in the horizontal scanning circuit unit 60. The horizontal scanning circuit unit 60 sequentially scans the holding units of each column of the reading circuit unit 50 and sequentially outputs the pixel signals held in each to the output circuit unit 70.

[0019] The output circuit section 70 has an external interface circuit and is a circuit section for outputting the pixel signal output from the readout circuit section 50 to the outside of the photoelectric converter 100. The external interface circuit provided by the output circuit section 70 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied as the external interface circuit. Examples of SerDes transmission circuits include an LVDS (Low Voltage Differential Signaling) circuit and an SLVS (Scalable Low Voltage Signaling) circuit. The output circuit section 70 may further have a signal processing circuit that performs predetermined digital signal processing on the pixel signal output from the readout circuit section 50, prior to the external interface circuit.

[0020] The control pulse generation unit 80 is a control circuit that generates control signals to control the operation and timing of the vertical scanning circuit unit 40, the readout circuit unit 50, and the horizontal scanning circuit unit 60, and supplies them to each functional block. At least a portion of the control signals that control the operation and timing of the vertical scanning circuit unit 40, the readout circuit unit 50, and the horizontal scanning circuit unit 60 may be supplied from outside the photoelectric converter 100.

[0021] Note that the connection configuration of each functional block of the photoelectric converter 100 is not limited to the configuration example shown in Figure 1, and can also be configured as shown in Figure 2, for example.

[0022] In the configuration example shown in Figure 2, output lines 16 extending in a first direction are provided for each row of the pixel array in the pixel region 10. Each output line 16 is connected to a pixel 12 aligned in the first direction, forming a common signal line for these pixels 12. Additionally, control lines 18 extending in a second direction are provided for each column of the pixel array in the pixel region 10. Each control line 18 is connected to a pixel 12 aligned in the second direction, forming a common signal line for these pixels 12.

[0023] Each row's control line 18 is connected to the horizontal scanning circuit unit 60. The horizontal scanning circuit unit 60 receives a control signal output from the control pulse generation unit 80, generates a control signal for reading pixel signals from the pixels 12, and supplies it to the pixels 12 via the control lines 18. Specifically, the horizontal scanning circuit unit 60 sequentially scans multiple pixels 12 in the pixel area 10 in column units and outputs the pixel signals of the pixels 12 in each row belonging to the selected column to the output line 16.

[0024] Each row's output line 16 is connected to the readout circuit unit 50. The readout circuit unit 50 includes a plurality of holding units (not shown) corresponding to each row of the pixel array in the pixel area 10, and has the function of holding the pixel signals of the pixels 12 of each row, which are output column by column from the pixel area 10 via the output line 16, in the holding unit of the corresponding row.

[0025] The readout circuit 50 receives a control signal output from the control pulse generation unit 80 and sequentially outputs the pixel signals held in the holding unit for each row to the output circuit 70. Other configurations in the example configuration shown in Figure 2 may be the same as those in the example configuration shown in Figure 1.

[0026] Figure 3 is a block diagram showing an example of the configuration of a pixel 12. Each pixel 12 has a photoelectric conversion unit 20 and a signal processing unit 30, as shown in Figure 3. The photoelectric conversion unit 20 has a photoelectric conversion element 22 and outputs a signal corresponding to the incident light. The signal processing unit 30 is a signal processing circuit that processes the signal output from the photoelectric conversion unit 20. The signal processing unit 30 may be configured to include, for example, a functional block 30A including a quench element 32 and a waveform shaping circuit 34, and a functional block 30B including a processing circuit 36 ​​and a selection circuit 38. In the pixel configuration shown in Figure 3, the control lines 14 of each row may include a signal line 14A to which a control signal pRES is supplied from the vertical scanning circuit unit 40, and a signal line 14B to which a control signal pSEL is supplied from the vertical scanning circuit unit 40.

[0027] The photoelectric conversion element 22 may be an avalanche photodiode (hereinafter referred to as "APD"). The anode of the APD constituting the photoelectric conversion element 22 is connected to a node to which voltage VL is supplied. The cathode of the APD constituting the photoelectric conversion element 22 is connected to one terminal of the quench element 32 and to the input node of the waveform shaping circuit 34. The connection node between the photoelectric conversion element 22, the quench element 32, and the waveform shaping circuit 34 is the output node of the photoelectric conversion unit 20 and is also the input node of the signal processing unit 30. The other terminal of the quench element 32 is connected to a node to which a voltage VH higher than voltage VL is supplied. Voltages VL and VH are set so that a reverse bias voltage sufficient for the APD to perform avalanche multiplication operation is applied. In one example, a negative high voltage is applied as voltage VL, and a positive voltage of about the power supply voltage is applied as voltage VH. For example, voltage VL is about -20V to -30V, and voltage VH is about 2V to 3V. For simplicity, in the following explanation, we will denote the voltage VL as -Vbd and the voltage VH as Vex. Here, Vbd is the breakdown voltage of the APD, and Vex is the excess bias. That is, a voltage is applied between the cathode and anode of the APD, which is the breakdown voltage Vbd plus the excess bias Vex.

[0028] The photoelectric conversion element 22 can be composed of an APD as described above. By supplying the APD with a reverse bias voltage sufficient for avalanche multiplication, the carriers generated by the incidence of light on the APD undergo avalanche multiplication, and an avalanche current is generated. There are two operating modes when a reverse bias voltage is supplied to the APD: Geiger mode and linear mode. Geiger mode is an operating mode in which the voltage applied between the anode and cathode is a reverse bias voltage greater than the breakdown voltage of the APD. Linear mode is an operating mode in which the voltage applied between the anode and cathode is a reverse bias voltage near or below the breakdown voltage of the APD. An APD operating in Geiger mode is called a SPAD (Single Photon Avalanche Diode). The APD constituting the photoelectric conversion element 22 may operate in linear mode or in Geiger mode, but a SPAD is more preferable because it has a larger potential difference than a linear mode APD and the effect of improving the signal-to-noise ratio is more pronounced.

[0029] In the circuit configuration shown in Figure 3, the anode of the APD is at a fixed potential and the signal is taken from the cathode side. However, the cathode of the APD may also be at a fixed potential and the signal may be taken from the anode side. In the former case, the signal charge is electrons. In the latter case, the signal charge is holes. Furthermore, this embodiment describes the case where one node of the APD is at a fixed potential, but the potentials of both nodes may fluctuate. The following description shows a configuration in which electrons are used as the signal charge. When holes are used as the signal charge, the conductivity type of the semiconductor regions constituting each part of the photoelectric conversion element 22 will be the opposite conductivity type to that of the configuration described below.

[0030] The quench element 32 has the function of converting the change in avalanche current generated in the photoelectric conversion element 22 into a voltage signal. Furthermore, the quench element 32 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, reducing the voltage applied to the photoelectric conversion element 22 and suppressing avalanche multiplication. This operation by the quench element 32 to suppress avalanche multiplication is called the quench operation. The quench element 32 also has the function of returning the voltage supplied to the photoelectric conversion element 22 to voltage VH by allowing current to flow to compensate for the voltage drop caused by the quench operation. This operation by the quench element 32 to return the voltage supplied to the photoelectric conversion element 22 to voltage VH is called the recharge operation. The quench element 32 can be composed of a resistor, a MOS transistor, or the like.

[0031] The waveform shaping circuit 34 has an input node to which the output signal from the photoelectric conversion unit 20 is supplied, and an output node. The waveform shaping circuit 34 has the function of converting the analog signal supplied from the photoelectric conversion unit 20 into a pulse signal. The waveform shaping circuit 34 may be composed of logic circuits including NOT gates (inverter circuits), NOR gates, NAND gates, etc. The output node of the waveform shaping circuit 34 is connected to the processing circuit 36.

[0032] The processing circuit 36 ​​has an input node to which the output signal of the waveform shaping circuit 34 is supplied, a control node connected to the control line 14, and an output node. The processing circuit 36 ​​has the function of performing predetermined signal processing on the output signal of the waveform shaping circuit 34 and holding the processed signal or processing result. The processing circuit 36 ​​is not particularly limited, but may be configured to include, for example, a counter circuit and memory. If the processing circuit 36 ​​has a counter circuit, the processing circuit 36 ​​counts the pulses superimposed on the signal output from the waveform shaping circuit 34 and holds the count value, which is the counting result. The signals supplied from the vertical scanning circuit unit 40 to the processing circuit 36 ​​via the control line 14 may include an enable signal for controlling the pulse counting period (exposure period) and a reset signal for resetting the count value held by the processing circuit 36. Figure 3 shows, as an example, a reset signal (control signal pRES) supplied via the signal line 14A. The output node of the processing circuit 36 ​​is connected to the selection circuit 38.

[0033] The selection circuit 38 has the function of switching the electrical connection state (connected or disconnected) between the processing circuit 36 ​​and the output line 16. The selection circuit 38 switches the connection state between the processing circuit 36 ​​and the output line 16 in accordance with the selection signal supplied from the vertical scanning circuit unit 40 via the control line 14 (in the configuration example of Figure 2, the selection signal supplied from the horizontal scanning circuit unit 60 via the control line 18). Figure 3 shows, as an example, the selection signal (control signal pSEL) supplied via the signal line 14B. The processing circuit 36 ​​may include a buffer circuit for outputting signals.

[0034] Pixel 12 is typically a unit structure that outputs a pixel signal for forming an image. However, in cases where the purpose is distance measurement using the TOF (Time of Flight) method, pixel 12 does not necessarily have to be a unit structure that outputs a pixel signal for forming an image. That is, pixel 12 can also be a unit structure that outputs a signal for measuring the time and amount of light that arrived.

[0035] Furthermore, the signal processing unit 30 does not necessarily need to be provided for each pixel 12; a single signal processing unit 30 may be provided for multiple pixels 12. In this case, a single signal processing unit 30 can be used to sequentially perform signal processing for multiple pixels 12.

[0036] Next, the basic operation of the photoelectric conversion unit 20 in the photoelectric conversion device according to this embodiment will be explained using Figures 4 and 5. Figures 4 and 5 are diagrams illustrating the basic operation of the photoelectric conversion element 22, the quench element 32, and the waveform shaping circuit 34 in the photoelectric conversion device according to this embodiment. Figure 4 shows the operation when the quench element 32 is composed of passive elements, and Figure 5 shows the operation when the quench element 32 is composed of active elements. For the sake of simplicity, we will assume here that the waveform shaping circuit 34 is composed of an inverter circuit.

[0037] First, the operation when the quench element 32 is composed of passive elements will be explained. When the quench element 32 is composed of passive elements, for example, the quench element 32 may be composed of a resistive element or a diode-connected MOS transistor. Figure 4(a) is a circuit diagram of the photoelectric conversion element 22, the quench element 32, and the waveform shaping circuit 34. Figure 4(b) shows the waveform of the signal at the input node (node ​​A) of the waveform shaping circuit 34. Figure 4(c) shows the waveform of the signal at the output node (node ​​B) of the waveform shaping circuit 34.

[0038] At time t0, a reverse bias voltage of (Vbd + Vex), corresponding to a potential difference of (VH - VL), is applied to the photoelectric element 22. A reverse bias voltage sufficient to cause avalanche multiplication is applied between the anode and cathode of the APD constituting the photoelectric element 22. However, when no photons are incident on the photoelectric element 22, there are no carriers that serve as seeds for avalanche multiplication. Therefore, avalanche multiplication does not occur in the photoelectric element 22, and no current flows through the photoelectric element 22.

[0039] At the following time t1, assume that a photon is incident on the photoelectric conversion element 22. When a photon is incident on the photoelectric conversion element 22, electron-hole pairs are generated by photoelectric conversion, and avalanche multiplication occurs using these carriers as a seed, causing an avalanche multiplication current to flow through the photoelectric conversion element 22. This avalanche multiplication current flows through the quench element 32, causing a voltage drop across the quench element 32, and the voltage at node A begins to drop. When the voltage drop at node A becomes large and reaches approximately Vex, avalanche multiplication stops at time t3, and the voltage level at node A stops dropping further. The potential at which avalanche amplification stops is approximately 0V, that is, the potential at which the voltage across the photoelectric conversion element 22 is approximately Vbd.

[0040] When the avalanche multiplication in the photoelectric conversion element 22 stops, a current flows from the node with voltage VH to node A via the quench element 32 to compensate for the voltage drop, and the voltage at node A gradually increases. Subsequently, at time t5, node A settles back to its original voltage level.

[0041] The waveform shaping circuit 34 binarizes the signal input from node A according to a predetermined threshold and outputs it from node B. Specifically, the waveform shaping circuit 34 outputs a low-level signal from node B when the voltage level of node A exceeds the threshold, and outputs a high-level signal from node B when the voltage level of node A is below the threshold. For example, as shown in Figure 4(b), suppose the voltage of node A was below the threshold during the period from time t2 to time t4. In this case, as shown in Figure 4(c), the signal level at node B is low during the period from time t0 to time t2 and from time t4 to time t5, and high during the period from time t2 to time t4.

[0042] Thus, the analog signal input from node A is waveform-shaped into a digital signal by the waveform shaping circuit 34. The pulse signal output from the waveform shaping circuit 34 in response to the incidence of photons on the photoelectric conversion element 22 is the photon detection pulse signal.

[0043] Next, the operation when the quench element 32 is composed of an active element will be described. When the quench element 32 is composed of an active element, for example, it may be composed of a MOS transistor that operates with an external control signal. Figure 5(a) is a circuit diagram of the photoelectric conversion element 22, the quench element 32, and the waveform shaping circuit 34. Figure 5(b) shows the waveform of the signal at the input node (node ​​C) of the quench element 32. Figure 5(c) shows the waveform of the signal at the input node (node ​​A) of the waveform shaping circuit 34. Figure 5(d) shows the waveform of the signal at the output node (node ​​B) of the waveform shaping circuit 34.

[0044] In the circuit shown in Figure 5(a), the quench element 32 is made up of a P-type MOS transistor. The source of the P-type MOS transistor is connected to the voltage VH node, and the drain of the P-type MOS transistor is connected to the cathode of the photoelectric conversion element 22 and the input node of the waveform shaping circuit 34. Node A is the connection node between the drain of the P-type MOS transistor, the cathode of the photoelectric conversion element 22, and the input node of the waveform shaping circuit 34. A periodic pulse signal (hereinafter referred to as the reset pulse signal) is input to the gate (node ​​C) of the P-type MOS transistor, for example, as shown in Figure 5(b). The reset pulse signal is a falling-edge pulse that transitions from a high level to a low level. The P-type MOS transistor turns off when node C is high, disconnecting node A from the voltage VH node, and turns on when node C is low, resetting node A to voltage VH.

[0045] When a reset pulse signal is input to node C at time t1, the P-type MOS transistor turns on, and node A is reset to voltage VH. When node C returns to high level, the P-type MOS transistor turns off, and node A becomes floating at voltage VH.

[0046] At the following time t2, assume that a photon is incident on the photoelectric conversion element 22. When a photon is incident on the photoelectric conversion element 22, electron-hole pairs are generated by photoelectric conversion, and avalanche multiplication occurs using these carriers as a seed, causing an avalanche multiplication current to flow through the photoelectric conversion element 22. This avalanche multiplication current flows through the quench element 32, causing a voltage drop across the quench element 32, and the voltage at node A begins to drop. When the voltage drop at node A becomes large and reaches approximately Vex, avalanche multiplication stops at time t4, and the voltage level at node A stops dropping further. The potential at which avalanche amplification stops is approximately 0V, that is, the potential at which the voltage across the photoelectric conversion element 22 is approximately Vbd. Node A remains in a floating state at the lowered potential.

[0047] When a reset pulse signal is input to node C again at time t5, the P-type MOS transistor turns on, and node A is reset to voltage VH again.

[0048] The waveform shaping circuit 34 binarizes the signal input from node A according to a predetermined threshold and outputs it from node B. Specifically, the waveform shaping circuit 34 outputs a low-level signal from node B when the voltage level at node A exceeds the threshold, and outputs a high-level signal from node B when the voltage level at node A is below the threshold. For example, as shown in Figure 5(c), suppose the voltage at node A was below the threshold during the period from time t3 to time t5. In this case, as shown in Figure 5(d), the signal level at node B is low during the period from time t0 to time t3 and from time t5 onwards, and high during the period from time t3 to time t5.

[0049] Thus, the analog signal input from node A is waveform-shaped into a digital signal by the waveform shaping circuit 34. The pulse signal output from the waveform shaping circuit 34 in response to the incidence of photons on the photoelectric conversion element 22 is the photon detection pulse signal.

[0050] In the operation shown in Figure 5, if no photons are incident between time t1 and time t5, node A remains at voltage VH and node B remains at a low level. Furthermore, if a photon is incident again between time t2 and time t5, i.e., when the potential of node A has decreased, the photoelectric conversion element 22 cannot undergo further avalanche multiplication. Therefore, the maximum number of photon incidents that can be detected by the waveform shaping circuit 34 during the period from time t1 to time t5 is one.

[0051] Thus, in the operation shown in Figure 5, it is possible to distinguish whether the number of photons incident during one cycle of the reset pulse signal is zero or one or more. On the other hand, if two or more photons are incident during one cycle of the reset pulse signal, it is not possible to distinguish between them, which may result in signal detection loss.

[0052] In the case where photons are incident one after another without interruption, the operation shown in Figure 4 results in a state where the avalanche multiplication in the photoelectric conversion element 22 does not stop, and the avalanche current continues to flow, a so-called pile-up state. In this pile-up state, no photon detection pulse signal is generated, and only current flows unnecessarily, which is a major problem in SPAD operation.

[0053] On the other hand, in the operation shown in Figure 5, it is not possible to distinguish between two or more photons if they are incident during one cycle of the reset pulse signal, but it has the advantage of not causing the pile-up that can occur in the operation shown in Figure 4. While signal detection loss can certainly occur in the operation shown in Figure 5, SPADs are primarily intended for photon detection in situations with few incident photons, and in such situations, it is rare for multiple photons to be incident during one cycle of the reset pulse, so there is almost no signal detection loss. For this reason, the operation shown in Figure 5 is often applied, especially when using SPADs as image sensors.

[0054] The photoelectric conversion device 100 according to this embodiment may be formed on a single substrate, or it may be configured as a stacked type photoelectric conversion device by stacking multiple substrates. In the latter case, for example, as shown in Figure 6, it can be configured as a stacked type photoelectric conversion device in which a sensor substrate 110 (first substrate) and a circuit board 180 (second substrate) are stacked and electrically connected. At least the photoelectric conversion unit 20, which is one of the components of the pixel 12, can be arranged on the sensor substrate 110. The signal processing unit 30, which is one of the components of the pixel 12, can be arranged on the circuit board 180. The photoelectric conversion unit 20 and the signal processing unit 30 are electrically connected via connecting wiring provided for each pixel 12. Furthermore, the circuit board 180 can also include a vertical scanning circuit unit 40, a readout circuit unit 50, a horizontal scanning circuit unit 60, an output circuit unit 70, and a control pulse generation unit 80.

[0055] The photoelectric conversion unit 20 and signal processing unit 30 for each pixel 12 may be provided on the sensor substrate 110 and the circuit board 180 so as to overlap in a plan view. The vertical scanning circuit unit 40, the readout circuit unit 50, the horizontal scanning circuit unit 60, the output circuit unit 70, and the control pulse generation unit 80 may be arranged around the pixel region 10 composed of multiple pixels 12. Here, "plan view" refers to viewing from a direction perpendicular to the surface of the sensor substrate 110.

[0056] By configuring a stacked photoelectric converter 100, the integration density of elements can be increased, leading to improved functionality. In particular, by arranging the photoelectric conversion unit 20 and the signal processing unit 30 on separate substrates, the photoelectric conversion elements 22 can be arranged at high density without sacrificing the light-receiving area of ​​the photoelectric conversion elements 22, thereby improving photon detection efficiency.

[0057] Furthermore, the number of substrates constituting the photoelectric converter 100 is not limited to two; the photoelectric converter 100 may be constructed by stacking three or more substrates. For example, when the photoelectric converter 100 is constructed by stacking three substrates, the photoelectric conversion unit 20, one of the components of the pixel 12, can be placed on the sensor substrate. Alternatively, the functional block 30A, one of the components of the pixel 12, can be placed on the first circuit board, and the functional block 30B, one of the components of the pixel 12, can be placed on the second circuit board. By separating the substrates on which the components are placed according to the characteristics of the elements constituting each functional block, a manufacturing process suitable for each element can be applied, thereby improving the performance of the photoelectric converter.

[0058] Furthermore, while Figure 6 assumes chips that have been diced as sensor substrate 110 and circuit board 180, the sensor substrate 110 and circuit board 180 are not limited to chips. For example, each of the sensor substrate 110 and circuit board 180 may be a wafer. Also, the sensor substrate 110 and circuit board 180 may be stacked in wafer form and then diced, or they may be made into chips and then stacked and bonded.

[0059] Next, the specific element structure of the photoelectric converter 100 according to this embodiment will be described with reference to Figure 7. Figure 7 is a schematic cross-sectional view showing the structure of the photoelectric converter according to this embodiment.

[0060] The photoelectric converter 100 according to this embodiment can be configured as a stacked type photoelectric converter in which a sensor substrate 110 and a circuit board 180 are stacked, as shown in Figure 7, for example. The sensor substrate 110 has a semiconductor layer 120 having a first surface 122 and a second surface 124 facing the first surface 122, and a wiring structure layer 150 provided on the side of the first surface 122 of the semiconductor layer 120. An optical structure layer 190 may be arranged on the side of the second surface 124 of the semiconductor layer 120. The circuit board 180 is stacked on the side of the wiring structure layer 150 of the sensor substrate 110. The bonding surface 170 in Figure 6 is the bonding portion between the sensor substrate 110 and the circuit board 180. In the photoelectric converter of this embodiment, the side of the second surface 124 of the semiconductor layer 120 on which the optical structure layer 190 is provided becomes the light-receiving surface into which the light to be detected is incident. In other words, the photoelectric converter of this embodiment is a so-called back-illuminated type photoelectric converter.

[0061] The semiconductor layer 120 is, for example, a thinned single-crystal silicon substrate and contains a predetermined concentration of N-type or P-type impurities. In this embodiment, as an example, a semiconductor layer 120 made by thinning an N-type silicon substrate with a low impurity concentration is assumed. The semiconductor layer 120 is provided with a photoelectric conversion element 22 that includes an N-type semiconductor region, a P-type semiconductor region, and a semiconductor region. The specific structure of the photoelectric conversion element 22 will be described later. In this embodiment, the method of detecting changes in cathode potential is used as the basis, as shown in Figures 4 and 5. However, a method of detecting changes in anode potential may also be used.

[0062] The wiring structure layer 150 includes an insulating layer 152 and a wiring layer 154 disposed within the insulating layer 152. The wiring layer 154 includes an anode electrode 156 (second electrode) connected to a P-type semiconductor region 136, a cathode electrode 158 (first electrode) connected to an N-type semiconductor region 126, and a pad electrode 160 composed of the wiring layer furthest from the semiconductor layer 120.

[0063] The circuit board 180 is laminated on the side of the wiring structure layer 150 of the sensor board 110. The joint surface 170 in Figure 6 is the joint between the sensor board 110 and the circuit board 180. The circuit board 180 has a semiconductor layer on which elements such as transistors are provided, and a wiring structure layer provided on top of the semiconductor layer. For the sake of simplicity, Figure 7 shows only the pad electrode 182, which is made up of the uppermost wiring layer, and some wiring layers 184 connected to the pad electrode 182, among the semiconductor layer and wiring structure layer that make up the circuit board 180. The sensor board 110 and the circuit board 180 can be physically and electrically connected, for example, by a metal joint between the metal member that makes up the pad electrode 160 and the metal member that makes up the pad electrode 182. The circuit board 180 may be made up of multiple boards.

[0064] The optical structure layer 190 may comprise a pinning film 192, a planarization layer 194, and a microlens layer containing a plurality of microlenses 196. The optical structure layer 190 may also further include a filter layer (not shown). Various optical filters, such as color filters, infrared cut filters, and monochrome filters, can be applied to the filter layer. Known materials can be used for the pinning film 192.

[0065] Next, the specific element structure of the photoelectric conversion element 22 in the photoelectric conversion device 100 according to this embodiment will be described using Figures 8 and 9. Figure 8 is a plan view showing the structure of the photoelectric conversion element in the photoelectric conversion device according to this embodiment. Figure 9 is a schematic cross-sectional view showing the structure of the photoelectric conversion element in the photoelectric conversion device according to this embodiment. Figure 8 corresponds to a plan view of the semiconductor layer 120 as seen from the side of the first surface 122. Figure 9 is a cross-sectional view taken along the line IX-IX' in Figure 8.

[0066] As shown in Figures 8 and 9, the semiconductor layer 120 is provided with an N-type semiconductor region 126, P-type semiconductor regions 128, 130, 132, 134, 136, and semiconductor regions 138, 140. The P-type semiconductor region 130 is provided on the side of the second surface 124 of the semiconductor layer 120 in cross-sectional view. The P-type semiconductor region 130 is provided over the entire area where the photoelectric conversion elements 22 are arranged, and overlaps with the N-type semiconductor region 126, P-type semiconductor regions 128, 132, 134, 136, and semiconductor regions 138, 140 in plan view. When configuring a back-illuminated type photoelectric conversion device, it is preferable to arrange the P-type semiconductor region 134 so that it is in contact with the second surface 124. By configuring it in this way, the generation of dark current on the second surface 124 can be prevented. The P-type semiconductor region 132 is provided at the boundary portion between adjacent photoelectric conversion elements 22. In other words, the P-type semiconductor region 132 is provided so as to surround each of the regions where the photoelectric conversion elements 22 are arranged in a plan view. The P-type semiconductor region 132 is provided from the first surface 122 of the semiconductor layer 120 to the depth to which the P-type semiconductor region 134 is arranged. In Figures 8 and 9, one photoelectric conversion element 22 is placed in the region surrounded by the P-type semiconductor region 132, but two or more photoelectric conversion elements 22 may be placed in each of the regions surrounded by the P-type semiconductor region 132.

[0067] In this specification, "plan view" refers to viewing the semiconductor layer 120 from the direction normal to the light incident surface (second surface 124) or the opposite surface (first surface 122). "Cross-sectional view" refers to viewing a cross-section of the semiconductor layer 120 parallel to the normal direction of the first surface 122 or the second surface 124 from the direction normal to the cross-section.

[0068] Inside the region enclosed by the P-type semiconductor regions 130 and 132, there are N-type semiconductor regions 126, P-type semiconductor regions 128, 134, and 136, and semiconductor regions 138 and 140. The N-type semiconductor region 126 is located on the side of the first surface 122 of the semiconductor layer 120, spaced apart from the P-type semiconductor region 132. The N-type semiconductor region 126 extends from the first surface 122 to a depth D3 on the side of the second surface 124. The P-type semiconductor region 128 extends from a depth D4 on the side of the second surface 124 beyond depth D3 to a depth D5 further on the side of the second surface 124 beyond depth D4. The P-type semiconductor region 128 is in contact with the P-type semiconductor region 132 at its peripheral edge in a plan view. The P-type semiconductor region 136 is arranged in a plan view so as to surround the N-type semiconductor region 126, extending from a depth D1 between the first surface 122 and depth D3 to a depth D2 that is deeper than depth D1 and approximately the same as depth D3, or shallower than depth D3. The P-type semiconductor region 136 is in contact with the N-type semiconductor region 126. In Figure 8, the P-type semiconductor region 136 is spaced apart from the P-type semiconductor region 132 at its peripheral edge in a plan view, but it may be in contact with it. The P-type semiconductor region 134 is provided on the side of the first surface 122 of the semiconductor layer 120, in contact with the P-type semiconductor region 132 and spaced apart from the N-type semiconductor region 126. The P-type semiconductor region 134 may be in contact with the P-type semiconductor region 136, for example, as shown in Figure 8. The portion of the region from the first surface 122 to depth D4 that excludes the N-type semiconductor region 126 and the P-type semiconductor regions 132, 134, and 136 is the semiconductor region 138. Furthermore, the region between the P-type semiconductor region 128 and the P-type semiconductor region 130 is the semiconductor region 140. The conductivity type of the semiconductor regions 138 and 140 is not particularly limited and may be either N-type or P-type.

[0069] The N-type semiconductor region 126 constitutes the cathode of the APD and is the part that contacts the cathode electrode 158, and is made of an N-type semiconductor containing a high concentration of N-type impurities. The P-type semiconductor region 134 is the part that contacts the anode electrode 156 of the APD and is made of a P-type semiconductor containing a high concentration of P-type impurities. The P-type semiconductor region 128 is the region that becomes the anode of the APD and is made of a P-type semiconductor containing P-type impurities. The P-type semiconductor region 128 is provided at a depth on the second surface 124 side of the cathode (N-type semiconductor region 126) and extends over almost the entire area where the photoelectric conversion element 22 is located. The semiconductor region 140 is a photoelectric conversion region and is made of a semiconductor containing a low concentration of N-type or P-type impurities. The semiconductor region 138 is made of a semiconductor containing a low concentration of N-type or P-type impurities, and during operation, at least the vicinity of the N-type semiconductor region 126 becomes depleted.

[0070] In the photoelectric conversion element 22 of this embodiment, the depletion layer formed in the pn junction between the N-type semiconductor region 126 and the P-type semiconductor region 128 becomes the avalanche multiplication region. The P-type semiconductor region 132 not only serves as an element isolation region but also as a path for supplying anode potential to the P-type semiconductor region 128 that constitutes the anode of the APD. That is, the anode potential supplied from the anode electrode 156 is supplied to the P-type semiconductor regions 128 and 130 via the P-type semiconductor regions 134 and 132. As a result, the potential of the P-type semiconductor regions 132, 128, and 130 becomes the anode potential.

[0071] By applying a predetermined reverse bias voltage between the cathode electrode 158 and the anode electrode 156, a high electric field is applied to the pn junction between the N-type semiconductor region 126 and the P-type semiconductor region 128, enabling operation as an APD. During APD operation, depletion occurs in the P-type semiconductor region 128, at least in the portion that overlaps with the N-type semiconductor region 126 in a plan view, with the depletion penetrating both above and below. As a result, the signal charge generated by photon incidence into the semiconductor region 140 flows into the N-type semiconductor region 126 through the depleted region of the P-type semiconductor region 128 formed directly below the cathode, causing avalanche multiplication in the process.

[0072] Here, the first surface 122 of the semiconductor layer 120 is the end of the atomic arrangement that makes up the semiconductor, so it is known that semiconductor atoms tend to have dangling bonds and that many carrier generation levels exist there. Therefore, when the APD is operating, electron-hole carrier pairs are generated at a high rate from the vicinity of the first surface 122 around the depleted cathode. When some of these reach the strong electric field region between the cathode and anode, they cause avalanche multiplication and become a factor that increases the dark count rate (DCR). DCR is the number of dark-time generated carriers per unit time in a SPAD. DCR is the main component of dark-time noise in a SPAD and it is desirable to reduce it as much as possible.

[0073] From this perspective, in the photoelectric conversion element 22 of this embodiment, a P-type semiconductor region 136 is provided around the N-type semiconductor region 126 in a plan view. The P-type semiconductor region 136 is located on the side of the first surface 122 that is less than the high-electric-field region where avalanche multiplication occurs, and has a peak in the impurity concentration of P-type impurities at the depth between the first surface 122 and the depth D3. The reason why the photoelectric conversion element 22 of this embodiment has such a P-type semiconductor region 136 will be explained below.

[0074] In this specification, "impurity concentration" refers to the effective impurity concentration, that is, the net impurity concentration (effective impurity concentration) after subtracting the amount offset by reverse-conducting impurities. In other words, the region where the concentration of P-type impurities is higher than the concentration of N-type impurities is a P-type semiconductor region where the impurity concentration is obtained by subtracting the concentration of N-type impurities from the concentration of P-type impurities. Similarly, the region where the concentration of N-type impurities is higher than the concentration of P-type impurities is an N-type semiconductor region where the impurity concentration is obtained by subtracting the concentration of P-type impurities from the concentration of N-type impurities.

[0075] Figure 10 is a graph showing the depth distribution of impurities along a perpendicular line passing through the center of the N-type semiconductor region 126 in a plan view. The horizontal axis represents the depth in the direction from the first surface 122 to the second surface 124, and the vertical axis represents the impurity concentration (logarithmic scale). Figure 10 shows the depth distribution of N-type impurities 126N constituting the N-type semiconductor region 126, the depth distribution of P-type impurities 128P constituting the P-type semiconductor region 128, and the depth distribution of P-type impurities 136P constituting the P-type semiconductor region 136.

[0076] In Figure 10, the depth D3 is the depth of the bottom surface of the N-type semiconductor region 126 (cathode), i.e., the depth on the side of the second surface 124 of the N-type semiconductor region 126. In the operating state of the APD, the concentration of N-type impurities in the N-type semiconductor region 126 is 1 × 10⁻⁶ 17 cm -3 Because regions below a certain level become depleted, the effective cathode is an N-type semiconductor region 126 with an N-type impurity concentration of 1 × 10⁻⁶. 17 cm -3 This refers to the portion exceeding a certain degree. Therefore, in this specification, the concentration of N-type impurities on the P-type semiconductor region 128 is 1 × 10⁻⁶. 17 cm -3 The depth at which this occurs is defined as the depth D3 of the bottom surface of the N-type semiconductor region 126. The region on the side of the second surface 124 that is deeper than depth D3 is a high-electric-field region where avalanche multiplication occurs.

[0077] The p-type impurities 136P that constitute the p-type semiconductor region 136 can be present not only around the N-type semiconductor region 126 in a plan view, but also in the area overlapping with the N-type semiconductor region 126. Therefore, when observing the depth distribution of impurities along a perpendicular line passing through the center of the N-type semiconductor region 126, as shown in Figure 10, the p-type impurities 136P constituting the p-type semiconductor region 136 exist between the first surface 122 and depth D3. However, since the impurity concentration of p-type impurities 136P is sufficiently small compared to the impurity concentration of N-type impurities 126N, the net conductivity type in the area where the N-type semiconductor region 126 and the p-type semiconductor region 136 overlap is N-type. The p-type semiconductor region 136 does not exhibit any unique effects. Furthermore, providing the p-type semiconductor region 136 in the area overlapping with the N-type semiconductor region 126 has advantages such as preventing characteristic variations caused by misalignment between the two regions.

[0078] On the other hand, if we focus on the region that does not overlap with the N-type semiconductor region 126 in a plan view, for example, along the perpendicular line passing through point C (see Figures 8 and 9), the impurity concentration of the P-type impurities constituting the P-type semiconductor region 136 is higher than the impurity concentration of the impurities constituting the semiconductor region 138. Therefore, the conductivity type of the portion corresponding to the P-type impurity 136P becomes P-type, and the function of the P-type semiconductor region 136 becomes apparent.

[0079] The depth D6 shown in Figure 10 is the depth at which the concentration of P-type impurities constituting the P-type semiconductor region 136 peaks. Depth D6 is located on the side of the second surface 124 to the first surface 122, and on the side of the first surface 122 to the depth D3. On the perpendicular line passing through point C, the concentration of P-type impurities on the first surface 122 and at depth D3 is sufficiently lower than the concentration of P-type impurities at depth D6. In other words, the P-type semiconductor region 136 is required to have a steep concentration gradient of P-type impurities with respect to depth. In this sense, in regions that do not overlap with the N-type semiconductor region 126 in a plan view, it is more preferable that the conductivity type on the first surface 122 and its vicinity, and on depth D3 and its vicinity, is N-type. Note that when the conductivity type around depth D3 is N-type, this includes the case where it is N-type at a depth deeper than but close to depth D3, and the case where it is N-type from a location deeper than depth D6 to a depth close to depth D3.

[0080] Now, in the structure described above, let's consider the generation of carriers from the carrier generation level of the first surface 122. As already mentioned, when the SPAD is in operation, the region surrounding the N-type semiconductor region 126 is depleted regardless of its conductivity type. Carriers are then generated at a high rate from the depleted interface level of the first surface 122. If we define the direction parallel to the first surface 122 and the second surface 124 as the transverse direction, the transverse component of the electric field is large around the N-type semiconductor region 126 in a plan view. Therefore, electrons generated on the first surface 122 drift toward the cathode, the N-type semiconductor region 126, and holes generated on the first surface 122 drift toward the anode, the P-type semiconductor region 128. These carriers cause avalanche multiplication and are counted as DCR when they reach the high electric field region between the N-type semiconductor region 126 and the P-type semiconductor region 128.

[0081] In this case, the P-type semiconductor region 136 acts as a potential barrier for electrons, so that for electrons generated near the first surface 122, the first surface 122 and the surrounding region become stable regions with a potential minimum. On the other hand, the P-type semiconductor region 136 also becomes a stable region with a potential minimum for holes generated near the first surface 122. Therefore, both electrons and holes generated near the first surface 122 are prevented from diffusing in the depth direction by the P-type semiconductor region 136, making it difficult for them to reach the high electric field region.

[0082] In other words, around the N-type semiconductor region 126 in a plan view, the first surface 122 and its vicinity become electron evacuations, and the P-type semiconductor region 136 becomes a hole evacuation path. Having the conductivity type of the first surface 122 and its vicinity around the N-type semiconductor region 126 being N-type is more effective in forming electron evacuations. However, even if the conductivity type of the first surface 122 and its vicinity, as well as the depth D3 and its vicinity, is P-type around the N-type semiconductor region 126 in a plan view, evacuations can be formed depending on the conditions. According to the inventors' considerations and simulations, it is possible to secure electron evacuations by setting the P-type impurity concentration around the first surface 122 and its vicinity, and the depth D3 and its vicinity, to a concentration of 1 / 2 or less of the peak impurity concentration of the P-type semiconductor region 136. In other words, in at least one of the first surface 122 and its vicinity, and depth D3 and its vicinity, the P-type impurity concentration should be set to 1 / 2 or less of the peak impurity concentration of the P-type semiconductor region 136, or an N-type semiconductor region should be provided. If an N-type semiconductor region is provided, the maximum impurity concentration in the N-type semiconductor region should be set to a lower concentration than the maximum impurity concentration in the N-type semiconductor region 126.

[0083] Figure 11 is a schematic cross-sectional view showing the structure of a photoelectric conversion element according to a reference example. In the photoelectric conversion element 22 according to the reference example, a P-type semiconductor region 136 with a uniformly low impurity concentration is provided around the N-type semiconductor region 126, extending from the first surface 122 of the semiconductor layer to a depth D4. In this structure, when the P-type semiconductor region 136 becomes depleted, the potential of the P-type semiconductor region 136 is affected by the cathode potential of the N-type semiconductor region 126, becoming high at the first surface 122 and decreasing towards the depth, resulting in a potential gradient that pushes holes towards deeper areas. Similarly, electrons may diffuse towards deeper areas away from the N-type semiconductor region 126. In short, this structure does not form a carrier discharge path, and it is not possible to reduce the DCR caused by carriers generated on the first surface 122 of the semiconductor layer.

[0084] The effects of this embodiment become more pronounced when the structure is such that the conductivity of the first surface 122 and its vicinity, as well as the depth D3 and its vicinity, is N-type around the N-type semiconductor region 126 in a plan view. Therefore, N-type impurities may be actively introduced into the first surface 122 and its vicinity, and the depth D3 and its vicinity, to provide an N-type semiconductor region. This N-type semiconductor region may be provided in approximately the same area as the P-type semiconductor region 136 in a plan view, or it may be provided in the entire area where the photoelectric conversion element 22 is arranged.

[0085] In the configuration examples shown in Figures 8 and 9, the P-type semiconductor region 136 and the P-type semiconductor region 134 are directly connected. However, the P-type semiconductor region 136 does not necessarily need to be directly connected to the P-type semiconductor region 134. For example, even if a low-impurity concentration N-type semiconductor region exists between the P-type semiconductor region 134 and the P-type semiconductor region 136, if this N-type semiconductor region is depleted during operation, the P-type semiconductor region 136 can function as a hole discharge path to the P-type semiconductor region 134. Of course, the P-type semiconductor region 136 may also be directly connected to the P-type semiconductor region 134 or the P-type semiconductor region 132. Furthermore, in the configuration examples shown in Figures 8 and 9, there are two P-type semiconductor regions 134, but there may be one, or three or more. Also, the P-type semiconductor region 136 does not need to function as a hole discharge path for multiple P-type semiconductor regions 134; it only needs to function as a hole discharge path for at least one P-type semiconductor region 134.

[0086] Thus, according to this embodiment, since a P-type semiconductor region having an impurity concentration peak at a position shallower than the bottom surface of the cathode is provided around the cathode, noise caused by carriers generated from carrier generation levels within the photoelectric conversion element can be reduced.

[0087] [Second Embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figure 12. Figure 12 is a schematic cross-sectional view showing the structure of the photoelectric conversion element in the photoelectric conversion device according to this embodiment. The same reference numerals are used for the components of the photoelectric conversion device according to the first embodiment, and their descriptions are omitted or simplified.

[0088] The photoelectric conversion device according to this embodiment is the same as the photoelectric conversion device according to the first embodiment, except that the structure of the photoelectric conversion element 22 is different. In this embodiment, the differences between the photoelectric conversion element of this embodiment and the photoelectric conversion element of the first embodiment will be described in detail, and parts that are common to the photoelectric conversion element of the first embodiment will be omitted from the explanation as appropriate.

[0089] The photoelectric conversion element 22 of this embodiment differs from the photoelectric conversion element of the first embodiment in that the structure of the N-type semiconductor region 126 is different. Specifically, as shown in Figure 12, the N-type semiconductor region 126 of the photoelectric conversion element 22 of this embodiment has a constricted portion 142 in the depth direction. The constricted portion 142 of the N-type semiconductor region 126 is located at the same depth as the P-type semiconductor region 136, and more preferably near the depth D6 where the concentration of P-type impurities constituting the P-type semiconductor region 136 peaks.

[0090] Figure 13 is a graph showing the depth distribution of impurities along a perpendicular line passing through the center of the N-type semiconductor region 126. The horizontal axis represents the depth in the direction from the first surface 122 to the second surface 124, and the vertical axis represents the impurity concentration (logarithmic scale). Figure 13 shows the concentration distribution of N-type impurities 126-1N and 126-2N constituting the N-type semiconductor region 126, the concentration distribution of P-type impurity 128P constituting the P-type semiconductor region 128, and the concentration distribution of P-type impurity 136P constituting the P-type semiconductor region 136.

[0091] In the photoelectric conversion element 22 of this embodiment, the N-type semiconductor region 126 can be formed, for example, by performing ion implantation of N-type impurities multiple times under conditions with different projection ranges. In Figure 13, N-type impurity 126-1N shows the distribution of N-type impurities implanted under conditions where the projection range is shallower than the depth D6, and N-type impurity 126-2N shows the distribution of N-type impurities implanted under conditions where the projection range is deeper than the depth D6. Here, the N-type semiconductor regions formed by these ion implantations will be referred to as N-type semiconductor regions 126-1 and 126-2, respectively. The projection range of the implanted ions can be arbitrarily changed by appropriately setting the acceleration energy according to the ion species.

[0092] N-type semiconductor region 126-1 has a peak in the concentration of N-type impurities on the side of the first surface 122, relative to the depth D6. N-type semiconductor region 126-2 has a peak in the concentration of N-type impurities on the side of the second surface 124, relative to the bottom surface of the second surface 124 of N-type semiconductor region 126-1. Furthermore, N-type semiconductor regions 126-1 and 126-2 are provided such that at least a portion of the bottom edge on the second surface 124 side of N-type semiconductor region 126-1 and at least a portion of the bottom edge on the first surface 122 side of N-type semiconductor region 126-2 overlap. N-type semiconductor region 126-1 and N-type semiconductor region 126-2 conduct electricity at the overlapping portion, and their potentials are approximately the same. In other words, in the photoelectric conversion element 22 of this embodiment, N-type semiconductor region 126-1 and N-type semiconductor region 126-2 together constitute a single cathode. The connection between the N-type semiconductor region 126-1 and the N-type semiconductor region 126-2 is located at the same depth as the P-type semiconductor region 136.

[0093] Impurities added by ion implantation are distributed not only in the depth direction but also in the horizontal direction. Furthermore, the smaller the area of ​​the region to be implanted and the deeper the formation location, the more convex the cross-sectional shape of the formed semiconductor region becomes, with a greater curvature in the center. This is because the concentration of impurities constituting the semiconductor region decreases as they move away from the center, and the impurity distribution tends to spread out as the formation location deepens. As a result, the width of the N-type semiconductor regions 126-1 and 126-2 in a plan view near the depth D6 where the tails of N-type semiconductor region 126-1 and N-type semiconductor region 126-2 overlap is smaller than the maximum width of the N-type semiconductor regions 126-1 and 126-2 in a plan view. This portion corresponds to the constricted portion 142 of the N-type semiconductor region 126.

[0094] The N-type semiconductor regions 126-1 and 126-2 may have the same shape in a plan view, but do not necessarily need to be the same shape, and their sizes in a plan view may differ. However, if the N-type semiconductor regions 126-1 and 126-2 have substantially the same shape in a plan view, they can be formed through the same masking process, which has the advantage of simplifying the manufacturing process.

[0095] The P-type semiconductor region 136 can be provided at substantially the same depth as the depth at which the N-type semiconductor regions 126-1 and 126-2 overlap. It is desirable that the peak impurity concentration of the P-type semiconductor region 136 be lower than the concentration of N-type impurities at the depth where the N-type semiconductor regions 126-1 and 126-2 overlap. This is because if the concentration of P-type impurities constituting the P-type semiconductor region 136 becomes higher than the concentration of N-type impurities, there is a possibility that electrical conduction between the N-type semiconductor regions 126-1 and 126-2 cannot be maintained.

[0096] Also in the present embodiment, in the cathode region formed by the N-type semiconductor region 126, the depth D3 at which the N-type impurity concentration on the side of the P-type semiconductor region 128 becomes 1×10 17 cm -3 is defined as the bottom surface of the cathode. The reason for defining the bottom surface of the cathode based on the N-type impurity concentration of 1×10 17 cm -3 is the same as in the first embodiment. The region on the side of the second surface 124 deeper than the depth D3 is a high electric field region where avalanche multiplication occurs. Since the P-type semiconductor region 136 is provided at substantially the same depth as the depth at which the N-type semiconductor regions 126-1 and 126-2 overlap, the depth D3 of the bottom surface of the cathode is located closer to the second surface 124 than the depth D6 at which the concentration of the P-type impurity 136P peaks.

[0097] Generally, in charge-collecting SPADs, the cathode size is small relative to the pixel size. When a high voltage is applied between the anode and cathode during operation, electric field lines concentrate at the cathode, resulting in a high electric field strength near the cathode. Meanwhile, electrons generated on the first surface 122 drift toward the cathode along the first surface 122 and its vicinity, and are accelerated by the electric field near the cathode. At this time, some of the electrons accelerated by the electric field near the cathode may maintain their kinetic energy even when they enter the neutral region within the cathode near the cathode edge, causing impact ionization. The holes from the carrier pairs generated by impact ionization then move by diffusion through the neutral region near the cathode edge.

[0098] In the structure of the photoelectric conversion element according to the first embodiment and the reference example, holes generated in the neutral region inside the cathode by the mechanism described above reach the bottom of the cathode with a certain probability due to diffusion. The bottom of the cathode is the location with the highest electric field strength in the photoelectric conversion element, and therefore has the highest probability of causing avalanche multiplication. For this reason, the DCR may increase due to holes that reach the bottom of the cathode in this way.

[0099] In the photoelectric conversion element 22 of this embodiment, there is a possibility that holes may be generated by impact ionization at the cathode in contact with the first surface 122, that is, at the edge of the N-type semiconductor region 126. However, as shown in Figure 12, the cathode of the photoelectric conversion element 22 of this embodiment has a constricted portion 142 at the depth where the N-type semiconductor region 126-1 and the N-type semiconductor region 126-2 overlap. As mentioned above, this constricted portion 142 is caused by the fact that the N-type semiconductor region 126-2 has a convex shape and the peak depth of the impurity concentration is located deeper than the bottom surface of the N-type semiconductor region 126-1.

[0100] In a plan view, the areas surrounding the N-type semiconductor regions 126-1 and 126-2 are depleted, generating a lateral electric field. However, at the constricted portion 142 of the cathode, the depleted region appears to intrude into the cathode. Holes generated in the neutral region near the edge of the N-type semiconductor region 126 attempt to diffuse in the direction of the second surface 124. However, at the constricted portion 142, they exit the N-type semiconductor region 126 and are discharged through the P-type semiconductor region 136, which is a hole discharge channel. Therefore, holes rarely reach the bottom of the cathode, i.e., the bottom of the N-type semiconductor region 126, at a depth D3, thus preventing them from being counted as DCR. To further clarify the constricted structure of the cathode, P-type impurities may be introduced in a region approximately the same as the N-type semiconductor region 126 and at approximately the same depth as the constricted portion 142 in a plan view.

[0101] Furthermore, in a plan view, the area surrounding the N-type semiconductor region 126 may be the first surface 122 and its vicinity, as well as the depth D3 and its vicinity, which may be an N-type semiconductor region or a P-type semiconductor region having a P-type impurity concentration of 1 / 2 or less of the peak impurity concentration of the P-type semiconductor region 136.

[0102] Figure 14 is a schematic cross-sectional view showing the structure of a photoelectric conversion element according to a modified example of this embodiment. The photoelectric conversion element shown in Figure 14 has, in addition to the components of the photoelectric conversion element in Figure 12, further N-type semiconductor regions 144 and 146. The N-type semiconductor region 144 is located around the N-type semiconductor region 126 in a plan view, at a depth on and near the first surface 122. The N-type semiconductor region 146 is located around the N-type semiconductor region 126 in a plan view, at a depth greater than the peak depth of the P-type semiconductor region 136. In other words, the N-type semiconductor region 146 is located in a region that overlaps with the P-type semiconductor region 136 in a plan view, such that it has an impurity concentration peak between the P-type semiconductor region 136 and a depth D3.

[0103] In the photoelectric conversion element shown in Figure 14, the N-type semiconductor region 144 functions as an electron discharge channel, and the P-type semiconductor region 136 functions as a potential barrier for electrons. The P-type semiconductor region 136 also functions as a hole discharge channel, but the N-type semiconductor region 146 acts as a potential barrier for holes, effectively preventing holes in the P-type semiconductor region 136 from diffusing to deeper regions. This further enhances the DCR reduction effect. The maximum impurity concentration in the N-type semiconductor regions 144 and 146 is set to a lower concentration than the maximum impurity concentration in the N-type semiconductor region 126.

[0104] Thus, according to this embodiment, since a P-type semiconductor region having an impurity concentration peak at a position shallower than the bottom surface of the cathode is provided around the cathode, noise caused by carriers generated from the carrier generation level within the photoelectric conversion element can be reduced. Furthermore, by providing a constricted portion in the depth direction of the cathode, carriers generated from the carrier generation level can be discharged more effectively, further reducing noise.

[0105] [Third Embodiment] A photodetection system according to a third embodiment of the present invention will be described with reference to Figure 15. Figure 15 is a block diagram showing the schematic configuration of the photodetection system according to this embodiment. In this embodiment, a photodetection sensor to which the photoelectric converter 100 of the first or second embodiment is applied will be described.

[0106] The photoelectric converter 100 described in the first or second embodiment above is applicable to various light detection systems. Examples of applicable light detection systems include imaging systems such as digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in light detection systems. Figure 15 shows a block diagram of a digital still camera as an example of these.

[0107] The photodetection system 200 illustrated in Figure 15 includes a photoelectric converter 201, a lens 202 for forming an optical image of a subject onto the photoelectric converter 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and aperture 204 form an optical system that focuses light onto the photoelectric converter 201. The photoelectric converter 201 is the photoelectric converter 100 described in the first or second embodiment, which converts the optical image formed by the lens 202 into image data.

[0108] The photodetection system 200 also includes a signal processing unit 208 that processes the output signal from the photoelectric converter 201. The signal processing unit 208 generates image data from the digital signal output by the photoelectric converter 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The photoelectric converter 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photon detection element of the photoelectric converter 201 is formed, or it may be formed on a semiconductor layer different from the semiconductor layer on which the photon detection element of the photoelectric converter 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor layer as the photoelectric converter 201.

[0109] The light detection system 200 further includes a buffer memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the light detection system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the light detection system 200 or it may be detachable. In addition, communication between the recording medium control I / F unit 216 and the recording medium 214, and communication from the external I / F unit 212, may be performed wirelessly.

[0110] Furthermore, the photodetection system 200 includes an overall control / calculation unit 218 that controls various calculations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the photoelectric converter 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the photodetection system 200 only needs to have at least the photoelectric converter 201 and the signal processing unit 208 that processes the output signals output from the photoelectric converter 201. The timing generation unit 220 may be mounted on the photoelectric converter 201. In addition, the overall control / calculation unit 218 and the timing generation unit 220 may be configured to perform some or all of the control functions of the photoelectric converter 201.

[0111] The photoelectric converter 201 outputs the imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the photoelectric converter 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal. The signal processing unit 208 may also be configured to perform distance measurement calculations on the signal output from the photoelectric converter 201.

[0112] Thus, according to this embodiment, by configuring a photodetection system using the photoelectric conversion device of the first or second embodiment, a photodetection system capable of acquiring higher quality images can be realized.

[0113] [Fourth Embodiment] A distance image sensor according to a fourth embodiment of the present invention will be described with reference to Figure 16. Figure 16 is a block diagram showing the schematic configuration of the distance image sensor according to this embodiment. In this embodiment, the distance image sensor will be described as an example of a photodetection system to which the photoelectric converter 100 of the first or second embodiment is applied.

[0114] As shown in Figure 16, the distance image sensor 300 according to this embodiment may be configured to include an optical system 302, a photoelectric converter 304, an image processing circuit 306, a monitor 308, and a memory 310. This distance image sensor 300 receives light (modulated light or pulsed light) that is irradiated from a light source device 320 toward the subject 330 and reflected from the surface of the subject 330, and acquires a distance image corresponding to the distance to the subject 330.

[0115] The optical system 302 consists of one or more lenses and has the role of forming an image of the image light (incident light) from the subject 330 onto the light-receiving surface (sensor part) of the photoelectric converter 304.

[0116] The photoelectric converter 304 is the photoelectric converter 100 described in the first or second embodiment, and has the function of generating a distance signal indicating the distance to the subject 330 based on the image light from the subject 330, and supplying the generated distance signal to the image processing circuit 306.

[0117] The image processing circuit 306 has the function of performing image processing to construct a distance image based on the distance signal supplied from the photoelectric converter 304.

[0118] The monitor 308 has the function of displaying the distance image (image data) obtained by the image processing in the image processing circuit 306. The memory 310 also has the function of storing (recording) the distance image (image data) obtained by the image processing in the image processing circuit 306.

[0119] Thus, according to this embodiment, by configuring a distance image sensor using the photoelectric conversion device of the first or second embodiment, it is possible to realize a distance image sensor capable of acquiring distance images containing more accurate distance information, in conjunction with improving the characteristics of the pixel 12.

[0120] [Fifth Embodiment] An endoscopic surgical system according to a fifth embodiment of the present invention will be described with reference to Figure 17. Figure 17 is a schematic diagram showing an example of the configuration of the endoscopic surgical system according to this embodiment. In this embodiment, the endoscopic surgical system will be described as an example of a photodetection system to which the photoelectric converter 100 of the first or second embodiment is applied.

[0121] Figure 17 illustrates a surgeon (physician) 460 performing surgery on a patient 472 on a patient bed 470 using an endoscopic surgical system 400.

[0122] As shown in Figure 17, the endoscopic surgical system 400 of this embodiment may consist of an endoscope 410, surgical instruments 420, and a cart 430 equipped with various devices for endoscopic surgery. The cart 430 may be equipped with a Camera Control Unit (CCU) 432, a light source device 434, an input device 436, a treatment instrument control device 438, a display device 440, and the like.

[0123] The endoscope 410 comprises a barrel 412, the tip of which is inserted into the body cavity of the patient 472 for a predetermined length, and a camera head 414 connected to the base end of the barrel 412. Figure 17 illustrates the endoscope 410 configured as a so-called rigid endoscope having a rigid barrel 412, but the endoscope 410 may also be configured as a so-called flexible endoscope having a flexible barrel. The endoscope 410 is held in a movable state by an arm 416.

[0124] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 412. A light source device 434 is connected to the endoscope 410, and the light generated by the light source device 434 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 412, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 472. The endoscope 410 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0125] The camera head 414 contains an optical system and a photoelectric converter (not shown), and reflected light from the object being observed (observation light) is focused by the optical system into the photoelectric converter. The photoelectric converter converts the observation light into electrical signals and generates an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The photoelectric converter 100 described in the first or second embodiment can be used as the photoelectric converter. The image signal is transmitted to the CCU 432 as RAW data.

[0126] The CCU432 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 410 and the display device 440. Furthermore, the CCU432 receives an image signal from the camera head 414 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0127] The display device 440 displays an image based on an image signal that has been processed by the CCU 432, under control from the CCU 432.

[0128] The light source device 434 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 410 when photographing the surgical area, etc.

[0129] The input device 436 is an input interface for the endoscopic surgical system 400. The user can input various types of information and instructions to the endoscopic surgical system 400 via the input device 436.

[0130] The treatment instrument control device 438 controls the driving of the energy treatment instrument 450 for purposes such as tissue cauterization, incision, or blood vessel sealing.

[0131] The light source device 434 that supplies illumination light to the endoscope 410 when photographing the surgical area can be composed of, for example, an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 434. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 414 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0132] Furthermore, the light source device 434 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 414 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0133] Furthermore, the light source device 434 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue is utilized. Specifically, by irradiating with narrowband light compared to the irradiation light used during normal observation (i.e., white light), predetermined tissues such as blood vessels on the surface of mucosa can be imaged with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light can be irradiated onto body tissue and fluorescence from the body tissue can be observed, or a reagent such as indocyanine green (ICG) can be injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the body tissue to obtain a fluorescence image. The light source device 434 may be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0134] Thus, according to this embodiment, by configuring an endoscopic surgical system using the photoelectric conversion device of the first embodiment, an endoscopic surgical system capable of acquiring higher quality images can be realized.

[0135] [Sixth Embodiment] A photodetection system and mobile body according to the sixth embodiment of the present invention will be described with reference to Figures 18 to 20. Figure 18 is a schematic diagram showing an example of the configuration of a mobile body according to this embodiment. Figure 19 is a block diagram showing a schematic configuration of the photodetection system according to this embodiment. Figure 20 is a flowchart showing the operation of the photodetection system according to this embodiment. In this embodiment, an example of application to an in-vehicle camera is shown as a photodetection system to which the photoelectric converter 100 of the first or second embodiment is applied.

[0136] Figure 18 is a schematic diagram showing an example of the configuration of a mobile body (vehicle system) according to this embodiment. Figure 17 shows the configuration of a vehicle 500 (automobile) as an example of a vehicle system incorporating a photodetection system to which a photoelectric converter according to the first or second embodiment is applied. Figure 18(a) is a schematic front view of the vehicle 500, Figure 18(b) is a schematic top view of the vehicle 500, and Figure 18(c) is a schematic rear view of the vehicle 500. The vehicle 500 is equipped with a pair of photoelectric converters 502 on its front. Here, the photoelectric converters 502 are the photoelectric converters 100 described in the first embodiment. The vehicle 500 also includes an integrated circuit 503, an alarm device 512, and a main control unit 513.

[0137] Figure 19 is a block diagram showing an example configuration of a photodetection system 501 mounted on a vehicle 500. The photodetection system 501 includes a photoelectric converter 502, an image preprocessing unit 515, an integrated circuit 503, and an optical system 514. The photoelectric converter 502 is the photoelectric converter 100 described in the first or second embodiment. The optical system 514 forms an optical image of the subject on the photoelectric converter 502. The photoelectric converter 502 converts the optical image of the subject formed by the optical system 514 into an electrical signal. The image preprocessing unit 515 performs predetermined signal processing on the signal output from the photoelectric converter 502. The functions of the image preprocessing unit 515 may be incorporated into the photoelectric converter 502. The photodetection system 501 is provided with at least two sets of the optical system 514, photoelectric converter 502, and image preprocessing unit 515, and the output from the image preprocessing unit 515 of each set is input to the integrated circuit 503.

[0138] The integrated circuit 503 is an integrated circuit for imaging system applications and includes an image processing unit 504, an optical distance measuring unit 506, a disparity calculation unit 507, an object recognition unit 508, and an anomaly detection unit 509. The image processing unit 504 processes the image signal output from the image preprocessing unit 515. For example, the image processing unit 504 performs image processing such as development and defect correction on the output signal from the image preprocessing unit 515. The image processing unit 504 includes a memory 505 for temporarily holding the image signal. The memory 505 may store, for example, the location of known defective pixels in the photoelectric converter 502.

[0139] The optical distance measuring unit 506 focuses on and measures the distance of the subject. The parallax calculation unit 507 calculates distance information from multiple image data (parallax images) acquired by multiple photoelectric converters 502. Each of the photoelectric converters 502 may be configured to acquire various information such as distance information. The object recognition unit 508 recognizes subjects such as cars, roads, signs, and people. When the anomaly detection unit 509 detects an anomaly in the photoelectric converter 502, it notifies the main control unit 513 of the anomaly.

[0140] The integrated circuit 503 may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination of these.

[0141] The main control unit 513 coordinates and controls the operation of the light detection system 501, vehicle sensor 510, control unit 520, etc. Note that the vehicle 500 does not necessarily have to have the main control unit 513. In this case, the photoelectric converter 502, vehicle sensor 510, and control unit 520 send and receive control signals via a communication network. For example, the CAN standard may be applied to the transmission and reception of these control signals.

[0142] The integrated circuit 503 has the function of receiving control signals from the main control unit 513 or transmitting control signals and set values ​​to the photoelectric converter 502 via its own control unit.

[0143] The light detection system 501 is connected to the vehicle sensor 510 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the external environment and the state of other vehicles and obstacles. The vehicle sensor 510 also serves as a distance information acquisition means for acquiring distance information to objects. Furthermore, the light detection system 501 is connected to the driver assistance control unit 511, which performs various driving assistance functions such as automatic steering, automatic cruising, and collision avoidance. In particular, regarding the collision judgment function, it determines whether a collision with another vehicle or obstacle has occurred and estimates a collision based on the detection results of the light detection system 501 and the vehicle sensor 510. This enables avoidance control when a collision is estimated and activation of safety devices in the event of a collision.

[0144] Furthermore, the light detection system 501 is also connected to a warning device 512 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 513 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 512 warns the user by sounding an alarm, displaying warning information on a display screen such as the car navigation system or instrument panel, or vibrating the seat belt or steering wheel.

[0145] In this embodiment, the light detection system 501 captures images of the area around the vehicle, for example, the front or rear. Figure 18(b) shows an example of the arrangement of the light detection system 501 when it captures images of the area in front of the vehicle.

[0146] As described above, the photoelectric converter 502 is positioned in front of the vehicle 500. Specifically, it is preferable for acquiring distance information between the vehicle 500 and the object being photographed and for determining the possibility of collision if the two photoelectric converters 502 are positioned symmetrically with respect to the axis of symmetry, considering the center line with respect to the vehicle 500's direction of movement or external shape (e.g., vehicle width). Furthermore, it is preferable that the photoelectric converter 502 is positioned so as not to obstruct the driver's field of view when the driver is visually observing the situation outside the vehicle 500 from the driver's seat. It is preferable that the warning device 512 is positioned so as to be easily visible to the driver.

[0147] Next, the fault detection operation of the photoelectric converter 502 in the photodetection system 501 will be explained using Figure 20. The fault detection operation of the photoelectric converter 502 can be performed according to steps S110 to S180 shown in Figure 20.

[0148] Step S110 is a step in which the photoelectric converter 502 is configured for startup. Specifically, settings for the operation of the photoelectric converter 502 are transmitted from outside the photodetection system 501 (e.g., the main control unit 513) or from inside the photodetection system 501, and the imaging operation and fault detection operation of the photoelectric converter 502 are started.

[0149] Next, in step S120, a pixel signal is acquired from the active pixels. Also, in step S130, an output value is acquired from a fault detection pixel provided for fault detection. This fault detection pixel, like the active pixels, is equipped with a photoelectric conversion element. A predetermined voltage is written to this photoelectric conversion element. The fault detection pixel outputs a signal corresponding to the voltage written to this photoelectric conversion element. Note that steps S120 and S130 may be reversed.

[0150] Next, in step S140, a determination is made between the expected output value of the fault-detection pixel and the actual output value from the fault-detection pixel. If the determination in step S140 shows that the expected output value and the actual output value match, the process proceeds to step S150, where it is determined that the imaging operation is functioning normally, and the process moves to step S160. In step S160, the pixel signals of the scanned row are transmitted to the memory 505 for temporary storage. After that, the process returns to step S120 and continues the fault detection operation. On the other hand, if the determination in step S140 shows that the expected output value and the actual output value do not match, the process proceeds to step S170. In step S170, it is determined that there is an abnormality in the imaging operation, and an alarm is sent to the main control unit 513 or the alarm device 512. The alarm device 512 displays that an abnormality has been detected on its display unit. Subsequently, in step S180, the photoelectric converter 502 is stopped, and the operation of the photodetection system 501 is terminated.

[0151] In this embodiment, an example is shown where the flowchart is looped every row, but the flowchart may be looped every multiple rows, or the fault detection operation may be performed every frame. The alarm in step S170 may be notified to an external party via a wireless network.

[0152] Furthermore, although this embodiment describes control to avoid collisions with other vehicles, it can also be applied to control that automatically follows other vehicles or control that automatically drives without deviating from the lane. Moreover, the light detection system 501 can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0153] [Seventh Embodiment] A photodetection system according to the seventh embodiment of the present invention will be described with reference to Figure 21. Figure 21 is a schematic diagram showing an example of the configuration of the photodetection system according to this embodiment. In this embodiment, an example of application to eyeglasses (smart glasses) will be described as a photodetection system to which the photoelectric converter 100 of the first or second embodiment is applied.

[0154] Figure 21(a) shows eyeglasses 600 (smart glasses) relating to one application example. The eyeglasses 600 have lenses 601, a photoelectric converter 602, and a control device 603.

[0155] The photoelectric converter 602 is the photoelectric converter 100 described in the first or second embodiment, and is provided on the lens 601. There may be one or more photoelectric converters 602. Furthermore, when using multiple photoelectric converters 602, multiple types of photoelectric converters 602 may be used in combination. The arrangement position of the photoelectric converter 602 is not limited to that shown in Figure 21(a). A display device (not shown) including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 601.

[0156] The control device 603 functions as a power supply that provides power to the photoelectric converter 602 and the display device. The control device 603 also has a function to control the operation of the photoelectric converter 602 and the display device. The lens 601 is provided with an optical system for focusing light onto the photoelectric converter 602.

[0157] Figure 21(b) shows eyeglasses 610 (smart glasses) relating to another application example. The eyeglasses 610 have lenses 611 and a control device 612. The control device 612 may be equipped with a photoelectric converter (not shown) corresponding to a photoelectric converter 602 and a display device.

[0158] The lens 611 is equipped with a photoelectric converter within the control device 612 and an optical system for projecting light from the display device, thereby projecting an image. The control device 612 functions as a power supply to provide power to the photoelectric converter and the display device, and also has a function to control the operation of the photoelectric converter and the display device.

[0159] The control device 612 may further include a gaze detection unit that detects the wearer's gaze. In this case, the control device 612 can be provided with an infrared light emitter, and the infrared light emitted from the infrared light emitter can be used for gaze detection. Specifically, the infrared light emitter emits infrared light towards the eyeball of the user who is gazing at the displayed image. An image capture unit having a light-receiving element detects the reflected light from the eyeball of the emitted infrared light, thereby obtaining an image of the eyeball. By having a reduction means that reduces the light from the infrared light emitter to the display unit in a planar view, the deterioration of image quality can be reduced.

[0160] The user's gaze towards a displayed image can be detected from an image of the eyeball obtained by imaging with infrared light. Any known method can be applied to gaze detection using the image of the eyeball. As an example, a gaze detection method based on the Purkinje image obtained by the reflection of the irradiated light from the cornea can be used. More specifically, gaze detection processing based on the pupil-corneal reflection method is performed. Using the pupil-corneal reflection method, the user's gaze is detected by calculating a gaze vector representing the orientation (rotation angle) of the eyeball based on the pupil image and the Purkinje image contained in the image of the eyeball.

[0161] The display device of this embodiment may include a photoelectric converter having a light-receiving element and be configured to control the displayed image based on the user's gaze information from the photoelectric converter. Specifically, the display device determines a first field of view area that the user is fixated on and a second field of view area other than the first field of view area, based on the gaze information. The first and second field of view areas may be determined by the control device of the display device or by an external control device. If an external control device determines them, this information is transmitted to the display device via communication. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than the resolution of the first field of view area.

[0162] Furthermore, the display area may have a first display area and a second display area different from the first display area, and may be configured to determine the area with higher priority from the first display area and the second display area based on gaze information. The first display area and the second display area may be determined by the control device of the display device or by an external control device. If the external control device makes the determination, it is communicated to the display device via communication. The resolution of the high-priority area may be controlled to be higher than the resolution of the areas other than the high-priority area. In other words, the resolution of areas with relatively lower priority may be lower.

[0163] AI may be used to determine the first field of view area and the areas with higher priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to the target object at the end of the line of sight from the image of the eye, using the image of the eye and the direction the eye was actually looking in that image as training data. The AI ​​program may be installed in the display device, the photoelectric converter, or an external device. If installed in an external device, it will be transmitted to the display device via communication.

[0164] When display control is based on visual detection, this method is preferably applicable to smart glasses that further include a photoelectric converter for capturing images of the surrounding environment. The smart glasses can display the captured external information in real time.

[0165] [Eighth Embodiment] An apparatus according to the eighth embodiment of the present invention will be described with reference to Figure 22. Figure 22 is a block diagram showing the schematic configuration of the apparatus according to this embodiment.

[0166] Figure 22 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of the photoelectric converter 100 described in the first or second embodiment. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0167] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0168] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0169] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0170] The EQP (Equipment Equipped Device) shown in Figure 22 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the EQP can be transportation equipment (mobile devices) such as vehicles, ships, and aircraft. Additionally, the EQP can be medical equipment such as endoscopes and CT scanners.

[0171] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0172] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0173] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0174] Furthermore, the circuit configuration of the pixel 12 is not limited to the above embodiment. For example, a switch such as a transistor may be provided between the photoelectric conversion element 22 and the quench element 32, or between the photoelectric conversion element 22 and the signal processing unit 30, to control the electrical connection state between them. Alternatively, a switch such as a transistor may be provided between the node to which voltage VH is supplied and the quench element 32, and / or between the node to which voltage VL is supplied and the photoelectric conversion element 22, to control the electrical connection state between them. In addition, multiple photoelectric conversion elements 22 may be provided for a single pixel 12.

[0175] Furthermore, in the circuit configuration of the pixel 12 in the above embodiment, the anode side of the APD is set to a fixed potential and signal charge (electrons) is extracted from the cathode side. However, it is also possible to configure the APD so that the cathode side is set to a fixed potential and signal charge (holes) is extracted from the anode side. In this case, the conductivity type of each semiconductor region described in the above embodiment may be an inverse conductivity type.

[0176] Furthermore, although the above embodiment describes an example of application to a so-called back-illuminated photoelectric converter, it is also possible to apply it to a so-called front-illuminated photoelectric converter. In a front-illuminated photoelectric converter, light incident from the side of the first surface 122 of the semiconductor layer 120 is converted into photoelectric energy in the semiconductor region 140, and the structure of the photoelectric conversion element 22 may be the same as in the above embodiment.

[0177] Furthermore, although the above embodiment shows a configuration in which a counter circuit is used as the processing circuit 36, a TDC (Time to Digital Converter) and memory may be used instead of the counter circuit. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 34 is converted into a digital signal by the TDC. When measuring the timing of the pulse signal, the TDC is supplied with a control pulse pREF (reference signal) from the vertical scanning circuit unit 40 via the control line 14. The TDC uses the control pulse pREF as a reference and acquires the signal as a digital signal when the input timing of the signal output from each pixel 12 is set to a relative time.

[0178] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0179] The above-disclosed embodiment includes the following configuration. (Composition 1) A photoelectric conversion element provided on a semiconductor layer having a first surface and a second surface opposite to the first surface, A first semiconductor region of a first conductivity type is arranged from the first surface to a first depth, A second semiconductor region of a second conductivity type is arranged to surround the first semiconductor region in a plan view, and has a peak in impurity concentration at a second depth between the first surface and the first depth. A third semiconductor region of second conductivity type, which is positioned closer to the second surface than the first semiconductor region and constitutes an avalanche photodiode, is located between it and the first semiconductor region. A photoelectric conversion element characterized by having the following features. (Configuration 2) The width of the first semiconductor region in a plan view at the same depth as the depth to which the second semiconductor region is located is smaller than the maximum width of the first semiconductor region in a plan view. A photoelectric conversion element according to configuration 1, characterized by the above. (Composition 3) The first semiconductor region includes a fourth semiconductor region of the first conductivity type, which is arranged in contact with the first surface and has an impurity concentration peak on the side of the first surface that is deeper than the second depth, and a fifth semiconductor region of the first conductivity type, which has an impurity concentration peak between the second depth and the first depth and is in contact with the fourth semiconductor region at the same depth to which the second semiconductor region is arranged. A photoelectric conversion element according to configuration 1 or 2, characterized by the above. (Composition 4) In a plan view, on the side of the first surface that is greater than the second depth of the region overlapping with the second semiconductor region, the impurity concentration of the second semiconductor region is less than or equal to half the impurity concentration of the second semiconductor region at the second depth. A photoelectric conversion element according to any one of configurations 1 to 3, characterized by the above. (Composition 5) The material further comprises a sixth semiconductor region of the first conductivity type, which is located on the side of the first plane that overlaps with the second semiconductor region in a plan view. A photoelectric conversion element according to any one of configurations 1 to 3, characterized by the above. (Composition 6) The maximum impurity concentration in the sixth semiconductor region is lower than the maximum impurity concentration in the first semiconductor region. A photoelectric conversion element according to configuration 5, characterized by the features described herein. (Composition 7) In a plan view, the impurity concentration of the second semiconductor region at the first depth in the region overlapping with the second semiconductor region is less than or equal to half the impurity concentration of the second semiconductor region at the second depth. A photoelectric conversion element according to any one of configurations 1 to 6, characterized by the above. (Composition 8) In a plan view, the region overlapping with the second semiconductor region further comprises a seventh semiconductor region of the first conductivity type, which is arranged such that there is a peak in impurity concentration between the second semiconductor region and the first depth. A photoelectric conversion element according to any one of configurations 1 to 6, characterized by the above. (Composition 9) The maximum impurity concentration in the seventh semiconductor region is lower than the maximum impurity concentration in the first semiconductor region. A photoelectric conversion element according to configuration 8, characterized by the above. (Composition 10) The impurity concentration in the second semiconductor region at the second depth is lower than the impurity concentration in the first semiconductor region at the second depth. A photoelectric conversion element according to any one of configurations 1 to 9, characterized by the above. (Composition 11) The impurities of the second conductivity type constituting the second semiconductor region are also introduced into the region that overlaps with the first semiconductor region in a plan view. A photoelectric conversion element according to configuration 10, characterized by the above. (Composition 12) It further has an eighth semiconductor region located closer to the second surface than the third semiconductor region, The avalanche photodiode is configured to multiply the signal charge generated in the eighth semiconductor region. A photoelectric conversion element according to any one of configurations 1 to 11, characterized by the above. (Composition 13) During the operation of the avalanche photodiode, the area around the first semiconductor region becomes depleted. A photoelectric conversion element according to any one of configurations 1 to 12, characterized by the above. (Composition 14) In a plan view, a ninth semiconductor region of second conductivity type is arranged to surround the region in which the first semiconductor region, the second semiconductor region and the third semiconductor region are located, and is connected to the third semiconductor region at the periphery of the third semiconductor region. The material further comprises a tenth semiconductor region of second conductivity type, which is provided in contact with the second surface, overlaps with the first semiconductor region, the second semiconductor region and the third semiconductor region in a plan view, and is connected to the ninth semiconductor region. A photoelectric conversion element according to any one of configurations 1 to 12, characterized by the above. (Composition 15) The present invention further comprises a first electrode connected to the first semiconductor region and a second electrode connected to the ninth semiconductor region. A photoelectric conversion element according to configuration 14, characterized by the features described above. (Composition 16) The second semiconductor region is formed by ion implantation. A photoelectric conversion element according to any one of configurations 1 to 15, characterized by the above. (Composition 17) A photoelectric conversion device having multiple pixels arranged in multiple rows and multiple columns, Each of the plurality of pixels includes a photoelectric conversion element according to any one of configurations 1 to 16, and a signal processing circuit that processes the signal output from the photoelectric conversion element. A photoelectric conversion device characterized by the following features. (Composition 18) A first substrate including the semiconductor layer on which each of the plurality of pixels is provided with the photoelectric conversion element, A second substrate on which each of the plurality of pixels is provided with the signal processing circuit, A photoelectric conversion device according to configuration 17, characterized by having the following features. (Composition 19) A photoelectric conversion device according to configuration 17 or 18, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A light detection system characterized by having the following features. (Composition 20) The signal processing device generates a distance image representing distance information to the object based on the signal. The photodetection system according to configuration 19, characterized by the above. (Composition 21) It is a mobile object, A photoelectric conversion device according to configuration 17 or 18, Distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal output from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features. (Composition 22) A photoelectric conversion device according to configuration 17 or 18, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features. [Explanation of Symbols]

[0180] 12... pixels 22... Photoelectric conversion element 100... Photoelectric converter 126,144,146…N-type semiconductor region 128, 130, 132, 136…P-type semiconductor region 156... Anode electrode 158... Cathode electrode

Claims

1. A photoelectric conversion element provided on a semiconductor layer having a first surface and a second surface opposite to the first surface, A first semiconductor region of a first conductivity type is arranged from the first surface to a first depth, A second semiconductor region of a second conductivity type is arranged to surround the first semiconductor region in a plan view, and has a peak in impurity concentration at a second depth between the first surface and the first depth. A third semiconductor region of second conductivity type, which is positioned closer to the second surface than the first semiconductor region and constitutes an avalanche photodiode, is located between it and the first semiconductor region. A photoelectric conversion element characterized by having the following features.

2. The width of the first semiconductor region in a plan view at the same depth as the second semiconductor region is located is smaller than the maximum width of the first semiconductor region in a plan view. The photoelectric conversion element according to claim 1.

3. The first semiconductor region includes a fourth semiconductor region of the first conductivity type, which is arranged in contact with the first surface and has an impurity concentration peak on the side of the first surface that is deeper than the second depth, and a fifth semiconductor region of the first conductivity type, which has an impurity concentration peak between the second depth and the first depth and is in contact with the fourth semiconductor region at the same depth to which the second semiconductor region is arranged. The photoelectric conversion element according to claim 1.

4. In a plan view, on the side of the first surface that is greater than the second depth of the region overlapping with the second semiconductor region, the impurity concentration of the second semiconductor region is less than or equal to half the impurity concentration of the second semiconductor region at the second depth. A photoelectric conversion element according to any one of claims 1 to 3.

5. The semiconductor further comprises a sixth semiconductor region of the first conductivity type, which is located on the side of the first surface that overlaps with the second semiconductor region in a plan view. A photoelectric conversion element according to any one of claims 1 to 3.

6. The maximum impurity concentration in the sixth semiconductor region is lower than the maximum impurity concentration in the first semiconductor region. The photoelectric conversion element according to claim 5, characterized in that it is a photoelectric conversion element.

7. In a plan view, the impurity concentration of the second semiconductor region at the first depth in the region overlapping with the second semiconductor region is 1 / 2 or less of the impurity concentration of the second semiconductor region at the second depth. A photoelectric conversion element according to any one of claims 1 to 3.

8. In a plan view, the region overlapping with the second semiconductor region further comprises a seventh semiconductor region of the first conductivity type, which is arranged such that there is a peak in impurity concentration between the second semiconductor region and the first depth. A photoelectric conversion element according to any one of claims 1 to 3.

9. The maximum impurity concentration in the seventh semiconductor region is lower than the maximum impurity concentration in the first semiconductor region. The photoelectric conversion element according to claim 8.

10. The impurity concentration in the second semiconductor region at the second depth is lower than the impurity concentration in the first semiconductor region at the second depth. A photoelectric conversion element according to any one of claims 1 to 3.

11. The impurities of the second conductivity type constituting the second semiconductor region are also introduced into the region that overlaps with the first semiconductor region in a plan view. The photoelectric conversion element according to claim 10, characterized in that it is a photoelectric conversion element.

12. It further has an eighth semiconductor region located closer to the second surface than the third semiconductor region, The avalanche photodiode is configured to multiply the signal charge generated in the eighth semiconductor region. A photoelectric conversion element according to any one of claims 1 to 3.

13. During the operation of the avalanche photodiode, the area around the first semiconductor region becomes depleted. A photoelectric conversion element according to any one of claims 1 to 3.

14. In a plan view, a ninth semiconductor region of the second conductivity type is arranged to surround the region in which the first semiconductor region, the second semiconductor region and the third semiconductor region are located, and is connected to the third semiconductor region at the periphery of the third semiconductor region. The present invention further comprises a tenth semiconductor region of second conductivity type, which is provided in contact with the second surface, overlaps with the first semiconductor region, the second semiconductor region and the third semiconductor region in a plan view, and is connected to the ninth semiconductor region. A photoelectric conversion element according to any one of claims 1 to 3.

15. The present invention further comprises a first electrode connected to the first semiconductor region and a second electrode connected to the ninth semiconductor region. The photoelectric conversion element according to claim 14.

16. The second semiconductor region is formed by ion implantation. The photoelectric conversion element according to claim 1.

17. A photoelectric conversion device having multiple pixels arranged in multiple rows and multiple columns, Each of the plurality of pixels comprises a photoelectric conversion element according to any one of claims 1 to 3, and a signal processing circuit for processing the signal output from the photoelectric conversion element. A photoelectric conversion device characterized by the following features.

18. A first substrate including the semiconductor layer on which each of the plurality of pixels is provided with the photoelectric conversion element, A second substrate on which each of the plurality of pixels is provided with the signal processing circuit, The photoelectric conversion device according to claim 17, characterized by having the following features.

19. The photoelectric conversion device according to claim 17, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A light detection system characterized by having the following features.

20. The signal processing device generates a distance image representing distance information to the object based on the signal. The light detection system according to claim 19, characterized in that it is as described above.

21. It is a mobile object, The photoelectric conversion device according to claim 17, Distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal output from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

22. The photoelectric conversion device according to claim 17, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features.

Images