Semiconductor equipment

Abstract

To obtain a semiconductor device that allows external adjustment of the error signal output period without increasing the number of external terminals. [Solution] A control semiconductor element 3b controls switching elements 1d to 1f. A capacitance adjustment unit 5 has a capacitor C3 and a conductive part 16c. A molded resin 7 seals the switching elements 1d to 1f, the control semiconductor element 3b, and the capacitance adjustment unit 5. The control semiconductor element 3b has a protection circuit 8 that outputs an error signal when it detects an abnormality in the semiconductor device. The protection circuit 8 is connected to the capacitor C3 via the conductive part 16c, charges the capacitor C3 while outputting the error signal, and stops outputting the error signal and discharges the capacitor C3 when the voltage of the charged capacitor C3 exceeds a threshold. An opening 7a is provided in the molded resin 7. The conductive part 16c of the capacitance adjustment unit 5 is exposed from the molded resin 7 by the opening 7a.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor device in which a switching element and a control semiconductor element for controlling the same are encapsulated with a molding resin, the output period of an error signal can be adjusted by adjusting the capacitance of a protection circuit that outputs the error signal. However, providing a capacitor outside the device increases the area around the device. On the other hand, when a capacitor is built into the device, the capacitance value of the capacitor cannot be adjusted from the outside. In contrast, a semiconductor device has been proposed in which an opening is formed in the molding resin to expose a part of the terminal of the lead frame (see, for example, Patent Document 1). By accommodating a chip capacitor in the opening and connecting one end of the chip capacitor to the exposed terminal, the capacitance can be adjusted from the outside.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional semiconductor device, since the other end of the chip capacitor needs to be drawn out to the outside, there is a problem that the number of external terminals of the semiconductor device increases.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to obtain a semiconductor device capable of adjusting the output period of an error signal from the outside without increasing the number of external terminals.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure comprises a switching element, a control semiconductor element for controlling the switching element, a capacitance adjustment unit having a capacitance and a conductive portion, and a molded resin for sealing the switching element, the control semiconductor element, and the capacitance adjustment unit. The control semiconductor element has a protection circuit that outputs an error signal when it detects an abnormality in the semiconductor device. The protection circuit is connected to the capacitance via the conductive portion, charges the capacitance while outputting the error signal, stops outputting the error signal and discharges the capacitance when the voltage of the charged capacitance exceeds a threshold. An opening is provided in the molded resin, and the conductive portion of the capacitance adjustment unit is exposed from the molded resin through the opening. [Effects of the Invention]

[0007] In this disclosure, the capacitance value of the capacitor connected to the protection circuit can be adjusted by whether or not the conductive portion exposed from the molded resin is cut from the outside. Furthermore, since it is not necessary to house a capacitor in the opening of the molded resin, the number of external terminals does not increase. As a result, the output period of the error signal can be adjusted from the outside without increasing the number of external terminals. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing a semiconductor device according to Embodiment 1. [Figure 2] This is a circuit diagram showing a mechanism according to Embodiment 1. [Figure 3] This is a circuit diagram showing the protection circuit for the second control semiconductor element according to Embodiment 1. [Figure 4] This is a top view showing the capacity adjustment unit according to Embodiment 1. [Figure 5] This is a top view showing the capacity adjustment unit according to Embodiment 1. [Figure 6] This is a cross-sectional view showing the capacity adjustment unit according to Embodiment 1. [Figure 7] This is a plan view showing a semiconductor device according to Embodiment 2. [Figure 8]This is a circuit diagram showing the protection circuit for the second control semiconductor element according to Embodiment 2. [Figure 9] This is a top view showing the capacity adjustment unit according to Embodiment 2. [Figure 10] This is a cross-sectional view showing the capacity adjustment unit according to Embodiment 2. [Figure 11] This is a plan view showing a semiconductor device according to Embodiment 3. [Figure 12] This is a circuit diagram showing the protection circuit for the second control semiconductor element according to Embodiment 3. [Figure 13] This is a top view showing the capacity adjustment unit according to Embodiment 3. [Figure 14] This is a plan view showing a semiconductor device according to Embodiment 4. [Figure 15] This is a cross-sectional view showing the capacity adjustment unit according to Embodiment 4. [Figure 16] This is a plan view showing a semiconductor device according to Embodiment 5. [Modes for carrying out the invention]

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repetition of the description may be omitted.

[0010] Embodiment 1 Figure 1 is a plan view showing a semiconductor device according to Embodiment 1. Figure 2 is a circuit diagram showing a semiconductor device according to Embodiment 1. This semiconductor device is an Intelligent Power Module (IPM) in which switching elements 1a to 1f, diodes 2a to 2f, and first and second control semiconductor elements 3a and 3b are modularized as a single electronic component. The switching elements 1a to 1f and diodes 2a to 2f constitute an inverter that converts DC voltage to three-phase AC.

[0011] The switching elements 1a, 1b, and 1c are the upper arms of a three-phase inverter. The switching elements 1d, 1e, and 1f are the lower arms of the three-phase inverter. The switching elements 1a to 1f are, for example, insulated-gate bipolar transistors (IGBTs), but may also be field-effect transistors. The diodes 2a to 2f are freewheel diodes connected in antiparallel to the switching elements 1a to 1f, respectively. The first control semiconductor element 3a is a high voltage integrated circuit (HVIC) that controls the switching elements 1a, 1b, and 1c. The second control semiconductor element 3b is a low voltage integrated circuit (LVIC) that controls the switching elements 1d, 1e, and 1f.

[0012] Lead terminal 4 P ,4 U ,4 V ,4 W ,4 NU ,4 NV ,4 NW ,4 VNC ,4 VP1 [[ID=2Y]] VUFB ,4 UP ,4 VVFB ,4 VP [[ID=)0]],4 VWFB ,4 WP ,4 VN1 ,4 CFo ,4 UN ,4 VN ',4 WN ,4 FO ,4 CIN ' is a lead frame.

[0013] The switching elements 1a, 1b, and 1c and the diodes 2a, 2b, and 2c are mounted on the die pad portion of the lead terminal 4 P The collectors of the switching elements 1a, 1b, and 1c and the cathodes of the diodes 2a, 2b, and 2c are connected to the lead terminal 4 P The switching element 1d and the diode 2d are connected to the lead terminal 4 UIt is mounted on the die pad portion. The collector of the switching element 1d and the cathode of the diode 2d are connected to lead terminal 4. U It is connected to the switch element 1e and diode 2e at lead terminal 4. V It is mounted on the die pad portion. The collector of switching element 1e and the cathode of diode 2e are connected to terminal V. Switching element 1f and diode 2f are connected to lead terminal 4. W It is mounted on the die pad portion. The collector of switching element 1f and the cathode of diode 2f are connected to lead terminal 4. W Connected.

[0014] The emitter of switching element 1a, the anode of diode 2a, and lead terminal 4 U These are connected by wires in the following order: the emitter of switching element 1b, the anode of diode 2b, and lead terminal 4. V These are connected by wires in the following order: the emitter of switching element 1c, the anode of diode 2c, and lead terminal 4. W These are connected by wires in the following order: the emitter of switching element 1d, the anode of diode 2d, and lead terminal 4. NU These are connected by wires in the following order: the emitter of switching element 1e, the anode of diode 2e, and lead terminal 4. NV These are connected by wires in the following order: the emitter of switching element 1f, the anode of diode 2f, and lead terminal 4. NW They are connected by wires in order.

[0015] The first and second control semiconductor elements 3a and 3b have lead terminals 4 VNCIt is mounted on the die pad portion. The terminals UOUT, VOUT, and WOUT of the first control semiconductor element 3a are connected to the gates of the switching elements 1a, 1b, and 1c, respectively. The terminals UOUT, VOUT, and WOUT of the second control semiconductor element 3b are connected to the gates of the switching elements 1d, 1e, and 1f, respectively. Terminals UOUT, VOUT, and WOUT are terminals that output drive signals for the switching elements. The terminals VUS, VVS, and VWS of the first control semiconductor element 3a are wire-connected to the emitter electrodes of the switching elements 1a, 1b, and 1c, respectively, and lead terminal 4 U ,4 V ,4 W Connected.

[0016] The terminals VCC, VUB, UP, VVB, VP, VWB, WP, and COM of the first control semiconductor element 3a are each lead terminals 4. VP1 ,4 VUFB ,4 UP ,4 VVFB ,4 VP ,4 VWFB ,4 WP ,4 VNC It is connected by wire. Terminal VCC is the power terminal. Terminals VUB, VVB, and VWB are the P-side drive power supply voltage terminals. Terminals UP, VP, and WP are input terminals for receiving control signals from an external logic circuit (not shown). Terminal COM is the ground terminal.

[0017] The terminals VCC, UN, VN, WN, Fo, CFo, VNC, and CIN of the second control semiconductor element 3b are each lead terminals 4. VN1 ,4 UN ,4 VN ,4 WN ,4 Fo ,4 CFo ,4 VNC ,4 CIN It is connected by wires. Terminals UN, VN, and WN are input terminals for receiving control signals from external logic circuits. Terminal Fo is an error signal output terminal that outputs an error signal. Terminal VNC is a grounded terminal. When a signal is input to terminal CIN during short circuit detection, the second control semiconductor element 3b shuts off the switching element of the lower arm.

[0018] Diode 2g is connected to lead terminal 4 VUFB It is mounted on. The cathode of diode 2g is connected to lead terminal 4. VUFB It is connected to lead terminal 4. The anode of diode 2g is connected to lead terminal 4. VP1 It is connected to the wire. Diode 2h is connected to lead terminal 4. VVFB It is mounted on. The cathode of diode 2h is connected to lead terminal 4. VVFB It is connected to lead terminal 4. The anode of diode 2h is connected to lead terminal 4. VP1 It is wired to lead terminal 4. Diode 2i is connected to lead terminal 4. VWFB It is mounted on. The cathode of diode 2i is connected to lead terminal 4. VWFB It is connected to lead terminal 4. The anode of diode 2i is connected to lead terminal 4. VP1 It is connected to the lead terminal 4. The capacitance adjustment unit 5 is connected to the lead terminal 4. CFo ,4 VNC It is located at [location].

[0019] The insulating sheet 6 has lead terminals 4 on which switching elements 1a to 1f and diodes 2a to 2f are placed. P ,4 U ,4 V ,4 W It is attached to the underside of the die pad portion. The molded resin 7 seals the switching elements 1a to 1f, diodes 2a to 2i, first and second control semiconductor elements 3a and 3b, capacitance adjustment section 5, each lead terminal, and each wire. The tip of each lead terminal protrudes from the molded resin 7. Note that lead terminal 4 CFo The tip of the component does not protrude from the molded resin 7. The insulating sheet 6 is exposed from the molded resin 7 on the underside of the device. Heat from the switching elements 1a to 1f and diodes 2a to 2f is dissipated through the insulating sheet 6. An opening 7a is provided in the molded resin 7, and a part of the capacitance adjustment section 5 is exposed from the molded resin 7.

[0020] The first control semiconductor element 3a controls the operation of switching elements 1a, 1b, and 1c based on the outputs from terminals UOUT, VOUT, and WOUT, respectively. The terminals UOUT, VOUT, and WOUT of the second control semiconductor element 3b are connected to the gates of switching elements 1d, 1e, and 1f, respectively. The second control semiconductor element 3b controls the operation of switching elements 1d, 1e, and 1f based on the outputs from terminals UOUT, VOUT, and WOUT, respectively.

[0021] Diodes 2g, 2h, and 2i are boost diodes used to charge externally attached bootstrap capacitors (not shown). Specifically, bootstrap capacitors are connected between terminals VUB and VUS, between terminals VVB and VVS, and between terminals VWB and VWS of the first control semiconductor element 3a, thereby realizing a bootstrap circuit. The bootstrap capacitor connected between terminals VUB and VUS is connected in series with diode 2g and switching element 1d between terminals VP1 and NU of the semiconductor device. When switching element 1d is turned on by a signal from terminal UOUT of the second control semiconductor element 3b, the bootstrap capacitor is charged. The bootstrap capacitors connected between terminals VVB and VVS, and the bootstrap capacitors connected between terminals VWB and VWS are charged in the same way. These bootstrap capacitors supply the power consumption of the first control semiconductor element 3a. By mounting boost diodes inside the device, it becomes unnecessary to mount boost diodes outside the device, thus enabling a reduction in the substrate area of ​​the semiconductor device.

[0022] Figure 3 is a circuit diagram showing the protection circuit of the second control semiconductor element according to Embodiment 1. The second control semiconductor element 3b has a protection circuit 8 that outputs an error signal when it detects an abnormality in the semiconductor device, such as overcurrent, a drop in the control power supply voltage, or overheating. Internal capacitors C1 and C2 of the second control semiconductor element 3b and an external capacitor C3 are connected in parallel between the protection circuit 8 and ground potential. Capacitor C3 is connected to the protection circuit 8 via terminal CFo.

[0023] In the protection circuit 8, the error signal generated by the error signal generation unit 9 is output from terminal Fo via the SR flip-flop 10 and the N-MOS transistor 11. Specifically, when the SR flip-flop 10 receives an error signal from input S, its output Q becomes high, the N-MOS transistor 11 turns ON, and terminal Fo becomes low. At this time, the P-MOS transistor 12 turns OFF, so the current from the constant current source 13 charges capacitors C1, C2, and C3. When the voltage across the charged capacitors C1, C2, and C3 exceeds the threshold of the comparator 14, a reset signal is sent to input R of the SR flip-flop 10, the N-MOS transistor 11 turns OFF, and terminal Fo becomes high. At this time, the P-MOS transistor 12 turns ON, and capacitors C1, C2, and C3 are discharged.

[0024] Therefore, the protection circuit 8 charges capacitors C1, C2, and C3 while outputting an error signal, and when the voltage of the charged capacitors C1, C2, and C3 exceeds a threshold, it stops outputting the error signal and discharges capacitors C1, C2, and C3. The larger the combined capacitance value of capacitors C1, C2, and C3, the longer it takes to reach the threshold of the comparator 14, and thus the longer the error signal output time. To adjust this error signal output time, it is necessary to adjust the capacitance values ​​of the capacitors connected to the protection circuit 8.

[0025] Figures 4 and 5 are top views showing the capacitance adjustment unit according to Embodiment 1. Figure 6 is a cross-sectional view showing the capacitance adjustment unit according to Embodiment 1. In the second control semiconductor element 3b, the protection circuit 8 is connected to terminal Fo and terminal CFo, respectively. The protection circuit 8 is connected to one end of capacitors C1 and C2 via wirings 15a and 15b, respectively. The other ends of capacitors C1 and C2 and terminal VNC are connected to wiring 15c, which is at ground potential. Terminal Fo is connected to lead terminal 4 by wire 16a. Fo It is connected to [this]. Wires 15a, 15b, and 15c are, for example, aluminum wires.

[0026] Lead terminal 4 VNC and lead terminal 4CFo A chip capacitor, capacitor C3, is connected between them. Terminal VNC is connected to lead terminal 4 by wire 16b. VNC It is connected to terminal CFo by wire 16c and lead terminal 4 CFo It is connected to the capacitor C3 via wire 16c. Capacitor C3 and wires 16b and 16c constitute the capacitance adjustment section 5.

[0027] Wires 16b and 16c are exposed from the molded resin 7 through the opening 7a. Therefore, as shown in Figures 5 and 6, wire 16c can be cut by external laser trimming. Alternatively, the wire can be cut with a cutting tool such as scissors. This disconnects the connection between the protection circuit 8 and capacitor C3, reducing the capacitance value of the capacitor connected to the protection circuit 8. In other words, if you want to increase the capacitance value of the capacitor connected to the protection circuit 8, do not cut the wire; if you want to decrease the capacitance value, cut the wire to prevent capacitor C3 from being connected in parallel.

[0028] As described above, in this embodiment, the capacitance value of the capacitor connected to the protection circuit 8 can be adjusted by whether or not the wire 16c exposed from the molded resin 7 is cut from the outside. Also, since it is not necessary to house a capacitor in the opening 7a of the molded resin 7, the number of external terminals does not increase. As a result, the output period of the error signal can be adjusted from the outside without increasing the number of external terminals. In addition, since it is not necessary to add a capacitor around the device to adjust the output period of the error signal, the area around the semiconductor device can also be reduced. When it is desired to connect a capacitance value to the protection circuit 8 that is larger than the capacitance value inside the second control semiconductor element 3b, an external capacitor C3 is used as in this embodiment.

[0029] Embodiment 2 Figure 7 is a plan view showing a semiconductor device according to Embodiment 2. The capacitance adjustment unit 5 is built into the second control semiconductor element 3b.

[0030] Figure 8 is a circuit diagram showing the protection circuit for the second control semiconductor element according to Embodiment 2. Capacitor C3 is not provided outside the second control semiconductor element 3b, and capacitors C1 and C2 inside the second control semiconductor element 3b constitute the capacitance adjustment unit 5.

[0031] Figure 9 is a top view showing the capacitance adjustment unit according to Embodiment 2. Figure 10 is a cross-sectional view showing the capacitance adjustment unit according to Embodiment 2. Capacitors C1 and C2, connected in parallel to each other, constitute the capacitance of the capacitance adjustment unit 5. Wirings 15a and 15b connect capacitors C1 and C2 to the protection circuit 8, respectively.

[0032] Parts of the wiring 15a and 15b are exposed from the molded resin 7 through the opening 7a. Therefore, as shown in Figure 10, one or both of the wiring 15a and 15b can be cut by external laser trimming. This disconnects the connection between the protection circuit 8 and capacitors C1 and C2, reducing the capacitance value of the capacitors connected to the protection circuit 8. In other words, the capacitance value of the capacitors connected to the protection circuit 8 can be adjusted by whether or not to cut the exposed wiring 15a and 15b from the outside. This allows the output period of the error signal to be adjusted externally without increasing the number of external terminals, similar to Embodiment 1. Furthermore, the capacitance value can be finely adjusted by selecting whether or not to disconnect the connection between the multiple capacitors C1 and C2 connected in parallel.

[0033] Embodiment 3 Figure 11 is a plan view showing a semiconductor device according to Embodiment 3. The capacitance adjustment unit 5 is located outside the second control semiconductor element 3b and has lead terminals 4 CFo It is located on top of [something].

[0034] Figure 12 is a circuit diagram showing a protection circuit for a second control semiconductor element according to Embodiment 3. Internal capacitors C1 and C2 of the second control semiconductor element 3b and external capacitors C3 and C4 are connected in parallel between the protection circuit 8 and ground potential. Capacitors C3 and C4 are connected to the protection circuit 8 via terminals CFo.

[0035] Figure 13 is a top view showing the capacitance adjustment unit according to Embodiment 3. The capacitance adjustment unit 5 is a semiconductor chip 18 connected to lead terminal 4 CFo It is provided on top of the semiconductor chip 18. Electrodes 18a, 18b and wiring 18c, 18d are provided on the upper surface of the semiconductor chip 18. The electrodes 18a, 18b and wiring 18c, 18d are made of, for example, aluminum.

[0036] Electrode 18a is connected to lead terminal 4 at ground potential by wire 16b VNC It is connected to the lead terminal 4. Electrode 18b is connected to the bottom electrode of the semiconductor chip 18 via a through-hole. The bottom electrode is connected to lead terminal 4. CFo It is joined by solder or the like. Lead terminal 4 CFo It is connected to terminal CFo of the second control semiconductor element 3b by wire 16c. One end of capacitors C3 and C4 is connected to electrode 18a, and the other end is connected to electrode 18b via wires 18c and 18d, respectively.

[0037] Parts of the wiring 18c and 18d are exposed from the molded resin 7 through the opening 7a. Therefore, one or both of the wiring 18c and 18d can be cut by external laser trimming. The capacitance value of the capacitor connected to the protection circuit 8 can be adjusted by whether or not the exposed wiring 18c and 18d from the molded resin 7 is cut from the outside. This allows the output period of the error signal to be adjusted from the outside without increasing the number of external terminals, similar to Embodiment 1. Furthermore, the capacitance value can be finely adjusted by selecting whether or not to disconnect the connection of the multiple capacitors C3 and C4 that are connected in parallel with each other.

[0038] Embodiment 4 Figure 14 is a plan view showing a semiconductor device according to Embodiment 4. Figure 15 is a cross-sectional view showing a capacitance adjustment unit according to Embodiment 4. A retractable cover 19 is provided on the opening 7a. The cover 19 allows the upper part of the capacitance adjustment unit 5 to be opened only when adjusting the capacitance, and the opening 7a to be closed when not adjusting the capacitance. This prevents foreign matter from entering from outside the device, thereby improving the reliability of the semiconductor device. Other configurations and effects are the same as in Embodiment 1.

[0039] Embodiment 5 Figure 16 is a plan view showing a semiconductor device according to Embodiment 5. Switching elements 1a to 1f are composed of a transistor and a freewheeling diode on a single chip, for example, an RC-IGBT (Reverse Conductive) composed of an IGBT and a freewheeling diode on a single chip. This allows for the omission of diodes 2a to 2f, thereby miniaturizing the semiconductor device and thus reducing the substrate area of ​​the semiconductor device. Other configurations and effects are the same as in Embodiment 1.

[0040] Furthermore, the switching elements 1a to 1f and diodes 2a to 2f are not limited to those made of silicon, but may also be made of wide-bandgap semiconductors with a larger bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. Semiconductor chips made of such wide-bandgap semiconductors can be miniaturized because they have high voltage resistance and current density. By using these miniaturized semiconductor chips, semiconductor devices incorporating these chips can also be miniaturized and highly integrated. In addition, because semiconductor chips have high heat resistance, the heat sink fins can be miniaturized and the water-cooled section can be air-cooled, allowing for further miniaturization of the semiconductor device. Moreover, because semiconductor chips have low power loss and high efficiency, the semiconductor device can be made more efficient.

[0041] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. Various aspects of this disclosure are described below as appendices. (Note 1) Switching element and A control semiconductor element that controls the switching element, A capacitance adjustment unit having capacitance and a conductive part, The system comprises the switching element, the control semiconductor element, and a molding resin that seals the capacitance adjustment section. The control semiconductor element has a protection circuit that outputs an error signal when an abnormality in the semiconductor device is detected. The protection circuit is connected to the capacitor via the conductive part, charges the capacitor while outputting the error signal, and stops outputting the error signal and discharges the capacitor when the voltage of the charged capacitor exceeds a threshold. An opening is provided in the aforementioned mold resin. A semiconductor device characterized in that the conductive portion of the capacitance adjustment section is exposed from the molded resin through the opening. (Note 2) The aforementioned capacitance has a chip capacitor, The conductive part has a wire connecting the chip capacitor and the protection circuit. The semiconductor device according to Appendix 1, characterized in that the wire is exposed from the mold resin through the opening. (Note 3) The aforementioned capacitance has a plurality of capacitors connected in parallel with each other. The conductive part has a plurality of wires that connect the plurality of capacitors and the protection circuit, respectively. The semiconductor device according to Appendix 1, characterized in that the plurality of wirings are exposed from the molded resin through the opening. (Note 4) The semiconductor device according to Appendix 3, characterized in that the capacitance adjustment unit is built into the control semiconductor element. (Note 5) The semiconductor device according to Appendix 3, characterized in that the capacitance adjustment unit is provided outside the control semiconductor element and on a lead terminal. (Note 6) The semiconductor device according to any one of the appendices 1 to 5, further comprising a lid that can be opened and closed provided in the aforementioned opening. (Note 7) The semiconductor device according to any one of the appendices 1 to 6, characterized in that the switching element comprises a transistor and a freewheeling diode on a single chip. (Note 8) The semiconductor device according to any one of the appendices 1 to 7, characterized in that the switching element is formed of a wide-bandgap semiconductor. [Explanation of Symbols]

[0042] 1a~1f Switching elements, 3b Second control semiconductor element, 4 CFo Lead terminals, 5 Capacitance adjustment section, 7 Molded resin, 7a Opening, 8 Protection circuit, 15a, 15b, 18c, 18d Wiring, 16b, 16c Wire, 19 Cover, C1, C2, C3, C4 Capacitors

Claims

1. Switching element and A control semiconductor element that controls the switching element, A capacitance adjustment unit having capacitance and a conductive part, The system comprises the switching element, the control semiconductor element, and a molding resin that seals the capacitance adjustment section. The control semiconductor element has a protection circuit that outputs an error signal when an abnormality in the semiconductor device is detected. The protection circuit is connected to the capacitor via the conductive part, charges the capacitor while outputting the error signal, and stops outputting the error signal and discharges the capacitor when the voltage of the charged capacitor exceeds a threshold. An opening is provided in the aforementioned mold resin. A semiconductor device characterized in that the conductive portion of the capacitance adjustment section is exposed from the molded resin through the opening.

2. The aforementioned capacitance has a chip capacitor, The conductive part has a wire connecting the chip capacitor and the protection circuit. The semiconductor device according to claim 1, characterized in that the wire is exposed from the mold resin through the opening.

3. The aforementioned capacitance has a plurality of capacitors connected in parallel with each other. The conductive part has a plurality of wires that connect the plurality of capacitors and the protection circuit, respectively. The semiconductor device according to claim 1, characterized in that the plurality of wirings are exposed from the molded resin through the opening.

4. The semiconductor device according to claim 3, characterized in that the capacitance adjustment unit is built into the control semiconductor element.

5. The semiconductor device according to claim 3, characterized in that the capacitance adjustment unit is provided outside the control semiconductor element on a lead terminal.

6. The semiconductor device according to any one of claims 1 to 5, further comprising a lid that can be opened and closed provided in the opening.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that the switching element comprises a transistor and a freewheeling diode on a single chip.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that the switching element is formed of a wide-bandgap semiconductor.

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