Semiconductor equipment

Abstract

This technology reduces power consumption while detecting semiconductor device degradation with high accuracy using HCI (Hyper-Compression Identification). [Solution] The semiconductor device comprises an oscillator circuit including a plurality of logic gate groups connected in series, a frequency counter for measuring the oscillation frequency of the oscillator circuit, and a comparator for comparing the oscillation frequency of the oscillator circuit measured by the frequency counter with a reference value. Each of the plurality of logic gate groups is composed of a transistor and includes a first to third logic gate connected in series with each other. The first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates. The driving forces of the first to third logic gates are the same.

Description

Technical Field

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[0001] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device that detects deterioration of a semiconductor element due to hot carriers.

Background Art

[0002] In recent years, semiconductor devices have been highly integrated with the development of fine processing process technology. On the other hand, as semiconductor devices are miniaturized, the problem of reducing the power supply voltage of the power supply voltage system has become an issue. Therefore, the electric field strength of internal elements constituting semiconductor devices tends to increase. In particular, in a MOS (Metal-Oxide-Semiconductor) transistor, a hot carrier phenomenon (hereinafter also referred to as HCI) in which hot carriers generated by an increase in the electric field strength are injected into the gate insulating film occurs. Due to this hot carrier phenomenon, there has been a problem that the threshold voltage of the MOS transistor deteriorates (increases).

[0003] In this regard, for example, Japanese Unexamined Patent Application Publication No. 2017-34207 (Patent Document 1) proposes a method for detecting deterioration of a semiconductor element due to HCI of a semiconductor element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] On the other hand, in the above method, a method of combining an inverter with a large driving force and an inverter with a small driving force has been proposed, but the inverter with a large driving force has a large power consumption.

[0006] <00oo031>This disclosure was made to solve the above-mentioned problems, specifically to detect semiconductor device degradation using highly accurate HCI while reducing power consumption.

[0007] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0008] A semiconductor device according to this disclosure comprises an oscillator circuit including a plurality of logic gate groups connected in series, a frequency counter for measuring the oscillation frequency of the oscillator circuit, and a comparator for comparing the oscillation frequency of the oscillator circuit measured by the frequency counter with a reference value. Each of the plurality of logic gate groups is composed of a transistor and includes a first to third logic gate connected in series with respect to each other. The first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates. The driving forces of the first to third logic gates are the same.

[0009] A semiconductor device according to another aspect of the present disclosure includes a first oscillator circuit capable of accelerating the degradation of a transistor due to hot carrier injection by oscillation operation, a first frequency counter for measuring the oscillation frequency of the first oscillator circuit, and a first calculation circuit for calculating the difference between the oscillation frequency of the first oscillator circuit measured by the first frequency counter and a first reference value. Furthermore, the semiconductor device includes a second oscillator circuit capable of suppressing the degradation of a transistor due to hot carrier injection by oscillation operation, a second frequency counter for measuring the oscillation frequency of the second oscillator circuit, and a second calculation circuit for calculating the difference between the oscillation frequency of the second oscillator circuit measured by the second frequency counter and a second reference. Furthermore, the semiconductor device includes a detection circuit for detecting degradation due to hot carrier injection based on the difference calculated by the first and second calculation circuits. [Effects of the Invention]

[0010] According to one embodiment of a semiconductor device, it is possible to detect the HCI degradation of a semiconductor element with high accuracy while reducing power consumption. [Brief explanation of the drawing]

[0011] [Figure 1] This figure illustrates the configuration of a semiconductor device 1 according to Embodiment 1 of this disclosure. [Figure 2] This figure shows the change in the oscillation frequency of an oscillation circuit according to Embodiment 1 of this disclosure over time. [Figure 3] This figure shows an example configuration of the oscillation circuit 202 (ring oscillator) according to Embodiment 1. [Figure 4] This diagram illustrates the configuration of a NAND gate NAD according to Embodiment 1. [Figure 5] This figure illustrates the time-dependent changes in the voltage at each node of the oscillator circuit 202 according to Embodiment 1. [Figure 6] This figure shows an example configuration of the oscillator circuit 205 according to Embodiment 2. [Figure 7] This figure illustrates a NOR gate NR according to Embodiment 2. [Figure 8] This figure shows an example configuration of an oscillator circuit 208 according to a modified example of Embodiment 2. [Figure 9] This figure illustrates a modified example of the NAND gate ND according to Embodiment 2. [Figure 10] This figure shows an example configuration of the oscillator circuit 210 according to Embodiment 3. [Figure 11] This figure illustrates a NOR gate NRD according to Embodiment 3. [Figure 12] This diagram illustrates the difference in lifetimes of P-channel MOS transistors PT1 and PT2 due to HCI (Hyperconductive Computation). [Figure 13] This figure shows an example configuration of an oscillator circuit 212 according to a modified example of Embodiment 3. [Figure 14] This figure illustrates a modified example of Embodiment 3 of a NAND gate NDD. [Figure 15]It is a diagram showing a configuration example of the oscillation circuit 214 according to Embodiment 4. [Figure 16] It is a diagram for explaining the circuit configuration (non-oscillation operation) of the composite gate G according to Embodiment 4. [Figure 17] It is a diagram for explaining the circuit configuration (oscillation operation) of the composite gate G according to Embodiment 4. [Figure 18] It is a diagram for explaining the cause of frequency deviation of the oscillation circuit according to the comparative example. [Figure 19] It is a diagram for explaining the cause of frequency deviation of the oscillation circuit 214 according to Embodiment 4. [Figure 20] It is a diagram for explaining a method of detecting HCI degradation based on the combination of oscillation circuits according to Embodiment 4. [Figure 21] It is a diagram for explaining a method of detecting HCI degradation based on the combination of oscillation circuits according to a modification of Embodiment 4.

Mode for Carrying Out the Invention

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0013] [Embodiment 1] FIG. 1 is a diagram for explaining the configuration of the semiconductor device 1 according to Embodiment 1 of the present disclosure. Referring to FIG. 1, the semiconductor device 1 includes a logic circuit 100, a control circuit 500, and a detection circuit 10. The logic circuit 100 executes a predetermined logical operation according to an instruction from the control circuit 500. The control circuit 500 controls the entire semiconductor device 1. The detection circuit 10 detects degradation due to HCI of the semiconductor elements of the semiconductor device 1.

[0014] The detection circuit 10 includes an oscillation circuit 200, a dummy oscillation circuit 200#, a counter 300, and a comparator 400.

[0015] In this example, the oscillator circuit 200 will be described as using a ring oscillator as an example. The oscillator circuit 200 oscillates by being composed of an odd number of logic gates. The oscillator circuit 200 performs oscillation operations according to instructions from the control circuit 500. Based on the oscillation signal from the oscillator circuit 200, for example, the clock operation of the semiconductor device 1 is performed. The control circuit 500 can instruct the oscillator circuit 200 to oscillate or to stop the oscillation operation. The counter 300 counts the input of the oscillation signal from the oscillator circuit 200 and measures the oscillation frequency of the oscillator circuit 200. The measured oscillation frequency is output to the comparator 400.

[0016] The dummy oscillator circuit 200# has the same circuit configuration as the oscillator circuit 200, and under normal circumstances, it does not oscillate according to the instructions of the control circuit 500, but oscillates when detection (measurement) occurs. Since the dummy oscillator circuit 200# does not oscillate under normal circumstances, the degradation of the semiconductor elements is suppressed. The counter 300 counts the input of the oscillation signal from the oscillator circuit 200# and measures the oscillation frequency of the oscillator circuit 200#. The measured oscillation frequency is output to the comparator 400.

[0017] The comparator 400 compares the oscillation frequency of the oscillator circuit 200 output by the counter 300 with the oscillation frequency of the dummy oscillator circuit 200# output by the counter 300. When the difference between the oscillation frequency of the oscillator circuit 200 and the oscillation frequency of oscillator circuit 200# reaches a predetermined difference, the comparator 400 outputs the result to the control circuit 500. The control circuit 500 determines the degradation life of the semiconductor device 1 based on the result from the comparator 400. In this example, a method has been described in which a dummy oscillator circuit 200# is provided to measure a reference value of the oscillation frequency to be compared. This makes it possible to determine the degradation life of the semiconductor device 1 based on the oscillation frequency of the oscillator circuit 200, taking into account the deviation of the oscillation frequency (reference value) due to environmental fluctuations of the dummy oscillator circuit 200#. However, this is not limited to this, and for example, an initial value (predetermined value) of the oscillation frequency of the oscillator circuit 200 may be stored in the comparator 400 in advance without providing a dummy oscillator circuit 200#, and a method of comparing with this predetermined value may be adopted. For example, initial values ​​may be stored in non-volatile memory (not shown).

[0018] The control circuit 500 is connected to the logic circuit 100, the oscillator circuit 200, and the dummy oscillator circuit 200#. The control circuit 500 controls the oscillation of the oscillator circuits 200 and 200#. The control circuit 500 outputs an alarm to a display device (not shown) or the like that indicates that the semiconductor device 1 has reached its degradation lifespan, based on a signal from the comparator 400 (a signal indicating that the oscillation frequency of the oscillator circuit 200 is lower than a reference value by a predetermined difference or more). In another context, the control circuit 500 may be included in the detection circuit 10 or the logic circuit 100, etc.

[0019] As the oscillator circuit 200 operates, the transistors constituting the oscillator circuit 200 degrade due to HCI, and their operating speed slows down. Therefore, the oscillation frequency of the oscillator circuit 200 decreases.

[0020] Figure 2 is a diagram showing the change in the oscillation frequency of an oscillator circuit according to Embodiment 1 of this disclosure over time. Referring to Figure 2, the oscillation frequency of the oscillator circuit 200 decreases while the circuit is operating. Therefore, the detection circuit 10 can determine the degree of degradation of the transistors constituting the oscillator circuit 200 by comparing the oscillation frequency of the oscillator circuit 200 with a reference value. For example, the reference value corresponds to the oscillation frequency of the dummy oscillator circuit 200#.

[0021] The detection circuit 10 may be configured so that the oscillation circuit 200 operates only while the logic circuit 100 is operating, thereby allowing the degree of degradation of the transistors constituting the logic circuit 100 to be determined.

[0022] Figure 3 shows an example configuration of an oscillator circuit 202 (ring oscillator) according to Embodiment 1. Referring to Figure 3, the oscillator circuit 202 according to Embodiment 1 includes a plurality of logic gate groups. Specifically, the oscillator circuit 202 includes a NAND gate 10 and logic gate groups R31 to R3m. The NAND gate 10 and logic gate groups R31 to R3m are connected in series.

[0023] Each of the logic gate groups R31 to R3m consists of a transistor and includes a first to third logic gate connected in series with each other. Furthermore, the first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates, and the driving forces of the first to third logic gates are set to be the same.

[0024] In this example, the logic gate group R31 includes inverters G31 to G33 with the same driving force. Inverter G32 and n 4-input NAND gates NAD1 to NADn are connected in parallel.

[0025] The output from the preceding inverter is input to three of the four input NAND gate terminals, NAD1, ..., NADn. The remaining input terminal is connected to a fixed voltage VSS.

[0026] The output of inverter G31 is connected to inverter G32 and the 4-input NAND gates NAD1 to NADn. Therefore, the fan-out number of inverter G31 is n+1. "Fan-out number" refers to the number of logic gates to which the output of a logic gate is connected. The output of inverter G32 is connected to inverter G33. Therefore, the fan-out number of inverter G32 is 1. The fan-out number of inverter G33 is 1.

[0027] The four input NAND gates NAD0...NADn have their outputs open. The reason for connecting these NAND gates in parallel is to increase the total capacitance of the output nodes of inverter G31. Therefore, the outputs of these NAND gates may be open or connected to the subsequent inverter G33.

[0028] The output capacity of inverter G31 increases in proportion to the number of logic gates connected in parallel.

[0029] The configuration of the other logic gate groups R32 to R3m is the same as that of logic gate group R31, so a detailed explanation will not be repeated.

[0030] Figure 4 is a diagram illustrating the configuration of a NAND gate NAD according to Embodiment 1. Referring to Figure 4, the NAND gate NAD includes P-channel MOS transistors PT3 to PT6 and N-channel MOS transistors NT3 to NT6. The P-channel MOS transistors PT3 to PT6 are connected in parallel to each other between the power supply voltage VDD and the output node. The N-channel MOS transistors NT3 to NT6 are connected in series between the output node and the fixed voltage VSS. The P-channel MOS transistor PT3 and the N-channel MOS transistor NT3 are connected to node B1. The P-channel MOS transistor PT4 and the N-channel MOS transistor NT4 are connected to node B2. The P-channel MOS transistor PT5 and the N-channel MOS transistor NT5 are connected to node B3. The P-channel MOS transistor PT6 and the N-channel MOS transistor NT6 are connected to node B4.

[0031] In this example, nodes B1 to B3 are connected to the output of the preceding inverter G. On the other hand, node B4 is connected to the fixed voltage VSS.

[0032] Figure 5 illustrates the time-dependent changes in the node voltages of the oscillator circuit 202 according to Embodiment 1. Referring to Figure 5, in this example, the node voltages V23, which is the input node of inverter G31 of the logic gate group R31, V24, which is the input node of inverter G32, V25, which is the input node of inverter G33, and V26, which is the output node of inverter G33 are shown.

[0033] At time T21, upon receiving the output signal from the NAND gate 10, the node voltage V23 begins to switch (rise) from 0 (Low) to V23_MAX (High). After a predetermined time has elapsed, at time T28, upon receiving the output signal from the NAND gate 10, the node voltage V23 begins to switch (fall) from High to Low.

[0034] The rise or fall of node voltage V23 is steep. This is because the fan-out number of NAND gate 10 is 1.

[0035] At time T22, the node voltage V24 begins to fall from V24_MAX (High) to 0 (Low). After a predetermined time has elapsed, at time T29, the node voltage V24 begins to rise from Low to High.

[0036] The rise and fall of node voltage V24 are the gentlest. This is because inverter G31 has a fan-out of n+1, resulting in a large load capacity.

[0037] At time T22, the output node voltage of inverter G31 is at its maximum value, V24_MAX. On the other hand, the input node voltage V23_T22 of inverter G31 is close to V23_MAX. The node voltage V23_T22 is high. This is because the rise of node voltage V23 is steep. Therefore, at time T22, the HCI degradation of inverter G31 is significant.

[0038] At time T23, the input node voltage of inverter G23 is at its maximum value, V23_MAX. On the other hand, the output node voltage V24_T23 of inverter G23 is close to V24_MAX. The node voltage V24_T23 is high because the falling slope of node voltage V24 is gentle. Therefore, at time T23, the HCI degradation of inverter G31 is large. In other words, the period from time T22 to T23 is a time of large HCI degradation for inverter G31.

[0039] A characteristic of the transistors that make up a logic gate is that the output node voltage of the logic gate is affected by the input node voltage. For example, if the time change (slope) of the input node voltage of the logic gate is gradual, the slope of the output node voltage will also be somewhat gradual.

[0040] At time T24, the node voltage V25 begins to rise from 0 (Low) to V25_MAX (High). The node voltage V25 reaches V25_MAX (High) at time T27. After a predetermined time has elapsed, at time T30, the node voltage V25 begins to fall from High to Low. In this case, the node voltage V25 is affected by the gradual change (slope) of the input node voltage, and its slope is somewhat gentle.

[0041] At time T25, the node voltage V26 begins to fall from V26_MAX (High) to 0 (Low). The node voltage V26 becomes 0 at time T26. After a predetermined time has elapsed, at time T31, the node voltage V26 begins to rise from Low to High.

[0042] The fall or rise of node voltage V26 is steep. This is because the fan-out of inverter G33 is 1. Here, node voltage V25 is affected by the time variation (slope) of node voltage V24, but node voltage V26 is no longer affected and has the same time variation (slope) as node voltage V23. The following configurations are similar.

[0043] In other words, the first fan-out number of the first logic gate in each logic gate group is greater than the second fan-out numbers of the second and third logic gates. Furthermore, the driving forces of the first to third logic gates are set to be the same as those of the first to third logic gates. With this configuration, the oscillator circuit 202 has high sensitivity to HCI degradation for each switching operation (time domain B). By using an oscillator circuit 202 according to this configuration, it is possible to detect the HCI degradation of the transistors constituting the logic circuit 100 with high sensitivity.

[0044] In contrast to conventional methods that combine inverters with high and low driving forces, the driving forces of the logic gates (inverters) in the oscillation circuit 202 according to Embodiment 1 are set to be the same, resulting in lower power consumption. Therefore, it is possible to detect semiconductor element degradation with high accuracy using HCI while reducing power consumption.

[0045] Furthermore, the oscillator circuit 202 is equipped with a selector SEL. The output of selector SEL is connected to one of the inputs of NAND gate 10. Selector SEL receives the outputs of logic gate group R32 and logic gate group R3m, and switches the inputs using the control signal SL to output the result.

[0046] When selector SEL selects logic gate group R3m, the oscillator circuit 202 oscillates using NAND gate 10 and logic gate groups R31 to R3m. When selector SEL selects logic gate group R32, the number of logic gates used for oscillation is reduced compared to when selector SEL selects logic gate group R3m. The oscillation period of a ring oscillator type oscillator circuit is determined by the delay time of each oscillating logic gate and the number of stages of oscillating logic gates. Therefore, when selector SEL selects logic gate group R32, the total delay time is reduced, causing the oscillator circuit to oscillate at high speed. Consequently, the number of switching cycles per unit time for each inverter increases, and the sensitivity of the oscillator circuit 205 to HCI degradation is higher when fewer logic gates are used for oscillation.

[0047] The HCI degradation of each inverter constituting the oscillation circuit 202 varies even among inverters with equal driving force. Therefore, when detecting the HCI degradation of the oscillation circuit 202, the more inverters used for oscillation, the more the oscillation circuit 202 can suppress the influence of HCI degradation variations between each inverter. Thus, when detecting the HCI degradation of the oscillation circuit 202, the selector SEL selects the logic gate group R3m and oscillates using all the logic gates constituting the oscillation circuit 202.

[0048] An oscillator circuit with an adjustable oscillation stage configuration can switch between a stress application mode and an HCI degradation detection mode. Specifically, the selector SEL switches between the stress application mode and the HCI degradation detection mode according to the control signal SL.

[0049] The stress application mode is a mode that increases HCI degradation sensitivity by using short-stage oscillation. The HCI degradation detection mode is a mode that detects HCI degradation by suppressing the effects of HCI degradation variations through long-stage oscillation.

[0050] The number of NAND gates connected in parallel to the logic gate group R31, R32, ..., R3m may be the same or different.

[0051] Furthermore, while we have described a 4-input NAND gate NAD0...NADn as an example, it is not limited to 4 inputs; it can be changed to a 2-input or 3-input NAND gate. Also, it is not limited to NAND gates; a NOR gate with one input terminal connected to the power supply voltage VDD can be used.

[0052] For example, by using an oscillator circuit 202 that conforms to this configuration, it is possible to detect the HCI degradation of the transistors constituting the logic circuit 100 with high sensitivity. On the other hand, the degradation of semiconductor elements is affected not only by HCI but also by BTI (Bias Temperature Instability).

[0053] [Embodiment 2] Figure 6 shows an example configuration of an oscillator circuit 205 according to Embodiment 2. Referring to Figure 6, the oscillator circuit 205 includes a plurality of logic gate groups. Specifically, the oscillator circuit 205 includes a NOR gate 11 and logic gate groups R41 to R4m. The NOR gate 11 and logic gate groups R41 to R4m are connected in series. Each of the logic gate groups R41 to R4m is composed of a transistor and includes a first to third logic gate connected in series with each other. Furthermore, the first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates, and the driving forces of the first to third logic gates are set to be the same with respect to each other.

[0054] In this example, the logic gate group R41 includes a NOR gate NR with the same driving force. Furthermore, the NOR gate NR1 and n 4-input NAND gates are connected in parallel. Specifically, the NOR gate NR1 and n 4-input NAND gates are connected in parallel, as explained in Figure 3.

[0055] The four-input NAND gates NAD1, ..., NADn have their outputs open. The reason for connecting these NAND gates in parallel is to increase the total capacitance of the output side of the NOR gate NR0. Therefore, the outputs of these NAND gates may be open or connected to the subsequent NOR gate NR2.

[0056] The fan-out number for NOR gate NR0 is n+1. The fan-out number for NOR gate NR1 is 1. The fan-out number for NOR gate NR2 is 1.

[0057] The configuration of the other logic gate groups R42 to R4m is the same as that of logic gate group R41, so a detailed explanation will not be repeated.

[0058] Therefore, in the oscillator circuit 205 according to Embodiment 2, similar to the oscillator circuit 202 according to Embodiment 1, the first fan-out number of the first logic gate in each logic gate group is greater than the second fan-out numbers of the second and third logic gates. Furthermore, the driving forces of the first to third logic gates are set to be the same. With this configuration, the oscillator circuit 205 has high sensitivity to HCI degradation for each switching operation (time domain B). By using the oscillator circuit 205 according to this configuration, it is possible to detect the HCI degradation of the transistors constituting the logic circuit 100 with high sensitivity.

[0059] Figure 7 illustrates a NOR gate NR according to Embodiment 2. Referring to Figure 7, the configuration of the NOR gate NR is shown. The NOR gate NR includes P-channel MOS transistors PT0 and PT1 and N-channel MOS transistors NT0 and NT1. The P-channel MOS transistors PT0 and PT1 are connected in series between the power supply voltage VDD and the output node. The N-channel MOS transistors NT0 and NT1 are connected in parallel to each other between the output node and the fixed voltage VSS. The P-channel MOS transistors PT0 and N-channel MOS transistors NT1 are connected to node A2. The P-channel MOS transistors PT1 and N-channel MOS transistors NT0 are connected to node A1.

[0060] In this example, node A2 receives the input of the control signal mod. The control signal mod is set to "0" ("L" level) when the oscillator circuit is operating (oscillating operation) and to "1" ("H" level) when the oscillator circuit is not operating (non-oscillating operation). The control signal mod is output from the control circuit 500. When the control signal mod is "1", the P-channel MOS transistor PT1 is set to a non-conducting state. The transistors that perform the switching operation are the P-channel MOS transistor PT1 and the N-channel MOS transistor NT0. When the oscillator circuit 208 is not oscillating, the P-channel MOS transistor PT0 is in a non-conducting state, so the voltage between the source and gate of the P-channel MOS transistor PT1 is extremely small compared to the power supply voltage VDD. Therefore, it is possible to suppress the effect of BTI (Bias Temperature Instability) on the P-channel MOS transistor PT1. Also, when the control signal mod is "1", the output signal of the NOR gate NR0 becomes "0", and that signal is connected to node A1 of the next NOR gate, so there is no effect of BTI on the N-channel MOS transistor NT0.

[0061] Therefore, in detecting HCI degradation using the oscillator circuit 205 according to Embodiment 2 of this disclosure, the influence of degradation due to BTI of the P-channel MOS transistor is suppressed in particular, enabling highly accurate detection of HCI degradation.

[0062] Figure 8 shows an example configuration of an oscillator circuit 208 according to a modified example of Embodiment 2. Referring to Figure 8, the oscillator circuit 208 includes a plurality of logic gate groups. Specifically, the oscillator circuit 208 includes a NAND gate 10 and logic gate groups R51 to R5m. The NAND gate 10 and logic gate groups R51 to R5m are connected in series. Each of the logic gate groups R51 to R5m is composed of a transistor and includes a first to third logic gate connected in series with each other. Furthermore, the first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates, and the driving forces of the first to third logic gates are set to be the same as each other.

[0063] In this example, the logic gate group R51 to R5m includes NAND gate ND with the same driving force. Furthermore, NAND gate ND1 and n 4-input NAND gates are connected in parallel.

[0064] The four-input NAND gates NAD1, ..., NADn that constitute the logic gate group R51 have their output sides open. The reason for connecting these NAND gates in parallel is to increase the total capacitance of the output side of the NOR gate NR0. Therefore, the output sides of these NAND gates may be open or connected to the subsequent NAND gate ND2.

[0065] The fan-out number for NAND gate ND0 is n+1. The fan-out number for NAND gate ND1 is 1. The fan-out number for NAND gate ND2 is 1.

[0066] The configuration of the other logic gate groups R52 to R5m is the same as that of logic gate group R51, so a detailed explanation will not be repeated.

[0067] Therefore, in the oscillator circuit 208 according to the modified embodiment 2, similar to the oscillator circuit 205 according to embodiment 2, the first fan-out number of the first logic gate in each logic gate group is greater than the second fan-out numbers of the second and third logic gates. Furthermore, the driving forces of the first to third logic gates are set to be the same as those of the first to third logic gates. With this configuration, the oscillator circuit 208 has high sensitivity to HCI degradation for each switching operation (time domain B). By using the oscillator circuit 208 according to this configuration, it is possible to detect the HCI degradation of the transistors constituting the logic circuit 100 with high sensitivity.

[0068] Figure 9 illustrates a NAND gate ND according to a modification of Embodiment 2. Referring to Figure 9, the NAND gate ND includes P-channel MOS transistors PT10, PT11 and N-channel MOS transistors NT10, NT11. The P-channel MOS transistors PT10, PT11 are connected in parallel to each other between the power supply voltage VDD and the output node. The N-channel MOS transistors NT10, NT11 are connected in series between the output node and the fixed voltage VSS. The P-channel MOS transistors PT10 and N-channel MOS transistors NT10 are connected to node A1. The P-channel MOS transistors PT11 and N-channel MOS transistors NT11 are connected to node B2.

[0069] In this example, node A2 receives the input of the control signal modb. The control signal modb is the inverse signal of the control signal mod, and is set to "1" ("H" level) when the oscillator circuit is operating (oscillating operation) and to "0" ("L" level) when the oscillator circuit is not operating (non-oscillating operation). The control signal modb is output from the control circuit 500. When the control signal modb is "0", the N-channel MOS transistor NT11 is set to a non-conducting state. When the control signal modb is "1", the N-channel MOS transistor NT11 is set to a conducting state. The transistors that perform the switching operation are the P-channel MOS transistor PT10 and the N-channel MOS transistor NT10. When the oscillator circuit 208 is not oscillating, the control signal modb is "0", and the N-channel MOS transistor NT11 of the NAND gate ND is in a non-conducting state, so the voltage between the source and gate of the N-channel MOS transistor NT10 is extremely small compared to the power supply voltage VDD. Therefore, it is possible to suppress the effect of BTI (Bias Temperature Instability) on the N-channel MOS transistor NT10. Also, when the control signal modb is "0", the output signal of the NAND gate ND0 becomes "1", and since that signal is connected to node A1 of the next NAND gate, no effect of BTI occurs on the P-channel MOS transistor PT10.

[0070] Therefore, in detecting HCI degradation using the oscillator circuit 208 according to a modified embodiment 2 of this disclosure, the influence of degradation due to BTI of the N-channel MOS transistor is suppressed in particular, and highly accurate detection of HCI degradation is possible.

[0071] [Embodiment 3] Figure 10 shows an example configuration of an oscillator circuit 210 according to Embodiment 3. Referring to Figure 10, the oscillator circuit 210 includes a plurality of logic gate groups. Specifically, the oscillator circuit 210 includes a NOR gate 11 and logic gate groups R61 to R6m. The NOR gate 11 and logic gate groups R61 to R6m are connected in series. Each of the logic gate groups R61 to R6m is composed of a transistor and includes a first to third logic gate connected in series with each other. Furthermore, the first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates, and the driving forces of the first to third logic gates are set to be the same with respect to each other.

[0072] In this example, the logic gate group R61 includes a NOR gate NRD with the same driving force. Furthermore, the NOR gate NRD1 and n 4-input NAND gates are connected in parallel. The 4-input NAND gates NAD1, ..., NADn have open outputs. The reason for connecting these NAND gates in parallel is to increase the total capacitance of the output side of the NOR gate NR0. Therefore, the outputs of these NAND gates may be open or connected to the subsequent NOR gate NRD2.

[0073] The fan-out number for NOR gate NRD0 is n+1. The fan-out number for NOR gate NRD1 is 1. The fan-out number for NOR gate NRD2 is 1.

[0074] The configuration of the other logic gate groups R62 to R6m is the same as that of logic gate group R61, so a detailed explanation will not be repeated.

[0075] Therefore, in the oscillator circuit 210 according to Embodiment 3, similar to the oscillator circuit 202 according to Embodiment 1, the first fan-out number of the first logic gate in each logic gate group is greater than the second fan-out numbers of the second and third logic gates. Furthermore, the driving forces of the first to third logic gates are set to be the same. With this configuration, the oscillator circuit 210 has high sensitivity to HCI degradation for each switching operation (time domain B). By using the oscillator circuit 210 according to this configuration, it is possible to detect the HCI degradation of the transistors constituting the logic circuit 100 with high sensitivity.

[0076] Figure 11 illustrates a NOR gate NRD according to Embodiment 3. Referring to Figure 11, the NOR gate NRD includes P-channel MOS transistors PT0 to PT3 and N-channel MOS transistors NT0 to NT3. The P-channel MOS transistors PT0 to PT2 are connected in series with each other between the power supply voltage VDD and the output node. The N-channel MOS transistors NT0 to NT2 are connected in parallel with each other between the output node and the fixed voltage VSS. The P-channel MOS transistor PT0 and the N-channel MOS transistor NT2 are connected to node A3. The P-channel MOS transistor PT1 and the N-channel MOS transistor NT1 are connected to node A2. The P-channel MOS transistor PT2 and the N-channel MOS transistor NT0 are connected to node A1.

[0077] In this example, node A1 is connected to a fixed voltage VSS. Node A2 receives the output signal of the preceding NOR gate. Node A3 receives the input of the control signal mod. The control signal mod is set to "0" ("L" level) when the oscillator circuit is operating (oscillating operation) and to "1" ("H" level) when the oscillator circuit is not operating (non-oscillating operation). This control signal mod is output from the control circuit 500. When the control signal mod is "1", the P-channel MOS transistor PT0 is set to a non-conducting state. When the control signal mod is "0", the P-channel MOS transistor PT0 is set to a conducting state. The transistors that perform the switching operation are the P-channel MOS transistor PT1 and the N-channel MOS transistor NT1. When the oscillator circuit 210 is in non-oscillating operation, the control signal mod is "1", and the P-channel MOS transistor PT0 of the NOR gate NRD is in a non-conducting state, so the voltage between the source and gate of the P-channel MOS transistor PT1 is extremely small compared to the power supply voltage VDD. Therefore, it is possible to suppress the effect of BTI (Bias Temperature Instability) on the P-channel MOS transistor PT1. Also, when the control signal mod is "1", the output signal of the NOR gate NRD0 becomes "0", and since that signal is connected to node A1 of the next NOR gate, no effect of BTI occurs on the N-channel MOS transistor NT0.

[0078] In detecting HCI degradation using the oscillation circuit 210 according to Embodiment 3 of this disclosure, the influence of degradation due to BTI is suppressed, and highly accurate detection of HCI degradation is possible.

[0079] Furthermore, the P-channel MOS transistor PT1, which performs the switching operation, is connected to the output node via the P-channel MOS transistor PT2. This configuration makes it possible to suppress the HCI degradation of the P-channel MOS transistor PT1.

[0080] Figure 12 illustrates the difference in lifetime due to HCI between P-channel MOS transistors PT1 and PT2. Referring to Figure 12, the cases where P-channel MOS transistor PT2 is selected as the transistor performing the switching operation and the cases where P-channel MOS transistor PT1 is selected are shown. Here, the contour lines pHCI of the lifetime due to HCI of the P-channel MOS transistors are shown. It shows that transistors with a smaller source-drain voltage have a longer lifetime. In other words, compared to inputting the signal from the preceding NOR gate to node A1, which is the gate of P-channel MOS transistor PT2, inputting the signal from the preceding NOR gate to node A2, which is the gate of P-channel MOS transistor PT1, is more effective in suppressing HCI degradation.

[0081] In detecting HCI degradation using the oscillator circuit 210 according to Embodiment 3 of this disclosure, the effect of HCI-induced degradation of the P-channel MOS transistor is particularly suppressed. This enables highly accurate detection of HCI degradation for the N-channel MOS transistor.

[0082] Figure 13 shows an example configuration of an oscillator circuit 212 according to a modified example of Embodiment 3. Referring to Figure 13, the oscillator circuit 212 includes a plurality of logic gate groups. Specifically, the oscillator circuit 212 includes a NAND gate 10 and logic gate groups R71 to R7m. The NAND gate 10 and logic gate groups R71 to R7m are connected in series. Each of the logic gate groups R71 to R7m is composed of a transistor and includes a first to third logic gate connected in series with each other. Furthermore, the first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates, and the driving forces of the first to third logic gates are set to be the same with respect to each other.

[0083] In this example, the logic gate group R71 includes NAND gate NDD with the same driving force. Furthermore, NAND gate NDD1 and n 4-input NAND gates are connected in parallel.

[0084] The four-input NAND gates NAD1, ..., NADn have their outputs open. The reason for connecting these NAND gates in parallel is to increase the total capacitance of the output side of the NOR gate NR0. Therefore, the outputs of these NAND gates may be open or connected to the subsequent NOR gate NR2.

[0085] The fan-out number for NAND gate NDD0 is n+1. The fan-out number for NAND gate NDD1 is 1. The fan-out number for NAND gate NDD2 is 1.

[0086] The configuration of the other logic gate groups R72 to R7m is the same as that of logic gate group R71, so a detailed explanation will not be repeated.

[0087] Therefore, in the oscillator circuit 212 according to the modification of Embodiment 3, similar to the oscillator circuit 202 according to Embodiment 1, the first fan-out number of the first logic gate in each logic gate group is greater than the second fan-out numbers of the second and third logic gates. Furthermore, the driving forces of the first to third logic gates are set to be the same as those of the first to third logic gates. With this configuration, the oscillator circuit 212 has high sensitivity to HCI degradation for each switching operation (time domain B). By using the oscillator circuit 212 according to this configuration, it is possible to detect the HCI degradation of the transistors constituting the logic circuit 100 with high sensitivity.

[0088] Figure 14 illustrates a NAND gate NDD according to a modification of Embodiment 3. Referring to Figure 14, the NAND gate NDD includes P-channel MOS transistors PT10 to PT12 and N-channel MOS transistors NT10 to NT12. The P-channel MOS transistors PT10 to PT12 are connected in parallel to each other between the power supply voltage VDD and the output node. The N-channel MOS transistors NT10 to NT12 are connected in series to each other between the output node and the fixed voltage VSS. The P-channel MOS transistor PT10 and the N-channel MOS transistor NT10 are connected to node A1. The P-channel MOS transistor PT11 and the N-channel MOS transistor NT11 are connected to node A2. The P-channel MOS transistor PT12 and the N-channel MOS transistor NT12 are connected to node A3.

[0089] In this example, node A1 is connected to the power supply voltage VDD. Node A2 receives the output signal of the preceding NAND gate as input. Node A3 receives the input of the control signal modb. The control signal modb is set to "1" ("H" level) when the oscillator circuit is operating (oscillating operation) and to "0" ("L" level) when the oscillator circuit is not operating (non-oscillating operation). This control signal modb is output from the control circuit 500. When the control signal modb is "0", the N-channel MOS transistor NT12 is set to a non-conducting state. When the control signal modb is "1", the N-channel MOS transistor NT12 is set to a conducting state. The transistors that perform the switching operation are the N-channel MOS transistor NT11 and the P-channel MOS transistor PT11. When the oscillator circuit 212 is not oscillating, the control signal modb is "0", and the N-channel MOS transistor NT12 of the NAND gate NDD is in a non-conducting state, so the voltage between the source and gate of the N-channel MOS transistor NT11 is extremely small compared to the power supply voltage VDD. Therefore, it is possible to suppress the effect of BTI (Bias Temperature Instability) on the N-channel MOS transistor NT11. Also, when the control signal modb is "0", the output signal of the NAND gate NDD0 becomes "1", and since that signal is connected to node A1 of the next NAND gate, no effect of BTI occurs on the P-channel MOS transistor PT10.

[0090] In detecting HCI degradation using an oscillation circuit 212 according to a modified example of Embodiment 3 of this disclosure, the influence of degradation due to BTI is suppressed, and highly accurate detection of HCI degradation is possible.

[0091] Furthermore, the N-channel MOS transistor NT11, which performs the switching operation, is connected to the output node via the N-channel MOS transistor NT10. This configuration makes it possible to reduce the source-drain voltage, as explained in Figure 12, and suppress the HCI degradation of the N-channel MOS transistor NT11.

[0092] In detecting HCI degradation using an oscillator circuit 212 according to a modified example of Embodiment 3 of this disclosure, the effect of HCI degradation on N-channel MOS transistors is particularly suppressed. This makes it possible to detect HCI degradation with high accuracy for P-channel MOS transistors.

[0093] By using the oscillation circuit with the above configuration, it is possible to detect HCI degradation separately for P-type and N-type MOS transistors.

[0094] Furthermore, while the above example described a 3-input NAND gate or NOR gate, the same principles apply to 4-input NAND gates or NOR gates.

[0095] [Embodiment 4] Embodiment 4 describes a more accurate HCI degradation detection method by combining various oscillation circuits.

[0096] Figure 15 shows an example configuration of an oscillator circuit 214 according to Embodiment 4. Referring to Figure 15, the oscillator circuit 214 comprises an inverter IV and composite gates G0 to Gn. The composite gates G0 to Gn are connected in series, and the output of the final stage composite gate Gn is fed back to the first stage composite gate FG0.

[0097] Figure 16 illustrates the circuit configuration (non-oscillating operation) of a composite gate G according to Embodiment 4. Referring to Figure 16, the composite gate G includes P-channel MOS transistors PT20 to PT22 and N-channel MOS transistors NT20 to NT22. The P-channel MOS transistors PT20 to PT22 are connected in series with each other between the power supply voltage VDD and the output node. The N-channel MOS transistors NT20 and NT21 are connected in series with each other between the output node and the fixed voltage VSS. The N-channel MOS transistor NT20 is connected in parallel with the N-channel MOS transistors NT20 and NT21 and between the fixed voltage VSS and the output node.

[0098] The P-channel MOS transistor PT21 and the N-channel MOS transistor NT21 are connected to node A2. The P-channel MOS transistor PT22 is connected to node A1. The P-channel MOS transistor PT20 is connected to node A3. The N-channel MOS transistor NT20 is connected to node B1. The N-channel MOS transistor NT22 is connected to node B2.

[0099] In this example, node A1 is connected to a fixed voltage VSS during both oscillating and non-oscillating operation. Node A2 receives the output signal of the preceding NOR gate. Nodes A3 and B2 receive the control signal mod as input. Node B1 of the first stage composite gate G receives an external signal as input. Node B1 of the second and subsequent stage composite gates G1 to Gn receives the inverted control signal modb, which is the inverted signal of the control signal mod via inverter IV.

[0100] The control signal mod is set to "0" ("L" level) when the oscillator circuit is operating (oscillating operation) and to "1" ("H" level) when the oscillator circuit is not operating (non-oscillating operation). The inverting control signal modb is set to "1" ("H" level) when the oscillator circuit is operating (oscillating operation) and to "0" ("L" level) when the oscillator circuit is not operating (non-oscillating operation). The control signal mod is output from the control circuit 500.

[0101] When the oscillator circuit 214 is not oscillating, the P-channel MOS transistor PT20 is in a non-conducting state, so the voltage between the source and gate of the P-channel MOS transistor PT21 is extremely small compared to the power supply voltage VDD. Therefore, it is possible to suppress the effect of BTI (Bias Temperature Instability) on the P-channel MOS transistor PT21.

[0102] Furthermore, the source-drain voltage of the P-channel MOS transistor PT21 is extremely small. Therefore, it is possible to suppress the HCI degradation of the P-channel MOS transistor PT21.

[0103] Furthermore, when the oscillator circuit 214 is not oscillating, the N-channel MOS transistor NT21 is in a non-conducting state, so the voltage between the source and gate of the N-channel MOS transistor NT20 is extremely small compared to the power supply voltage VDD. Therefore, it is possible to suppress the effect of BTI (Bias Temperature Instability) on the N-channel MOS transistor NT21.

[0104] Furthermore, the source-drain voltage of the N-channel MOS transistor NT21 is extremely small. Therefore, it is possible to suppress the HCI degradation of the N-channel MOS transistor NT21.

[0105] Figure 17 illustrates the circuit configuration of the composite gate G according to Embodiment 4 (during oscillation operation). Referring to Figure 17, in this example, node A1 is connected to a fixed voltage VSS during both oscillation and non-oscillating operation. Node A2 receives the output signal of the preceding NOR gate. Nodes A3 and B2 receive the input of the control signal mod. Node B1 of the first stage composite gate G receives an external signal input. Nodes B1 of the second and subsequent stage composite gates G1 to Gn receive the input of an inverted control signal modb, which is the inverted signal of the control signal mod via inverter IV.

[0106] During oscillation of the oscillator circuit 214, the control signal mod is "0", and the P-channel MOS transistor PT20 of the composite gate G is in a conducting state. The N-channel MOS transistor NT22 is in a non-conducting state. In addition, the P-channel MOS transistor PT22 and the N-channel MOS transistor NT20 are set to a conducting state.

[0107] Furthermore, the P-channel MOS transistor PT21, which performs the switching operation, is connected to the output node via the P-channel MOS transistor PT22. In addition, the N-channel MOS transistor NT21 is connected to the output node via the N-channel MOS transistor NT20. This configuration makes it possible to suppress HCI degradation of the P-channel MOS transistor PT21 and the N-channel MOS transistor NT21. In other words, the oscillator circuit 214 according to Embodiment 4 is capable of suppressing both BTI degradation and HCI degradation of the P-channel MOS transistor and the N-channel MOS transistor.

[0108] Figure 18 illustrates the causes of frequency deviation in an oscillator circuit according to the comparative example. Referring to Figure 18, the degradation factors of semiconductor elements that cause frequency deviation in the oscillator circuit of the comparative example will be explained. These include HCI degradation of the P-channel MOS transistor during oscillation (AC-pHCI), HCI degradation of the N-channel MOS transistor during oscillation (AC-nHCI), BTI (Bias Temperature Instability) degradation during oscillation (AC-BTI), and BTI degradation during non-oscillating operation (DC-BTI).

[0109] Figure 19 is a diagram illustrating the cause of frequency deviation in the oscillator circuit 214 according to Embodiment 4. Referring to Figure 19, the case in which oscillator circuits 214, 214# and arithmetic circuit 50 are provided is shown. As described above, oscillator circuit 214 is an oscillator circuit that can suppress HCI degradation and BTI degradation of P-channel MOS transistors and N-channel MOS transistors even when oscillating. Oscillator circuit 214# is the same circuit as oscillator circuit 214 but does not oscillate. Alternatively, instead of oscillator circuit 214#, the frequency value during the initial operation of oscillator circuit 214 may be stored.

[0110] The calculation circuit 50 calculates the frequency fluctuation rate ΔF0 based on the difference between the frequency F0 output from the oscillation circuit 214 and the frequency F0# output from the oscillation circuit 214#. The frequency fluctuation rate ΔF0 corresponds to the frequency shift due to BTI (Bias Temperature Instability) degradation (AC-BTI) during oscillation operation. Specifically, the calculation circuit 50 calculates ΔF0 by 1 - F0 / F0#.

[0111] Figure 20 illustrates a method for detecting HCI degradation based on a combination of oscillation circuits according to Embodiment 4. Referring to Figure 20, a case is shown in which oscillation circuits 210, 210#, oscillation circuits 214, 214#, and calculation circuits 50, 52, 54 are provided.

[0112] Oscillator circuit 210 is an oscillator capable of suppressing HCI degradation and BTI degradation of the P-channel MOS transistor when it is in oscillation mode. Oscillator circuit 210# is the same circuit as oscillator circuit 210 but does not oscillate. Alternatively, instead of oscillator circuit 210#, the frequency value at the time of initial operation of oscillator circuit 210 may be stored.

[0113] The calculation circuit 52 calculates the frequency fluctuation rate ΔF1 based on the difference between the frequency F1 output from the oscillator circuit 210 and the frequency F1# output from the oscillator circuit 210#. The frequency fluctuation rate ΔF1 corresponds to the frequency shift due to the HCI degradation (AC-nHCI) and BTI (Bias Temperature Instability) degradation (AC-BTI) of the N-channel MOS transistor during oscillation operation. Specifically, the calculation circuit 52 calculates ΔF1 by 1-F1 / F1#.

[0114] As described above, the oscillator circuit 214 is an oscillator circuit that can suppress HCI degradation and BTI degradation even when it is in oscillation mode. Oscillator circuit 214# is the same circuit as oscillator circuit 214 but does not oscillate. Alternatively, instead of oscillator circuit 214#, the frequency value at the time of initial operation of oscillator circuit 214 may be stored.

[0115] The calculation circuit 50 calculates the frequency fluctuation rate ΔF0 based on the difference between the frequency F0 output from the oscillation circuit 214 and the frequency F0# output from the oscillation circuit 214#. The frequency fluctuation rate ΔF0 corresponds to the frequency shift due to BTI (Bias Temperature Instability) degradation (AC-BTI) during oscillation operation. Specifically, the calculation circuit 50 calculates ΔF0 by 1 - F0 / F0#.

[0116] Therefore, the arithmetic circuit 54 outputs a frequency fluctuation rate ΔF2 based on the difference between the output from the arithmetic circuit 52 and the output from the arithmetic circuit 50. The frequency fluctuation rate ΔF2 corresponds to the frequency shift caused by the HCI degradation (AC-nHCI) of the N-channel MOS transistor.

[0117] In other words, by combining various oscillation circuits, it is possible to detect degradation of N-channel MOS transistors, particularly HCI, due to oscillation. For example, by using an oscillation circuit according to this configuration, it is possible to detect HCI degradation of the N-channel MOS transistors constituting the logic circuit 100 with high sensitivity.

[0118] Figure 21 illustrates a method for detecting HCI degradation based on a combination of oscillation circuits according to a modified example of Embodiment 4. Referring to Figure 21, the case in which oscillation circuits 212, 212#, oscillation circuits 214, 214#, and calculation circuits 50, 52, 54 are provided is shown.

[0119] Oscillator circuit 212 is an oscillator capable of suppressing HCI degradation and BTI degradation of the P-channel MOS transistor when it is in oscillation mode. Oscillator circuit 212# is the same circuit as oscillator circuit 212 but does not oscillate. Alternatively, instead of oscillator circuit 212#, the frequency value at the time of initial operation of oscillator circuit 212 may be stored.

[0120] The calculation circuit 52 calculates the frequency fluctuation rate ΔF3 based on the difference between the frequency F3 output from the oscillator circuit 212 and the frequency F3# output from the oscillator circuit 212#. The frequency fluctuation rate ΔF3 corresponds to the frequency shift due to the HSCI degradation (AC-pHCI) and BTI (Bias Temperature Instability) degradation (AC-BTI) of the P-channel MOS transistor during oscillation operation. Specifically, the calculation circuit 52 calculates ΔF3 by 1-F3 / F3#.

[0121] As described above, the oscillator circuit 214 is an oscillator circuit that can suppress HCI degradation and BTI degradation even when it is in oscillation mode. Oscillator circuit 214# is the same circuit as oscillator circuit 214 but does not oscillate. Alternatively, instead of oscillator circuit 214#, the frequency value at the time of initial operation of oscillator circuit 214 may be stored.

[0122] The calculation circuit 50 calculates the frequency fluctuation rate ΔF0 based on the difference between the frequency F0 output from the oscillation circuit 214 and the frequency F0# output from the oscillation circuit 214#. The frequency fluctuation rate ΔF0 corresponds to the frequency shift due to BTI (Bias Temperature Instability) degradation (AC-BTI) during oscillation operation. Specifically, the calculation circuit 50 calculates ΔF0 by 1 - F0 / F0#.

[0123] Therefore, the arithmetic circuit 54 outputs a frequency fluctuation rate ΔF4 based on the difference between the output from the arithmetic circuit 52 and the output from the arithmetic circuit 50. The frequency fluctuation rate ΔF4 corresponds to the frequency shift caused by the HCI degradation (AC-pHCI) of the P-channel MOS transistor.

[0124] In other words, by combining various oscillation circuits, it is possible to detect degradation of P-channel MOS transistors, particularly degradation due to HCI, caused by oscillation. For example, by using an oscillation circuit according to this configuration, it is possible to detect HCI degradation of P-channel MOS transistors constituting the logic circuit 100 with high sensitivity.

[0125] The method according to Embodiment 4 makes it possible to separate the P-type or N-type transistors of a transistor and detect the HCI degradation of semiconductor elements with high accuracy.

[0126] Although the present disclosure has been described in detail based on embodiments, it goes without saying that the present disclosure is not limited to embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0127] 1 semiconductor device, 10 detection circuits, 50, 52, 54 arithmetic circuits, 100 logic circuits, 200, 202, 204, 205, 208, 210, 212, 214 oscillator circuits, 300 counters, 400 comparators, 500 control circuits.

Claims

1. An oscillator circuit including a group of logic gates connected in series, A frequency counter for measuring the oscillation frequency of the aforementioned oscillation circuit, The system includes a comparator that compares the oscillation frequency of the oscillation circuit, measured by the frequency counter, with a reference value. Each of the aforementioned plurality of logic gate groups is composed of a transistor and includes a first to third logic gate connected in series with respect to each other. The first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates. A semiconductor device in which the driving forces of the first to third logic gates are the same as those of the first to third logic gates.

2. The semiconductor device according to claim 1, wherein the oscillator circuit includes a selection circuit that changes the number of connection stages of the plurality of logic gate groups connected in series.

3. The semiconductor device according to claim 1, wherein the reference value is the initial value counted by the frequency counter.

4. The system further includes a dummy oscillator circuit with the same circuit configuration as the aforementioned oscillator circuit, which does not oscillate under normal conditions but oscillates when measurement is performed. The semiconductor device according to claim 1, wherein the reference value is the oscillation frequency of the dummy oscillator circuit measured by the frequency counter during the measurement.

5. Each of the first to third logic gates is: First and second transistors are connected in series between a first voltage and a second voltage via an output node, and are set to conduct / non-conduct in a complementary manner according to the input signal when the oscillator circuit is oscillating, A third transistor is connected between the first transistor and the first voltage, and is set to conduct during the oscillation operation of the oscillator circuit and to be non-conductive during non-oscillating operation, in order to reduce the gate-source voltage of the first transistor. The semiconductor device according to claim 1, further comprising a fourth transistor connected in parallel with the second transistor between the output node and the second voltage, and set to conduct when the oscillator circuit is not oscillating.

6. Each of the first to third logic gates is: The semiconductor device according to claim 5, further comprising a fifth transistor connected between the first transistor and the output node, which conducts during the oscillation operation of the first oscillator circuit.

7. A first oscillation circuit capable of accelerating the degradation of a transistor due to hot carrier injection through oscillation operation, A first frequency counter for measuring the oscillation frequency of the first oscillation circuit, A first calculation circuit that calculates the difference between the oscillation frequency of the first oscillation circuit measured by the first frequency counter and a first reference value, A second oscillation circuit capable of suppressing degradation of the transistor due to hot carrier injection caused by the oscillation operation, A second frequency counter for measuring the oscillation frequency of the second oscillation circuit, A second calculation circuit that calculates the difference between the oscillation frequency of the second oscillation circuit measured by the second frequency counter and a second reference, A semiconductor device comprising: a detection circuit that detects degradation due to hot carrier injection based on the difference calculated by the first and second calculation circuits.

8. The semiconductor device according to claim 7, wherein the first oscillation circuit accelerates the degradation of a P-type transistor due to hot carrier injection.

9. The semiconductor device according to claim 7, wherein the first oscillation circuit accelerates the degradation of an N-type transistor by hot carrier injection.

10. The semiconductor device according to claim 7, wherein the first and second reference values ​​are initial values ​​counted by the first and second frequency counters.

11. A first dummy oscillator circuit having the same circuit configuration as the first oscillator circuit, which does not oscillate under normal conditions but oscillates when measurement is performed, The system further includes a second dummy oscillator circuit having the same circuit configuration as the second oscillator circuit, which does not oscillate under normal conditions but oscillates during measurement. The semiconductor device according to claim 7, wherein the first and second reference values ​​are the oscillation frequencies of the first and second dummy oscillator circuits measured by the frequency counter during the measurement.

12. The first oscillator circuit includes a group of logic gates connected in series, Each of the aforementioned plurality of logic gate groups is composed of a transistor and includes a first to third logic gate connected in series with respect to each other. The first fan-out number of the first logic gate is greater than the second fan-out numbers of the second and third logic gates. The semiconductor device according to claim 7, wherein the driving forces of the first to third logic gates are the same as those of the first to third logic gates.

13. Each of the first to third logic gates is: First and second transistors are connected in series between a first voltage and a second voltage via an output node, and are set to conduct / non-conduct in a complementary manner according to the input signal when the first oscillator circuit is oscillating, A third transistor is connected between the first transistor and the first voltage, conducts during the oscillation operation of the first oscillator circuit, and is set to be non-conductive during non-oscillating operation, in order to reduce the gate-source voltage of the first transistor. The semiconductor device according to claim 12, further comprising a fourth transistor connected in parallel with the second transistor between the output node and the second voltage, and set to conduct when the first oscillator circuit is in non-oscillating operation.

14. Each of the first to third logic gates is: The semiconductor device according to claim 13, further comprising a fifth transistor connected between the first transistor and the output node, which conducts during the oscillation operation of the first oscillator circuit.

15. The second oscillator circuit includes a fourth logic gate connected in series with the same number of stages as the plurality of logic gates in the first oscillator circuit. The fourth logic gate is, Fifth and sixth transistors are connected in series between the first voltage and the second voltage via an output node, and are set to conduct / non-conduct complementaryly according to the input signal when the second oscillator circuit is oscillating, A seventh transistor is connected between the fifth transistor and the first voltage, conducts during the oscillation operation of the second oscillator circuit, and is set to be non-conductive during non-oscillating operation, in order to reduce the gate-source voltage of the fifth transistor. An eighth transistor is connected in parallel with the sixth transistor between the output node and the second voltage, and is set to conduct when the oscillator circuit is not oscillating, A ninth transistor connected between the fifth transistor and the output node, The semiconductor device according to claim 13, further comprising a tenth transistor connected between the sixth transistor and the output node.

16. The ninth transistor is set to conduct during the oscillation and non-oscillating operation of the second oscillator circuit. The semiconductor device according to claim 15, wherein the tenth transistor is set to conduct when the second oscillator circuit is oscillating and is set to non-conductive when it is not oscillating.

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