Active balun circuit

Abstract

This provides an active balun circuit that offers a more uniform balance of balanced signals than conventional circuits. [Solution] The first amplifier circuit comprises a first amplifier transistor and a third amplifier transistor connected in parallel to the first amplifier transistor and biased in the same way as the first amplifier transistor, and inverts and amplifies an input signal which is a non-balanced signal to output an inverted signal which is one side of a balanced signal; and the second amplifier circuit comprises a second amplifier transistor which is larger in size than the first amplifier transistor and biased in the same way as the first amplifier transistor, and inverts and amplifies the inverted signal to output a non-inverted signal which is the other side of a balanced signal.

Description

Technical Field

[0005] , , ,

[0001] The present invention relates to an active balun circuit.

Background Art

[0002] As is well known, a balun circuit is a circuit that converts an unbalanced signal into a balanced signal. Patent Document 1 below discloses an active balun circuit used in a wireless communication system (see FIG. 4). This active balun circuit combines a source-grounded amplifier circuit and a gate-grounded amplifier circuit, generates one of the balanced signals by inverting and amplifying an input signal (unbalanced signal) with the source-grounded amplifier circuit, and generates the other of the balanced signals by non-invertingly amplifying the input signal with the gate-grounded amplifier circuit.

[0003] Also, Patent Document 2 below discloses a low-noise amplifier that functions as an active balun circuit (see FIG. 1). This low-noise amplifier is formed by cascading two emitter-grounded amplifier circuits, generates one of the balanced signals by inverting and amplifying an input signal (unbalanced signal) with the first-stage emitter-grounded amplifier circuit, and generates the other of the balanced signals by inverting and amplifying one of the balanced signals with the second-stage emitter-grounded amplifier circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the above background technology has a problem in that the amplitude and phase balance in the balanced signal is not sufficient. Specifically, in the active balun circuit of Patent Document 1, the amplitude and phase balance in the balanced signal deteriorates due to non-uniform delay and gain in the common-source amplifier circuit and common-gate amplifier circuit. On the other hand, in the active balun circuit of Patent Document 2, the amplitude and phase balance in the balanced signal deteriorates due to non-uniform delay and gain in the two common-emitter amplifier circuits.

[0006] This invention has been made in view of the circumstances described above, and aims to provide an active balun circuit in which the balance of the balanced signal is more uniform than in conventional circuits. [Means for solving the problem]

[0007] To achieve the above objective, the present invention employs a first solution for an active balun circuit, comprising: a first amplification circuit comprising a first amplification transistor and a third amplification transistor connected in parallel to the first amplification transistor and biased in the same way as the first amplification transistor, which inverts and amplifies an input signal that is an unbalanced signal to output an inverted signal that is one side of a balanced signal; and a second amplification circuit comprising a second amplification transistor that is larger in size than the first amplification transistor and biased in the same way as the first amplification transistor, which inverts and amplifies the inverted signal to output a non-inverted signal that is the other side of a balanced signal.

[0008] In the present invention, as a second solution relating to the active balun circuit, the means adopted is that, in the first solution described above, the output of the first amplification transistor and the input of the second amplification transistor are electrically connected via a capacitor.

[0009] In the present invention, as a third solution relating to the active balun circuit, the means adopted is that, in the first or second solution described above, the input of the first amplification transistor and the output of the second amplification transistor are electrically connected via a capacitor.

[0010] In the present invention, as a fourth solution relating to the active balun circuit, a means is adopted in which, in any of the first to third solutions described above, a cascode transistor is connected to each of the first, second, and third amplification transistors.

[0011] In the present invention, as a fifth solution relating to the active balun circuit, the first amplification transistor, the second amplification transistor, and the third amplification transistor are connected in common at either their source terminal or emitter terminal, in any of the first to fourth solutions described above.

[0012] In this invention, as a sixth solution relating to the active balun circuit, the method adopted is that, in any of the second to fifth solutions described above, the capacitor is a variable capacitor. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide an active balun circuit in which the balance of the balanced signal is more uniform than in conventional circuits. [Brief explanation of the drawing]

[0014] [Figure 1] This is a circuit diagram showing the configuration of an active balun circuit according to the first embodiment of the present invention. [Figure 2] This is a characteristic diagram showing the amplitude balance of an active balun circuit according to the first embodiment of the present invention. [Figure 3] This is a characteristic diagram showing the phase balance of an active balun circuit according to the first embodiment of the present invention. [Figure 4] This is a circuit diagram showing the configuration of an active balun circuit according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0015] Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, an active balun circuit A according to the first embodiment of the present invention will be described with reference to Figures 1 to 3. As shown in Figure 1, this active balun circuit A includes an input terminal Tin, a first capacitor 1, a first resistor 2, a second capacitor 3, a second resistor 4, a first bias terminal Tb1, a first transistor 5, a third resistor 6, a second transistor 7, a second bias terminal Tb2, a fourth resistor 8, a power supply terminal Td, a third capacitor 9, a first output terminal Toutn, a fifth resistor 10, a third bias terminal Tb3, a third transistor 11, a fourth transistor 12, a sixth resistor 13, a fourth bias terminal Tb4, a fifth transistor 14, a sixth transistor 15, a fifth bias terminal Tb5, a seventh resistor 16, a fourth capacitor 17, a second output terminal Toutp, a fifth capacitor 18, and a variable capacitor 19.

[0016] Here, among the above components, the second resistor 4, the first transistor 5, the third resistor 6, the second transistor 7, the fourth resistor 8, the fifth resistor 10, the third transistor 11, the fourth transistor 12, the sixth resistor 13, the fifth transistor 14, the sixth transistor 15, the seventh resistor 16, the fifth capacitor 18, and the variable capacitor 19 constitute the main circuit of the active balun circuit A.

[0017] This main circuit has a basic configuration as a differential amplifier circuit, which combines a first amplifier circuit and a second amplifier circuit. Of the components that make up the main circuit, the second resistor 4, the first transistor 5, the third resistor 6, the second transistor 7, the fourth resistor 8, the fifth resistor 10, the third transistor 11, and the fourth transistor 12 constitute the first amplifier circuit. In addition, the third resistor 6, the sixth resistor 13, the fifth transistor 14, the sixth transistor 15, and the seventh resistor 16 constitute the second amplifier circuit.

[0018] That is, the first amplifier circuit and the second amplifier circuit constitute a differential amplifier circuit with the third resistor 6 as a commonly connected source resistor. Such a main circuit is responsible for the main function of the active balun circuit A. That is, the main circuit of the active balun circuit A according to the present embodiment uses a differential amplifier circuit (active circuit) instead of a passive circuit, and thus has a function of actively converting an unbalanced signal into a balanced signal.

[0019] Among the components constituting the main circuit, the fifth capacitor 18 and the variable capacitor 19 that do not constitute the first amplifier circuit and the second amplifier circuit are circuit elements that ac-couple the first amplifier circuit and the second amplifier circuit. Although details will be described later, the fifth capacitor 18 is a feedback capacitor that feeds back a part of the output of the second amplifier circuit to the first amplifier circuit. On the other hand, the variable capacitor 19 is a coupling capacitor that supplies a part of the output of the first amplifier circuit to the second amplifier circuit.

[0020] Input terminal Tin, first capacitor 1, first resistor 2, second capacitor 3, first bias terminal Tb1, second bias terminal Tb2, power supply terminal Td, first output terminal Toutn, third capacitor 9, third bias terminal Tb3, fourth bias terminal Tb4, fifth bias terminal Tb5, fourth capacitor 17, and second output terminal Toutp, other than such components, are components for assisting the main circuit of the active balun circuit A.

[0021] In such an active balun circuit A, the input terminal Tin is connected to one end of the first capacitor 1 as shown in the figure. Also, this input terminal Tin is connected to a signal source outside the active balun circuit A. A high-frequency signal in a predetermined frequency band, for example, in the range of several to several tens of GHz, is input from the signal source to such an input terminal Tin. This high-frequency signal is an unbalanced signal and is the input signal of the active balun circuit A according to the present embodiment.

[0022] The first capacitor 1 has one end connected to the input terminal Tin, and the other end connected to one end of the first resistor 2 and one end of the second capacitor 3. This first capacitor 1 is a matching capacitor having a predetermined capacitance (first capacitance), and together with the first resistor 2, it constitutes a matching circuit having a predetermined impedance.

[0023] The first resistor 2 has one end connected to the other end of the first capacitor 1 and one end of the second capacitor 3, and the other end is grounded. This first resistor 2 is a matching resistor having a predetermined resistance value (first resistance value), and together with the first capacitor 1, it constitutes a matching circuit having a predetermined impedance.

[0024] This matching circuit is used to achieve impedance matching with the aforementioned signal source, and its impedance is set to match the output impedance of the signal source.

[0025] The second capacitor 3 has one end connected to the other end of the first capacitor 1 and one end of the first resistor 2, and the other end connected to the gate terminal of the first transistor 5, one end of the second resistor 4 and one end of the fifth capacitor 18. This second capacitor 3 is a coupling capacitor having a predetermined capacitance (second capacitance), and it DC-separates the matching circuit and the main circuit.

[0026] The second resistor 4 has one end connected to the gate terminal of the first transistor 5, the other end of the second capacitor 3, and one end of the fifth capacitor 18, and the other end connected to the first bias terminal Tb1. This second resistor 4 is a bias resistor having a predetermined resistance value (second resistance value), and applies a predetermined gate bias voltage (first bias voltage Vb) to the gate terminal of the first transistor 5.

[0027] The first bias terminal Tb1 is connected to the other end of the second resistor 4. Furthermore, this first bias terminal Tb1 is connected to the first output terminal of the bias circuit outside of the active balun circuit A. This first bias output terminal Tb1 supplies the first bias voltage Vb applied from the first output terminal of the bias circuit to the second resistor 4.

[0028] As shown in the figure, the first transistor 5 is cascode-connected to the second transistor 7. This first transistor 5 is an n-type MOS transistor having a predetermined size (first element size S1). The gate terminal of this first transistor 1 is connected to the other end of the second capacitor 3, one end of the second resistor 4, and one end of the fifth capacitor 18, while the source terminal is connected to the source of the third transistor 11, the source terminal of the fifth transistor 14, and one end of the third resistor 6.

[0029] Furthermore, the drain terminal of this first transistor 5 is connected to the source terminal of the second transistor 7 and one end of the variable capacitor 19. An input signal (high-frequency signal) is input to the gate terminal of this first transistor 5 via the input terminal Tin, the matching circuit, and the second capacitor 3.

[0030] A first drain current Id1, corresponding to the first bias voltage Vb, flows from the drain terminal to the source terminal of the first transistor 5. The first transistor 5 also outputs an inverted signal, which is the input signal (high-frequency signal) with its phase reversed, from its drain terminal to the source terminal of the second transistor 7 and one end of the variable capacitor 19. Such a first transistor 5 corresponds to the first amplifying transistor in the present invention.

[0031] The third resistor 6 has one end connected to the source terminal of the first transistor 5, the source of the third transistor 11, and the source terminal of the fifth transistor 14, and the other end is grounded. This third resistor 6 is a source resistor having a predetermined resistance value (third resistance value) and sets the voltage amplification ratio of the first transistor 5, the third transistor 11, and the fifth transistor 14.

[0032] As shown in the figure, the second transistor 7 is a cascode transistor cascode-connected to the first transistor 5. This second transistor 7 is an n-type MOS transistor whose size is not limited to the same size as the first transistor 5 (first element size S1). The gate terminal of this second transistor 7 is connected to the second bias terminal Tb2 and the gate terminal of the fourth transistor 12, and the source terminal is connected to the drain terminal of the first transistor 5 and one end of the variable capacitor 19.

[0033] Furthermore, the drain terminal of this second transistor 7 is connected to one end of the fourth resistor 8, the drain terminal of the fourth transistor 12, and one end of the third capacitor 9. In this second transistor 7, the same first drain current Id1 as that of the first transistor 5 flows from the drain terminal to the source terminal.

[0034] Furthermore, the second transistor 7 outputs the inverting amplification signal input to the source terminal from the first transistor 5 to one end of the third capacitor 9 in phase without inverting its phase. In other words, the second transistor 7 outputs an inverted signal, which has its phase inverted with respect to the input signal (unbalanced signal), to the third capacitor 9 as one end of the balanced signal. Note that the first transistor 5 and the second transistor 7 constitute the first cascode circuit.

[0035] The second bias terminal Tb2 is connected to the gate terminal of the second transistor 7 and the gate terminal of the fourth transistor 12. Furthermore, this second bias terminal Tb2 is connected to the second output terminal of the bias circuit outside of the active balun circuit A. This second bias terminal Tb2 applies the second bias voltage Vcas, which is applied from the second output terminal of the bias circuit, to the gate terminals of the second transistor 7 and the fourth transistor 12.

[0036] The fourth resistor 8 has one end connected to the drain terminal of the second transistor 7, the drain terminal of the fourth transistor 12, and one end of the third capacitor 9, and the other end connected to the power supply terminal Td and the other end of the seventh resistor 16. This fourth resistor 8 is a drain resistor having a predetermined resistance value (fourth resistance value) and sets the voltage amplification ratio of the first transistor 5 and the third transistor 11. The drain terminals of the second transistor 7 and the fourth transistor 12, to which one end of the fourth resistor 8 and one end of the third capacitor 9 are commonly connected, are the output terminals of the first amplifier circuit.

[0037] The power terminal Td is connected to the other end of the fourth resistor 8 and the other end of the seventh resistor 16. Furthermore, this power terminal Td is connected to a DC power supply of a predetermined voltage outside the active balun circuit A. This power terminal Td supplies operating power for the first transistor 5, the second transistor 7, the third transistor 11, and the fourth transistor 12 to the other end of the fourth resistor 8. Additionally, the power terminal Td supplies operating power for the fifth transistor 14 and the sixth transistor 15 to the other end of the seventh resistor 16.

[0038] The third capacitor 9 has one end connected to the drain terminals of the second transistor 7 and the fourth transistor 12, and the other end connected to the first output terminal Toutn. This third capacitor 9 is a coupling capacitor having a predetermined capacitance (third capacitance), and it blocks the DC component at the drain terminal of the second transistor 7, supplying only the inverted signal to the first output terminal Toutn.

[0039] The first output terminal Toutn is connected to the other end of the third capacitor 9. This first output terminal Toutn is also connected to the first input terminal of the subsequent circuit outside of the active balun circuit A. The first output terminal Toutn outputs the inverted signal input from the second transistor 7 via the third capacitor 9 to the first input terminal of the subsequent circuit as one of the balanced signals in the active balun circuit A.

[0040] The fifth resistor 10 has one end connected to the gate terminal of the third transistor 11 and the other end connected to the third bias terminal Tb3. This fifth resistor 10 is a bias resistor having a predetermined resistance value (fifth resistance value) and applies a first bias voltage Vb, which is the same as the gate bias voltage of the first transistor 5, to the gate terminal of the third transistor 11.

[0041] The third bias terminal Tb3 is connected to the other end of the fifth resistor 10. Furthermore, this third bias terminal Tb3 is connected to the first output terminal of the bias circuit outside of the active balun circuit A. In other words, this third bias terminal Tb3 supplies the first bias voltage Vb applied from the first output terminal of the bias circuit to the fifth resistor 10.

[0042] The third transistor 11 is a cascode transistor connected in cascode mode to the fourth transistor 12, as shown in the figure. This third transistor 11 is an n-type MOS transistor whose size is determined by the ratio of the size of the first transistor 5 to the size of the second transistor 7 = the size of the third transistor 11 to the size of the fourth transistor 12. The gate terminal of this third transistor 11 is connected to one end of the fifth resistor 10, and its source terminal is connected to one end of the third resistor 6, the source terminal of the first transistor 5, and the source terminal of the fifth transistor 14.

[0043] Furthermore, the drain terminal of this third transistor 11 is connected to the source terminal of the fourth transistor 12. Such a third transistor 11 is a DC circuit to which no input signal (high-frequency signal) is input, and the same first bias voltage Vb as that of the first transistor 5 is applied as the gate bias voltage. That is, a second drain current Id2 corresponding to the same first bias voltage Vb as in the case of the first transistor 5 flows from the drain terminal to the source terminal of the third transistor 11. Such a third transistor 11 corresponds to the third amplification transistor in the present invention.

[0044] The fourth transistor 12 is an n-type MOS transistor whose size is determined by the ratio of the size of the first transistor 5 to the size of the second transistor 7 = the ratio of the size of the third transistor 11 to the size of the fourth transistor 12. The gate terminal of the fourth transistor 12 is connected to the second bias terminal Tb2 and the gate terminal of the second transistor 7, and its source terminal is connected to the drain terminal of the third transistor 11.

[0045] Furthermore, the drain terminal of the fourth transistor 12 is connected to one end of the fourth resistor 8, the drain terminal of the second transistor 7, and one end of the third capacitor 9. As shown in the figure, this fourth transistor 12 is a cascode transistor cascode-connected to the third transistor 11, and the same second drain current Id2 as that of the third transistor 11 flows from the drain terminal to the source terminal. The third transistor 11 and the fourth transistor 12 constitute a second cascode circuit.

[0046] The sixth resistor 13 has one end connected to the gate terminal of the fifth transistor 14 and the other end of the variable capacitor 19, and the other end connected to the fourth bias terminal Tb4. This sixth resistor 13 is a bias resistor having a predetermined resistance value (sixth resistance value), and applies a first bias voltage Vb, which is the same as the gate bias voltage of the first transistor 5 and the third transistor 11, to the gate terminal of the fifth transistor 14.

[0047] The fourth bias terminal Tb4 is connected to the other end of the sixth resistor 13. Furthermore, this fourth bias terminal Tb4 is connected to the first output terminal of the bias circuit outside of the active balun circuit A. In other words, this fourth bias terminal Tb4 supplies the first bias voltage Vb applied from the first output terminal of the bias circuit to the sixth resistor 13.

[0048] The fifth transistor 14 is cascode-connected to the sixth transistor 15, as shown in the figure. This fifth transistor 14 is an n-type MOS transistor having the combined size of the first transistor 5 and the third transistor 11. The gate terminal of this fifth transistor 14 is connected to one end of the sixth resistor 13 and the other end of the variable capacitor 19, and its source terminal is connected to the source terminal of the first transistor 5, one end of the third resistor 6 and the source terminal of the third transistor 11.

[0049] Furthermore, the drain terminal of this fifth transistor 14 is connected to the source terminal of the sixth transistor 15 and the other end of the fifth capacitor 18. The inverted signal output from the drain terminal of the first transistor 5 is input to the gate terminal of this fifth transistor 14 via the variable capacitor 19.

[0050] In such a fifth transistor 14, a third drain current Id3 corresponding to the first bias voltage Vb flows from the drain terminal to the source terminal. Furthermore, this fifth transistor 14 outputs a non-inverting signal, which is in phase with the input signal, from its drain terminal to the source terminal of the sixth transistor 15 and the other end of the fifth capacitor 18, after inverting and amplifying the inverting signal input to its gate terminal via the variable capacitor 19. Such a fifth transistor 14 corresponds to the second amplification transistor in the present invention.

[0051] As shown in the figure, the sixth transistor 15 is a cascode transistor cascode-connected to the fifth transistor 14. This sixth transistor 15 is an n-type MOS transistor having the combined size of the second transistor 7 and the fourth transistor 12. The gate terminal of this sixth transistor 15 is connected to the fifth bias terminal Tb5, and the source terminal is connected to the drain terminal of the fifth transistor 14 and the other end of the fifth capacitor 18.

[0052] Furthermore, the drain terminal of this sixth transistor 15 is connected to one end of the seventh resistor 16 and one end of the fourth capacitor 17. In this sixth transistor 15, the same third drain current Id3 as that of the fifth transistor 14 flows from the drain terminal to the source terminal.

[0053] Furthermore, the sixth transistor 15 outputs the non-inverting signal input to the source terminal from the fifth transistor 14 to one end of the fourth capacitor 17 in phase without inverting its phase. In other words, the sixth transistor 15 outputs the non-inverting signal, which is in phase with the input signal (unbalanced signal), to the fourth capacitor 17 as the other end of the balanced signal.

[0054] Furthermore, the fifth transistor 14 and the sixth transistor 15 constitute a third cascode circuit. In addition, the drain terminal of the sixth transistor 15, to which one end of the seventh resistor 16 and one end of the fourth capacitor 17 are connected in common, is the output terminal of the second amplifier circuit.

[0055] The fifth bias terminal Tb5 is connected to the gate terminal of the sixth transistor 15. Furthermore, this fifth bias terminal Tb5 is connected to the second output terminal of the bias circuit outside of the active balun circuit A. This fifth bias terminal Tb5 applies the second bias voltage Vcas, which is applied from the second output terminal of the bias circuit, to the gate terminal of the sixth transistor 15.

[0056] The seventh resistor 16 has one end connected to the drain terminal of the sixth transistor 15 and one end of the fourth capacitor 17, and the other end connected to the power supply terminal Td and the other end of the fourth resistor 8. This seventh resistor 16 is a drain resistor having a predetermined resistance value (seventh resistance value) and sets the voltage amplification factor of the fifth transistor 14.

[0057] The fourth capacitor 17 has one end connected to the drain terminal of the sixth transistor 15 and one end of the seventh resistor 16, and the other end connected to the second output terminal Toutp. This fourth capacitor 17 is a coupling capacitor having a predetermined capacitance (fourth capacitance), and it blocks the DC component at the drain terminal of the sixth transistor 15, supplying only the non-inverting signal to the second output terminal Toutp.

[0058] The second output terminal Toutp is connected to the other end of the fourth capacitor 17. This second output terminal Toutp is also connected to the second input terminal of the subsequent circuit outside of the active balun circuit A. The second output terminal Toutp outputs the non-inverting signal input from the sixth transistor 15 via the fourth capacitor 17 to the second input terminal of the subsequent circuit as the other half of the balanced signal in the active balun circuit A.

[0059] The fifth capacitor 18 has one end connected to the other end of the second capacitor 3, one end of the second resistor 4, and the gate terminal of the first transistor 5, and the other end connected to the drain terminal of the fifth transistor 14 and the source terminal of the sixth transistor 15. This fifth capacitor 18 is a feedback capacitor having a predetermined capacitance (fifth capacitance), and it feeds back a portion of the non-inverting signal output from the drain terminal of the fifth transistor 14 to the gate terminal of the first transistor 5.

[0060] The variable capacitor 19 has one end connected to the drain terminal of the first transistor 5 and the source terminal of the second transistor 7, and the other end connected to the gate terminal of the fifth transistor 14 and one end of the sixth resistor 13. This variable capacitor 19 has a capacitance (variable capacitance) that can be freely adjusted within a predetermined range, and is a coupling capacitor that inputs a portion of the inverting signal output from the drain terminal of the first transistor 5 to the gate terminal of the fifth transistor 14.

[0061] Here, the second cascode circuit is provided to compensate for the DC performance of the first cascode circuit relative to the third cascode circuit. The size of the first transistor 5 : the size of the third transistor 11 = the size of the second transistor 7 : the size of the fourth transistor 12 = S1:S2. The sizes of the first to fourth transistors 5, 7, 11, and 12 refer to the gate width when the gate length is the same.

[0062] In this embodiment, the first element size S1 and the second element size S2 are set to be smaller than the third element size S3. Furthermore, the combined size of the first element size S1 and the second element size S2 is set to be the same as the third element size S3, as shown in equation (1) below. S1 + S2 = S3 (1)

[0063] The combined size of the first transistor 5 and the third transistor 11 is the same as the size of the fifth transistor 14. Also, the combined size of the second transistor 7 and the fourth transistor 12 is the same as the size of the sixth transistor 15.

[0064] Due to this relative size relationship between the first, second, and third transistors, the first drain current Id1 flowing through the first transistor 5 and the second transistor 7, the second drain current Id2 flowing through the third transistor 11 and the fourth transistor 12, and the third drain current Id3 flowing through the fifth transistor 14 and the sixth transistor 15 satisfy the relationship shown in equation (2) below. Id1 + Id2 = Id3 (2)

[0065] In the active balun circuit A according to this embodiment, the main circuit has a basic configuration as a differential amplifier circuit. In this embodiment, the relationship between the sizes of the first element, the second element, and the third element is optimally set to satisfy the relationship in equation (1) above, thereby ensuring uniformity of the balance of the pair of drain currents in the differential amplifier circuit.

[0066] Next, the operation and performance of the active balun circuit A according to this embodiment will be described in detail with reference to Figure 1.

[0067] In this active balun circuit A, the input signal (high-frequency signal) input from the signal source to the input terminal Tin is input to the first amplifier circuit via the matching circuit. The first amplifier circuit generates an inverted signal by inverting and amplifying the input signal. This inverted signal is supplied from the first amplifier circuit to the first output terminal Toutn via the third capacitor 9, and is output from the first output terminal Toutn to the subsequent circuit as one of the balanced signals.

[0068] Furthermore, a portion of the inverted signal generated by the first amplifier circuit is input to the second amplifier circuit via the variable capacitor 19. The second amplifier circuit generates a non-inverted signal by inverting and amplifying the inverted signal. This non-inverted signal is supplied from the second amplifier circuit to the second output terminal Toutp via the fourth capacitor 17, and is output from the second output terminal Toutp to the subsequent circuit as the other half of the balanced signal.

[0069] In the basic operation of such an active balun circuit A, the drain terminal of the first transistor 5 of the first amplifier circuit is connected to the source terminal of the second transistor 7, which has a gate-grounded structure with low input impedance. Therefore, the voltage amplitude of the inverted signal at the drain terminal of the first transistor 5 is smaller than the voltage amplitude of the input signal at the gate terminal of the first transistor 5.

[0070] Furthermore, due to the loss of the variable capacitor 19, the voltage amplitude of the inverted signal input from the drain terminal of the first transistor 5 to the gate terminal of the fifth transistor 14 of the second amplifier circuit via the variable capacitor 19 is smaller than the voltage amplitude of the input signal at the gate terminal of the first transistor 5.

[0071] As is well known, the drain current of a MOS transistor is determined by the product of the voltage amplitude of the input signal at the gate terminal and the transconductance gm, which is determined by the size (element size) of the MOS transistor. Therefore, in order to make the collector currents of the first transistor 5 and the fifth transistor 14 equal, the sizes of the first transistor 5 and the fifth transistor 14 should be determined such that they are inversely related to the ratio between the voltage amplitude of the input signal at the gate terminal of the first transistor 5 and the voltage amplitude of the inverted signal at the gate terminal of the fifth transistor 14.

[0072] For example, if the voltage amplitude of the input signal at the gate terminal of the fifth transistor 14 is half (50%) the voltage amplitude of the inverted signal at the gate terminal of the first transistor 5, then the size of the fifth transistor 14 (number of fingers if the gate length is the same) should be set to twice that of the first transistor 5 (the reciprocal of 50%).

[0073] Furthermore, the voltage amplitude of the inverted signal output from the first amplifier circuit is determined by the product of the drain current of the first amplifier circuit and the resistance value of the fourth resistor 8 (the fourth resistance value). Similarly, the voltage amplitude of the non-inverted signal output from the second amplifier circuit is determined by the product of the drain current of the second amplifier circuit and the resistance value of the seventh resistor 16 (the seventh resistance value).

[0074] Furthermore, the fifth capacitor 18 and the variable capacitor 19 function as feedback capacitors for the first and second amplifier circuits that constitute the differential amplifier circuit. In other words, the fifth capacitor 18 and the variable capacitor 19 cancel out the gate-drain parasitic capacitance of the first transistor 5 (first parasitic capacitance Cgd1) and the gate-drain parasitic capacitance of the fifth transistor 14 (fifth parasitic capacitance Cgd5).

[0075] Here, if the relationship between the capacitance of the fifth capacitor 18 (the fifth capacitance C5) and the capacitance of the variable capacitor 19 (the variable capacitance Ck) is set such that C5 < Ck, then the relationship Cgd1 > Cgd5 holds. Suppose that the phases of the input signal at the gate terminal of the first transistor 5 and the inverted signal at the gate terminal of the fifth transistor 14 are aligned as a relatively inverted phase relationship. Then, the phase of the inverted signal generated by the first transistor 5 is relatively delayed with respect to the phase of the non-inverted signal output from the drain terminal of the fifth transistor 14.

[0076] In the active balun circuit A according to this embodiment, the capacitance of the variable capacitor 19 (the variable capacitance Ck) with respect to the capacitance of the fifth capacitor 18 (the fifth capacitance C5) is set so that the phases of the inverted signal output from the drain terminal of the first transistor 5 and the non-inverted signal output from the drain terminal of the fifth transistor 14 are aligned as a relatively inverted phase relationship.

[0077] Regarding the capacitance of the variable capacitor 19 (the variable capacitance Ck), it may be a fixed capacitance similar to the fifth capacitance C5 so that the phases of the inverted signal output from the drain terminal of the first transistor 5 and the non-inverted signal output from the drain terminal of the fifth transistor 14 are aligned as a relatively inverted phase relationship.

[0078] In the active balun circuit A according to this embodiment, instead of adopting a capacitor with a fixed capacitance, a variable capacitor 19 (the variable capacitance Ck) is adopted. That is, in this active balun circuit A, by adjusting the variable capacitance Ck, even when the voltage amplitude and phase related to the drain currents of the first transistor 5 and the fifth transistor 14 change due to variations such as process, power supply voltage, and temperature, the identity of the amplitude and phase between the inverted signal (one of the balanced signals) generated by the first amplifier circuit and the non-inverted signal (the other of the balanced signals) generated by the second amplifier circuit is ensured.

[0079] Furthermore, the first amplifier circuit of this embodiment includes a first cascode circuit consisting of a first transistor 5 and a second transistor 7, as well as a second cascode circuit consisting of a third transistor 11 and a fourth transistor 12. That is, the first amplifier circuit includes a second cascode circuit DC-parallel connected to the first cascode circuit, and both are similarly biased.

[0080] Furthermore, the first transistor 5, the second transistor 7, the third transistor 11, and the fourth transistor 12 are set according to the relationship shown in equation (1) above for each element size. In addition, the first cascode circuit and the second cascode circuit are equally biased by the first bias voltage Vb and the second bias voltage Vcas.

[0081] When the resistance value of the fourth resistor 8 (fourth resistance value) and the resistance value of the seventh resistor 16 (seventh resistance value) are equal, the third drain current Id3 of the third cascode circuit is equal to the sum of the first drain current Id1 of the first cascode circuit and the second drain current Id2 of the second cascode circuit, as shown in equation (2).

[0082] In other words, the bias voltage (DC voltage) at the output terminal of the first amplifier circuit (the output terminal of both the first and second cascode circuits) and the output terminal of the second amplifier circuit (the output terminal of the third cascode circuit) are equal. Therefore, the operating balance of the differential amplifier circuit, which is composed of the first and second amplifier circuits, is set uniformly.

[0083] Figure 2 is a characteristic diagram (simulation result) showing the amplitude balance between the balanced signal of the active balun circuit A according to the first embodiment, i.e., the inverted signal at the first output terminal Toutn and the non-inverted signal at the second output terminal Toutp. In Figure 2, (a) shows the amplitude characteristics of the balanced signal in the active balun circuit A, and (b) shows the amplitude characteristics when the fifth capacitor 18 is omitted from the active balun circuit A.

[0084] This amplitude characteristic indicates that a good amplitude balance of the balanced signal is achieved in both the active balun circuit A according to the first embodiment and the active balun circuit in which the fifth capacitor 18 is omitted from the active balun circuit A.

[0085] Furthermore, this amplitude characteristic shows that, in a comparison between the active balun circuit A according to the first embodiment and the active balun circuit in which the fifth capacitor 18 is omitted from the active balun circuit A, the active balun circuit in which the fifth capacitor 18 is omitted from the active balun circuit A has better amplitude balance in the higher frequency range.

[0086] Furthermore, Figure 3 is a characteristic diagram (simulation result) showing the phase balance of the balanced signal of the active balun circuit A according to the first embodiment. In Figure 3, (a) shows the phase characteristics of the balanced signal in the active balun circuit A, and (b) shows the phase characteristics when the fifth capacitor 18 is omitted from the active balun circuit A.

[0087] This phase characteristic indicates that good phase balance of the balanced signal is achieved in both the active balun circuit A according to the first embodiment and the active balun circuit in which the fifth capacitor 18 is omitted from the active balun circuit A.

[0088] Furthermore, this phase characteristic indicates that, in a comparison between the active balun circuit A according to the first embodiment and the active balun circuit obtained by omitting the fifth capacitor 18 from the active balun circuit A, the active balun circuit A according to the first embodiment has better phase balance in the higher frequency range.

[0089] As shown in Figures 2 and 3, the amplitude characteristics and phase characteristics tend to be inversely related depending on the presence or absence of the fifth capacitor 18. That is, for amplitude balance, omitting the fifth capacitor 18 results in better performance, but for phase balance, not omitting the fifth capacitor 18 results in better performance. However, including the fifth capacitor 18 increases the number of design parameters, which has the advantage of making it easier to find the optimal values ​​for amplitude balance and phase balance.

[0090] The active balun circuit A according to this first embodiment includes a first amplifier circuit comprising a first transistor 5 (first amplification transistor) and a third transistor 11 (third amplification transistor) connected in parallel to the first transistor 5 (first amplification transistor) and biased in the same way as the first transistor 5 (first amplification transistor), which inverts and amplifies an input signal that is an unbalanced signal and outputs an inverted signal that is one side of a balanced signal; and a second amplifier circuit comprising a fifth transistor 14 (second amplification transistor) that is larger in size than the first transistor 5 (first amplification transistor) and biased in the same way as the first transistor 5 (first amplification transistor), which inverts and amplifies the inverted signal and outputs a non-inverted signal that is the other side of a balanced signal.

[0091] According to this first embodiment, since it includes a first amplification circuit comprising a first transistor 5 (first amplification transistor) and a third transistor 11 (third amplification transistor), and a second amplification circuit comprising a fifth transistor 14 (second amplification transistor), it is possible to provide an active balun circuit A in which the balance of the balanced signal is more uniform than in conventional circuits.

[0092] Furthermore, in the active balun circuit A according to the first embodiment, the output of the first transistor 5 (first amplification transistor) and the input of the fifth transistor 14 (second amplification transistor) are electrically connected via a variable capacitor 19 (capacitor). According to this first embodiment, the input level of the inverted signal to the second amplification circuit can be adjusted by adjusting the capacitance of the variable capacitor 19. Therefore, according to the first embodiment, it is possible to make the balance of the balanced signal more uniform.

[0093] Furthermore, in the active balun circuit A according to the first embodiment, the input of the first transistor 5 (first amplification transistor) and the output of the fifth transistor 14 (second amplification transistor) are electrically connected via the fifth capacitor 18. According to this first embodiment, a portion of the non-inverting signal, which is the output of the fifth transistor 14 (second amplification transistor), is negatively fed back to the input of the first amplification circuit, making it possible to further stabilize the operation of the active balun circuit A.

[0094] Furthermore, in the active balun circuit A according to the first embodiment, the second transistor 7, the sixth transistor 15, and the fourth transistor 12 are connected to the first transistor 5 (first amplifier transistor), the fifth transistor 14 (second amplifier transistor), and the third transistor 11 (third amplifier transistor) as cascode transistors, respectively. According to this first embodiment, the frequency characteristics can be improved compared to the case where the cascode transistors are omitted.

[0095] [Second Embodiment] Next, with reference to Figure 4, an active balun circuit B according to a second embodiment of the present invention will be described.

[0096] As shown in the figure, the configuration of the output section in the main circuit of this active balun circuit B differs from that of the active balun circuit A according to the first embodiment. That is, the output section in the main circuit of the active balun circuit A according to the first embodiment is composed of a pair of resistors, namely the fourth resistor 8 and the seventh resistor 16.

[0097] In contrast, the output section of the main circuit of the active balun circuit B according to the second embodiment is composed of two pairs of transistors, namely the seventh transistor 20, the eighth transistor 21, the ninth transistor 22, and the tenth transistor 23.

[0098] The seventh transistor 20 is a p-type MOS transistor having a predetermined size (fourth element size). The gate terminal of this seventh transistor 20 is connected to its own drain terminal, the drain terminal of the second transistor 7, one end of the third capacitor 9, the drain terminal of the fourth transistor 12, the drain terminal of the eighth transistor 21, and the gate terminal of the tenth transistor 23.

[0099] Furthermore, the drain terminal of the seventh transistor 20 is connected to its own gate terminal, the drain terminal of the second transistor 7, one end of the third capacitor 9, the drain terminal of the fourth transistor 12, the drain terminal of the eighth transistor 21, and the gate terminal of the tenth transistor 23. In addition, the source terminal of the seventh transistor 20 is connected to the power supply terminal Td, the source terminal of the eighth transistor 21, the source terminal of the ninth transistor 22, and the source terminal of the tenth transistor 23.

[0100] The eighth transistor 21 is a p-type MOS transistor having the same size (fourth element size) as the seventh transistor 20. The gate terminal of this eighth transistor 21 is connected to the drain terminal of the sixth transistor 15, one end of the fourth capacitor 17, the gate terminal and drain terminal of the ninth transistor 22, and the drain terminal of the tenth transistor 23.

[0101] Furthermore, the drain terminal of the eighth transistor 21 is connected to the drain terminal of the second transistor 7, one end of the third capacitor 9, the drain terminal of the fourth transistor 12, the drain terminal and gate terminal of the seventh transistor 20, and the gate terminal of the tenth transistor 23. In addition, the source terminal of the eighth transistor 21 is connected to the power supply terminal Td, the source terminal of the seventh transistor 20, the source terminal of the ninth transistor 22, and the source terminal of the tenth transistor 23.

[0102] The ninth transistor 22 is a p-type MOS transistor having the same size (fourth element size) as the seventh transistor 20 and the eighth transistor 21. The gate terminal of this ninth transistor 22 is connected to its own drain terminal, the drain terminal of the sixth transistor 15, one end of the fourth capacitor 17, the drain terminal of the tenth transistor 23, and the gate terminal of the eighth transistor 21.

[0103] Furthermore, the drain terminal of the ninth transistor 22 is connected to its own gate terminal, the drain terminal of the sixth transistor 15, one end of the fourth capacitor 17, the drain terminal of the tenth transistor 23, and the gate terminal of the eighth transistor 21. In addition, the source terminal of the ninth transistor 22 is connected to the power supply terminal Td, the source terminal of the seventh transistor 20, the source terminal of the eighth transistor 21, and the source terminal of the tenth transistor 23.

[0104] The 10th transistor 23 is a p-type MOS transistor having the same size (4th element size) as the 7th transistor 20, the 8th transistor 21, and the 9th transistor 22. The gate terminal of this 10th transistor 23 is connected to the drain terminal of the 2nd transistor 7, one end of the 3rd capacitor 9, the drain terminal of the 4th transistor 12, the drain terminal of the 7th transistor 20, and the drain terminal of the 8th transistor 21.

[0105] Furthermore, the drain terminal of the 10th transistor 23 is connected to the drain terminal of the 6th transistor 15, one end of the 4th capacitor 17, the drain terminal and gate terminal of the 9th transistor 22, and the gate terminal of the 8th transistor 21. In addition, the source terminal of the 10th transistor 23 is connected to the power supply terminal Td, the source terminal of the 7th transistor 20, the source terminal of the 8th transistor 21, and the source terminal of the 9th transistor 22.

[0106] In the main circuit of such an active balun circuit B, the first amplifier circuit includes an output section in which the eighth transistor 21 and the seventh transistor 20, which is diode-connected, are connected in parallel. Furthermore, the gate terminal of the eighth transistor 21, which constitutes the output section of the first amplifier circuit, is connected to the output terminal of the second amplifier circuit.

[0107] On the other hand, the second amplifier circuit has an output section in which the 10th transistor 23 and the 9th transistor 22, which is diode-connected, are connected in parallel. Furthermore, the gate terminal of the 10th transistor 23, which constitutes the output section of the second amplifier circuit, is connected to the output terminal of the first amplifier circuit.

[0108] According to this second embodiment, since the output section of the main circuit is composed of the seventh transistor 20, the eighth transistor 21, the ninth transistor 22, and the tenth transistor 23, in addition to the effects of the active balun circuit A according to the first embodiment, it is possible to provide an active balun circuit B with better frequency characteristics than the active balun circuit A according to the first embodiment.

[0109] It should be noted that the present invention is not limited to the embodiments described above, and the following modifications are possible, for example. (1) In each of the above embodiments, the output of the first transistor 5 (first amplification transistor) and the input of the fifth transistor 14 (second amplification transistor) are electrically connected via a variable capacitor 19, but the present invention is not limited thereto. For example, a capacitor with a fixed capacitance may be used instead of the variable capacitor 19.

[0110] (2) In each of the above embodiments, a fifth capacitor 18 is provided as a feedback capacitor to electrically connect the input of the first transistor 5 (first amplification transistor) and the output of the fifth transistor 14 (second amplification transistor), but the present invention is not limited thereto. That is, the fifth capacitor 18 (feedback capacitor) may be omitted if necessary.

[0111] (3) In the above embodiment, the second transistor 7, the sixth transistor 15, and the fourth transistor 12 were connected as cascode transistors to the first transistor 5 (first amplifier transistor), the fifth transistor 14 (second amplifier transistor), and the third transistor 11 (third amplifier transistor), respectively, but the present invention is not limited thereto. That is, the second transistor 7, the sixth transistor 15, and the fourth transistor 12 (cascode transistors) may be omitted as needed.

[0112] (4) In the above embodiment, the source terminal of the first transistor 5 (first amplification transistor), the source terminal of the fifth transistor 14 (second amplification transistor), and the source terminal of the third transistor 11 (third amplification transistor), that is, the common-mode output terminals of the first amplification circuit and the second amplification circuit, were connected in common. However, the present invention is not limited thereto. For example, the common-mode output terminals of the first amplification circuit and the second amplification circuit may be interconnected via circuit elements such as resistors. [Explanation of symbols]

[0113] A, B…Active balun circuit, Tb1…First bias terminal, Tb2…Second bias terminal, Tb3…Third bias terminal, Tb4…Fourth bias terminal, Td…Power supply terminal, Tin…Input terminal, Toutn…First output terminal, Toutp…Second output terminal, 1…First capacitor, 2…First resistor, 3…Second capacitor, 4…Second resistor, 5…First transistor, 6…Third resistor, 7…Second transistor, 8…Fourth resistor, 9…Third capacitor, 10…Fifth resistor, 11…Third transistor, 12…Fourth transistor, 13…Sixth resistor, 14…Fifth transistor, 15…Sixth transistor, 16…Seventh resistor, 17…Fourth capacitor, 18…Fifth capacitor, 19…Variable capacitor, 20…Seventh transistor, 21…Eighth transistor, 22…Ninth transistor, 23…Tenth transistor

Claims

1. A first amplification circuit comprising a first amplification transistor and a third amplification transistor connected in parallel to the first amplification transistor and biased in the same way as the first amplification transistor, which inverts and amplifies an input signal that is a non-balanced signal and outputs an inverted signal that is one side of a balanced signal, The second amplification circuit comprises a second amplification transistor that is larger in size than the first amplification transistor and biased in the same way as the first amplification transistor, and inverts and amplifies the inverted signal to output a non-inverted signal which is the other half of the balanced signal. An active balun circuit characterized by having the following features.

2. The active balun circuit according to claim 1, characterized in that the output of the first amplification transistor and the input of the second amplification transistor are electrically connected via a capacitor.

3. The active balun circuit according to claim 1 or 2, characterized in that the input of the first amplification transistor and the output of the second amplification transistor are electrically connected via a capacitor.

4. The active balun circuit according to claim 1 or 2, characterized in that a cascode transistor is connected to each of the first, second, and third amplification transistors.

5. The active balun circuit according to claim 1 or 2, characterized in that the first amplification transistor, the second amplification transistor, and the third amplification transistor are connected in common to either their source terminal or emitter terminal.

6. The active balun circuit according to claim 2, characterized in that the capacitor is a variable capacitor.

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