Imaging device

Abstract

The present invention provides an imaging device that can speed up the readout of pixel signals when the number of pixel signals read out is reduced. [Solution] The imaging device comprises a pixel array having m first pixels and m second pixels arranged vertically, wherein the m first pixels output m first pixel signals and n second pixel signals, and the m second pixels output m third pixel signals and n fourth pixel signals, where n is less than m; m vertical signal lines including n first vertical signal lines and n second vertical signal lines; a control circuit that performs a first control to transmit the m first pixel signals to the m vertical signal lines and then transmit the m third pixel signals to the m vertical signal lines, and a second control to transmit the n second pixel signals to the n first vertical signal lines and simultaneously transmit the n fourth pixel signals to the n second vertical signal lines.

Description

Technical Field

[0001] This disclosure relates to an imaging device.

Background Art

[0002] Patent Document 1 discloses an imaging device. In the imaging device, unit pixels are arranged in a matrix. Also, four vertical signal lines are arranged for each column. The four vertical signal lines are respectively connected to four unit pixels provided in each column. The reading circuit reads the signals of the four unit pixels via the four vertical signal lines. Thereby, the reading unit can simultaneously read the signals of the unit pixels provided in four rows, and can speed up the reading of the signals (paragraphs 0012, 0014, 0023, and 0032).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an imaging device, it may be desired to speed up the reading of signals by reducing the number of signals read by pixel sharing or the like. However, in an imaging device, when the number of signals read is reduced, the number of vertical signal lines used for reading the signals is reduced, and it becomes a problem that the reading of the signals cannot be speeded up.

[0005] One aspect of this disclosure has been made in view of this problem. One aspect of this disclosure aims to provide, for example, an imaging device capable of speeding up the reading of pixel signals when the number of pixel signals read is reduced.

Means for Solving the Problems

[0006] An imaging device according to one aspect of this disclosure is: A pixel array comprising m first pixels and m second pixels arranged vertically, wherein the m first pixels output m first pixel signals and n second pixel signals, and the m second pixels output m third pixel signals and n fourth pixel signals, where n is less than m. m vertical signal lines including n first vertical signal lines and n second vertical signal lines, A control circuit that performs a first control, which involves transmitting the m first pixel signals to the m vertical signal lines and then transmitting the m third pixel signals to the m vertical signal lines, and a second control, which involves transmitting the n second pixel signals to the n first vertical signal lines and simultaneously transmitting the n fourth pixel signals to the n second vertical signal lines. It is equipped with. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of the imaging device according to the first embodiment. [Figure 2A] This is a block diagram showing the state when the first control is performed by the control circuit provided in the imaging device of the first embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit. [Figure 2B] This is a block diagram showing the state when the first control is performed by the control circuit provided in the imaging device of the first embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit. [Figure 3] This is a block diagram showing the state when the second control is performed by the control circuit provided in the imaging device of the first embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit. [Figure 4] This is a flowchart showing the first control flow performed by the control circuit provided in the imaging device of the first embodiment. [Figure 5] This flowchart shows the second control flow performed by the control circuit provided in the imaging device of the first embodiment. [Figure 6] This is a circuit diagram of the first odd-numbered pixels and the first even-numbered pixels provided in the imaging device of the first embodiment. [Figure 7] This is a circuit diagram of the second odd-numbered pixels and the second even-numbered pixels provided in the imaging device of the first embodiment. [Figure 8A] This block diagram shows the state when a second control is performed on the control circuit provided in the imaging device, which is equipped with m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit, as shown in the reference example. [Figure 8B] This block diagram shows the state when a second control is performed on the control circuit provided in the imaging device, which is equipped with m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit, as shown in the reference example. [Figure 9] This is a block diagram showing the state when the second control is performed by the control circuit provided in the imaging device of the second embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit. [Modes for carrying out the invention]

[0008] The embodiments of this disclosure will be described below with reference to the drawings. In the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] 1. First Embodiment 1.1 Imaging device Figure 1 is a block diagram of the imaging device according to the first embodiment.

[0010] The imaging device 1 of the first embodiment shown in FIG. 1 captures an image and outputs an image signal corresponding to the captured image. The imaging device 1 is a solid-state imaging device. The solid-state imaging device is a complementary metal oxide semiconductor (CMOS) image sensor. The techniques described below may also be employed in imaging devices other than CMOS image sensors.

[0011] As shown in FIG. 1, the imaging device 1 includes a pixel unit 101, a vertical scanning circuit 102, an analog / digital conversion circuit 103, and a controller 104.

[0012] As shown in FIG. 1, the pixel unit 101 includes p×q pixels 111, p row selection lines 112, and q vertical signal line groups

[0013] The p×q pixels 111 are arranged in a matrix. Therefore, the p×q pixels 111 constitute a pixel array of p rows and q columns. Thus, the p×q pixels 111 include p rows 121 and q columns 122. Each row 121 included in the p rows 121 has q pixels 111 belonging to it. Each column 122 included in the q columns 122 has p pixels 111 belonging to it. Each pixel 111 included in the p×q pixels 111 receives light, generates electric charges corresponding to the intensity of the received light, and accumulates the generated electric charges. Each pixel 111 discharges the accumulated electric charges when a row selection pulse 131 is applied to each pixel 111.

[0014] The p row selection lines 112 respectively correspond to the p rows 121. Each row selection line 112 included in the p row selection lines 112 is electrically connected to the vertical scanning circuit 102 and is electrically connected to the q pixels 111 belonging to the row 121 corresponding to each row selection line 112. Therefore, each row selection line 112 transmits the row selection pulse 131 output by the vertical scanning circuit 102 from the vertical scanning circuit 102 to the q pixels 111 and applies the transmitted row selection pulse 131 to the q pixels

[0015] The q vertical signal lines 113 correspond to q columns 122 respectively. Each vertical signal line group 113 included in the q vertical signal line groups 113 is electrically connected to p pixels 111 belonging to the column 122 to which each vertical signal line group 113 corresponds, and is also electrically connected to the analog / digital conversion circuit 103. Therefore, each vertical signal line group 113 transmits an analog signal 141 indicating the amount of charge discharged by the pixels 111 included in the p pixels 111 from the pixels 111 to the analog / digital conversion circuit 103, and supplies the transmitted analog signal 141 to the analog / digital conversion circuit 103. The supplied analog signal 141 has a voltage corresponding to the intensity of the light received by the pixel 111. The voltage of the analog signal 141 becomes lower as the intensity of the light received by the pixel 111 increases. The absolute value of the voltage of the analog signal 141 becomes larger as the intensity of the light received by the pixel 111 increases.

[0016] The vertical scanning circuit 102 scans the pixel section 101 in the vertical direction. The vertical scanning circuit 102 simultaneously selects r row selection lines 112 from the p row selection lines 112, and transmits a row selection pulse 131 to the selected r row selection lines 112. The vertical scanning circuit 102 sequentially changes the r row selection lines 112 to be selected. In this embodiment, r is 4. r may be any integer of 2 or more, and may be increased or decreased from 4.

[0017] Thereby, the pixel section 101 and the vertical scanning circuit 102 simultaneously supply r×q analog signals 141 indicating the amounts of charge discharged by the r×q pixels 111 belonging to the r rows 121 selected from the p rows 121 to the analog / digital conversion circuit 103. That is, the imaging device 1 can perform r - row simultaneous reading. The pixel section 101 and the vertical scanning circuit 102 sequentially change the r rows 121 to be selected.

[0018] The analog-to-digital conversion circuit 103 converts r × q analog signals 141 into r × q digital signals and outputs the resulting r × q digital signals. The output r × q digital signals constitute an image signal. The grayscale values ​​represented by the output r × q digital signals increase as the voltage of the r × q analog signals 141 decreases, and increase as the absolute value of the voltage of the r × q analog signals 141 increases.

[0019] The controller 104 controls the pixel unit 101, the vertical scanning circuit 102, and the analog / digital conversion circuit 103 to cause the pixel unit 101, the vertical scanning circuit 102, and the analog / digital conversion circuit 103 to perform the operations described below. The controller 104 is composed of electronic circuits. The vertical scanning circuit 102 and the controller 104 constitute a control circuit 151 that performs the first and second controls described below.

[0020] 1.2 Speeding up pixel signal readout when the number of pixel signals read out is reduced Figures 2A and 2B are block diagrams showing the state when the first control is performed by a control circuit provided in the imaging device of the first embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit. Figure 3 is a block diagram showing the state when the second control is performed by a control circuit provided in the imaging device of the first embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit.

[0021] Each row 122 comprises multiple pixel groups. These pixel groups are arranged vertically. As shown in Figures 2A, 2B, and 3, each pixel group 171 included in the multiple pixel groups comprises m first pixels 161 and m second pixels 162. The 2m pixels, consisting of m first pixels 161 and m second pixels 162, are arranged vertically.

[0022] As shown in Figure 2A, when the first control is performed and the vertical resolution is set to the maximum resolution, the m first pixels 161 perform a first operation in which they each output m first pixel signals 181. As shown in Figure 3, when the second control is performed and the vertical resolution is set to a resolution lower than the maximum resolution, the m first pixels 161 perform a second operation in which they combine the m first pixels 161 to form n first shared pixels 191, and each of the n first shared pixels 191 outputs n second pixel signals 201. As shown in Figure 2B, when the first control is performed and the vertical resolution is set to the maximum resolution, the m second pixels 162 perform a third operation in which they each output m third pixel signals 182. As shown in Figure 3, when the second control is performed and the vertical resolution is set to a resolution lower than the maximum resolution, the m second pixels 162 perform a fourth operation in which they combine the m second pixels 162 to form n second shared pixels 192, and each of the n second shared pixels 192 outputs n fourth pixel signals 202. In this embodiment, the resolution lower than the maximum resolution is half the resolution of the maximum resolution. Therefore, n is half of m. n only needs to be smaller than m and may be other than half of m.

[0023] As shown in Figures 2A, 2B, and 3, each group of vertical signal lines 113 comprises m vertical signal lines 211. The m vertical signal lines 211 include n first vertical signal lines 221 and n second vertical signal lines 222.

[0024] The m vertical signal lines 211 are electrically connected to m first pixels 161, each electrically connected to m second pixels 162, and each electrically connected to the analog / digital conversion circuit 103. The n first vertical signal lines 221 are electrically connected to n first shared pixels 191, each electrically connected to the analog / digital conversion circuit 103. The n second vertical signal lines 222 are electrically connected to n second shared pixels 192, each electrically connected to the analog / digital conversion circuit 103. As a result, the m vertical signal lines 211 transmit m first pixel signals 181 from the m first pixels 161 to the analog / digital conversion circuit 103, and m third pixel signals 182 from the m second pixels 162 to the analog / digital conversion circuit 103. The n first vertical signal lines 221 each transmit n second pixel signals 201 from the n first shared pixels 191 to the analog / digital conversion circuit 103. The n second vertical signal lines 222 each transmit n fourth pixel signals 202 from the m n second shared pixels 192 to the analog / digital conversion circuit 103.

[0025] The analog / digital conversion circuit 103 converts m first pixel signals 181 that have been transmitted into m digital signals, converts m third pixel signals 182 that have been transmitted into m digital signals, converts n second pixel signals 201 that have been transmitted into n digital signals, and converts n fourth pixel signals 202 that have been transmitted into n digital signals.

[0026] Figure 4 is a flowchart showing the first control flow performed by the control circuit provided in the imaging device of the first embodiment.

[0027] When the control circuit 151 performs the first control to set the vertical resolution to the maximum resolution, it performs step S101 shown in Figure 4, followed by step S102 shown in Figure 4, for each pixel group 171.

[0028] In step S101, the control circuit 151 causes m first pixels 161 to perform a first operation. As a result, the control circuit 151 causes the m first pixels 161 to output m first pixel signals 181, and transmits the output m first pixel signals 181 to m vertical signal lines 211.

[0029] In step S102, the control circuit 151 causes m second pixels 162 to perform a third operation. As a result, the control circuit 151 causes the m second pixels 162 to output m third pixel signals 182, and transmits the output m third pixel signals 182 to the m vertical signal lines 211.

[0030] Figure 5 is a flowchart showing the flow of the second control performed by the control circuit provided in the imaging device of the first embodiment.

[0031] When the control circuit 151 performs a second control to set the vertical resolution to a resolution lower than the maximum resolution, it simultaneously executes steps S111 and S112 shown in Figure 5 for each pixel group 171.

[0032] In step S111, the control circuit 151 causes m first pixels 161 to perform a second operation. As a result, the control circuit 151 causes the m first pixels 161 to output n second pixel signals 201, and transmits the output n second pixel signals 201 to n first vertical signal lines 221.

[0033] In step S112, the control circuit 151 causes m second pixels 162 to perform a fourth operation. As a result, the control circuit 151 causes the m second pixels 162 to output n fourth pixel signals 202, and transmits the output n fourth pixel signals 202 to n second vertical signal lines 222.

[0034] When the control circuit 151 performs the first control, it transmits m first pixel signals 181 through m vertical signal lines 211, as shown in Figure 2A, and then transmits m third pixel signals 182 through m vertical signal lines 211, as shown in Figure 2B. When the first control is performed, the m vertical signal lines 211 cannot be used simultaneously for reading out the m first pixel signals 181 and the m third pixel signals 182. For this reason, the reading out of the m first pixel signals 181 and the m third pixel signals 182 is performed in two cycles.

[0035] When the control circuit 151 performs the second control, as shown in Figure 3, it transmits n second pixel signals 201 through n first vertical signal lines 221 and simultaneously transmits n fourth pixel signals 202 through n second vertical signal lines 222. When the second control is performed, the n first vertical signal lines 221 can be used to read out the n second pixel signals 201, and at the same time, the n second vertical signal lines 222 can be used to read out the n fourth pixel signals 202. As a result, the reading out of n second pixel signals 201 and n fourth pixel signals 202 is performed in one cycle. This makes it possible to read out the n second pixel signals 201 and n fourth pixel signals 202 when the vertical resolution is lower than the maximum resolution faster than reading out the m first pixel signals 181 and m third pixel signals 182 when the vertical resolution is set to the maximum resolution. This allows for faster reading of pixel signals when the number of pixel signals read out is reduced. If the resolution lower than the maximum resolution is half the maximum resolution, the time required to read out n second pixel signals 201 and n fourth pixel signals 202 when the vertical resolution is lower than the maximum resolution is half the time required to read out m first pixel signals 181 and m third pixel signals 182 when the vertical resolution is the maximum resolution.

[0036] In the first embodiment, when the vertical resolution is lower than the maximum resolution, the vertical resolution is set to half of the maximum resolution. When the vertical resolution is half of the maximum resolution, each pixel group 171 is divided into two sets of pixel groups consisting of m first pixels 161 and m second pixels 162, and the m vertical signal lines 211 are divided into two sets of vertical signal line groups consisting of n first vertical signal lines 221 and n second vertical signal lines 222, and the pixel signals output by the two sets of pixel groups are transmitted by the two sets of vertical signal line groups, respectively. However, the vertical resolution may be set to one-third or less of the maximum resolution. When the vertical resolution is 1 / N of the maximum resolution, each pixel group 171 is divided into N sets of pixel groups, the m vertical signal lines 211 are divided into N sets of vertical signal line groups, and the pixel signals output by the N sets of pixel groups may be transmitted simultaneously by the N sets of vertical signal line groups, respectively.

[0037] 1.3 Pixel Circuit Figure 6 is a circuit diagram of the first odd-numbered pixel and the first even-numbered pixel provided in the imaging device of the first embodiment. Figure 7 is a circuit diagram of the second odd-numbered pixel and the second even-numbered pixel provided in the imaging device of the first embodiment. In Figures 6 and 7, the reset transistors provided in the first odd-numbered pixel, the first even-numbered pixel, the second odd-numbered pixel, and the second even-numbered pixel are omitted.

[0038] As shown in Figures 2A, 2B, 3, 6, and 7, m first pixels 161 contain n first odd-numbered pixels 231 and n first even-numbered pixels 232. m second pixels 162 contain n second odd-numbered pixels 233 and n second even-numbered pixels 234.

[0039] The n first odd-numbered pixels 231 are pixels positioned in odd positions in the vertical array of m first pixels 161. The n first even-numbered pixels 232 are pixels positioned in even positions in the vertical array of m first pixels 161. Therefore, the first odd-numbered pixels 231 and the first even-numbered pixels 232 are arranged alternately. The n second odd-numbered pixels 233 are pixels positioned in odd positions in the vertical array of m second pixels 162. The n second even-numbered pixels 234 are pixels positioned in even positions in the vertical array of m second pixels 162. Therefore, the second odd-numbered pixels 233 and the second even-numbered pixels 234 are arranged alternately.

[0040] As shown in Figures 2A, 2B, 3, and 6, each of the n first odd-numbered pixels 231 comprises a first photodiode 2311a and 2311b, a first charge transfer path 2312a and 2312b, a first transfer gate transistor 2313a and 2313b, a first floating diffusion (FD) 2314, a first charge discharge path 2315, a first amplification transistor 2316, and a first row selection transistor 2317. Each of the n first even-numbered pixels 232 comprises a second photodiode 2321a and 2321b, a second charge transfer path 2322a and 2322b, a second transfer gate transistor 2323a and 2323b, a second FD 2324, a second charge discharge path 2325, a second amplification transistor 2326, and a second row selection transistor 2327. As shown in Figures 2A, 2B, 3, and 7, each second odd-numbered pixel 233 in the n second odd-numbered pixels 233 comprises a third photodiode 2331a and 2331b, a third charge transfer path 2332a and 2332b, a third transfer gate transistor 2333a and 2333b, a third FD 2334, a third charge discharge path 2335, a third amplification transistor 2336, and a third row selection transistor 2337. Each of the n second even-numbered pixels 234 comprises a fourth photodiode 2341a and 2341b, a fourth charge transfer path 2342a and 2342b, a fourth transfer gate transistor 2343a and 2343b, a fourth FD 2344, a fourth charge discharge path 2345, a fourth amplification transistor 2346, and a fourth row selection transistor 2347.

[0041] Each of the first photodiodes 2311a and 2311b generates an electric charge corresponding to the intensity of light received by each first odd-numbered pixel 231. Each of the second photodiodes 2321a and 2321b generates an electric charge corresponding to the intensity of light received by each first even-numbered pixel 232. Each of the third photodiodes 2331a and 2331b generates an electric charge corresponding to the intensity of light received by each second odd-numbered pixel 233. Each of the fourth photodiodes 2341a and 2341b generates an electric charge corresponding to the intensity of light received by each second even-numbered pixel 234.

[0042] The first charge transfer paths 2312a and 2312b lead from the first photodiodes 2311a and 2311b to the first FD2314, respectively. The second charge transfer paths 2322a and 2322b lead from the second photodiodes 2321a and 2321b to the second FD2324, respectively. The third charge transfer paths 2332a and 2332b lead from the third photodiodes 2331a and 2331b to the third FD2334, respectively. The fourth charge transfer paths 2342a and 2342b lead from the fourth photodiodes 2341a and 2341b to the fourth FD2344, respectively.

[0043] When the first charge transfer paths 2312a and 2312b are closed, they transfer the charge generated by the first photodiodes 2311a and 2311b from the first photodiodes 2311a and 2311b to the first FD2314, respectively. When they are open, they do not transfer the charge. When the second charge transfer paths 2322a and 2322b are closed, they transfer the charge generated by the second photodiodes 2321a and 2321b from the second photodiodes 2321a and 2321b to the second FD2324, respectively. When they are open, they do not transfer the charge. If the third charge transfer paths 2332a and 2332b are closed, they transfer the charge generated by the third photodiodes 2331a and 2331b from the third photodiodes 2331a and 2331b to the third FD2334, respectively. If they are open, they do not transfer the charge. If the fourth charge transfer paths 2342a and 2342b are closed, they transfer the charge generated by the fourth photodiodes 2341a and 2341b from the fourth photodiodes 2341a and 2341b to the fourth FD2344, respectively. If they are open, they do not transfer the charge.

[0044] The first transfer gate transistors 2313a and 2313b open and close the first charge transfer paths 2312a and 2312b, respectively. The second transfer gate transistors 2323a and 2323b open and close the second charge transfer paths 2322a and 2322b, respectively. The third transfer gate transistors 2333a and 2333b open and close the third charge transfer paths 2332a and 2332b, respectively. The fourth transfer gate transistors 2343a and 2343b open and close the fourth charge transfer paths 2342a and 2342b, respectively.

[0045] The first FD2314 stores the charge transferred via the first charge transfer paths 2312a and 2312b. The second FD2324 stores the charge transferred via the second charge transfer paths 2322a and 2322b. The third FD2334 stores the charge transferred via the third charge transfer paths 2332a and 2332b. The fourth FD2344 stores the charge transferred via the fourth charge transfer paths 2342a and 2342b.

[0046] The n first charge discharge paths 2315 provided in the n first odd-numbered pixels 231 each lead from the n first FDs 2314 provided in the n first odd-numbered pixels 231 to the n first vertical signal lines 221. The n second charge discharge paths 2325 provided in the n first even-numbered pixels 232 each lead from the n second FDs 2324 provided in the n first even-numbered pixels 232 to the n second vertical signal lines 222. The n third charge discharge paths 2335 provided in the n second odd-numbered pixels 233 each lead from the n third FDs 2334 provided in the n second odd-numbered pixels 233 to the n first vertical signal lines 221. The n fourth charge discharge paths 2345 provided in the n second even-numbered pixels 234 each lead from the n fourth FDs 2344 provided in the n second even-numbered pixels 234 to the n second vertical signal lines 222.

[0047] If the n first charge discharge paths 2315 are closed, they transmit the charge accumulated in the n first FDs 2314 from the n first FDs 2314 to the n first vertical signal lines 221, respectively. If they are open, they do not transmit the charge. If the n second charge discharge paths 2325 are closed, they transmit the charge accumulated in the n second FDs 2324 from the n second FDs 2324 to the n second vertical signal lines 222, respectively. If they are open, they do not transmit the charge. If the n third charge discharge paths 2335 are closed, they transmit the charge accumulated in the n third FDs 2334 from the n third FDs 2334 to the n first vertical signal lines 221, respectively. If they are open, they do not transmit the charge. When the n fourth charge discharge paths 2345 are closed, they transmit the charge accumulated in the n fourth FDs 2344 from the n fourth FDs 2344 to the n second vertical signal lines 222, respectively. When they are open, they do not transmit the charge.

[0048] The first amplifying transistor 2316 amplifies the charge discharged by the first charge discharge path 2315. The second amplifying transistor 2326 amplifies the charge discharged by the second charge discharge path 2325. The third amplifying transistor 2336 amplifies the charge discharged by the third charge discharge path 2335. The fourth amplifying transistor 2346 amplifies the charge discharged by the fourth charge discharge path 2345.

[0049] The n first row selection transistors 2317 provided in the n first odd-numbered pixels 231 each open and close the n first charge discharge paths 2315. The n second row selection transistors 2327 provided in the n first even-numbered pixels 232 each open and close the n second charge discharge paths 2325. The n third row selection transistors 2337 provided in the n second odd-numbered pixels 233 each open and close the n third charge discharge paths 2335. The n fourth row selection transistors 2347 provided in the n second even-numbered pixels 234 each open and close the n fourth charge discharge paths 2345.

[0050] Each m first pixel 161 comprises n first charge mixing paths 241 and n first transistors 242. Each m second pixel 162 comprises n second charge mixing paths 251 and n second transistors 252.

[0051] The n first charge mixing paths 241 each lead from n first FD2314 to n second FD2324. The n second charge mixing paths 251 each lead from n third FD2334 to n fourth FD2344.

[0052] When the first charge mixing path 241 is closed, it causes the first FD2314 and the second FD2324 to conduct to each other, and when it is open, it prevents the first FD2314 and the second FD2324 from conducting to each other. When the first charge mixing path 241 is closed, the charge accumulated in the first FD2314 and the charge accumulated in the second FD2324 are mixed to each other. As a result, the first FD2314 and the second FD2324 are integrated, and a first shared pixel 191 having integrated FDs is formed. When the second charge mixing path 251 is closed, it causes the third FD2334 and the fourth FD2344 to conduct to each other, and when it is open, it prevents the third FD2334 and the fourth FD2344 from conducting to each other. When the second charge mixing path 251 is closed, the charge accumulated in the third FD2334 and the charge accumulated in the fourth FD2344 are mixed with each other. As a result, the third FD2334 and the fourth FD2344 are integrated, forming a second shared pixel 192 having the integrated FD.

[0053] The charge accumulated in the integrated FD provided in the first shared pixel 191 can be discharged by either the first charge discharge path 2315 or the second charge discharge path 2325. The charge accumulated in the integrated FD provided in the second shared pixel 192 can be discharged by either the third charge discharge path 2335 or the fourth charge discharge path 2345. When the second control is performed, in order to utilize all m vertical signal lines 211, the charge accumulated in the integrated FD provided in the first shared pixel 191 is discharged by the first charge discharge path 2315, which is electrically connected to the first vertical signal line 221. In addition, the charge accumulated in the integrated FD provided in the second shared pixel 192 is discharged by the fourth charge discharge path 2345, which is electrically connected to the second vertical signal line 222.

[0054] Each of the n first transistors 242 opens and closes the n first charge mixing paths 241. Each of the n second transistors 252 opens and closes the n second charge mixing paths 251.

[0055] In steps S101 and S102, which are performed when the first control is carried out, the control circuit 151 inputs an off signal to n first transistors 242 to open n first charge mixing paths 241, as shown in Figures 2A and 2B, and inputs an off signal to n second transistors 252 to open n second charge mixing paths 251. As a result, m first pixels 161 can accumulate charge in their independent FDs and output m first pixel signals 181, and m second pixels 162 can accumulate charge in their independent FDs and output m third pixel signals 182.

[0056] In step S101, which is performed when the first control is carried out, the control circuit 151, as shown in Figure 2A, inputs an ON signal to n first row selection transistors 2317 to close the n first charge discharge paths 2315, inputs an ON signal to n second row selection transistors 2327 to close the n second charge discharge paths 2325, inputs an OFF signal to n third row selection transistors 2337 to open the n third charge discharge paths 2335, and inputs an OFF signal to n fourth row selection transistors 2347 to open the n fourth charge discharge paths 2345. As a result, the control circuit 151 causes m first pixels 161 to output m first pixel signals 181, and does not cause m second pixels 162 to output pixel signals.

[0057] In step S102, which is performed when the first control is carried out, the control circuit 151, as shown in Figure 2B, inputs an off signal to n first row selection transistors 2317 to open n first charge discharge paths 2315 to the n first row selection transistors 2317, inputs an off signal to n second row selection transistors 2327 to open n second charge discharge paths 2325 to the n second row selection transistors 2327, inputs an on signal to n third row selection transistors 2337 to close n third charge discharge paths 2335 to the n third row selection transistors 2337, and inputs an on signal to n fourth row selection transistors 2347 to close n fourth charge discharge paths 2345 to the n fourth row selection transistors 2347. As a result, the control circuit 151 does not cause the m first pixels 161 to output pixel signals, but causes the m second pixels 162 to output m third pixel signals 182.

[0058] In steps S111 and S112, which are performed when the second control is carried out, the control circuit 151 inputs an ON signal to n first transistors 242 to cause the n first charge mixing paths 241 to close, as shown in Figure 3, and inputs an ON signal to n second transistors 252 to cause the n second charge mixing paths 251 to close. This results in the formation of n first shared pixels 191 and n second shared pixels 192.

[0059] In step S111, which is performed when the second control is carried out, the control circuit 151 inputs an ON signal to n first row selection transistors 2317 to close the n first charge discharge paths 2315, as shown in Figure 3, and inputs an OFF signal to n second row selection transistors 2327 to open the n second charge discharge paths 2325. As a result, the control circuit 151 causes the n first shared pixels 191 to output n second pixel signals 201 via the n first charge discharge paths 2315.

[0060] In step S112, which is performed when the second control is carried out, the control circuit 151 inputs an off signal to n third row selection transistors 2337 to open n third charge discharge paths 2335, as shown in Figure 3, and inputs an on signal to n fourth row selection transistors 2347 to close n fourth charge discharge paths 2345. As a result, the control circuit 151 causes n second shared pixels 192 to output n fourth pixel signals 202 via n fourth charge discharge paths 2345.

[0061] If the second control is performed, the control signal input to the row selection transistor for every four pixels is inverted between an on signal and an off signal.

[0062] The transfer of charges generated by the first photodiode 2311a, the second photodiode 2321a, the third photodiode 2331a, and the fourth photodiode 2341a to the first FD2314, the second FD2324, the third FD2334, and the fourth FD2344, and the discharge of said charges from the first FD2314, the second FD2324, the third FD2334, and the fourth FD2344, are performed first. The transfer of charges generated by the first photodiode 2311b, second photodiode 2321b, third photodiode 2331b, and fourth photodiode 2341b to the first FD2314, second FD2324, third FD2334, and fourth FD2344, and the discharge of such charges from the first FD2314, second FD2324, third FD2334, and fourth FD2344, occur later. That is, the first photodiode 2311a, second photodiode 2321a, third photodiode 2331a, and fourth photodiode 2341a are read ahead. Also, the first photodiode 2311b, second photodiode 2321b, third photodiode 2331b, and fourth photodiode 2341b are read behind.

[0063] 1.4 Comparison of Reference Examples and the First Embodiment Figures 8A and 8B are block diagrams showing the state when the second control is performed by the control circuit provided in the reference example imaging device, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit.

[0064] In the example shown in Figure 8A, n first vertical signal lines 221 transmit n second pixel signals 201 output by n first shared pixels 191 to the analog / digital conversion circuit 103. Also, as shown in Figure 8B, n first vertical signal lines 221 transmit n fourth pixel signals 202 output by n second shared pixels 192 to the analog / digital conversion circuit 103. However, n first vertical signal lines 221 cannot be used simultaneously for reading out n second pixel signals 201 and n fourth pixel signals 202. Therefore, in the imaging device of the reference example, n first vertical signal lines 221 transmit n second pixel signals 201, and then the n first vertical signal lines 221 transmit n fourth pixel signals 202. The n second vertical signal lines 222 are not used for reading out the pixel signals. The part of the analog / digital conversion circuit 103 that converts the pixel signals transmitted by the n second vertical signal lines 222 from analog to digital is also not used for analog / digital conversion of the pixel signals. Therefore, when the number of pixel signals to be read out is reduced, the capabilities of each vertical signal line group 113 and the analog / digital conversion circuit 103 are not utilized, and the reading of pixel signals cannot be increased in speed.

[0065] In contrast, in the first embodiment, as shown in Figure 3, n first vertical signal lines 221 transmit n second pixel signals 201 output by n first shared pixels 191 from the n first shared pixels 191 to the analog / digital conversion circuit 103. Also, n second vertical signal lines 222 transmit n fourth pixel signals 202 output by n second shared pixels 192 from the n second shared pixels 192 to the analog / digital conversion circuit 103. It is possible to use the n first vertical signal lines 221 to read out the n second pixel signals 201 and simultaneously use the n second vertical signal lines 222 to read out the n fourth pixel signals 202. Therefore, in the imaging device 1 of the first embodiment, n first vertical signal lines 221 transmit n second pixel signals 201, and at the same time, n second vertical signal lines 222 transmit n fourth pixel signals 202. All m vertical signal lines 211 are used. The part of the analog / digital conversion circuit 103 that converts the pixel signals transmitted by the n second vertical signal lines 222 from analog to digital is also used. Therefore, when the number of pixel signals to be read out is reduced, the capabilities of each vertical signal line group 113 and the analog / digital conversion circuit 103 are utilized, and the readout of pixel signals can be accelerated.

[0066] 2. Second Embodiment The following describes the differences between the second embodiment and the first embodiment. For aspects not described, the same configuration as that used in the first embodiment is used in the second embodiment.

[0067] Figure 9 is a block diagram showing the state when the second control is performed by the control circuit provided in the imaging device of the second embodiment, which includes m first pixels, m second pixels, m vertical signal lines, and an analog / digital conversion circuit.

[0068] In the second embodiment, when the second control is performed on m first pixels 161 and the vertical resolution is set to a resolution lower than the maximum resolution, a second operation is performed in which n second pixel signals 201 are output from n first remaining pixels 261 that remain from the m first pixels 161 through pixel decimation. Also, when the second control is performed on m second pixels 162 and the vertical resolution is set to a resolution lower than the maximum resolution, a fourth operation is performed in which n fourth pixel signals 202 are output from n second remaining pixels 262 that remain from the m second pixels 162 through pixel decimation. In this way, even when the resolution is reduced by pixel decimation, the readout of pixel signals can be accelerated when the number of pixel signals read out is reduced, just as when the resolution is reduced by pixel sharing.

[0069] This disclosure is not limited to the embodiments described above, and may be replaced with configurations that are substantially the same as those shown in the embodiments, configurations that produce the same effects, or configurations that can achieve the same purpose. [Explanation of Symbols]

[0070] 1. Imaging device 101 pixel section 102 Vertical scanning circuit 103 Analog / Digital Conversion Circuit 104 Controller 111 pixels 112 row selection lines 113 Vertical signal line group 121 lines 122 columns 131 row selection pulse 141 Analog signals 151 Control Circuit 161 First pixel 162 Second pixel 171 Each pixel group 181 First pixel signal 182 Third pixel signal 191 First shared pixel 192 Second shared pixel 201 Second pixel signal 202 Fourth pixel signal 211 Vertical signal line 221 First vertical signal line 222 Second vertical signal line 231 The first odd-numbered pixel 232 The first even-numbered pixel 233 The second odd-numbered pixel 234 The second even-numbered pixel 2311a, 2311b First photodiode 2312a, 2312b First charge transfer path 2313a, 2313b First transfer gate transistor 2314 First Floating Diffusion (FD) 2315 First charge discharge pathway 2316 First Amplifying Transistor 2317 First row selection transistor 2321a, 2321b Second photodiode 2322a, 2322b Second charge transfer path 2323a, 2323b Second transfer gate transistor 2324 Second FD 2325 Second charge discharge pathway 2326 Second Amplifying Transistor 2327 Second row selection transistor 2331a, 2331b Third photodiode 2332a, 2332b Third charge transfer path 2333a, 2333b Third transfer gate transistor 2334 Third FD 2335 Third charge discharge pathway 2336 Third Amplifying Transistor 2337 Third row selection transistor 2341a, 2341b Fourth photodiode 2342a, 2342b Fourth charge transfer path 2343a, 2343b Fourth transfer gate transistor 2344 The 4th FD 2345 The fourth charge discharge pathway 2346 Fourth Amplifying Transistor 2347 Fourth row selection transistor 241 First charge mixing path 242 First Transistor 251 Second charge mixing pathway 252 Second transistor 261 First remaining pixel 262 Second remaining pixels

Claims

1. A pixel array comprising m first pixels and m second pixels arranged vertically, wherein the m first pixels output m first pixel signals and n second pixel signals, and the m second pixels output m third pixel signals and n fourth pixel signals, where n is less than m. m vertical signal lines including n first vertical signal lines and n second vertical signal lines, A control circuit that performs a first control, which involves transmitting the m first pixel signals to the m vertical signal lines and then transmitting the m third pixel signals to the m vertical signal lines, and a second control, which involves transmitting the n second pixel signals to the n first vertical signal lines and simultaneously transmitting the n fourth pixel signals to the n second vertical signal lines. An imaging device equipped with the following features.

2. The m first pixels perform a first operation in which each of the m first pixels outputs the m first pixel signals, and a second operation in which each of the n first shared pixels, which are formed from the m first pixels through pixel sharing, outputs the n second pixel signals. The m second pixels perform a third operation in which each of the m second pixels outputs the m third pixel signals, and a fourth operation in which each of the n sets of second shared pixels formed from the m second pixels by pixel sharing outputs the n fourth pixel signals. The first control includes causing the m first pixels to perform the first operation, and then causing the m second pixels to perform the third operation. The second control includes causing the m first pixels to perform the second operation and simultaneously causing the m second pixels to perform the fourth operation. The imaging apparatus according to claim 1.

3. The m first pixels perform a first operation in which each of the m first pixels outputs a m first pixel signal, and a second operation in which each of the n first remaining pixels, which are left over from the m first pixels by pixel decimation, outputs a n second pixel signal. The m second pixels perform a third operation in which each of the m second pixels outputs the m third pixel signals, and a fourth operation in which each of the n second remaining pixels, which are left over from the m second pixels due to pixel decimation, outputs the n fourth pixel signals. The first control includes causing the m first pixels to perform the first operation, and then causing the m second pixels to perform the third operation. The second control includes causing the m first pixels to perform the second operation and simultaneously causing the m second pixels to perform the fourth operation. The imaging apparatus according to claim 1.

4. Each of the m first pixels comprises n first floating diffusions, n first charge discharge paths leading from each of the n first floating diffusions to each of the n first vertical signal lines, n first row selection transistors for opening and closing each of the n first charge discharge paths, n second floating diffusions, n second charge discharge paths leading from each of the n second floating diffusions to each of the n second vertical signal lines, and n second row selection transistors for opening and closing each of the n second charge discharge paths. The m second pixels each comprise n third floating diffusions, n third charge discharge paths leading from the n third floating diffusions to the n first vertical signal lines, n third row selection transistors for opening and closing the n third charge discharge paths, n fourth floating diffusions, n fourth charge discharge paths leading from the n fourth floating diffusions to the n second vertical signal lines, and n fourth row selection transistors for opening and closing the n fourth charge discharge paths. The first control includes causing the n first row selection transistors to close the n first charge discharge paths, the n second row selection transistors to close the n second charge discharge paths, the n third row selection transistors to open the n third charge discharge paths, the n fourth row selection transistors to open the n fourth charge discharge paths, and then causing the n first row selection transistors to open the n first charge discharge paths, the n second row selection transistors to open the n second charge discharge paths, the n third row selection transistors to close the n third charge discharge paths, and the n fourth row selection transistors to close the n fourth charge discharge paths. The second control includes causing the n first row selection transistors to close the n first charge discharge paths, the n second row selection transistors to open the n second charge discharge paths, and simultaneously causing the n third row selection transistors to open the n third charge discharge paths and the n fourth row selection transistors to close the n fourth charge discharge paths. The imaging apparatus according to any one of claims 1 to 3.

5. Each of the m first pixels comprises n first charge mixing paths leading from each of the n first floating diffusions to each of the n second floating diffusions, and n first transistors that open and close each of the n first charge mixing paths. Each of the m second pixels comprises n second charge mixing paths leading from each of the n third floating diffusions to each of the n fourth floating diffusions, and n second transistors that open and close each of the n second charge mixing paths. The first control includes causing the n first transistors to open the n first charge mixing paths, and causing the n second transistors to open the n second charge mixing paths, The second control includes causing the n first transistors to close the n first charge mixing paths and the n second transistors to close the n second charge mixing paths. The imaging apparatus according to claim 4.

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