Semiconductor package and method for manufacturing the same

Abstract

The present invention provides a semiconductor package and a method for manufacturing the same, in which multiple semiconductor elements arranged side by side are sealed with a molding resin, eliminating the constraints of wire connections and suppressing voids in the gaps between semiconductor elements. [Solution] The semiconductor package 1 has a plurality of semiconductor elements 3 arranged on a base portion 2 at intervals of a predetermined or less, and is sealed with a molding resin 5. At least one semiconductor element 3 has a recess 4 at a position facing the center of the gap between adjacent semiconductor elements 3. The gap between the recess 4 and the adjacent semiconductor element 3 is wider than the other gaps. In the manufacturing method of this semiconductor package 1, when forming the molding resin 5, the resin material is supplied from the opposite side of the base portion 2 and preferentially enters the recess 4 among the gaps between semiconductor elements 3, thereby expelling the air from the gap.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package and a method for manufacturing the same.

Background Art

[0002] Conventionally, a semiconductor package having a structure in which a plurality of semiconductor elements are arranged adjacent to each other on a lead frame and these semiconductor elements are sealed with a resin material is known. Examples of the plurality of semiconductor elements include a sensor element having a sensor portion, a control element having its control circuit, and the like. This type of semiconductor package is manufactured by mounting a plurality of semiconductor elements on a lead frame and then forming a mold resin that seals the plurality of semiconductor elements by a resin molding method such as compression molding. In recent years, miniaturization of semiconductor packages has been demanded from the viewpoint of cost reduction and the like, and the plurality of semiconductor elements are arranged at a narrow interval equal to or less than a predetermined value.

[0003] However, in this type of semiconductor package, when the gap between adjacent semiconductor elements is narrow, it becomes difficult for the resin material to enter the gap during the molding of the mold resin, and in particular, a void, that is, a gap that is not filled with the resin material, occurs near the center of the gap. When such a void occurs in this type of semiconductor package, the stress at the portion of the semiconductor element that contacts the void changes locally and randomly, so that the sensor characteristics and accuracy of the semiconductor element may deteriorate. Examples of a semiconductor package having a structure capable of suppressing the occurrence of such voids include those described in Patent Document 1.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The semiconductor package described in Patent Document 1 has two semiconductor elements, each having multiple electrode pads, arranged side by side, and multiple wires are bonded to the electrode pads of the two semiconductor elements, electrically connecting them via the wires. In this semiconductor package, the pitch between the electrode pads of one semiconductor element is larger than that of the other semiconductor element with respect to the direction of resin flow during mold resin molding, and the spacing of the groups of multiple wires widens as they move toward one side. As a result, this semiconductor package has a structure that can control the flow of resin filling the gap between the two semiconductor elements that are placed side by side at a narrow spacing, thereby suppressing the generation of voids.

[0006] However, the above semiconductor package requires a certain number of wires to connect two adjacent semiconductor elements, and it also restricts the layout of the wire bonding and the circuit elements. Furthermore, if the number of wires connected to the semiconductor elements is less than the specified number, dummy wires become necessary.

[0007] In view of the above, this disclosure aims to provide a semiconductor package and a method for manufacturing the same, having a structure in which a plurality of semiconductor elements are arranged side by side and sealed with a molding resin, without constraints on wire connections, and suppressing the generation of voids between semiconductor elements. [Means for solving the problem]

[0008] According to one aspect of this disclosure, a semiconductor device is Multiple semiconductor elements (3, 31-34) adjacent to each other at intervals of a predetermined or less, A base portion (2) which serves as a base on which multiple semiconductor elements are mounted, The device comprises a molding resin (5) that covers multiple semiconductor elements and fills the gaps between adjacent semiconductor elements, A group consisting of multiple adjacent semiconductor elements is defined as an element group, and the center (C) of the gap formed by the element group is defined as the gap center. At least one of the multiple semiconductor elements has a recess (4) formed at a position facing the gap center, which is away from the other semiconductor elements. The gap between a recess and an adjacent semiconductor element is called the recess gap, and the gaps between multiple adjacent semiconductor elements other than the recess gap are called other gaps, with the recess gap being larger than the other gaps.

[0009] This semiconductor package has multiple semiconductor elements arranged on a base at intervals of less than a predetermined distance, and the multiple semiconductor elements are covered with molding resin. At least one of the multiple semiconductor elements has a recess that is set away from the other semiconductor elements. The recess is formed at a position facing the center of the gap formed by the group of elements and constitutes a larger gap than the other gaps formed by adjacent multiple semiconductor elements. As a result, when the resin material that will become the molding resin is supplied from the upper surface of the multiple semiconductor elements on the side opposite to the base, the resin material will preferentially enter the recessed area in the gap between adjacent semiconductor elements. Therefore, even if multiple semiconductor elements are arranged at narrow intervals, this semiconductor package has a structure that does not restrict wire connections and suppresses the generation of voids between adjacent semiconductor elements.

[0010] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is: Prepare multiple semiconductor elements (3, 31-34) and a base (2), The process includes arranging multiple semiconductor elements on a base portion at intervals of a predetermined or less, and then forming a mold resin (5) that covers the multiple semiconductor elements and fills the gaps between adjacent multiple semiconductor elements, In preparing multiple semiconductor elements, a group consisting of multiple semiconductor elements arranged adjacent to each other is called an element group, and at least one semiconductor element is prepared in which a recess (4) is formed at a position facing the gap center (C) of the gap center, and away from other semiconductor elements. In forming the molded resin, the resin material is supplied from the opposite side of the base, and is preferentially filled into the recessed areas of the gap, thereby expelling the air from the gap.

[0011] In this semiconductor device manufacturing method, a plurality of semiconductor elements, each having at least one recess, and a base are prepared. A resin material is supplied from the upper side of the plurality of semiconductor elements opposite to the base to form a mold resin that covers the plurality of semiconductor elements. The recess is formed at a position facing the center of the gap formed by the group of elements, and constitutes a larger gap than the other gaps formed by adjacent plurality of semiconductor elements. In the mold resin formation process, the supplied resin material is preferentially allowed to enter the gap formed by the recess among the gaps between semiconductor elements, and the air in the gap is expelled. As a result, even if the plurality of semiconductor elements are arranged at narrow intervals, it is possible to manufacture a semiconductor package without wire connection constraints and with suppressed void generation between adjacent semiconductor elements.

[0012] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0013] [Figure 1] This is a perspective view showing a semiconductor package according to the first embodiment. [Figure 2] This is a perspective view of multiple semiconductor devices. [Figure 3] This is a view from direction III in Figure 1. [Figure 4A] This is an explanatory diagram of the molding process for molded resin. [Figure 4B] This is an explanatory diagram of the molding process of the mold resin, following Figure 4A. [Figure 5] This figure shows the comparison results of the void area ratio in semiconductor packages of the examples and comparative examples. [Figure 6] This is a perspective view showing a semiconductor package according to the second embodiment. [Figure 7] This is a view from the direction of arrow VII in Figure 6. [Figure 8] This figure corresponds to Figure 7 and shows another example of the groove shape in the second embodiment. [Figure 9]A figure corresponding to FIG. 7, showing another shape example of the groove portion in the second embodiment. [Figure 10] A figure corresponding to FIG. 3, showing a top view of the semiconductor package of the third embodiment. [Figure 11] A cross-sectional view taken along line XI-XI of FIG. 10. [Figure 12] A perspective view showing the semiconductor package of the fourth embodiment. [Figure 13] A figure corresponding to FIG. 3, showing a top view of the semiconductor package of the fifth embodiment. [Figure 14] A figure corresponding to FIG. 3, showing a top view of the semiconductor package of the sixth embodiment. [Figure 15] A figure corresponding to FIG. 3, showing a top view of the semiconductor package of the seventh embodiment. [Figure 16] A figure corresponding to FIG. 3, showing a top view of the semiconductor package of the eighth embodiment. [Figure 17] A figure corresponding to FIG. 3, showing a top view of a modified example of the semiconductor package of the eighth embodiment. [Figure 18] A figure corresponding to FIG. 3, showing a top view of the semiconductor package of the ninth embodiment. [Figure 19] A figure corresponding to FIG. 3, showing a top view of a modified example of the semiconductor package of the ninth embodiment. [Figure 20] A figure corresponding to FIG. 3, showing a top view of a modified example of the semiconductor package of the ninth embodiment. [Figure 21] A figure corresponding to FIG. 3, showing a top view of a modified example of the semiconductor package of the ninth embodiment.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present disclosure will be described based on the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

[0015] (First Embodiment) The semiconductor package 1 of the first embodiment comprises a base portion 2, a plurality of semiconductor elements 3, and a molding resin 5, as shown in Figure 1, for example, with the plurality of semiconductor elements 3 covered by the molding resin 5. In this embodiment, the case in which the semiconductor package 1 has two semiconductor elements 3 will be described as a representative example. In Figure 1, in order to make the configuration of the semiconductor package 1 easier to understand, a part of the outer outline of the plurality of semiconductor elements 3 covered by the molding resin 5 is shown with a solid line, and the outer outline of the part of each component that is not directly visible from the angle shown is shown with a dashed line. This is also the case for Figure 3 and Figures 6 to 10 and 12 to 21 which will be described in subsequent embodiments.

[0016] The base portion 2 is a component that serves as a base on which multiple semiconductor elements 3 are mounted. The base portion 2 is composed of, for example, a substrate such as a PCB, a lead frame made of copper or the like, a circuit chip having an ASIC that corresponds to multiple semiconductor elements 3, or a combination thereof, but is not limited to these, as long as it can mount multiple semiconductor elements 3. PCB and ASIC are abbreviations for Printed Circuit Board and Application Specific Integrated Circuit, respectively. The base portion 2 is a roughly plate-shaped component with a planar size larger than the group of elements made up of multiple semiconductor elements 3, and the multiple semiconductor elements 3 are mounted on its surface 2a using an adhesive or the like (not shown).

[0017] The multiple semiconductor elements 3 are, for example, sensor chips having a sensor section (not shown) or IC chips having a control circuit for the sensor, and are manufactured by known semiconductor processes. The multiple semiconductor elements 3 are, for example, two sensor chips, one of which is a gyro sensor and the other is an accelerometer, forming an IMU that detects three-dimensional inertial motion, but are not limited to this example. IMU is an abbreviation for Inertial Measurement Unit. The multiple semiconductor elements 3 are arranged side by side at intervals of a predetermined or less. For example, the multiple semiconductor elements 3 are arranged in parallel at narrow intervals such that the gap between adjacent semiconductor elements 3 is on the order of micrometers, such as 200 μm. The multiple semiconductor elements 3 have a recess 4 on the opposing surface 3c facing the other adjacent semiconductor element 3, which is recessed away from the other semiconductor element 3. The opposing surface 3c is, for example, as shown in Figure 2, the side surface of the semiconductor element 3 that connects the lower surface 3b facing the base section 2 and the upper surface 3a on the opposite side of the lower surface 3b, and faces the other semiconductor element 3.

[0018] For the sake of explanation, the semiconductor element 3 located on the left side in Figure 1 will be referred to as the "first semiconductor element 31," and the one located on the right side will be referred to as the "second semiconductor element 32." The view of the semiconductor package 1 and the multiple semiconductor elements 3 from the direction normal to the top surface 3a will be referred to as the "top view." In Figure 2, the opposing surface 3c of the second semiconductor element 32 is shown facing away from the first semiconductor element 31 in order to make the shape of the recess 4 easier to see.

[0019] In this embodiment, the recesses 4 are formed on the opposing surfaces 3c of the semiconductor elements 31 and 32, respectively. For example, as shown in Figure 3, the recess 4 is a substantially semicircular through groove with a substantially constant diameter when viewed from above, and it connects the upper surface 3a and the lower surface 3b. In Figure 3, the outlines of the semiconductor elements 31 and 32 covered with the molding resin 5 are shown with solid lines to make the shapes of the semiconductor elements 31 and 32 easier to understand. The recesses 4 are obtained by dicing a through hole formed between adjacent semiconductor elements by RIE or the like in a semiconductor wafer on which multiple semiconductor elements are formed. RIE is an abbreviation for Reactive Ion Etching.

[0020] The recess 4 is formed in the central part of the opposing surface 3c facing the center C, with the center position C being the central position in the gap between the multiple semiconductor elements 3 when viewed from above. In this embodiment, the recess 4 faces other recesses 4 formed on other adjacent semiconductor elements 3. The recess 4 is, for example, a groove having a substantially semicircular arc with a radius of curvature of 250 μm when viewed from above. The recess 4 is provided in the process of forming the mold resin 5 so that the resin material supplied to the gap between adjacent semiconductor elements 3 preferentially enters the gap over other gaps that are different from the recess 4, creating a flow of resin material that spreads to the other gaps from the recess 4. In other words, the recess 4 is a part that plays a role in suppressing void generation in the gap between adjacent semiconductor elements 31 and 32.

[0021] For the sake of simplicity in this explanation, the gaps between adjacent semiconductor elements 3 will be simply referred to as "gap," the gap formed by the recess 4 will be referred to as the "recess gap," and the portion of the gap that is different from the recess gap will be referred to as "other gaps." The recess gap is wider than the other gaps because it includes the recess 4.

[0022] The molded resin 5 is made of an insulating resin material such as epoxy resin, and covers a part of the base portion 2 and a plurality of semiconductor elements 3. The molded resin 5 is formed by a resin molding method such as compression molding or transfer molding, i.e., compression molding or transfer molding. In the case of compression molding, the molded resin 5 is formed using a mold 100 for compression molding, which consists of an upper mold 110 and a lower mold 120, as shown in Figure 4A. The upper mold 110 is heated to a predetermined temperature and the base portion 2 to which the semiconductor elements 31 and 32 are bonded is attached. The lower mold 120 is heated to a predetermined temperature and has a recess 121 that follows the outer shape of the molded resin 5, and molten resin material 50 is placed in the recess 121. Then, the lower mold 120 is raised toward the upper mold 110 and the upper mold 110 and lower mold 120 are brought together as shown in Figure 4B, and the molded resin 5 is formed by solidifying the resin material 50. At this time, the semiconductor elements 31 and 32 have recesses 4, and the resin material 50 preferentially enters the recesses with larger opening areas, creating a flow that spreads toward other gaps while expelling the air from the gaps, thus forming a molded resin 5 in which the generation of voids in the gaps is suppressed.

[0023] Furthermore, when forming the molded resin 5 by transfer molding, the generation of voids in the gap can be suppressed by using a top-gate method in which the resin material 50 is supplied from the upper surface 3a side of the semiconductor element 3. Thus, the molding method for the molded resin 5 can be any method in which the resin material 50 is supplied from the upper surface 3a side of the semiconductor element 3, and known resin molding methods other than compression molding and transfer molding may be employed.

[0024] The above describes the basic configuration of the semiconductor package 1 of this embodiment. The semiconductor package 1 has a structure in which the semiconductor elements 31 and 32 have recesses 4, thereby suppressing the generation of voids in the gaps.

[0025] Next, the results of evaluating the void area ratio in the semiconductor packages of the examples and comparative examples will be explained with reference to Figure 5.

[0026] In Figure 5, "Example" refers to the semiconductor package 1 described above. The comparative example in Figure 5 differs from semiconductor package 1 in that all of the semiconductor elements are rectangular plate-shaped and do not have a portion corresponding to the recess 4; otherwise, it is a semiconductor package with the same configuration. The example was manufactured by setting the gap between the two semiconductor elements 3 to 200 μm and forming mold resin 5 on the semiconductor elements 3 from the upper surface 3a side uniformly under the conditions of 3 MPa pressure and 175°C using epoxy resin and a compression molding machine manufactured by TOWA Corporation. In addition, the radius of curvature of the recess 4 of the semiconductor elements 31 and 32 in a top view was set to 250 μm. The comparative example sample was manufactured under the same conditions as the example, except that two of the semiconductor elements used did not have the recess 4.

[0027] For the examples and comparative examples, the void area ratio in the gaps was evaluated using a FineSAT FA200 ultrasonic flaw detection system manufactured by Hitachi Power Solutions, Ltd. In this evaluation, ultrasonic flaw detection (SAT) inspection was performed on the gaps from the base portion 2 side, and areas where the ultrasonic reflection waveform was inverted were identified as voids. The void area ratio (%) is the ratio of the void area to the area of ​​the gap between semiconductor elements in the SAT image.

[0028] When the comparative example samples were evaluated with n=3, the void area ratios were 0%, approximately 17%, and approximately 42%. In the case of the comparative example, since the gaps between multiple semiconductor elements are approximately constant, it is thought that when the resin material is supplied, air is easily trapped not only in the opening on the upper surface 3a side of the gap, but also from the side of the edge, causing voids to be generated randomly.

[0029] On the other hand, when the sample of the example was evaluated with n=3, the void area ratios were 0%, approximately 4%, and approximately 14%. This result suggests that a recess 4 is formed near the center of the gap between the semiconductor elements 3, and a structure is created that causes the resin material to preferentially enter the recess gap, thereby suppressing the formation of voids in the gap and reducing the area ratio of voids when voids occur.

[0030] According to this embodiment, a semiconductor package 1 is formed in which multiple semiconductor elements 3, each having a recess 4 that is far from other adjacent semiconductor elements 3, are arranged side by side, and these are sealed with a molding resin 5, thereby suppressing the generation of voids between the semiconductor elements 3. Furthermore, the semiconductor package 1 has recessed gaps with a large opening area, and during the molding of the molding resin 5, the resin material 50 preferentially enters from the recesses 4 and spreads to other gaps, creating a flow that eliminates constraints on wire connections between the multiple semiconductor elements 3. Because the generation of voids in the gaps between the multiple semiconductor elements 3 is suppressed in this semiconductor package 1, the deterioration of the sensor characteristics and sensor accuracy of the semiconductor elements 3 is suppressed.

[0031] (Second Embodiment) The semiconductor package 1 of the second embodiment differs from the first embodiment in that the semiconductor elements 31 and 32 have grooves 6, as shown in Figure 6, for example. This embodiment will mainly explain this difference.

[0032] In this embodiment, the semiconductor elements 31 and 32 have grooves 6 formed at the end of the opposing surface 3c on the base portion 2 side. For example, as shown in Figure 7, the grooves 6 have a tapered shape that narrows towards the upper surface 3a side, and are formed by dicing from the lower surface 3b side using a blade with an angled cutting edge. In Figure 7, the outlines of the semiconductor elements 31 and 32 covered with mold resin 5 are shown with solid lines to make the shapes of the semiconductor elements 31 and 32 easier to understand. This is also the case for Figures 8 and 9, which will be described later. The grooves 6 face, for example, the grooves 6 of the other opposing semiconductor element 3. The grooves 6 form a gap that is at least wider than other gaps, and in the molding process of the mold resin 5, they play a role in increasing the speed at which the resin material 50 that has entered from the recessed gap flows to the end of the gap after reaching the base portion 2. As a result, the structure is such that air in the gap is more easily discharged to the outside of the gap when the mold resin 5 is formed, and the generation of voids in the gap is suppressed.

[0033] The groove 6 may have a stepped shape in cross-sectional view, for example, as shown in Figure 8, or a curved shape, for example, as shown in Figure 9, and its shape may be changed as appropriate. In the case of a stepped shape, the groove 6 is formed, for example, in dicing cuts, by making a 50 μm deep cut in the semiconductor wafer using a first blade with a width of 200 μm, and then dividing it using a second blade with a width of 50 μm to form individual semiconductor chips. Thus, the shape and width of the groove 6 can be changed as appropriate by changing the shape and width of the blade used in the dicing cut. A chamfered shape such as a taper is preferable for the groove 6 because it tends to allow the resin material 50 to flow faster during the formation of the mold resin 5 compared to other shapes.

[0034] Furthermore, when ultrasonic testing was performed on the surface of the molded resin 5 opposite to the base portion 2 of the comparative example sample described in the first embodiment, a portion of the molded resin 5 was found to have peeled away from the base portion 2. In contrast, when the semiconductor package 1 of this embodiment was subjected to the same ultrasonic testing, no peeling of the molded resin 5 was observed. This is thought to be because the formation of grooves 6 in the semiconductor element 3 caused the portion of the molded resin 5 that entered the space formed by the grooves 6 to act like a wedge, thereby suppressing the peeling of the molded resin 5.

[0035] According to this embodiment, in addition to the effects of the first embodiment described above, the semiconductor package 1 is obtained in which the semiconductor element 3 has grooves 6, thereby further enhancing the effect of suppressing voids in the gaps and also suppressing the peeling of the mold resin 5.

[0036] (Third embodiment) The semiconductor package 1 of the third embodiment differs from the first embodiment in that the shape of the recess 4 is changed, as shown in Figures 10 and 11, for example. This embodiment will mainly describe this difference.

[0037] In this embodiment, as shown in Figure 11, the recess 4 has a notch shape in which the diameter in a top view decreases as it moves from the upper surface 3a side to the lower surface 3b side. For example, in a top view, the recess 4 has a roughly semi-conical notch shape, with a radius of curvature of 250 μm at the end on the upper surface 3a side and a radius of curvature of 200 μm at the end on the lower surface 3b side. When the injection pressure of the resin material 50 is constant during the formation of the mold resin 5, the area of ​​the recess gap formed by the notched recess 4 decreases as it moves towards the lower surface 3b, so the pressure of the resin material 50 becomes relatively higher towards the lower surface 3b side. In other words, the recess 4 accelerates the flow of the resin material 50 in the recess gap as it approaches the lower surface 3b, causing the resin material 50 to reach the surface of the base portion 2 faster than other gaps, creating a flow from there toward the edges, and playing a role in more effectively suppressing voids.

[0038] Furthermore, in this embodiment, the semiconductor element 3, similar to the second embodiment described above, has a groove 6 on its opposing surface 3c, which allows the resin material 50 injected from the recess 4 and reaching the base portion 2 to spread efficiently toward the end.

[0039] According to this embodiment, in addition to the effects of the first and second embodiments described above, the semiconductor package 1 has a recess 4 whose diameter decreases towards the lower surface 3b side, which allows the resin material 50 to reach the base portion 2 more quickly within the recess gap, thereby improving the effect of suppressing void generation.

[0040] (Fourth Embodiment) The semiconductor package 1 of the fourth embodiment differs from the first embodiment in that the base portion 2 has a slit portion 21, as shown in Figure 12, for example. This embodiment will mainly explain this difference. In Figure 12, a part of the outer casing of the base portion 2 covered with mold resin 5 is shown with a solid line to make the structure of the slit portion 21 easier to understand.

[0041] In this embodiment, the base portion 2 has a slit portion 21 formed on its surface 2a at a position overlapping with the gap between adjacent semiconductor elements 3. The slit portion 21 is, for example, a stepped groove formed linearly at a position overlapping with the gap between semiconductor elements 3, and its width on surface 2a is wider than the width of other gaps. The slit portion 21 has a depth of, for example, about 50 μm, but is not limited to this. The slit portion 21 is formed, for example, by dicing, and its width, shape, depth, etc., can be appropriately changed by changing the blade used for dicing. The slit portion 21 plays a role in accelerating the flow of resin toward the edge of the gap when the resin material 50 injected into the recessed gap reaches the base portion 2 during the formation of the mold resin 5, and in facilitating the expulsion of air from the gap to the outside. This further enhances the effect of suppressing the generation of voids in the gap.

[0042] Furthermore, the slit portion 21 is not limited to the example of extending in a substantially straight line as described above, but may overlap with the gaps between the multiple semiconductor elements 3, and may be formed as a groove with a shape that conforms to the shape of the gap when viewed from above.

[0043] According to this embodiment, the semiconductor package 1 can be obtained to have the same effects as the second embodiment described above.

[0044] (Fifth embodiment) The semiconductor package 1 of the fifth embodiment differs from the first embodiment in that, as shown in Figure 13, for example, the first semiconductor element 31 does not have a recess 4, while only the second semiconductor element 32 has a recess 4. This embodiment will mainly explain this difference.

[0045] In this embodiment, the second semiconductor element 32 is a recess-forming element having a recess 4, and the first semiconductor element 31 adjacent to the second semiconductor element 32, which does not have a recess 4, is an adjacent element. The semiconductor package 1 of this embodiment has a smaller recess gap width compared to the first embodiment, but is the same as the first embodiment in that the recess gap is wider than the other gaps. In other words, even if at least one of the adjacent semiconductor elements 3 has a recess 4 at the center position on the opposing surface 3c, the behavior of the resin material 50 preferentially entering the recess gap during the formation of the mold resin 5 is the same, and therefore void generation can be suppressed.

[0046] This embodiment also provides a semiconductor package 1 that offers the same effects as the first embodiment described above.

[0047] (Sixth Embodiment) The semiconductor package 1 of the sixth embodiment differs from the first embodiment in that, as shown in Figure 14, for example, the formation positions of the recesses 4 in the first semiconductor element 31 and the second semiconductor element 32 are offset when viewed from above. This embodiment will mainly explain this difference.

[0048] In this embodiment, one recess 4 of the semiconductor elements 31 and 32 is formed at the center of the opposing surface 3c, while the other recess 4 is formed at a position on the opposing surface 3c different from the center. For example, when viewed from above, the recess 4 of the first semiconductor element 31 is formed closer to the edge of the gap than the second semiconductor element 32, while the recess 4 of the second semiconductor element 32 is formed at the center of the gap. The two recesses 4 are not in completely offset positions, but at least a portion of them are facing each other. This is because if the recesses 4 were not completely offset and did not overlap, air pockets could form between the recesses in the gap. Thus, even when the two recesses 4 are offset and partially facing each other, the behavior of the resin material 50 preferentially entering the recess gap during the formation of the mold resin 5 remains the same, making it possible to suppress the generation of voids in the gap.

[0049] This embodiment also provides a semiconductor package 1 that offers the same effects as the first embodiment described above.

[0050] (Seventh Embodiment) The semiconductor package 1 of the seventh embodiment differs from the first embodiment in that, as shown in Figure 15, for example, each of the semiconductor elements 31 and 32 has a plurality of recesses 4. This embodiment will mainly explain this difference.

[0051] In this embodiment, the semiconductor elements 31 and 32 each have, for example, three recesses 4 on their opposing surfaces 3c, with at least one recess 4 formed in the center of the opposing surface 3c. Of the multiple recesses 4, the recess 4 facing the center of the gap in a top view is designated as the "central recess 41," and the other recesses 4 are designated as "end-side recesses 42," with the central recess 41 being wider than the end-side recesses 42. As a result, when forming the molded resin 5, the resin material 50 first enters the center of the gap, i.e., the central recess 41, then enters the end-side recesses 42, and then spreads out within the gap with the recesses 4 as the center. The resin material 50 then spreads outwards from the center of the gap towards the ends, creating a flow that efficiently expels the air in the gap to the outside. Therefore, the generation of voids in the gap is suppressed.

[0052] In the above explanation, the case in which semiconductor elements 31 and 32 each have three recesses 4 was described as a representative example, but the explanation is not limited to this, and the number and arrangement of the recesses 4 may be changed as appropriate.

[0053] This embodiment also provides a semiconductor package 1 that offers the same effects as the first embodiment described above.

[0054] (Eighth embodiment) The semiconductor package 1 of the eighth embodiment differs from the first embodiment in that, as shown in Figure 16, for example, the recesses 4 of the semiconductor elements 31 and 32 are formed with a width that extends across the entire surface 3c of the opposing surface. This embodiment will mainly explain this difference.

[0055] In this embodiment, the recess 4 is formed over the entire area of ​​the opposing surface 3c, and in a top view, the recess is recessed so that the center of the gap is furthest away from the other semiconductor element 3, and the shape approaches the other semiconductor element 3 towards the edge of the gap. In a top view, the recess 4 may be a wedge-shaped through groove where two flat surfaces intersect at the center of the gap, as shown in Figure 16, or it may be a through groove composed of a single curved surface, as shown in Figure 17. Even with such a configuration of the recess 4, when the mold resin 5 is formed, the resin material 50 preferentially enters the center of the gap and then spreads out towards the edge, thereby suppressing the generation of voids in the gap. In this embodiment, the recess 4 is formed by, for example, laser processing.

[0056] This embodiment also provides a semiconductor package 1 that offers the same effects as the first embodiment described above.

[0057] (Ninth Embodiment) The semiconductor package 1 of the ninth embodiment differs from the first embodiment in that it has three semiconductor elements 3, as shown in Figure 18, for example, and the configuration of the recess 4 has been changed. This embodiment will mainly describe this difference.

[0058] In this embodiment, the semiconductor package 1 includes a first semiconductor element 31, a second semiconductor element 32, and a third semiconductor element 33. The first semiconductor element 31 and the second semiconductor element 32 have recesses 4, while the third semiconductor element 33 does not have recesses 4. The third semiconductor element 33 is, for example, a rectangular plate, and when viewed from above, it is a rectangle wider than the combined width of the first semiconductor element 31 and the second semiconductor element 32.

[0059] In this embodiment, when viewed from above, the first semiconductor element 31 has sides 3ca facing the second semiconductor element 32 and 3cb facing the third semiconductor element 33 that are inclined so as they move toward the center of the gap, they move away from the other adjacent semiconductor elements 3. In other words, when viewed from above, the first semiconductor element 31 is a square shape obtained by deforming a rectangular shape, and is a shape obtained by moving only the one corner closest to the center C of the gap outwards from the center C of the rectangle. The recess 4 in the first semiconductor element 31 is composed of sides 3ca and 3cb.

[0060] In this embodiment, when viewed from above, the second semiconductor element 32 has sides 3cc facing the first semiconductor element 31 and sides 3cd facing the third semiconductor element 33 that are inclined so as they move toward the center C of the gap, they move away from the other adjacent semiconductor elements 3. The second semiconductor element 32 has the same configuration as the first semiconductor element 31, and the sides 3cc and 3cd form a recess 4.

[0061] In this embodiment, the gap between the three semiconductor elements 31-33 is wider closer to the center C when viewed from above, and the resin material 50 is preferentially injected towards the center C. As a result, a flow of resin material 50 is formed in the gap between the element group consisting of the three semiconductor elements 31-33, moving from the center to the edges, and the air in the gap is expelled to the outside, thereby suppressing the generation of voids in the gap.

[0062] This embodiment also provides a semiconductor package 1 that offers the same effects as the first embodiment described above.

[0063] (Modified version of the 9th embodiment) (1) As shown in Figure 19, for example, in a top view, the semiconductor elements 31 and 32 may have recesses 4 only at the intersection of two sides facing each other. In the first semiconductor element 31, the chamfered portion formed to connect sides 3ca and 3cb is a recess 4, and the recess 4 faces the semiconductor elements 32 and 33. In the second semiconductor element 32, the chamfered portion formed to connect sides 3cc and 3cd is a recess 4, and the recess 4 faces the semiconductor elements 31 and 33. Note that the recess 4 is not limited to a flat surface, and may be partially or entirely a curved surface. Even with such a configuration of recess 4, the resin material 50 preferentially flows into the center C of the gap formed by the group of elements, and then flows toward the edges of the gap, thereby suppressing the generation of voids in the gap.

[0064] This modified version also provides a semiconductor package 1 that offers the same effects as the ninth embodiment described above.

[0065] (2) The semiconductor package 1 may have four semiconductor elements 31 to 34, as shown in Figure 20, for example, and in a top view, each of the semiconductor elements 31 to 34 may have a recess 4 formed by two sides facing each other semiconductor element 3. In any of the semiconductor elements 31 to 34, the recess 4 is formed by two sides that, in a top view, are inclined to move away from the adjacent semiconductor element 3 as they move towards the center C of the gap.

[0066] Furthermore, as shown in Figure 21, for example, the semiconductor package 1 has four semiconductor elements 31 to 34, and in a top view, the chamfered portion 4 is formed so that each of the semiconductor elements 31 to 34 connects two adjacent sides to the other semiconductor elements 3.

[0067] In any of the above-described modifications, the semiconductor package 1 will have the same effects as the ninth embodiment described above.

[0068] (Other embodiments) This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence range. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less of those elements, fall within the scope and concept of this disclosure.

[0069] For example, in embodiments other than the third embodiment, the semiconductor package 1 may have a recess 4 whose diameter decreases as it approaches the lower surface 3b, and in embodiments other than the second and third embodiments, a groove 6 may be formed. For example, in the fifth embodiment, the semiconductor package 1 may have multiple recesses 4. For example, the semiconductor package 1 may have five or more semiconductor elements 3, or only some of the adjacent semiconductor elements 3 may have recesses 4. In this way, the semiconductor package 1 of each embodiment and its modified form may have some of its components freely and appropriately combined, except in cases where they are clearly incompatible.

[0070] It goes without saying that, in each of the above embodiments, the elements constituting the embodiment are not necessarily essential unless explicitly stated to be particularly essential or unless they are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, numerical values, quantities, or ranges of the components of the embodiment are mentioned, the embodiment is not limited to those specific numbers unless explicitly stated to be particularly essential or unless it is clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shape, positional relationship, etc., of the components are mentioned, the embodiment is not limited to those shapes, positional relationships, etc., unless explicitly stated or unless it is clearly limited to a specific shape, positional relationship, etc., in principle. [Explanation of Symbols]

[0071] 2...Base portion, 21...Slit portion, 3, 31~34...Semiconductor element, 3a...Top surface, 3b...Bottom surface, 3c...Opposite surface, 4...Recess, 5...Molded resin, 6...Groove portion, C...Center of the gap (between adjacent semiconductor elements)

Claims

1. A semiconductor package, Multiple adjacent semiconductor elements (3, 31-34) spaced at intervals of a predetermined or less, A base portion (2) which serves as a base on which multiple semiconductor elements are mounted, The device comprises a molding resin (5) that covers a plurality of semiconductor elements and fills the gaps between adjacent semiconductor elements, A group consisting of multiple adjacent semiconductor elements is defined as an element group, and the center (C) of the gap formed by the element group is defined as the gap center. At least one of the multiple semiconductor elements has a recess (4) formed at a position facing the gap center, which is away from the other semiconductor elements. A semiconductor package in which the gap between the recess and an adjacent semiconductor element is defined as the recess gap, and the gaps between a plurality of adjacent semiconductor elements other than the recess gap are defined as other gaps, wherein the recess gap is larger than the other gaps.

2. The semiconductor package according to claim 1, wherein, of the plurality of semiconductor elements, the surface facing the base portion is designated as the bottom surface (3b), the surface opposite to the bottom surface is designated as the top surface (3a), and the surface facing another semiconductor element is designated as the opposing surface (3c), and the recess is provided near the center of the opposing surface and is a notch or through groove extending in the direction connecting the top surface and the bottom surface.

3. The semiconductor package according to claim 2, wherein among a plurality of semiconductor elements, the semiconductor element having the recess is designated as a recess-forming element, and the semiconductor element adjacent to the recess of the recess-forming element is designated as an adjacent element, and the recess-forming element and the adjacent element have a groove (6) that is wider than the other gap at the end of the opposing surface on the lower surface side.

4. The semiconductor package according to claim 2, wherein the base portion faces the gaps formed by a plurality of adjacent semiconductor elements and has a slit portion (21) that is wider than the other gaps.

5. The semiconductor package according to any one of claims 2 to 4, wherein the diameter of the recess decreases towards the base portion.

6. A method for manufacturing semiconductor packages, The process involves preparing multiple semiconductor elements (3, 31-34) and a base (2), The process includes arranging a plurality of semiconductor elements on the base portion at intervals of a predetermined or less, and then forming a mold resin (5) that covers the plurality of semiconductor elements and fills the gaps between adjacent plurality of semiconductor elements, In preparing multiple semiconductor elements, a group consisting of multiple semiconductor elements arranged adjacent to each other is called an element group, and at least one semiconductor element is prepared in which a recess (4) is formed at a position facing the gap center (C) of the gap formed by the element group, and the recess is set away from the other semiconductor elements. A method for manufacturing a semiconductor package, wherein, in forming the molded resin, resin material is supplied from the opposite side of the base portion and preferentially filled into the recessed part of the gap, thereby expelling air from the gap.

7. The method for manufacturing a semiconductor package according to claim 6, wherein the resin material is supplied by a compression method or a transfer method when forming the mold resin.

8. A method for manufacturing a semiconductor package according to claim 6 or 7, wherein, in preparing a plurality of the semiconductor elements, a semiconductor wafer on which a plurality of the semiconductor elements are formed and through holes are provided between adjacent semiconductor elements is prepared, in which a cut is made through the through holes using a first blade, and then the through holes are divided using a second blade narrower than the first blade to prepare the semiconductor elements in which the recesses are formed.

Images