Power circuits, semiconductor devices, power supply units
The power supply circuit and semiconductor device integrate a detection circuit to control a cutoff transistor, addressing the challenge of overcurrent protection without increasing chip size, ensuring flexibility in meeting user and supplier needs.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2025-01-10
- Publication Date
- 2026-07-23
AI Technical Summary
Existing semiconductor devices with integrated regulator circuits face challenges in providing overcurrent protection without increasing chip size, as adding a cutoff transistor doubles the size of the output transistor and ON resistance, affecting package selection and user requirements.
A power supply circuit and semiconductor device design that includes a detection circuit and a cutoff transistor, where the detection circuit generates signals to control the cutoff transistor independently, allowing overcurrent protection without increasing chip size by isolating the operating characteristics of the output transistor from the cutoff transistor.
The design minimizes chip size changes while providing overcurrent protection, accommodating user and supplier requirements by enabling semiconductor devices with and without overcurrent protection through circuit board configurations.
Smart Images
Figure 2026121171000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a power supply circuit, a semiconductor device, and a power supply device.
Background Art
[0002] < Patent Document 1 discloses a semiconductor integrated circuit and a semiconductor device. The semiconductor integrated circuit and the semiconductor device enable overcurrent protection and adjustment of temperature characteristics. Specifically, the semiconductor integrated circuit and the semiconductor device include an overcurrent protection circuit.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
[0004] [Summary] One type of overcurrent protection circuit monitors the magnitude of the output current of a regulator circuit. The output current is provided by an output transistor of the regulator circuit. The output transistor has a sufficient size to conduct the current that the regulator circuit is to supply.
[0005] One method of detecting an excessive output current is to utilize the control signal provided from the control circuit to the output transistor instead of directly detecting the current flowing through the output transistor. Specifically, this method involves adding a detection circuit to the regulator circuit, and the output transistor and the detection circuit operate in response to the control signal. The detection circuit operates to generate a detection signal indicating the occurrence of an excessive output current in response to an undesirable value of the control signal. Also, an excessive current causes a large voltage change in the output of the regulator circuit, and this voltage change is fed back to the control circuit to change the control signal to the regulator circuit.
[0006] When the detection circuit indicates an excessive output current, the regulator circuit cuts off the current flowing to the output transistor, thereby stopping the excessive output current.
[0007] Specifically, a short circuit between the electrodes of an output transistor is one of the causes of overcurrent in a regulator circuit. For example, a short circuit between the source and drain of an output transistor causes an overcurrent. This overcurrent cannot be interrupted by controlling the gate of the output transistor. Accordingly, the interruption of the current is performed using a transistor provided as an interruption switch in the integrated circuit. On the other hand, interruption of the current requires a transistor in the path through which the current flows to the output transistor, specifically an interruption transistor. The output transistor and the interruption transistor are connected in series with each other.
[0008] The output transistor has a size, specifically a transistor width, that allows it to supply current to the regulator circuit. The cutoff transistor is connected in series with the output transistor, and the cutoff transistor is required to have a size, specifically a transistor width, that allows it to supply current to the regulator circuit.
[0009] In estimating transistor size, adding a cutoff transistor doubles the size of the output transistor in terms of the series connection of the output transistor and the cutoff transistor. Furthermore, adding a cutoff transistor doubles the size of the output transistor again in terms of the ON resistance of the regulator circuit output. Consequently, adding a cutoff transistor increases the chip size of the semiconductor device. Changes in the chip size of the semiconductor device may also be related to the package selection of the semiconductor device. Adding overcurrent protection functionality is related to these technical aspects.
[0010] Some users of integrated circuits incorporating regulator circuits, such as semiconductor devices with built-in microcomputers, require built-in overcurrent protection for the regulator circuit, while other users do not require overcurrent protection for semiconductor devices with built-in microcomputers. To meet these demands, semiconductor device suppliers offer multiple semiconductor devices (with and without overcurrent protection) for a particular function of microcomputer. Alternatively, suppliers can supply large chip-sized semiconductor devices with overcurrent protection to users who require semiconductor devices without overcurrent protection.
[0011] What is required is to provide power supply circuits, semiconductor devices, and power supply equipment that take into account both the user's requirements and the supplier's technical aspects.
[0012] The operating characteristics of an output transistor are affected by the characteristics of the cutoff transistor, such as its size. What is needed is to isolate the operating characteristics of the output transistor from those of the cutoff transistor in a semiconductor device that provides overcurrent protection.
[0013] A power supply circuit according to a first aspect of the present disclosure comprises a semiconductor device including a regulator circuit and a detection circuit, having a regulator power electrode, a regulator output electrode, a first power electrode, a second power electrode, and a detection output electrode; and a cutoff transistor connected between the first power electrode and the regulator power electrode and configured to operate in response to a detection signal received from the semiconductor device via the detection output electrode, wherein the regulator circuit includes a control circuit and an output transistor, the control circuit connected between the first power electrode and the second power electrode and configured to generate a control signal in response to the difference between a reference voltage from a reference voltage source and a feedback voltage from the output voltage of the regulator output electrode, the output transistor connected between the regulator power electrode and the regulator output electrode and configured to operate in response to the control signal, the detection circuit connected between the first power electrode and the second power electrode, the detection circuit generates a monitor voltage in response to the control signal, the detection circuit generates one or more detection signals based on a level signal indicating the level of the excess output current of the regulator circuit and the monitor voltage, and operates to provide the detection signals to the detection output electrode.
[0014] A semiconductor device according to a second aspect of this disclosure comprises a first power electrode, a second power electrode, a regulator power electrode, a regulator output electrode, a detection output electrode, a regulator circuit, and a detection circuit, wherein the regulator circuit includes a control circuit and an output transistor. The control circuit is connected between the first power electrode and the second power electrode and is configured to generate a control signal in response to the difference between a reference voltage from a reference voltage source and the output voltage of the regulator output electrode. The output transistor is connected between the regulator power electrode and the regulator output electrode and is configured to operate in response to the control signal. The detection circuit is connected between the first power electrode and the second power electrode and operates to provide the detection output electrode with one or more detection signals indicating the presence or absence of the excess output current, based on a level signal indicating the excess output current of the regulator circuit and the control signal.
[0015] A power supply device according to a third aspect of this disclosure comprises a semiconductor device according to a second aspect and a circuit board on which the semiconductor device is mounted. [Brief explanation of the drawing]
[0016] [Figure 1] Figure 1 is a schematic diagram showing the power supply circuit and semiconductor device according to this embodiment. [Figure 2] Figure 2 is a schematic diagram showing the power supply circuit and semiconductor device according to this embodiment. [Figure 3] Figure 3 is a schematic diagram showing an exemplary power supply circuit and semiconductor device according to this embodiment. [Figure 4] Figure 4 is a diagram illustrating the operation of the power supply circuit and semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a schematic diagram showing an exemplary power supply circuit and semiconductor device according to this embodiment. [Figure 6] Figure 6 is a diagram illustrating the operation of the power supply circuit and semiconductor device shown in Figure 5. [Figure 7] Figure 7 is a schematic diagram showing an exemplary power supply circuit and semiconductor device according to this embodiment.
[0017] [Detailed explanation] Hereinafter, embodiments for implementing the present disclosure will be described with reference to the drawings. The same parts are denoted by the same reference numerals, and redundant descriptions are omitted.
[0018] FIG. 1 is a drawing schematically showing a power supply circuit and a semiconductor device according to this embodiment. FIG. 2 is a drawing schematically showing a power supply circuit and a semiconductor device according to this embodiment.
[0019] Referring to FIG. 1, the power supply circuit 11(11b) includes a semiconductor device 13 and a cutoff transistor 15. Referring to FIG. 2, the power supply circuit 11(11c) includes a semiconductor device 13 without including the cutoff transistor 15.
[0020] Referring to FIGS. 1 and 2, the semiconductor device 13 includes a regulator circuit 17 such as a step-down regulator circuit and a detection circuit 19. The semiconductor device 13 includes a plurality of electrodes 21 such as pad electrodes. Exemplary electrodes include a first power supply electrode 21b, a second power supply electrode 21c, a regulator power supply electrode 21d, a regulator output electrode 21f, and a detection output electrode 21g (the reference numeral "21" is used when generally referring to electrodes without illustration).
[0021] The power supply circuit 11 can include a capacitor 28b connected to the regulator power supply electrode 21d. The power supply circuit 11 can include a capacitor 28c connected to the regulator output electrode 21f.
[0022] The semiconductor device 13 includes an internal power supply line 18 connected to the regulator output electrode 21f, and the semiconductor device 13 includes an internal circuit 24 connected to the output of the regulator circuit 17. The internal circuit 24 is connected to the internal power supply line 18 and is driven by the output voltage of the regulator circuit 17. Specifically, the internal circuit 24 receives a current I0 from the output of the regulator circuit 17 via the internal power supply line 18.
[0023] The cutoff transistor 15 is connected between the first power supply electrode 21b and the regulator power supply electrode 21d and can act as a switch. The cutoff transistor 15 is configured to operate in response to the detection signal SDET received from the semiconductor device 13 via the detection output electrode 21g.
[0024] The cutoff transistor 15 and the first power supply electrode 21b are connected to the power supply 10 to receive power. The first power supply electrode 21b is connected to the first power line 20 of the semiconductor device 13, and the second power supply electrode 21c is connected to the second power line 22 of the semiconductor device 13. The first power supply electrode 21b provides the first power supply voltage (VDD1), and the regulator power supply electrode 21d provides the second power supply voltage (VDD2). The second power supply voltage (VDD2) is connected to the power supply 10 via the cutoff transistor 15.
[0025] The regulator circuit 17 includes a control circuit 23 and an output transistor 25.
[0026] The control circuit 23 is connected between the first power line 20 of the first power electrode 21b and the second power line 22 of the second power electrode 21c. The control circuit 23 is configured to generate a control signal SCNT in response to a reference voltage VREF from a reference voltage source 27 and a feedback voltage from the output voltage of the regulator output electrode 21f. The feedback voltage can be provided from the output voltage of the regulator output electrode 21f via an internal or external internal voltage divider circuit, or directly.
[0027] The output transistor 25 is connected between the regulator power supply electrode 21d and the regulator output electrode 21f and is configured to operate in response to the control signal SCNT. The detection circuit 19 is connected between the first power line 20 and the first power supply electrode 21b and the second power line 22 and the second power supply electrode 21c. The detection circuit 19 generates a monitor voltage SMON indicating the value of the output current of the output transistor 25 in response to the control signal SCNT. The detection circuit 19 generates one or more detection signals SDET based on the level signal SLEV indicating the level of the excess output current of the regulator circuit 17 and the monitor voltage SMON. The detection circuit 19 also operates to provide the detection signal SDET to the detection output electrode 21g, for example, via the output port circuit 26.
[0028] The semiconductor device 13 includes a detection circuit 19 but does not include a cutoff transistor 15. The detection circuit 19 does not occupy a large size on the semiconductor device 13. The semiconductor device 13 has a reduced chip size due to the absence of the cutoff transistor 15. Furthermore, the absence of the cutoff transistor 15 allows for a reduction in the size of the output transistor 25, as already described. The cost of implementing overcurrent protection can be reduced in terms of the chip size of the semiconductor device 13.
[0029] The diagrams referenced in the following explanation depict transistor circuit symbols. These transistor symbols include p-type and n-type field-effect transistors. The source, drain, gate, and back gate of these transistors are denoted by the symbols "S," "D," "G," and "B," respectively.
[0030] The exemplary output transistor 25 can be a transistor in the semiconductor integrated circuit of the semiconductor device 13, and can include, for example, a p-type or n-type field-effect transistor, Figure 1 depicts a p-type field-effect transistor.
[0031] As can be understood from the following explanation, the cutoff transistor 15 may include a transistor independent of the transistor type of the semiconductor integrated circuit of the semiconductor device 13. An exemplary cutoff transistor 15 may include at least one of a p-type field-effect transistor, an n-type field-effect transistor, and a bipolar transistor. The sensing circuit 19 may provide one or more sensing signals SDET depending on the type of cutoff transistor 15. The exemplary cutoff transistor 15 may have the same conductivity type as the output transistor 25.
[0032] The output transistor 25 has a drain (D) connected to the regulator output electrode 21f, a gate (G) that receives the control signal SCNT, a source (S) connected to the regulator power supply electrode 21d, and a back gate (B) connected to this source (S).
[0033] The detection circuit 19 is configured to generate a detection signal SDET based on the level signal SLEV and the monitor voltage SMON. The detection circuit 19 is connected to the detection output electrode 21g, for example, via the output port circuit 26.
[0034] The exemplary detection circuit 19 may include a monitor circuit 31 and a comparison circuit 33. The monitor circuit 31 is configured to generate a monitor voltage SMON. The comparison circuit 33 is configured to compare a level signal SLEV with the monitor voltage SMON to generate a detection signal SDET. The comparison circuit 33 is connected, for example, to an output port circuit 26. The output port circuit 26 is connected to a detection output electrode 21g.
[0035] In the exemplary semiconductor device 13, the detection circuit 19 may include a selection circuit 30. The selection circuit 30 is connected to the output of the comparator circuit 33, the inverted output of the comparator circuit 33 (the inverted output of the inverter 34), and the signal line of the signal SIG from the internal circuit 24. The selection circuit 30 selects these multiple input signals in response to the selection signal SEL. The selection circuit 30 is connected to the output port circuit 26.
[0036] The monitor circuit 31 may include a first conversion circuit 35 and a second conversion circuit 37.
[0037] The first conversion circuit 35 generates a monitor current IMON in response to the control signal SCNT, and also generates a first voltage V1 corresponding to the monitor current IMON.
[0038] The second conversion circuit 37 generates a monitor voltage SMON based on the voltage V1 of the first conversion circuit 35.
[0039] Specifically, the first conversion circuit 35 may include a first load 41 and a first current source circuit 43. The first load 41 and the first current source circuit 43 are connected in series to form a first series connection 45, which is an exemplary first series connection 45 connected between the first power supply electrode 21b and the regulator output electrode 21f. The first load 41 may include, for example, a resistor R1.
[0040] The first current source circuit 43 supplies a monitor current IMON to the first load 41 in accordance with the current supplied by the output transistor 25 in response to the control signal SCNT. The first load 41 generates a differential voltage (difference) between the voltage at the first power supply electrode 21b (VDD1) and the first voltage V1 at the first conversion circuit 35. The differential voltage is determined according to the monitor current IMON.
[0041] The first current source circuit 43 includes a monitor transistor 47, which supplies current in response to a control signal SCNT. The monitor transistor 47 supplies a monitor current IMON associated with the output current IOUT of the output transistor 25. The monitor current IMON has a smaller value than the output current IOUT; for example, the output current IOUT can be 10 or 100 times the monitor current IMON. The exemplary first current source circuit 43 supplies the monitor current IMON to the internal power line 18.
[0042] Specifically, the monitor transistor 47 has a drain (D) connected to the regulator output electrode 21f, a gate (G) that receives the control signal SCNT, a source (S) connected to the first power supply electrode 21b via the first load 41, and a back gate (B) connected to the source.
[0043] The second conversion circuit 37 may include a second current source circuit 51 and a second load 53. The second current source circuit 51 and the second load 53 are connected in series to form a second series connection 55, and the second series connection 55 is connected between the first shared node SN1 of the first load 41 and the first current source circuit 43 and the second power supply electrode 21c.
[0044] The second conversion circuit 37 generates a monitor voltage SMON at the second shared node SN2 of the second current source circuit 51 and the second load 53. The second load 53 may include, for example, a resistor R2.
[0045] In the second conversion circuit 37, the second current source circuit 51 may include a current source transistor 57. The current source transistor 57 has a drain (D) connected to the second shared node SN2 of the second current source circuit 51 and the second load 53, a gate (G) connected to the reference line 60, a source connected to the second power supply electrode 21c, and a back gate (B) connected to the source.
[0046] The monitor circuit 31 may include a reference current source 49, which may include a reference current circuit 61 and a third load 63. The reference current circuit 61 and the third load 63 constitute a third series connection 65 connected in series between the first power supply electrode 21b and the second power supply electrode 21c. The third load 63 may include a load transistor 67. The load transistor 67 has a drain (D) and gate (G) connected to the reference line 60, a source (S) connected to the second power supply electrode 21c, and a back gate (B) connected to the source (S). Specifically, the load transistor 67 is diode-connected to constitute the third load 63. The reference current source 49 provides a voltage to the reference line 60 in response to the current of the reference current circuit 61.
[0047] The monitor circuit 31 further includes a level generation circuit 39, which generates a level signal SLEV indicating the level of the excess output current of the regulator circuit 17. The level generation circuit 39 is connected between the first power supply electrode 21b and the second power supply electrode 21c. The level generation circuit 39 includes a third series connection 75, which includes a third load 71 and a third current source circuit 73 connected in series with each other. The level generation circuit 39 provides the level signal SLEV to a third shared node SN3 of the third load 71 and the third current source circuit 73. The third load 71 may include, for example, a resistor R3.
[0048] The second current source circuit 51 is connected to the third load 63 of the reference current source 49, and the second current source circuit 51 and the third load 63 constitute a current mirror circuit. Furthermore, the third current source circuit 73 is connected to the third load 63 of the reference current source 49, and the third current source circuit 73 and the third load 63 constitute a current mirror circuit.
[0049] In the following explanation, "W1," "L1," "W2," and "L2" will be used as references for the explanation of the formulas, although these are not illustrated. The output transistor 25 and the monitor transistor 47 receive the control signal SCNT and supply currents (IOUT, IMON) respectively, corresponding to the size ratio of the transistors. The monitor transistor 47 has a gate width (W1) and a gate length (L1), while the output transistor 25 has a gate width (W2) and a gate length (L2). With respect to exemplary ratios, the ratio of the gate width (W2) to the gate length (L2) of the output transistor 25 (W2 / L2) is greater than the ratio of the gate width (W1) to the gate length (L1) of the monitor transistor (W1 / L1).
[0050] The detection circuit 19 may include a deactivation circuit, such as a switch SW, to deactivate the detection circuit 19. In the exemplary detection circuit 19, the level generation circuit 39 may include a switch SW. The switch SW controls the power supply to the third series connection 75. The overcurrent protection function can be activated by closing the switch SW. On the other hand, when the switch SW is opened, the exemplary level generation circuit 39 sets the level signal SLEV to zero, and the overcurrent protection function is deactivated. The comparator circuit 33 may also be deactivated. The monitor transistor 47 is connected to the internal power line 18 and also operates in response to the control signal SCNT even when the overcurrent protection is deactivated.
[0051] The exemplary semiconductor device 13 may have an activated mode and a deactivated mode for overcurrent protection. A mode signal that identifies these modes controls the conduction and non-conductivity of the switch SW via a mode signal line 32. This mode signal can be generated by an exemplary internal circuit 24 and provided to the switch SW via the mode signal line 32.
[0052] Referring to Figures 1 and 2, the power supply circuit 11 (11b, 11c) and the circuit board BD can constitute a power supply unit. The circuit board BD may include, for example, a printed circuit board. The exemplary semiconductor device 13 can be housed in a package and mounted on the circuit board BD, however, this disclosure is not limited thereto.
[0053] In the power supply circuit 11(11b) in Figure 1, the semiconductor device 13 and the cutoff transistor 15 are mounted on the circuit board BD. The detection signal SDET propagates from the semiconductor device 13 to the cutoff transistor 15 via the control line 36 on the circuit board BD.
[0054] In the power supply circuit 11(11c) of Figure 2, the semiconductor device 13 is mounted on the circuit board BD, which includes a conductor wire 40 connecting the first power supply electrode 21b and the regulator power supply electrode 21d. The switch SW is non-conductive, and the detection circuit 19 is deactivated. Where possible, the selection circuit 30 can be selected to provide the signal SIG to the output port circuit 26 in response to the selection signal SEL.
[0055] Figure 3 is a schematic diagram showing an exemplary power supply circuit and semiconductor device according to this embodiment. Figure 4 is a diagram showing the operation of the power supply circuit and semiconductor device shown in Figure 3. Figure 5 is a schematic diagram showing an exemplary power supply circuit and semiconductor device according to this embodiment. Figure 6 is a diagram showing the operation of the power supply circuit and semiconductor device shown in Figure 5. Figure 7 is a schematic diagram showing an exemplary power supply circuit and semiconductor device according to this embodiment.
[0056] In Figures 3, 5, and 7, the reference numerals shown in Figure 1 are used where possible. In Figure 4, the upper graph shows current on the horizontal axis and voltage on the vertical axis. In Figure 6, the upper graph shows current on the horizontal axis and voltage on the vertical axis.
[0057] Referring to Figure 3, a power supply circuit 11d is shown, which includes a semiconductor device 13 and a cutoff transistor 15b. In the exemplary power supply circuit 11d, the cutoff transistor 15b may include a p-type field-effect transistor (P1). For simplicity, the exemplary power supply circuit 11d does not include a selection circuit 30, and the detection circuit 19 is directly connected to the output port circuit 26.
[0058] In the normal operation of the regulator circuit 17 in Figure 3, the detection circuit 19 detects that no excessive output current is occurring and maintains the detection signal SDET at "L". This detection signal SDET causes the p-type field-effect transistor (P1) of the cutoff transistor 15b to conduct.
[0059] As the current flowing through the monitor transistor 47 increases, the voltage at the first shared node SN1 decreases. When the voltage at the first shared node SN1 decreases, the voltage at the second shared node SN1 of the monitor circuit 31 (monitor voltage SMON) decreases. The level signal SLEV, which indicates the level of the excess output current of the regulator circuit 17, is independent of the current flowing through the monitor transistor 47. In the detection circuit 19, as shown in the lower part of Figure 4, in response to the monitor voltage SMON crossing the level signal SLEV, the comparator circuit 33 detects that an excess output current has occurred and changes the detection signal SDET from "L" to "H". This detection signal SDET deconducts the p-type field-effect transistor (P1) of the cutoff transistor 15b. The exemplary output port circuit 26 is connected as a power supply system between the first power line 20 of the first power electrode 21b and the second power line 22 of the second power electrode 21c, and this power supply system determines the voltage values of the "L" and "H" voltage levels of the detection signal SDET.
[0060] Referring to Figure 5, the power supply circuit 11f is shown, which includes a semiconductor device 13 and a cutoff transistor 15c. The cutoff transistor 15c may include an n-type field-effect transistor (N4). The semiconductor device 13 includes an inverter 34 connected to the output of the comparator circuit 33. Note that, for simplicity, the exemplary power supply circuit 11f does not include a selection circuit 30, and the detection circuit 19 is directly connected to the output port circuit 26.
[0061] In the normal operation of regulator circuit 17 in Figure 5, the detection circuit 19 detects that no excessive output current is occurring and maintains the detection signal SDET at "H". This detection signal SDET causes the n-type field-effect transistor (N4) of the cutoff transistor 15b to conduct.
[0062] As the current flowing through the monitor transistor 47 increases, the voltage at the first shared node SN1 decreases. When the voltage at the first shared node SN1 decreases, the voltage at the second shared node SN1 (monitor voltage SMON) decreases. The level signal SLEV, which indicates the level of the excess output current of the regulator circuit 17, does not depend on the current flowing through the monitor transistor 47. As shown in the lower part of Figure 5, when the monitor voltage SMON crosses the level signal SLEV, the comparison circuit 33 detects that an excess output current has occurred and changes the detection signal SDET from "H" to "L". This detection signal SDET deconducts the n-type field-effect transistor (N4) of the cutoff transistor 15c.
[0063] Referring to Figure 7, a power supply circuit 11g is shown, which includes a semiconductor device 13 and a cutoff transistor 15d. The cutoff transistor 15d may include a bipolar transistor, such as an NPN bipolar transistor or a PNP bipolar transistor. An exemplary cutoff transistor 15d may include an NPN bipolar transistor (BP1). The power supply circuit 11g detects overcurrent according to the operating waveform shown in Figure 4 of the power supply circuit 11b. The comparator circuit 33 is configured to supply base current to the NPN bipolar transistor (BP1). In Figure 7, the base, emitter, and collector of the NPN bipolar transistor (BP1) are referred to as "B", "E", and "C", respectively. When used in the description of a bipolar transistor, the symbol "B" indicates the base.
[0064] Let's explain the operation in detail. In the normal operation of the regulator circuit 17, the detection circuit 19 detects that no excessive output current is occurring and maintains the detection signal SDET at "H". This detection signal SDET causes the npn bipolar transistor (BP1) of the cutoff transistor 15d to conduct. The output port circuit 26 can provide base current to the npn bipolar transistor (BP1).
[0065] When the current flowing through the monitor transistor 47 increases, the voltage at the first shared node SN1 decreases. When the voltage at the first shared node SN1 decreases, the voltage at the second shared node SN1 (monitor voltage SMON) decreases. The level signal SLEV, which indicates the level of the excess output current of the regulator circuit 17, does not depend on the current flowing through the monitor transistor 47. When the monitor voltage SMON crosses the level signal SLEV, the comparator circuit 33 detects that an excess output current has occurred and the detection circuit 19 changes the detection signal SDET from "H" to "L". This detection signal SDET deconducts the npn bipolar transistor (BP1) of the cutoff transistor 15d.
[0066] As described above, this embodiment makes it possible to minimize the change in size of the semiconductor device when providing overcurrent protection to the regulator circuit of a semiconductor device. This provides a power supply circuit, semiconductor device, and power supply device that take into account both the user requirements and the supplier's technical aspects.
[0067] As can be understood from the above description, this embodiment can have various aspects as shown below.
[0068] The first embodiment of the power supply circuit according to this embodiment comprises a semiconductor device including a regulator circuit and a detection circuit, having a regulator power electrode, a regulator output electrode, a first power electrode, a second power electrode, and a detection output electrode; and a cutoff transistor connected between the first power electrode and the regulator power electrode and configured to operate in response to a detection signal received from the semiconductor device via the detection output electrode, wherein the regulator circuit includes a control circuit and an output transistor, the control circuit connected between the first power electrode and the second power electrode and configured to generate a control signal in response to the difference between a reference voltage from a reference voltage source and a feedback voltage from the output voltage of the regulator output electrode, the output transistor connected between the regulator power electrode and the regulator output electrode and configured to operate in response to the control signal, the detection circuit connected between the first power electrode and the second power electrode, the detection circuit generates a monitor voltage in response to the control signal, the detection circuit generates one or more detection signals based on a level signal indicating the level of the excess output current of the regulator circuit and the monitor voltage, and operates to provide the detection signal to the detection output electrode.
[0069] This power supply circuit allows for the configuration of an overcurrent detection function using an output transistor and detection circuit within the semiconductor device, as well as a cutoff transistor outside the semiconductor device.
[0070] In a second power supply circuit according to the first embodiment of this embodiment, the output transistor may have a drain connected to the regulator power supply electrode, a gate that receives the control signal, and a source and a back gate connected to each other.
[0071] According to this power supply circuit, the semiconductor device can be provided with a regulator power supply electrode connected to the drain of the output transistor to configure an overcurrent detection function.
[0072] In the third power supply circuit according to the first or second embodiment of this model, the cutoff transistor may have the same conductivity type as the output transistor.
[0073] According to this power supply circuit, the cutoff transistor can be provided with the same conductivity type as the output transistor.
[0074] In the power supply circuit of the first, second, or fourth embodiment according to the third embodiment of this model, the cutoff transistor may include a p-type field-effect transistor, an n-type field-effect transistor, and / or a bipolar transistor.
[0075] According to this power supply circuit, the cutoff transistor can be a p-type field-effect transistor, an n-type field-effect transistor, or a bipolar transistor.
[0076] In the power supply circuit of the first, second, third, or fifth embodiment according to the first, second, third, or fourth embodiment of this embodiment, the detection circuit may include a monitor circuit and a comparison circuit, wherein the monitor circuit is configured to receive the control signal and generate the monitor voltage, and the comparison circuit is configured to compare the level signal and the monitor voltage to generate the detection signal.
[0077] According to this power supply circuit, the detection signal can be generated using a monitor circuit and a comparator circuit based on a comparison between a monitor voltage associated with a control signal and a level signal.
[0078] In a sixth power supply circuit according to the fifth embodiment of this embodiment, the monitor circuit may include a first conversion circuit that generates a current associated with the control signal and a voltage corresponding to the current, and a second conversion circuit that generates the monitor voltage based on the voltage of the first conversion circuit.
[0079] According to this power supply circuit, the first and second conversion circuits can generate a monitor voltage based on a voltage corresponding to the current associated with the control signal.
[0080] In the seventh power supply circuit according to the sixth embodiment of this embodiment, the first conversion circuit constitutes a first series connection including a first load and a first current source circuit connected in series between the first power supply electrode and the regulator power supply electrode, the first current source circuit supplies a current to the first load corresponding to the current supplied by the output transistor in response to the control signal, and the first load can generate a differential voltage between the voltage of the first conversion circuit and the voltage of the first power supply electrode.
[0081] According to this power supply circuit, the first conversion circuit generates a differential voltage using the current that the first current source circuit flows through to the first load in the first series connection of the first current source circuit in order to determine the generation of an overcurrent, and this differential voltage can be associated with the generation of an overcurrent.
[0082] In the eighth power supply circuit according to the seventh embodiment of this embodiment, the first current source circuit includes a monitor transistor that carries current in response to the control signal, the monitor transistor carries current associated with the output current of the output transistor, and the monitor transistor may have a drain connected to the regulator power electrode, a gate that receives the control signal, and a source and back gate connected to and connected to the first load.
[0083] According to this power supply circuit, the monitor transistor in the first current source circuit can determine the current to flow to the first load in response to the control signal.
[0084] In the ninth power supply circuit according to the eighth embodiment of this embodiment, the second conversion circuit includes a second series connector, the second series connector includes a second current source circuit and a second load connected in series between the first shared node of the first load and the first current source circuit and the first power supply electrode, and the second conversion circuit can provide the monitor voltage to the second load and the second shared node of the second current source circuit.
[0085] According to this power supply circuit, the second conversion circuit is connected between the first shared node of the first conversion circuit and the first power supply electrode, and can operate in response to the voltage of the first shared node.
[0086] In the tenth power supply circuit according to the ninth embodiment of this embodiment, the monitor circuit includes a reference current circuit connected between the first power supply electrode and the second power supply electrode, the reference current circuit is capable of generating a current associated with the value of the level signal.
[0087] This power supply circuit allows the reference current circuit to determine the current associated with the value of the level signal.
[0088] In the 11th power supply circuit according to the 10th embodiment of this embodiment, the second current source circuit is connected to the reference current circuit, and the second current source circuit and the reference current circuit can constitute a current mirror circuit.
[0089] According to this power supply circuit, the second current source circuit can receive a specified current via a current mirror circuit.
[0090] In a power supply circuit of the twelfth embodiment according to the tenth or eleventh embodiment of this embodiment, the monitor circuit includes a level generating circuit connected between the first power supply electrode and the second power supply electrode and generating the level signal, and the level generating circuit may include a third load and a third current source circuit connected in series with each other.
[0091] According to this power supply circuit, a level generation circuit operates between the first power supply electrode and the second power supply electrode to generate a level signal.
[0092] In the 13th power supply circuit according to the 12th embodiment of this embodiment, the second current source circuit and the third current source circuit are connected to the reference current circuit, and the third current source circuit and the reference current circuit can constitute a current mirror circuit.
[0093] According to this power supply circuit, the third current source circuit can receive a specified current via the current mirror circuit.
[0094] In a 14th power supply circuit according to any one of the first to 13th embodiments of this embodiment, the semiconductor device may include an internal power line connected to the regulator output electrode and an internal circuit connected to the internal power line and driven by the output voltage of the regulator circuit.
[0095] According to this power supply circuit, in a semiconductor device in which a detection circuit can detect the generation of an overcurrent, the internal circuit can be driven by the output voltage of a regulator circuit and a detection circuit connected to an internal power line.
[0096] A semiconductor device of the 15th embodiment according to this embodiment comprises a first power electrode, a second power electrode, a regulator power electrode, a regulator output electrode, a detection output electrode, a regulator circuit, and a detection circuit, wherein the regulator circuit includes a control circuit and an output transistor, the control circuit is connected between the first power electrode and the second power electrode and is configured to generate a control signal in response to the difference between a reference voltage from a reference voltage source and the output voltage of the regulator output electrode, the output transistor is connected between the regulator power electrode and the regulator output electrode and is configured to operate in response to the control signal, and the detection circuit is connected between the first power electrode and the second power electrode and operates to provide the detection output electrode with one or more detection signals indicating the presence or absence of the excess output current based on a level signal indicating the excess output current of the regulator circuit and the control signal.
[0097] This semiconductor device allows for the provision of semiconductor devices with and without overcurrent protection, thereby enabling the configuration of a power supply circuit.
[0098] The seventeenth embodiment of the power supply device according to this embodiment may include a semiconductor device disclosed herein and a circuit board on which the semiconductor device is mounted.
[0099] This semiconductor device allows for the provision of semiconductor devices with and without overcurrent protection, enabling the construction of power supply circuits. The presence or absence of overcurrent protection can be determined by the pattern of the wiring conductors on the circuit board and the presence or absence of a cutoff transistor.
[0100] A power supply device of the 17th embodiment according to the 16th embodiment of this embodiment further comprises a cutoff transistor connected between the first power supply electrode and the regulator power supply electrode of the semiconductor device and configured to operate in response to a detection signal received from the semiconductor device via the detection output electrode, and the circuit board may mount the cutoff transistor and have control lines connecting the cutoff transistor and the detection output electrode to control the cutoff transistor.
[0101] According to this power supply, the cutoff transistor mounted on the circuit board enables the power supply circuit to provide a product without overcurrent protection.
[0102] In the 18th power supply device according to the 16th embodiment of this embodiment, the circuit board may include a conductor wire connecting the first power supply electrode and the regulator power supply electrode.
[0103] According to this power supply device, the conductive wires patterned on the circuit board make it possible to provide a product without overcurrent protection for configuring the power supply circuit.
[0104] This disclosure is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit of this disclosure. All such modifications are included in the technical concept of this disclosure. [Explanation of symbols]
[0105] 10...power supply, 11, 11b, 11d, 11f, 11g...power supply circuit, 13. Semiconductor equipment, 15, 15b, 15c, 15d...cutoff transistors, 17. Regulator circuit, 18...Internal power line, 19. Detection circuit, 20...1st power line, 21b...1st power supply electrode, 21c...Second power supply electrode, 21d... Regulator power supply electrode, 21f... Regulator output electrode, 21g...Detection output electrode, 22...Second power line, 23. Control circuits, 24...internal circuit, 25... Output transistor, 26. Output port circuit, 27. Reference voltage source, 28b, 28c... Capacitors, 30...Selection circuit, 31. Monitor circuit, 32-mode signal line, 33...comparison circuit, 34... Inverter, 35...First conversion circuit, 36...Control lines, 37...Second conversion circuit, 39-level generation circuit, 40...Conductor wire, 41, 53, 63, 71... load, 43...Current source circuit, 45, 55, 65... series connection, 47... Monitor transistor, 49...Reference current source, 51...Current source circuit, 57...Current source transistor, 60...Reference line, 61...Reference current circuit, 67... Load transistor, 73...Current source circuit, 75...Series connection, BD... Circuit board, I0...current, IMON... Monitor current, IOUT...Output current, R1, R2, R3...Resistor, SCNT... control signal, SDET... detection signal, SEL...Selection signal, SIG...signal, SLEV... level signal, SMON... Monitor voltage, SN1, SN2, SN3... Shared nodes, SW...switch, V1...Voltage, VREF...Reference voltage.
Claims
1. A semiconductor device having a regulator power electrode, a regulator output electrode, a first power electrode, a second power electrode, and a detection output electrode, and including a regulator circuit and a detection circuit, A cutoff transistor is connected between the first power supply electrode and the regulator power supply electrode and is configured to operate in response to a detection signal received from the semiconductor device via the detection output electrode, Equipped with, The regulator circuit includes a control circuit and an output transistor. The control circuit is connected between the first power supply electrode and the second power supply electrode, and is configured to generate a control signal in response to the difference between a reference voltage from a reference voltage source and a feedback voltage from the output voltage of the regulator output electrode. The output transistor is connected between the regulator power supply electrode and the regulator output electrode and is configured to operate in response to the control signal. The detection circuit is connected between the first power supply electrode and the second power supply electrode. The detection circuit generates a monitor voltage in response to the control signal, The detection circuit generates one or more detection signals based on a level signal indicating the level of the excess output current of the regulator circuit and the monitor voltage, and operates to provide the detection signals to the detection output electrode. power circuit.
2. The output transistor has a drain connected to the regulator power supply electrode, a gate that receives the control signal, and a source and back gate connected to each other. The power supply circuit described in claim 1.
3. The cutoff transistor has the same conductivity type as the output transistor. The power supply circuit described in claim 1.
4. The cutoff transistor includes at least one of a p-type field-effect transistor, an n-type field-effect transistor, or a bipolar transistor. The power supply circuit described in claim 1.
5. The detection circuit includes a monitor circuit and a comparison circuit. The monitoring circuit is configured to receive the control signal and generate the monitoring voltage. The comparison circuit is configured to compare the level signal and the monitor voltage to generate the detection signal. A power supply circuit as described in any one of claims 1 to 4.
6. The monitoring circuit includes a first conversion circuit that generates a current associated with the control signal and a voltage corresponding to the current, and a second conversion circuit that generates the monitoring voltage based on the voltage of the first conversion circuit. The power supply circuit described in claim 5.
7. The first conversion circuit includes a first series connector, the first series connector includes a first load and a first current source circuit connected in series between the first power supply electrode and the regulator power supply electrode. The first current source circuit supplies a current to the first load corresponding to the current supplied by the output transistor in response to the control signal, and the first load generates a differential voltage between the voltage of the first conversion circuit and the voltage of the first power supply electrode. The power supply circuit described in claim 6.
8. The first current source circuit includes a monitor transistor that supplies current in response to the control signal, The monitor transistor supplies a current associated with the output current of the output transistor. The monitor transistor has a drain connected to the regulator power supply electrode, a gate that receives the control signal, and a source and back gate that are connected to the first load and connected to each other. The power supply circuit described in claim 7.
9. The second conversion circuit includes a second series connector, the second series connector includes a second current source circuit and a second load connected in series between the first shared node of the first load and the first current source circuit and the first power electrode. The second conversion circuit provides the monitor voltage to the second load and the second shared node of the second current source circuit. The power supply circuit described in claim 8.
10. The monitor circuit includes a reference current circuit connected between the first power supply electrode and the second power supply electrode. The reference current circuit generates a current associated with the value of the level signal. The power supply circuit described in claim 9.
11. The second current source circuit is connected to the reference current circuit, and the second current source circuit and the reference current circuit constitute a current mirror circuit. The power supply circuit described in claim 10.
12. The monitoring circuit includes a level generation circuit connected between the first power supply electrode and the second power supply electrode, which generates the level signal. The level generation circuit includes a third load and a third current source circuit connected in series with each other. The power supply circuit described in claim 10.
13. The third current source circuit is connected to the reference current circuit, and the third current source circuit and the reference current circuit constitute a current mirror circuit. The power supply circuit according to claim 12.
14. The semiconductor device includes an internal power line connected to the regulator output electrode and an internal circuit connected to the internal power line and driven by the output voltage of the regulator circuit. The power supply circuit described in claim 1.
15. First power supply electrode and The second power supply electrode and Regulator power supply electrodes, Regulator output electrode and Detection output electrode and Regulator circuit and Detection circuit and Equipped with, The regulator circuit includes a control circuit and an output transistor. The control circuit is connected between the first power supply electrode and the second power supply electrode, and is configured to generate a control signal in response to the difference between the reference voltage from the reference voltage source and the output voltage of the regulator output electrode. The output transistor is connected between the regulator power supply electrode and the regulator output electrode and is configured to operate in response to the control signal. The detection circuit is connected between the first power supply electrode and the second power supply electrode, and operates to provide the detection output electrode with one or more detection signals indicating the presence or absence of the excess output current, based on the level signal indicating the excess output current of the regulator circuit and the control signal. Semiconductor equipment.
16. A semiconductor device as described in claim 15, A circuit board on which the aforementioned semiconductor device is mounted, Equipped with, power supply.
17. The semiconductor device further comprises a cutoff transistor connected between the first power supply electrode and the regulator power supply electrode, and configured to operate in response to a detection signal received from the semiconductor device via the detection output electrode, The circuit board is equipped with the cutoff transistor and has control lines connecting the cutoff transistor and the detection output electrode to control the cutoff transistor. A power supply device as described in claim 16.
18. The circuit board includes a conductor wire connecting the first power supply electrode and the regulator power supply electrode. A power supply device as described in claim 16.