Mesh decoding device, mesh decoding method, and program

Abstract

The goal is to reduce the amount of code required for displacement decoding using arithmetic decoding by applying an inverse quantization offset, while also maintaining accuracy without causing mismatches during inverse quantization. [Solution] The inverse quantization unit 204C of the displacement amount decoding unit 204 of the mesh decoding device 200 according to the present invention comprises an inverse quantization offset decoding unit 204C2 that decodes an inverse quantization offset from a displacement amount bitstream, an inverse quantization offset carry unit 204C3D that generates and outputs a carry inverse quantization offset by carrying the inverse quantization offset, and an inverse quantization offset adder unit 204C3E that generates and outputs a first coefficient sequence by adding a carry inverse quantization offset to a carry coefficient sequence generated based on a carry level value obtained by carrying the level value sequence.

Description

[Technical Field]

[0001] The present invention relates to a mesh decoding device, a mesh decoding method, and a program. [Background technology]

[0002] Non-patent document 1 discloses a technique for decoding point clouds using video information and additional information called an atlas.

[0003] Non-Patent Document 2 discloses a technology that extends Non-Patent Document 1 to mesh decoding applications.

[0004] Specifically, Non-Patent Document 2 first decodes a rough basic mesh and detailed displacement amounts, and secondly, reconstructs the mesh from both. Here, there are two methods for decoding the displacement amount: one using a video codec and the other using arithmetic decoding. In the method using arithmetic decoding, the level value is decoded from the syntax, and then the displacement amount is decoded. In the method using a video codec, an inverse quantization offset value IQ offset can be added to the coefficient level value to reduce the amount of code at the same image quality. The inverse quantization offset has the effect of correcting during inverse quantization when dead zone quantization is used during encoding, and has the effect of reducing the amount of code at the same image quality. Non-Patent Document 3 proposes applying the inverse quantization offset, which was previously only supported by video codecs, to the displacement amount decoding method using arithmetic decoding in order to further reduce the amount of code at the same image quality. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] “Information technology - Coded Representation of Immersive Media - Part 5: Visual Volumetric Video-based Coding (V3C) and Video-based Point Cloud Compression (V-PCC),” ISO / IEC JTC 1 / SC 29 / WG 7, ISO / IEC 23090-5:2021(2E). [Non-Patent Document 2] “Text of ISO / IEC DIS 23090-29 Video-based mesh coding” ISO / IEC JTC 1 / SC 29 / WG 7 N01027. [Non-Patent Document 3] Emi Myoudou, Koki Kishimoto, Jianfeng Xu, Kyohei Unno, Kei Kawamura [V-DMC] [EE4.7] [New] Harmonization of Inverse Quantization Offset for AC-based displacement coding ISO / IEC JTC 1 / SC 29 / WG 7 m70088. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, the method described in Non-Patent Document 3 had a problem in that when applying an inverse quantization offset to displacement decoding using arithmetic decoding, unnecessary codes were generated in the conversion scheme specification part, resulting in poor encoding efficiency.

[0007] Furthermore, in displacement decoding using arithmetic decoding, fixed-point calculations are essential to prevent mismatches in the reference values ​​of interpretations during inverse quantization. However, the method described in Non-Patent Document 3 does not support integer arithmetic, including fixed-point arithmetic, and therefore had the potential to cause mismatches due to floating-point arithmetic.

[0008] Therefore, the present invention has been made in view of the above-mentioned problems, and aims to provide a mesh decoding device, a mesh decoding method, and a program that can reduce the amount of code required for displacement decoding using arithmetic decoding by applying an inverse quantization offset, while also preventing mismatches during inverse quantization and making it easier to maintain accuracy. [Means for solving the problem]

[0009] The first feature of the present invention is a mesh decoding device comprising a displacement amount decoding unit configured to decode and output a first coefficient sequence from a displacement amount bitstream, the displacement amount decoding unit comprising an arithmetic decoding unit configured to decode and output a level value sequence from the displacement amount bitstream by arithmetic decoding, and an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantization of the level value sequence, the inverse quantization unit comprising an inverse quantization offset decoding unit that decodes an inverse quantization offset from the displacement amount bitstream, an inverse quantization offset carry unit that generates and outputs a carry inverse quantization offset by carrying the inverse quantization offset, and an inverse quantization offset adder that generates and outputs the first coefficient sequence by adding the carry inverse quantization offset to a carry coefficient sequence generated based on the carry level value obtained by carrying the level value sequence.

[0010] A second feature of the present invention is a mesh decoding device comprising a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream, the displacement decoding unit comprising an arithmetic decoding unit configured to decode and output a level value sequence from the displacement bitstream by arithmetic decoding, and an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantization of the level value sequence, the inverse quantization unit comprising an inverse quantization offset decoding unit that decodes an inverse quantization offset from the displacement bitstream, The gist of the invention is that it comprises: a first inverse quantization unit that generates and outputs a double carry coefficient sequence by inverse quantization of the carry level value sequence obtained by carrying the level value sequence using an inverse quantization scale; an inverse quantization offset combined carry unit that generates and outputs a double carry inverse quantization offset by carrying the inverse quantization offset by multiplier 1, which is a scale relating to the level value, and multiplier 2, which is a scale relating to the inverse quantization scale; an inverse quantization offset addition unit that generates and outputs a corrected double carry coefficient sequence by adding the double carry inverse quantization offset to the double carry coefficient sequence; and a second decrement unit that generates and outputs the first coefficient sequence by decrementing the corrected double carry coefficient sequence by multiplier 2.

[0011] A third feature of the present invention is a mesh decoding device comprising a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream, the displacement decoding unit comprising an arithmetic decoding unit configured to decode and output a level value sequence from the displacement bitstream by arithmetic decoding, and an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantization of the level value sequence, the inverse quantization unit comprising an inverse quantization offset decoding unit that decodes an inverse quantization offset from the displacement bitstream, and an offset correction first inverse quantization unit that generates and outputs the first coefficient sequence, which is a corrected carry coefficient sequence, by multiplying a carry coefficient sequence generated based on a carry level value obtained by carrying the level value sequence by an inverse quantization scale, and correcting it using a multiplier of 1, which is a scale relating to the inverse quantization offset and the level value.

[0012] A fourth feature of the present invention is a mesh decoding method comprising the step of decoding and outputting a first coefficient sequence from a displacement bitstream, wherein the process unit comprises: step A of decoding and outputting a level value sequence from the displacement bitstream by arithmetic decoding; and step B of generating and outputting the first coefficient sequence by inverse quantization of the level value sequence, wherein in step B, an inverse quantization offset is decoded from the displacement bitstream, a carry-over inverse quantization offset is generated and output by carrying over the inverse quantization offset, and the first coefficient sequence is generated and output by adding the carry-over inverse quantization offset to a carry-over coefficient sequence generated based on the carry-over level value obtained by carrying over the level value sequence.

[0013] A fifth feature of the present invention is a program that causes a computer to function as a mesh decoding device, wherein the mesh decoding device includes a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream. The displacement amount decoding unit comprises an arithmetic decoding unit configured to decode and output a level value sequence from the displacement amount bitstream by arithmetic decoding, and an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantization of the level value sequence. The inverse quantization unit comprises an inverse quantization offset decoding unit that decodes an inverse quantization offset from the displacement amount bitstream, an inverse quantization offset carry unit that generates and outputs a carry inverse quantization offset by carrying the inverse quantization offset, and an inverse quantization offset adder that generates and outputs the first coefficient sequence by adding the carry inverse quantization offset to a carry coefficient sequence generated based on the carry level value obtained by carrying the level value sequence. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a mesh decoding apparatus, a mesh decoding method, and a program that can reduce the amount of code applied to displacement amount decoding using arithmetic decoding by applying an inverse quantization offset, and that can maintain accuracy without causing a mismatch during inverse quantization.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a mesh processing system 1 according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the functional blocks of a mesh decoding apparatus 200 according to an embodiment. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of a V3C unit. [Figure 4] FIG. 4 is a diagram showing an example of the syntax configuration of a V3C unit header. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a bitstream. [Figure 6] FIG. 6 is a diagram showing an example of the configuration of a displacement amount bitstream. [Figure 7] FIG. 7 is a diagram showing an example of the syntax configuration of a displ_nal_unit_header. [Figure 8] FIG. 8 is a diagram showing an example of the correspondence between a displ_nal_unit_type and the content of a payload. [Figure 9] FIG. 9 is a diagram showing an example of the syntax configuration of a displ_layer_rbsp. [Figure 10] FIG. 10 is a diagram showing an example of the syntax configuration of a displ_sequence_parameter_set_rbsp in Non-Patent Document 3. [Figure 11] FIG. 11 is a diagram showing an example of the syntax configuration of a displ_frame_parameter_set_rbsp in Non-Patent Document 3. [Figure 12]Figure 12 shows an example of the syntax configuration of displ_header in Non-Patent Document 3. [Figure 13] Figure 13 shows an example of the syntax configuration of displ_quantization_parameters in Non-Patent Document 3. [Figure 14] Figure 14 shows an example of the possible transformation methods for dsps_transform_method, dfps_transform_method, and dh_transform_method in Non-Patent Document 3. [Figure 15] Figure 15 shows an example of the syntax structure of displ_sequence_parameter_set_rbsp. [Figure 16] Figure 16 shows an example of the syntax structure of displ_header. [Figure 17] Figure 17 shows an example of the configuration of the displacement decoding unit 204 of a mesh decoding device 200 according to one embodiment. [Figure 18] Figure 18 shows an example of the configuration of the offset correction first inverse quantization unit 204C3 of the inverse quantization unit 204C of the first displacement amount decoding unit 2041 of the displacement amount decoding unit 204 of the mesh decoding device 200 according to one embodiment. [Figure 19] Figure 19 shows an example of the configuration of the first inverse quantization unit 204C3A of the offset correction first inverse quantization unit 204C3 of the first displacement amount decoding unit 2041 of the displacement amount decoding unit 204 of the mesh decoding device 200 according to one embodiment. [Figure 20] Figure 20 shows an example of the configuration of the offset correction first inverse quantization unit 204C3 of the inverse quantization unit 204C of the first displacement amount decoding unit 2041 of the displacement amount decoding unit 204 of the mesh decoding device 200 according to one embodiment. [Figure 21] Figure 21 shows an example of the configuration of the mesh reconstruction unit 206 of a mesh decoding device 200 according to one embodiment. [Figure 22]Figure 22 shows an example of the configuration of the sub-mesh reconstruction unit 206A of the mesh reconstruction unit 206 of the mesh decoding device 200 according to one embodiment. [Figure 23] Figure 23 is a flowchart showing an example of the processing of the first displacement decoding unit 2041 of the displacement decoding unit 204 of the mesh decoding device 200 according to one embodiment. [Figure 24] Figure 24 is a flowchart showing an example of the processing of the first displacement amount decoding unit 2041 of the displacement amount decoding unit 204 of the mesh decoding device 200 according to one embodiment. [Modes for carrying out the invention]

[0016] Embodiments of the present invention will be described below with reference to the drawings. Note that the components in the following embodiments can be replaced with existing components as appropriate, and various variations are possible, including combinations with other existing components. Therefore, the description of the following embodiments does not limit the content of the invention as described in the claims.

[0017] <First Embodiment> This embodiment is based on V3C described in Non-Patent Document 1. In V3C, the atlas is a collection of rectangular regions and related information arranged on a frame, corresponding to a three-dimensional space.

[0018] The mesh processing system 1 according to this embodiment will be described below with reference to Figures 1 to 24.

[0019] Figure 1 shows an example of the configuration of the mesh processing system 1 according to this embodiment. As shown in Figure 1, the mesh processing system 1 includes a mesh encoding device 100 and a mesh decoding device 200.

[0020] Figure 2 shows an example of the functional block of the mesh decoding device 200 according to this embodiment.

[0021] As shown in Figure 2, the mesh decoding device 200 includes a V3C unit separation unit 201, an atlas decoding unit 202, a basic mesh decoding unit 203, a displacement decoding unit 204, a texture decoding unit 205, and a mesh reconstruction unit 206.

[0022] The V3C unit separation unit 201 is configured to separate the bitstream into an atlas bitstream, a basic mesh bitstream, a displacement bitstream, and a texture bitstream.

[0023] The Atlas decoding unit 202 is configured to decode and output the Atlas from the Atlas bitstream.

[0024] The basic mesh decoding unit 203 is configured to decode and output the basic mesh from the basic mesh bitstream.

[0025] The displacement amount decoding unit 204 is configured to decode and output a level value image or a first coefficient sequence from the displacement amount bitstream.

[0026] The texture decoding unit 205 is configured to decode and output a texture from a texture bitstream. The texture decoding unit 205 may decode the texture using HEVC.

[0027] The mesh reconstruction unit 206 is configured to reconstruct and output a mesh using the atlas decoded by the atlas decoding unit 201, the basic mesh decoded by the basic mesh decoding unit 203, and the level value image or first coefficient sequence decoded by the displacement decoding unit 204.

[0028] (Bitstream structure) The bitstream may also be composed of multiple V3C units combined together.

[0029] Figure 3 shows an example of the configuration of a V3C unit. A V3C unit may consist of a V3C unit header and a V3C unit payload.

[0030] Figure 4 shows an example of the syntax configuration of a V3C unit header. The V3C unit header may include vuh_unit_type, which indicates the type of V3C unit.

[0031] Figure 5 shows an example of a bitstream configuration. The bitstream may consist of a V3C parameter set, an atlas bitstream, a basic mesh bitstream, a displacement bitstream, and a texture bitstream.

[0032] The vuh_unit_type may contain any of the following: V3C_VPS, which indicates the V3C parameter set; V3C_AD, which indicates the atlas bitstream; V3C_BMD, which indicates the basic mesh bitstream; V3C_GVD, which indicates the displacement bitstream; or V3C_AVD, which indicates the texture bitstream.

[0033] (Configuration of the displacement bitstream) Figure 6 shows an example of the configuration of a displacement bitstream. The displacement bitstream may also consist of a V3C unit payload with displ_nal_unit, which represents a NAL unit.

[0034] displ_nal_unit may consist of displ_nal_unit_header, which indicates the header of the NAL unit in the displacement bitstream, and the payload of the NAL unit in the displacement bitstream.

[0035] Figure 7 shows an example of the syntax structure of displ_nal_unit_header.

[0036] The displ_nal_unit_header may consist of a displ_nal_forbidden_zero_bit indicating the beginning of the write-protected section and a displ_nal_unit_type indicating the type of data in the payload.

[0037] Figure 8 shows an example of the correspondence between displ_nal_unit_type and the contents of the payload.

[0038] The contents of the payload may be defined as follows: if displ_nal_unit_type is 0, it is displ_sequence_parameter_set_rbsp, which represents the sequence parameter set for the displacement amount; if displ_nal_unit_type is 1, it is displ_frame_parameter_set_rbsp, which represents the frame parameter set for the displacement amount; and if displ_nal_unit_type is 2, it is displ_layer_rbsp, which represents the displacement amount data.

[0039] Figure 9 shows an example of the syntax structure of displ_layer_rbsp. displ_layer_rbsp may include displ_header, which indicates the displacement header, and displ_data_unit, which indicates the displacement data.

[0040] Figures 10 to 14 show an example of the syntax configuration and transformation method in Non-Patent Literature 3. The inverse quantization offset is applied only when the wavelet transform is used as the transformation method. Therefore, the inverse quantization offset is applicable only when the transformation method, transform_method, is a wavelet transform.

[0041] Figure 10 shows an example of the syntax configuration of displ_sequence_parameter_set_rbsp in Non-Patent Literature 3. displ_sequence_parameter_set_rbsp includes dsps_transform_method, which indicates the transformation method specified in the sequence layer.

[0042] Figure 11 shows an example of the syntax configuration of displ_frame_parameter_set_rbsp in Non-Patent Document 3. The displ_frame_parameter_set_rbsp shown in Figure 11 includes dfps_transform_method_enable_flag, which indicates whether or not a transformation method specified in the frame layer exists. In addition, if a transformation method specified in the frame layer exists, the displ_frame_parameter_set_rbsp shown in Figure 11 includes dfps_transform_method, which is the transformation method.

[0043] Figure 12 shows an example of the syntax configuration of displ_header in Non-Patent Literature 3. displ_header includes dh_transform_method_override_flag, which indicates the override of the transformation method specified in the displacement header layer. Also, if there is an override, displ_header includes dh_transform_method, which is the transformation method.

[0044] Figure 13 shows an example of the syntax configuration of displ_quantization_parameters in Non-Patent Document 3. displ_quantization_parameters includes dqp_inverse_quantization_offset_enable_flag, which indicates whether or not the inverse quantization offset is enabled. If the inverse quantization offset is enabled, displ_quantization_parameters includes dqp_inverse_quantization_offset_sign_delta, dqp_inverse_quantization_offset_value_log2_prec1_delta, and dqp_inverse_quantization_offset_value_log2_prec2_delta, which are numerical values ​​for calculating the value of the inverse quantization offset.

[0045] Figure 14 shows examples of possible transformation methods for dsps_transform_method, dfps_transform_method, and dh_transform_method in Non-Patent Literature 3. NONE indicates no transformation, LINEAR_LIFTING indicates a lifting wavelet transform, and RESERVED indicates that it is reserved and not currently implemented. dsps_transform_method, dfps_transform_method, and dh_transform_method in Non-Patent Literature 3 are the same as asve_transform_method, afve_transform_method, and mdu_transform_method.

[0046] However, if the transformation method is not a wavelet transform, the inverse quantization offset does not need to be applied, and therefore the transformation method does not need to be signaled by the displacement. Accordingly, the syntax can be modified as shown in Figures 15 and 16.

[0047] Figure 15 shows an example of the syntax configuration for displ_sequence_parameter_set_rbsp. displ_sequence_parameter_set_rbsp may include dsps_inverse_quantization_offset_present_flag, which indicates whether or not an inverse quantization offset exists.

[0048] Figure 16 shows an example of the syntax configuration of displ_header. displ_header may include dsps_inverse_quantization_offset_enable_flag, which indicates whether the inverse quantization offset is valid for the target data unit (the target frame if there is one data unit per frame) if an inverse quantization offset exists.

[0049] Furthermore, if the inverse quantization offset is enabled, displ_header may include dh_inverse_quantization_offset_sign, dh_verse_quantization_offset_value_log2_prec1_delta, and dh_inverse_quantization_offset_value_log2_prec2_delta, which are used to calculate the inverse quantization offset.

[0050] (Displacement decoding unit 204) Figure 17 shows an example of the configuration of the displacement decoding unit 204. As shown in Figure 17, the displacement decoding unit 204 comprises at least one of a first displacement decoding unit 2041 and a second displacement decoding unit 2042.

[0051] As shown in Figure 17, the first displacement decoding unit 2041 comprises an arithmetic decoding unit 204B and an inverse quantization unit 204C. The first displacement decoding unit 2041 may further include an adder 204D, an interpretation unit 204E, and a frame buffer 204F. If there is no interpretation, the first displacement decoding unit 2041 may not include the adder 204D, the interpretation unit 204E, and the frame buffer 204F.

[0052] The arithmetic decoding unit 204B is configured to decode and output the level value sequence level_coeff from the displacement bitstream using arithmetic decoding. Here, the arithmetic decoding unit 204B initially initializes all level values ​​to 0.

[0053] If ddu_nz_subBlock=0, which is the case when there are no non-zero values ​​in the subblock, the arithmetic decoding unit 204B may omit the determination of the level value by arithmetic decoding and output a zero vector as described later.

[0054] The inverse quantization unit 204C is configured to inversely quantize the level value sequence, generate a correction carry coefficient sequence with the inverse quantization offset added, and output it.

[0055] Here, the inverse quantization unit 204C is configured to perform inverse quantization of the level value sequence by multiplying by the inverse quantization scale iscale or by multiplying by the reciprocal of the inverse quantization scale and performing offset correction.

[0056] If there is no interpretation, the correction carry coefficient sequence calculated by the inverse quantization unit 204C becomes the first coefficient sequence.

[0057] If interpretation is available, the adder 204D is configured to add the predicted coefficient sequence obtained from the interpretation unit 204E and the correction carry coefficient sequence (actually, the predicted residual sequence) obtained from the inverse quantization unit 204C to generate and output a coefficient sequence (the first carry coefficient sequence of the reference frame or the double carry first coefficient sequence of the reference frame, sometimes collectively referred to as the first carry coefficient sequence of the reference frame). The coefficient sequence generated here is output to the frame buffer 204F.

[0058] The interpretation unit 204E is configured to read a reference frame indicated by a reference list from the frame buffer 204F, and perform interpretation using the carry first coefficient sequence or the double carry first coefficient sequence of the reference frame to generate and output a predicted coefficient sequence.

[0059] The interpretation unit 204E may determine the prediction coefficients for each frequency in the decoded frame by directly referencing the coefficients for the corresponding frequencies in the reference frame.

[0060] The frame buffer 204F is configured to acquire and store the predicted residual sequence or the predicted coefficient sequence from the first inverse quantization unit 204C or the adder 204D, respectively.

[0061] The frame buffer 204F is configured to output the first coefficient sequence of the reference frame according to control information (not shown).

[0062] The first digit down unit 204G may downshift the correction carry coefficient sequence using a multiplier of 1 (fixedpointprec1), which is a scale related to the level value described later. Scaling refers to changing the magnitude by multiplication or bit shifting. For example, the first digit down unit 204G may downshift the correction carry coefficient sequence output from the inverse quantization unit 204C by 2 fixedpointprec1 By multiplying by the reciprocal of (the correction down coefficient sequence output from the inverse quantization unit 204C is 2 fixesdpointprec1By dividing by (), the correction carry coefficient sequence is shifted down, and the first coefficient sequence is output. Fixedpointprec1 will be described later.

[0063] Such digit reduction may be performed after the inverse transformation described later (see Figure 22), or after the addition of the displacement, and depends on the type and range of the numerical values ​​used during encoding. Note that after such digit reduction, the correction digit reduction coefficient sequence may no longer be an integer.

[0064] The inverse quantization unit 204C avoids floating-point arithmetic and performs calculations using integers. The inverse quantization unit 204C carries over as needed to maintain the precision of valid numerical values. This entire set of calculations is sometimes referred to as fixed-point arithmetic. With this configuration, mismatches caused by floating-point arithmetic can be prevented by performing addition, subtraction, multiplication, and division using integers.

[0065] The inverse quantization unit 204C should increase the value within the range that does not overflow so that there are more significant digits, and round down, round up, or round to the nearest integer for digits below a certain level. In this way, the number of significant digits is increased by carrying over, and by making it an integer, the mismatch caused by floating-point numbers can be eliminated.

[0066] In this embodiment, increasing a value is called a carry, and decreasing a value is called a fall. Note that carry and fall may be not only binary carry and fall by bit shift, but also decimal carry and fall. Furthermore, using multipliers 1 and 2 described later, increasing 1 or a specific value may be called a carry, and using such multipliers 1 and 2 to decrease 1 or a specific value may be called a fall. Multiplier 1 is a scale related to the level value, and multiplier 2 is a scale related to the inverse quantization scale.

[0067] As shown in Figure 17, the inverse quantization unit 204C may include a first digit shift unit 204C1, an inverse quantization offset decoding unit 204C2, and an offset correction first inverse quantization unit 204C3.

[0068] If the level value sequence can already be decoded with an integer that has been carried over by a multiplier of 1, the first carry unit 204C1 is unnecessary, but the information of multiplier 1 is retained.

[0069] The first digit carry unit 204C1 is configured to generate and output a carry-over level value sequence by carrying over the absolute value of the level value sequence level_coeff using fixedpointprec1, which has a multiplier of 1.

[0070] The multiplier 1, fixedpointprec1, and the multiplier 2, fixedpointprec2 (described later), may be used as multipliers of a power of 2, or they may be used directly as scale values ​​without being raised to a power. Multiplier 1 is a scale value related to the carry (or cut) of the level value, and multiplier 2 is a scale value related to the carry (or cut) of the inverse quantization scale iscale (described later).

[0071] When multipliers 1 and 2 are used as multipliers for powers of 2, they can be used as bit shift amounts for carry and carry operations. With this configuration, processing can be done quickly through shift operations.

[0072] For example, multipliers 1 and 2 can be used as amounts to left or right bit shifts of 1 or specific numbers. (乗数1) Ya 2 (乗数2) It may be used by multiplying it by 1 or a specific number. If multiplier 1 or multiplier 2 is used directly as the scale value, it may be used by multiplying them (fixedpointprec1, fixedpointprec2) by 1 or a specific number. After that, integer arithmetic with increased precision is possible by converting the type to an integer type by truncating, rounding up, or rounding the decimal part. For example, the level value is decoded for each vertex, but by shifting the level value sequence level_coeff to the left by fixedpointprec1 bits, 2 (fixedpointprec1) The value is doubled to obtain a new carry level value, up_level_coeff. << indicates a left bit shift.

[0073] up_level_coeff=floor(level_coeff< <fixedpointprec1) For example, if fixedpointprec1 is set to 6, the multiplication factor becomes 64, and the decimal part can be truncated after multiplying by 64. Note that if coeff is given as an integer beforehand, there may be no need to carry over, but in that case, it is assumed that the multiplier 1 has already been left bit shifted or multiplied.

[0074] The inverse quantization offset decoding unit 204C2 is configured to decode and output inverse quantization offset information, which is the information necessary to calculate the inverse quantization offset, from the displacement bitstream. The inverse quantization offset information itself may be the inverse quantization offset itself. Alternatively, the inverse quantization offset decoding unit 204C2 may also include the calculation of the inverse quantization offset, which will be described later.

[0075] Such inverse quantization offset information may include dsps_inverse_qunatization_offset_enable_flag or dh_inverse_qunatization_offset_enable_flag indicating whether the inverse quantization offset is valid, dh_inverse_quantization_offset_sign indicating the sign of the inverse quantization offset value, dh_inverse_quantization_offset_value_log2_prec1_delta necessary for deriving the first term of the inverse quantization offset value, or dh_inverse_quantization_offset_value_log2_prec2_delta necessary for deriving the second term of the inverse quantization offset value.

[0076] Here, the value obtained from dh_inverse_quantization_offset_sign is denoted as the sign, the value related to the first offset term calculated from dh_inverse_quantization_offset_value_log2_prec1_delta is denoted as prec1, and the value related to the second offset term calculated from dh_inverse_quantization_offset_value_log2_prec2_delta is denoted as prec2.

[0077] In the inverse quantization offset decoding unit 204C2, the index i relates to the number of subdivisions, the index j relates to the number of dimensions of the displacement, and the index k relates to the zone.

[0078] The maximum dimension of the displacement quantity, MaxDimension (dimension j), should be set to 1 if the 1D displacement flag, asve_1d_displacement_flag, is 1, and 3 otherwise.

[0079] The index k for the zone may, for example, be information when k is 0 and the level value or coefficient is 0, information when k is 1 and the level value or coefficient is positive, or information when k is 2 and the level value or coefficient is negative.

[0080] In inverse quantization offset decoding, the codes sign, prec1, and prec2 may be decoded from the displacement bitstream.

[0081] Since prec1 and prec2 are differential information when the index i related to the number of subdivisions is not 0, if i is not 0, they can be calculated by adding prec1 and prec2 of i-1.

[0082] For example, for each index, the temporary sign_t, and the temporary prec1 and prec2, prec1_t and prec2_t, are decrypted as follows.

[0083] sign_t[i][j][k]=dh_inverse_quantization_offset_sign[i][j][k] prec1_t[i][j][k]=dh_inverse_quantization_offset_delta_value_log2_prec1_delta[i][j][k] prec2_t[i][j][k]=dh_inverse_quantization_offset_delta_value_log2_prec2_delta[i][j][k] Then, for each index, we obtain the sign `sign`. For example, if `sign_t` is 0, we can set `sign` to 1, and otherwise, we can set `sign` to -1.

[0084] sign[i][j][k]=sign_t[i][j][k]== 0 ? 1 : (-1) Then, for each index, if i is 0, prec1_t is copied directly to prec1; otherwise, the prec1 for i-1 is added.

[0085] prec1[i][j][k]=( i == 0 ?prec1_t[i][j][k]:( prec1_t[i][j][k]+prec1[i-1][j][k])) The same applies to prec2.

[0086] prec2[i][j][k]=( i == 0 ?prec2_t[i][j][k]:( prec2_t[i][j][k]+prec2[i-1][j][k])) For example, these prec1, prec2, and sign are called inverse quantization offset information, but this is not the only way to refer to them. Alternatively, instead of separating them into prec1, prec2, and sign, they can be combined and decoded as the inverse quantization offset dh_iq_offset_value[i][j][k]. In this case, the inverse quantization offset information becomes the inverse quantization offset itself. Therefore, there are cases where the inverse quantization offset information and the inverse quantization offset are not distinguished.

[0087] From now on, we will omit the indices i, j, and k, and explain them as if prec1 and prec2 were integers.

[0088] The offset correction first inverse quantization unit 204C3 is configured to multiply the carry level value sequence output from the first carry unit 204C1 by the inverse quantization scale (quantization step) iscale, and then perform a correction (addition) using the inverse quantization offset obtained from the inverse quantization offset information to generate and output a correction carry coefficient sequence.

[0089] As shown in Figure 18, the offset correction first inverse quantization unit 204C3 comprises a first inverse quantization unit 204C3A, a second digit down unit 204C3B, an inverse quantization offset calculation unit 204C3C, an inverse quantization offset digit up unit 204C3D, and an inverse quantization offset addition unit 204C3E.

[0090] The processing of the inverse quantization offset calculation unit 204C3C may be performed simultaneously with the decoding.

[0091] If this process is performed simultaneously with decoding, the inverse quantization offset iq_offset is calculated using the inverse quantization offset information in equation (2) described later. Carry-over is performed afterward. In this case, the output of the inverse quantization offset decoding unit 204C2 is the inverse quantization offset. On the other hand, the processing of the inverse quantization offset calculation unit 204C3C may be performed simultaneously with the carry-over.

[0092] The following will explain some examples.

[0093] The first inverse quantization unit 204C3A is configured to generate and output a double carry coefficient sequence up2_coeff by multiplying the carry level value sequence by the inverse quantization scale. Details will be described later.

[0094] The second bit shift unit 204C3B is configured to generate and output the carry coefficient sequence up_coeff by shifting the double carry coefficient sequence using a multiplier of 2. For example, if multiplier 2 is set to 23, the second bit shift unit 204C3B will bit-shift the double carry coefficient sequence 23 bits to the right. Further details will be described later.

[0095] The inverse quantization offset calculation unit 204C3C and the inverse quantization offset carry unit 204C3D4 may perform processing simultaneously. Furthermore, the calculation of the inverse quantization offset may not be necessary in some cases.

[0096] The inverse quantization offset calculation unit 204C3C is configured to generate and output an inverse quantization offset from the inverse quantization offset information.

[0097] The inverse quantization offset carry unit 204C3D is configured to generate and output a carry inverse quantization offset up_iq_offset from the inverse quantization offset value.

[0098] Here, the inverse quantization offset carry unit 204C3D needs to carry the numerators of the first and second terms of the inverse quantization offset before the division occurs.

[0099] For example, the inverse quantization offset carry unit 204C3D carries the numerator mentioned above using fixedpointprec1 with a multiplier of 1.

[0100] According to the above configuration, by making both the numerator and denominator of the inverse quantization offset integers, operations can be performed using integers.

[0101] Furthermore, the inverse quantization offset carry unit 204C3D can convert the inverse quantization offset to an integer value by using round(), round up(), or floor().

[0102] To calculate the carry quantization offset up_iq_offset by performing the processing by the inverse quantization offset calculation unit 204C3C and the inverse quantization offset carry increment unit 204C3D, for example, the following equation (1) can be used. Here, << indicates a left bit shift, and >> indicates a right bit shift.

[0103] up_iq_offset = sign × (floor((1 << fixedpointprec1) / 2 prec1 ) + floor((1 << fixedpointprec1) / 2 prec2 ) … Equation (1) The rounding process may be performed after offset decoding (calculation).

[0104] up_iq_offset = sign × (floor(1 << fixedpointprec1) / 2 prec1 + (1 << fixedpointprec1) / 2 prec2 ) … Equation (1) Here, (1 << (fixedpointprec1) / 2 prec1 is the first term of the inverse quantization offset, and (1 << fixedpointprec1) / 2 prec2 is the second term of the inverse quantization offset. Also, the numerator is 1 << fixedpointprec1 for both the first term and the second term.

[0105] The inverse quantization offset addition unit 204C3E is configured to generate and output a corrected carry coefficient sequence up_coeff' by adding the carry inverse quantization offset up_iq_offset to the carry coefficient sequence up_coeff.

[0106] up_coeff and up_iq_offset are both raised by the multiplier 1 with the same bit shift amount of fixedpointprec1 bits and can be added.

[0107] up_coeff' = up_coeff + up_iq_offset Note that the up_iq_offset to be added will differ depending on the zone of up_coeff. For example, if up_coeff is 0, k=0; if up_coeff is positive, k=1; and if up_coeff is negative, k=2, and the offset value up_iq_offset[i][j][k] may be added. i is the number of subdivisions, and j is the dimension. Note that the zone can also be determined using the level value, the double carry level value, or the double carry coefficient sequence.

[0108] Figure 19 shows an example of the configuration of the first inverse quantization unit 204C3A.

[0109] As shown in Figure 19, the first inverse quantization unit 204C3A comprises an inverse quantization scale calculation unit 204C3A1 and an inverse quantization scale multiplication unit 204C3A2.

[0110] The inverse quantization scale calculation unit 204C3A1 is configured to generate and output the inverse quantization scale iscale. Here, the inverse quantization scale calculation unit 204C3A1 is configured to generate and output the inverse quantization scale iscale from qp values ​​(not shown), etc.

[0111] A method for directly calculating the inverse quantization scale iscale is described in Non-Patent Document 2.

[0112] Furthermore, the calculated inverse quantization scale iscale may be specified in advance in the mesh decoding device 200.

[0113] Furthermore, the inverse quantization scale may be prepared with a carry-over by the multiplier fixedpointprec2, which is 2. For example, the inverse quantization scale may already be prepared with fixedpointprec2 set to 23, resulting in a bit shift to the left by approximately 23 bits.

[0114] The inverse quantization scale multiplication unit 204C3A2 is configured to generate and output a double carry coefficient sequence by multiplying the carry level value sequence by the inverse quantization scale.

[0115] Depending on the calculation method, the inverse quantization scale multiplication unit 204C3A2 may be configured to generate and output a double carry coefficient sequence by multiplying the carry level value sequence by the reciprocal of the inverse quantization scale.

[0116] With this configuration, a carry-over can be achieved twice by multiplying the carry-over level value sequence by the inverse quantization scale, using multipliers 1 and 2. For example, if multiplier 1 is set to 6 and multiplier 2 to 23, the level value sequence will be left-shifted by 6 bits by multiplier 1 and then by 23 bits by multiplier 2. In this way, the double carry-over coefficient sequence up2_coeff is generated and output.

[0117] up2_coeff=up_level_coeff×iscale As shown in Figure 18, the second digit reduction section 204C3B is configured to perform a reduction using a multiplier of 2. This reduction is a reduction with respect to the inverse quantization scale.

[0118] For example, the second digit down unit 204C3B adds a value obtained by left-shifting 1 by 22 bits so that it can be rounded, then right-shifts the multiplier 2, which is 23 bits, to generate and output the carry coefficient sequence up_coeff, thereby eliminating the effect of the carry in the inverse quantization scale.

[0119] up_coeff=floor((up2_coeff+(1<<22))>>23) Furthermore, the above formula can be expressed as follows using fixedpointprec2.

[0120] up_coeff=floor((up2_coeff+(1<<fixedpointprec2-1)))> >fixedpointprec2 Referring to Figure 20, another configuration of the offset correction first inverse quantization unit 204C3 will be described.

[0121] In the example shown in Figure 18, in the inverse quantum offset carry section 204C3D, when fixedpointprec1 is 6, all decimal points below 1 / fixedpointprec1 (1 / 64) become 0, indicating a problem with accuracy.

[0122] Furthermore, increasing the multiplier 1 can unnecessarily increase the level value, leading to increased computational complexity and a higher likelihood of overflow. Therefore, we want to maintain accuracy without increasing the multiplier 1.

[0123] Therefore, the following describes a method for maintaining accuracy by carrying the inverse quantization offset twice and adding it to the double-carried coefficient sequence.

[0124] In the configuration shown in Figure 20, the offset correction first inverse quantization unit 204C3 comprises a first inverse quantization unit 204C3A, an inverse quantization offset calculation unit 204C3F, an inverse quantization offset carry unit 204C3G, an inverse quantization offset second digit carry unit 204C3H, an inverse quantization offset addition unit 204C3I, and a second digit decrement unit 204C3J.

[0125] Since the inverse quantization offset lift section 204C3G and the inverse quantization offset second lift section 204C3H may be performed simultaneously with multiplier 1 and multiplier 2, as described later, the quantization offset lift section 204C3G and the inverse quantization offset second lift section 204C3H are collectively referred to as the "inverse quantization offset combined lift section".

[0126] The first inverse quantization unit 203C3A, the inverse quantization offset calculation unit 204C3F, and the inverse quantization offset carry unit 204C3G have the same functions as the first inverse quantization unit 203C3A, the inverse quantization offset calculation unit 204C3C, and the inverse quantization offset carry unit 204C3D shown in Figure 18, respectively, so their explanation is omitted.

[0127] The inverse quantization offset calculation unit 204C3F, the inverse quantization offset carry unit 204C3G, and the inverse quantization offset second carry unit 204C3H may be configured to process simultaneously and generate and output a double carry inverse quantization offset up2_iq_offset from the inverse quantization offset information.

[0128] The processing order of the inverse quantization offset calculation unit 204C3F, the inverse quantization offset carry unit 204C3G, and the inverse quantization offset second digit carry unit 204C3H does not matter.

[0129] The inverse quantization offset when no carry is performed is calculated by the following equation (2). The sign is 1 or -1.

[0130] iq_offset=sign×(floor(1 / 2 prec1 ) + floor(1 / 2 prec2 )) … Formula (2) Here, the first term is 1 / 2 prec1 Therefore, the second term is 1 / 2 prec2 The numerator is 1.

[0131] The double-carry inverse quantization offset is obtained by the following equation (3).

[0132] up2_iq_offset=sign×(floor((1<<(fixedpointorec1+fixedpointorec2)) / 2 prec1 )+floor((1<<(fixedpointorec1+fixedpointorec2)) / 2 prec2 )) … Equation (3) Based on equation (3), the inverse quantization offset calculation unit 204C3F, the inverse quantization offset carry unit 204C3G, and the inverse quantization offset second digit carry unit 204C3H will be explained together.

[0133] The inverse quantization offset carry unit 204C3G performs a carry by bit-shifting the inverse quantization offset to the left by fixedpointprec1 bits, which is a multiplier of 1, for the numerators of the first and second terms of equation (2).

[0134] The inverse quantization offset second digit carry section 204C3H further shifts the bits left by fixedpointprec2 on the numerators of the first and second terms of equation (2) and then carries them up.

[0135] Here, the inverse quantization offset carry section 204C3G and the second inverse quantization offset carry section 204C3H may be left bit-shifted together by adding multiplier 1 for the level value and multiplier 2 for the inverse quantization scale. In other words, the combined inverse quantization offset carry section, which combines the inverse quantization offset carry section 204C3G and the second inverse quantization offset carry section 204C3H, may be left bit-shifted together by 1 << (multiplier 1 + multiplier 2), as shown in the numerators of the first and second terms of equation (3). When both multiplier 1 and multiplier 2 carrys are performed, this is called a double carry. The method does not matter as long as the meaning is the same.

[0136] The inverse quantization offset calculation unit 204C3F calculates the first term as shown in equation (3) prec1 The division is performed. Here, the inverse quantization offset calculation unit 204C3F converts the division result to an integer by truncating (floor()), rounding up, or rounding to the nearest integer if the result is not an integer.

[0137] The inverse quantization offset calculation unit 204C3F calculates the second term as shown in equation (3) prec2 The division is performed. Here, the inverse quantization offset calculation unit 204C3F converts the division result to an integer by truncating (floor()), rounding up, or rounding to the nearest integer if the result is not an integer.

[0138] The inverse quantization offset calculation unit 204C3F adds the above calculation results, multiplies by the sign, and calculates a double carry inverse quantization offset. By carrying the inverse quantization offset using multipliers 1 and 2 in this way, the number of significant digits when adding the inverse quantization offsets increases, the accuracy is improved, and the coding efficiency is enhanced compared to carrying the inverse quantization offset using only multiplier 1. Furthermore, there is no need to change the values ​​of multipliers 1 or 2.

[0139] The inverse quantization offset summing unit 204C3I is configured to generate and output a corrected double carry coefficient sequence up2_coeff' by adding a double carry inverse quantization offset up2_iq_offset to the input double carry coefficient sequence up2_coeff.

[0140] up2_coeff'=up2_coeff+up2_iq_offset The second digit down section 203C3J is configured to generate and output a corrected carry coefficient sequence by downshifting the corrected double carry coefficient sequence using a multiplier of 2.

[0141] For example, the second digit shift 203C3J may be performed by right-shifting fixedpointprec2 bits, which has a multiplier of 2, to achieve the aforementioned digit shift.

[0142] Alternatively, the second digit shift 203C3J may be calculated by adding a value obtained by left-shifting 1 by (fixedpointprec2 - 1) bits, and then right-shifting it by fixedpointprec2 bits.

[0143] If we set fixedpointprec2 to 23, then it becomes as follows:

[0144] up_coeff'=floor((up2_coeff'+(1<<22))>>23)) As shown in Figure 17, the second displacement decoding unit 2042 includes an image decoding unit 204A.

[0145] Here, the video decoding unit 204A is configured to decode and output a level value image from the displacement bitstream.

[0146] (Mesh reconstruction unit 206) Figure 21 shows an example of the configuration of the mesh reconstruction unit 206. As shown in Figure 21, the mesh reconstruction unit 206 comprises a submesh reconstruction unit 206A and a submesh joining unit 206B.

[0147] The submesh reconstruction unit 206A is configured to generate and output a submesh sequence using the basic mesh and a level value image or a first coefficient sequence.

[0148] The submesh merging unit 206B is configured to generate and output a single mesh by merging a series of submesh rows.

[0149] Figure 22 shows an example of the configuration of the submesh reconstruction unit 206A. As shown in Figure 22, the submesh reconstruction unit 206A includes a subdivision unit 206A1, a displacement amount decoding method determination unit 206A2, a displacement amount sequence generation unit 206A3, a level value image processing unit 206A4, a coefficient sequence processing unit 206A5, an image unfolding unit 206A6, a second inverse quantization unit 206A7, an inverse transformation unit 206A8, a displacement amount addition unit 206A9, and an inverse quantization offset addition unit 206A10. As mentioned above, the coefficient downshifting unit may be performed at a timing corresponding to the encoder's carry-over timing.

[0150] The subdivision unit 206A1 is configured to generate additional subdivision vertices and their connection information from the aligned basic mesh using a subdivision method indicated by the control information.

[0151] The subdivision unit 206A1 outputs a subdivision mesh that combines the basic mesh, the added subdivision vertices, and their connection information.

[0152] The displacement amount decoding method determination unit 206A2 is configured to output a level value image or a first coefficient sequence by determining the method for decoding the displacement amount from the information indicated by the control information.

[0153] The displacement sequence generation unit 206A3 is configured to generate and output a displacement sequence by generating an N-dimensional zero vector using the number N of displacements indicated by the control information.

[0154] The level value image processing unit 206A4 is configured to generate and output a processed level value image by processing the level value image.

[0155] The coefficient sequence processing unit 206A5 is configured to generate and output a processed coefficient sequence by processing the first coefficient sequence.

[0156] The image unfolding unit 206A6 is configured to generate and output a sequence of level values ​​by unfolding a processing level value image.

[0157] The second inverse quantization unit 206A7 inversely quantizes the level value sequence.

[0158] The inverse quantization offset summing unit 206A10 is configured to add an inverse quantization offset value to the inverse quantized level value sequence to generate and output a second coefficient sequence.

[0159] The inverse transformation unit 206A8 is configured to generate and output a displacement amount sequence by inversely transforming the second coefficient sequence or the machining coefficient sequence. Here, the inverse transformation unit 206A8 may also inversely transform the machining coefficient sequence using an inverse DCT or an inverse wavelet transform.

[0160] The displacement amount addition unit 206A9 is configured to generate and output a submesh by adding a series of displacement amounts to a subdivided mesh.

[0161] With the configuration of the submesh reconstruction unit 206A described above, it becomes possible to correctly reconstruct the mesh by determining the method for decoding the displacement amount and performing appropriate branching and processing accordingly.

[0162] (Processing of the inverse quantization unit 2041 and the first displacement decoding unit) Figure 23 is a flowchart showing an example of the processing performed by the first displacement decoding unit 2041. This processing is performed for each frame.

[0163] As shown in Figure 23, in step S101, the first displacement amount decoding unit 2041 decodes the input displacement amount bitstream and outputs a level value sequence.

[0164] In step S102, the first displacement decoding unit 2041 generates and outputs a carry-over level value sequence by carrying over the level value using a multiplier of 1.

[0165] For example, the first displacement decoding unit 2041 uses a multiplier of 1 to bit-shift the level value sequence to the left to increase the value, then rounds it down, up, or to the nearest integer to obtain an integer, and outputs it as a carry-over level value sequence.

[0166] In step S103, the first displacement decoding unit 2041 performs first inverse quantization. Specifically, in step S1031, the first displacement decoding unit 2041 calculates the inverse quantization scale, and in step S1032, multiplies the carry level value by the inverse quantization scale to generate and output a double carry coefficient sequence.

[0167] In step S104, the first displacement decoding unit 2041 performs a second-digit downshift using multiplier 2. For example, the first displacement decoding unit 2041 right-shifts the double-digit carry coefficient sequence using multiplier 2.

[0168] In step S105, the first displacement decoding unit 2041 determines whether the inverse quantization offset is valid. If it is valid, for example iq_offset_enable_flag=1, the operation proceeds to step S106; otherwise, for example iq_offset_enable_flag=1, the operation proceeds to step S109.

[0169] In step S106, the first displacement decoding unit 2041 decodes information regarding the inverse quantization offset from the displacement bitstream.

[0170] In step S107, the first displacement decoding unit 2041 calculates the inverse quantization offset from the information regarding the inverse quantization offset, performs a carry using a multiplier of 1, and calculates the carry inverse quantization offset.

[0171] For example, the first displacement decoding unit 2041 calculates the carry inverse quantization offset by bit-shifting the calculated inverse quantization offset to the left by a multiplier of 1 to increase its value, and then rounding it down, up, or to the nearest integer to obtain an integer value.

[0172] In step S108, the first displacement decoding unit 2041 calculates a corrected carry coefficient sequence by adding a carry inverse quantization offset to the carry coefficient sequence.

[0173] In step S109, the first displacement decoding unit 2041 determines whether the frame type of the displacement is interframe or not. If yes, the operation proceeds to step S110; if no, the operation proceeds to step S111.

[0174] In step S110, the first displacement decoding unit 2041 adds the predicted value obtained from the reference frame.

[0175] In step S111, the first displacement decoding unit 2041 may perform a bit shift by multiplier 1. For example, the first displacement decoding unit 2041 performs a bit shift to the right by multiplier 1. The timing of the bit shift is not limited to this point. Bit shifting may not be necessary depending on the numerical value.

[0176] In step S112, the first displacement amount decoding unit 2041 determines whether the level value sequence (coefficient sequence) currently being processed corresponds to the final displacement amount ID. If yes, this operation ends; if no, this operation proceeds to step S113. Displacement amount IDs are assigned to groups of level values ​​(displacement amount data units) and information (data headers) in the arithmetic decoding described in Non-Patent Literature 2, and one or more displacement amount IDs are assigned to each frame.

[0177] In step S113, the first displacement decoding unit 2041 proceeds to process the level value sequence corresponding to the next displacement ID.

[0178] (Example of modification to the processing of the first displacement decoding unit 2041) Figure 24 is a flowchart showing an example of the processing of the first displacement decoding unit of the inverse quantization unit 2041. This processing is performed for each frame.

[0179] As shown in Figure 24, in step S201, the first displacement amount decoding unit 2041 decodes the input displacement amount bitstream and outputs a level value sequence.

[0180] In step S202, the first displacement decoding unit 2041 generates and outputs a carry-over level value by carrying over the level value sequence using a multiplier of 1.

[0181] For example, the first displacement decoding unit 2041 uses a multiplier of 1 to bit-shift the level value sequence to the left to increase the value, then rounds it down, up, or to the nearest integer to obtain an integer, and outputs it as a carry-over level value sequence.

[0182] In step S203, the first displacement decoding unit 2041 performs first inverse quantization. Specifically, in step S2031, the first displacement decoding unit 2041 calculates the inverse quantization scale, and in step S2032, multiplies the carry level value by the inverse quantization scale to generate and output a double carry coefficient sequence.

[0183] In step S204, the first displacement decoding unit 2041 determines whether the inverse quantization offset is valid. If it is valid, for example iq_offset_enable_flag=1, the operation proceeds to step S105; otherwise, for example iq_offset_enable_flag=1, the operation proceeds to step S109.

[0184] In step S205, the first displacement decoding unit 2041 decodes information regarding the inverse quantization offset from the displacement bitstream.

[0185] In step S206, the first displacement decoding unit 2041 calculates a double carry inverse quantization offset from the information regarding the inverse quantization offset. The first displacement decoding unit 2041 calculates a double carry inverse quantization offset by carrying the inverse quantization offset by multiplier 1 and then by carrying it again by multiplier 2.

[0186] In step S207, the first displacement decoding unit 2041 calculates a corrected double carry coefficient sequence by adding a double carry inverse quantization offset to the double carry coefficient sequence.

[0187] In step S208, the first displacement decoding unit 2041 performs a second-digit downshift on the corrected double carry coefficient sequence using multiplier 2 and outputs the corrected carry coefficient sequence. For example, the first displacement decoding unit 2041 can calculate the corrected carry coefficient sequence by right-shifting the corrected double carry coefficient sequence using multiplier 2.

[0188] In step S209, the first displacement amount decoding unit 2041 determines whether the frame type of the displacement amount is interframe or not. If yes, the operation proceeds to step S210; if no, the operation proceeds to step S211.

[0189] In step S210, the first displacement decoding unit 2041 adds the predicted value obtained from the reference frame.

[0190] In step S211, the first displacement decoding unit 2041 may perform a bit shift by multiplier 1. For example, the first displacement decoding unit 2041 performs a bit shift to the right by multiplier 1. The timing of the bit shift is not limited to this point. Bit shifting may not be necessary depending on the numerical value.

[0191] In step S212, the first displacement decoding unit 2041 determines whether the level value sequence (coefficient sequence) currently being processed corresponds to the final displacement ID. If yes, this operation ends; if no, this operation proceeds to step S213.

[0192] In step S213, the first displacement decoding unit 2041 proceeds to processing the level value sequence corresponding to the next displacement ID.

[0193] The mesh coding device 100 and mesh decoding device 200 described above may be implemented as programs that cause a computer to execute each function (each process). [Industrial applicability]

[0194] Furthermore, according to this embodiment, for example, it is possible to achieve an overall improvement in service quality in video communication, thereby contributing to Goal 9 of the United Nations-led Sustainable Development Goals (SDGs), "Build resilient infrastructure, promote sustainable industrialization and foster innovation." [Explanation of symbols]

[0195] 1…Mesh processing system 100... Mesh coding device 200... Mesh Decoder 201...V3C unit separation section 202... Atlas Decoding Unit 203...Basic Mesh Decoding Unit 204...Displacement Decoding Unit 2041...First displacement decoding unit 204B... Arithmetic Decoding Unit 204C...Inverse quantization section 204C1...First digit lift section 204C2...Inverse quantization offset decoding unit 204C3...Offset correction first inverse quantization unit 204C3A...first inverse quantization section 204C3A1...Inverse quantization scale calculation unit 204C3A2...Inverse quantization scale multiplication unit 204C3B... Second digit downshift 204C3C, 204C3F... Inverse quantization offset calculation unit 204C3D, 204C3G... Inverse quantization offset carry section 204C3E, 204C3I... Inverse quantization offset summing unit 204C3H... Inverse quantization offset, second digit boost section 204C3J... Second digit down part 204D... Adder 204E...Interface prediction unit 204F... Frame buffer 204G... First digit downshift 204H...Inverse quantization offset summing section 2042...Second displacement decoding unit 204A...Video decoding unit 205... Texture Decoding Unit 206...Mesh reconstruction section 206A...Submesh reconstruction section 206A1…Subdivision section 206A2...Displacement Amount Decoding Method Determination Unit 206A3...Displacement amount sequence generation unit 206A4...Level Value Image Processing Section 206A5…Coefficient row processing section 206A6…Image Expansion Section 206A7…Second inverse quantization unit 206A8...Inverse conversion section 206A9...Displacement amount addition section 206A10...Inverse quantization offset summing unit 206B...Submesh connection

Claims

1. A mesh decoding device, The system includes a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream, The displacement amount decoding unit is An arithmetic decoding unit is configured to decode and output a level value sequence from the displacement bitstream by arithmetic decoding, The system comprises an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantizing the aforementioned level value sequence, The aforementioned inverse quantization unit is An inverse quantization offset decoding unit that decodes the inverse quantization offset from the displacement bitstream, The inverse quantization offset carry unit generates and outputs a carry inverse quantization offset by carrying the aforementioned inverse quantization offset, A mesh decoding device comprising: an inverse quantization offset addition unit that generates and outputs the first coefficient sequence by adding the carry inverse quantization offset to a carry coefficient sequence generated based on a carry level value obtained by carrying the level value sequence.

2. The mesh decoding device according to claim 1, characterized in that the inverse quantization offset carry-over unit carries over the inverse quantization offset by a multiplier 1 which is a scale relating to the level value.

3. The mesh decoding apparatus according to claim 1, characterized in that the inverse quantization offset carry unit sets the inverse quantization offset to an integer after the carry.

4. The aforementioned inverse quantization unit is A first inverse quantization unit generates and outputs a double carry coefficient sequence by inverse quantizing the carry level value sequence using the aforementioned inverse quantization scale, The system includes a second downshift unit that generates and outputs the carry coefficient sequence by downshifting the double carry coefficient sequence using a multiplier 2, which is a scale related to the inverse quantization scale, The mesh decoding device according to claim 1, characterized in that the inverse quantization offset addition unit generates and outputs the first coefficient sequence by adding the carry inverse quantization offset to the carry coefficient sequence.

5. A mesh decoding device, The system includes a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream, The displacement amount decoding unit is An arithmetic decoding unit is configured to decode and output a level value sequence from the displacement bitstream by arithmetic decoding, The system comprises an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantizing the aforementioned level value sequence, The aforementioned inverse quantization unit is An inverse quantization offset decoding unit that decodes the inverse quantization offset from the displacement bitstream, A first inverse quantization unit generates and outputs a double carry coefficient sequence by inverse quantization of the carry level value sequence obtained by carrying the aforementioned level value sequence using an inverse quantization scale, The inverse quantization offset combined carry unit generates and outputs a double carry inverse quantization offset by carrying the inverse quantization offset by multiplier 1, which is a scale related to the level value, and multiplier 2, which is a scale related to the inverse quantization scale. An inverse quantization offset addition unit generates and outputs a corrected double carry coefficient sequence by adding the double carry inverse quantization offset to the double carry coefficient sequence, A mesh decoding device comprising: a second downshifting unit that generates and outputs the first coefficient sequence by downshifting the corrected double carry coefficient sequence using the multiplier 2.

6. The aforementioned inverse quantization offset combined carry unit is, An inverse quantization offset carry unit generates and outputs a carry inverse quantization offset by carrying the aforementioned inverse quantization offset by the multiplier 1, The mesh decoding device according to claim 5, further comprising: a second carry-over inverse quantization offset unit that generates and outputs the double carry-over inverse quantization offset by carrying over the carry-over inverse quantization offset by the multiplier 2.

7. The mesh decoding apparatus according to claim 5, characterized in that the inverse quantization offset overall carry unit sets the inverse quantization offset to an integer after the carry.

8. A mesh decoding device, The system includes a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream, The displacement amount decoding unit is An arithmetic decoding unit is configured to decode and output a level value sequence from the displacement bitstream by arithmetic decoding, The system comprises an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantizing the aforementioned level value sequence, The aforementioned inverse quantization unit is An inverse quantization offset decoding unit that decodes the inverse quantization offset from the displacement bitstream, A mesh decoding device comprising an offset-corrected first inverse quantization unit that generates and outputs a first coefficient sequence, which is a corrected carry coefficient sequence, by multiplying a carry coefficient sequence generated based on a carry level value obtained by carrying the level value sequence by an inverse quantization scale, and correcting it using a multiplier 1, which is a scale relating to the inverse quantization offset and the level value.

9. A mesh decoding method, The process includes decoding and outputting a first coefficient sequence from a displacement bitstream. The aforementioned process section is Step A involves decoding and outputting a level value sequence from the displacement bitstream by arithmetic decoding, The process includes step B, which generates and outputs the first coefficient sequence by inverse quantizing the level value sequence, In step B, The inverse quantization offset is decoded from the displacement bitstream. By carrying over the aforementioned inverse quantization offset, a carry-over inverse quantization offset is generated and output. A mesh decoding method characterized by generating and outputting the first coefficient sequence by adding the carry inverse quantization offset to a carry coefficient sequence generated based on a carry level value obtained by carrying the level value sequence.

10. A program that makes a computer function as a mesh decoding device, The mesh decoding device includes a displacement decoding unit configured to decode and output a first coefficient sequence from a displacement bitstream. The displacement amount decoding unit is An arithmetic decoding unit is configured to decode and output a level value sequence from the displacement bitstream by arithmetic decoding, The system comprises an inverse quantization unit configured to generate and output the first coefficient sequence by inverse quantizing the aforementioned level value sequence, The aforementioned inverse quantization unit is An inverse quantization offset decoding unit that decodes the inverse quantization offset from the displacement bitstream, The inverse quantization offset carry unit generates and outputs a carry inverse quantization offset by carrying the aforementioned inverse quantization offset, A program characterized by comprising: an inverse quantization offset addition unit that generates and outputs the first coefficient sequence by adding the carry inverse quantization offset to a carry coefficient sequence generated based on a carry level value obtained by carrying the level value sequence.

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