Optical sensing device and manufacturing method

Abstract

The present invention generally relates to addressing the limited space within a SPAD chip for arranging a single-photon avalanche diode (SPAD) array, in-pixel circuitry, row driver circuitry, and column readout circuitry. [Solution] A SPAD image sensor comprising at least three device layers. The first device layer has a SPAD array. The second device layer provides the in-pixel circuitry for the SPADs. Row driver circuitry, column readout circuitry, and other circuitry are located in the third or fourth device layer. The first device layer can be manufactured using a streamlined process that does not produce any transistors. The second device layer can be manufactured using a mature process technology that provides high-voltage transistors. The third and optional fourth device layers can be manufactured using an advanced process technology that provides high-density transistors with lower operating voltages than required for the in-pixel circuitry. This structure increases the number of SPAD pixels that can be provided per unit device area and is cost-effective.

Description

[Technical Field]

[0001] This invention generally relates to optical sensing devices and methods for manufacturing optical sensing devices. [Background technology]

[0002] A single-photon avalanche diode (SPAD) is a type of solid-state photodetector capable of detecting single photons in imaging, distance measurement, and other applications. An SPAD includes an absorption region and a multiplication region. The multiplication region contains a reverse-biased pn junction. A photon absorbed in the absorption region generates electron-hole pairs. Charge carriers are accelerated by the high electric field of the reverse-biased pn junction. The accelerated charge carriers cause collisional ionization and avalanche multiplication processes, resulting in a detectable signal. In Geiger mode, the pn junction is reverse-biased above the breakdown voltage, making the avalanche process self-sustaining. A quench process resets the SPAD after a detection event. [Overview of the project] [Problems that the invention aims to solve]

[0003] The present invention generally relates to addressing the limited space within a SPAD chip for arranging SPAD arrays, in-pixel circuits, row driver circuits, and column readout circuits. [Means for solving the problem]

[0004] In one embodiment of the present invention, the integrated circuit device includes a first device layer, a second device layer, and a third device layer. The first device layer includes a first semiconductor substrate and a SPAD array. The second device layer includes a second semiconductor substrate, is bonded to the first device layer, and includes an intrapixel circuit, and row and column connectors. The intrapixel circuit includes a quench circuit and a recharge circuit configured to quench avalanche events in the SPAD. The third device layer includes a third semiconductor substrate, is bonded to the second device layer, and includes a row driver circuit and a column read circuit configured to address the intrapixel circuit in the second device layer through the row and column connectors.

[0005] In one embodiment of the present invention, a method for manufacturing an integrated circuit device includes forming a first device layer including a first semiconductor substrate, forming a second device layer including a second semiconductor substrate, and forming a third device layer including a third semiconductor substrate. The first device layer includes an array of single-photon avalanche diodes (SPADs). The second device layer includes in-pixel circuits corresponding to the SPADs, row connectors and column connectors, and corresponding to the row connectors and column connectors. Through-silicon electrode The third device layer includes TSVs. The third device layer includes row driver circuits and column read circuits. The first device layer is bonded to the second device layer, and each SPAD in the first device layer is electrically connected to the corresponding in-pixel circuit in the second device layer by individual bonds. The third device layer is bonded to the second device layer, and the row connectors and column connectors in the second device layer are electrically connected to the row driver circuits and column read circuits in the third device layer via TSVs.

[0006] In one embodiment of the present invention, a method for manufacturing an integrated circuit device includes processing a first semiconductor substrate including a first front-end-of-line (FEOL) process for forming a SPAD array; processing a second semiconductor substrate including a second front-end-of-line process for forming an array of in-pixel circuits including a quench circuit and a recharge circuit, and a back-end-of-line (BEOL) process for forming row buses and column buses for the array of in-pixel circuits; processing a third semiconductor substrate including a third front-end-of-line process for forming row driver circuits and column readout circuits; bonding the second semiconductor substrate to the first semiconductor substrate, wherein the bonding forms a pixel-level electrical connection between the SPAD array and the array of in-pixel circuits; and bonding the second semiconductor substrate to the third semiconductor substrate, wherein the bonding forms an electrical connection between the row driver circuits and the row buses and between the column readout circuits and the column buses. [Effects of the Invention]

[0007] Based on the above, by rearranging the row driver circuit, column readout circuit, and other such circuits, the area of ​​peripheral circuits is reduced, allowing more chip area to be allocated to the SPAD, thereby improving the achievable resolution and efficiency of the SPAD-based image sensor. [Brief explanation of the drawing]

[0008] Aspects of the present invention are best understood from the following detailed description, to be read in conjunction with the accompanying drawings. In accordance with industry standard practice, features are not drawn to scale. Furthermore, dimensions of various features within individual drawings may be arbitrarily enlarged or reduced relative to one another to facilitate illustration or to provide emphasis.

[0009] [Figure 1] This is an exploded view of an integrated circuit (IC) device according to an embodiment of the present invention. [Figure 2] This is a circuit diagram of a SPAD pixel circuit according to an embodiment of the present invention. [Figure 3]This is a cross-sectional view of an IC device according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 12] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 13] This is a cross-sectional view illustrating an IC device manufacturing process according to an embodiment of the present invention. [Figure 14] This is a flowchart of the process according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] The present invention provides many different embodiments, or examples, for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, forming the first feature above or over the second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features so that the first and second features are not in direct contact.

[0011] Spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatial relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientation depicted in the figures. The device or apparatus may be in other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Terms such as "first", "second", "third", "fourth", etc. are merely general identifiers and, therefore, may be interchangeable in various embodiments. For example, an element (e.g., an aperture) may be referred to as a "first" element in some embodiments, but the element may be referred to as a "second" element in other embodiments.

[0012] The p-n junction of the SPAD is reverse-biased by a high voltage (>10V) beyond the breakdown voltage. The quenching circuit, the recharge circuit, and other pixel-integrated circuits of the SPAD use transistors that operate at these high voltages. These high-voltage transistors use a mature semiconductor technology that inherently has a relatively large minimum transistor pitch. In a multilayer device, the pixel-integrated circuits can be arranged in an array of a second device layer, having substantially the same footprint as the SPAD array of the first device layer, so that each pixel-integrated circuit is arranged directly opposite the corresponding SPAD and can be connected thereto by a short connection. The circuit that interfaces with the pixel-integrated circuits, including at least a row driver circuit and a column readout circuit, is usually arranged in a peripheral area adjacent to the edge of the pixel-integrated circuit array. Since the peripheral circuits occupy a significant amount of space, the SPAD pixel-integrated circuits and the SPAD itself are limited to 20-~25% of the total chip area.

[0013] The present invention solves this problem by repositioning the row driver circuit, the column readout circuit, and other such circuits to a third device layer. The third device layer can operate at a lower voltage than the second device layer (e.g., <2.8V), and thus can be manufactured with an advanced process technology that provides high-density transistors limited to a lower operating voltage. In some embodiments, a fourth device layer is also included. The fourth device layer may provide an application-specific integrated circuit (ASIC). By reducing the area of the peripheral circuits, more chip area can be devoted to the SPAD, improving the achievable resolution and efficiency of the SPAD-based image sensor.

[0014] Thus, one aspect of the present invention is an integrated circuit device including at least three device layers. The first device layer includes a semiconductor substrate having an SPAD array. In some embodiments, this layer is dedicated to photon detection, contains no transistors, and enables the manufacture of the SPAD using a streamlined process adapted to provide a high-sensitivity and efficient SPAD.

[0015] The second device layer is bonded to the first device layer at the pixel level and contains intra-pixel circuits, including at least a quench circuit and a recharge circuit for the SPAD. Since these intra-pixel circuits operate at high voltages, this layer is manufactured using a semiconductor process suitable for high-voltage transistors, which requires relatively large transistor spacing. This can be a mature technology that offers high reliability and low cost.

[0016] The third device layer is bonded to the second device layer. This third device layer includes row driver circuits, column readout circuits, and other circuits that may provide logic or control functions. Since these circuits do not need to operate at high voltages, they can be manufactured using more advanced semiconductor techniques with smaller transistor spacing, enabling higher circuit density and a reduced footprint for those circuits. The electrical connection between the second and third device layers is facilitated by row and column connectors on the second device layer and through-silicon electrodes (TSVs) extending through the second device layer. In some embodiments, the row driver circuits and column readout circuits occupy the same area as if they were on the second device layer, which is outside the footprint of the SPAD and the in-pixel circuit array. This arrangement maintains short connection lengths and enables efficiency equivalent to what would be achieved if these circuits were located on the second device layer.

[0017] In some embodiments, additional functionality is integrated into a third device layer. In some embodiments, this additional functionality includes clock management circuits such as a phase-locked loop (PLL) and a delay-locked loop (DLL). In some embodiments, this additional functionality includes an image signal processor (ISP). The PLL, DLL, and ISP circuits may be located within the footprint of the SPAD array. In some embodiments, the integrated circuit device includes a fourth device layer. The fourth device layer may include an application-specific integrated circuit (ASIC) that provides higher levels of processing and interface functionality. The first three device layers may be limited to image sensing functionality, while the ASIC may provide other functionality that leverages the image sensing functionality.

[0018] Another aspect of the present invention is a method for manufacturing an integrated circuit device. This method involves forming and bonding three (or more) device layers in such a way as to ensure reliable electrical connectivity while allowing each layer to be manufactured using a semiconductor process optimized for its specific function. This method enables the efficient integration of SPAD arrays and high-voltage circuits, while simultaneously allowing logic and control to be implemented in high-density low-voltage circuits, thereby increasing the area available for photon detection.

[0019] Figure 1 illustrates an exploded view of an integrated circuit device 100 according to several embodiments. The integrated circuit device 100 includes a bonded first device layer 101, a second device layer 103, and a third device layer 105. The first device layer 101 includes a SPAD array 111. In some embodiments, the SPAD array 111 includes approximately 32 × 32 to approximately 320 × 232 pixels (individual SPADs). In some embodiments, the SPAD array 111 includes more than 320 × 232 pixels. In some embodiments, the SPAD array includes more than 1 million pixels. A larger number of pixels provides higher resolution. The present invention provides a structure that enables the provision of a larger number of pixels on a chip of a given size.

[0020] The SPADs in the SPAD array 111 include absorption regions provided by a photosensitive semiconductor. These absorption regions may be part of a semiconductor substrate, embedded in the semiconductor substrate, or in the form of mesas on the semiconductor substrate. The absorption regions can be any suitable semiconductor, selected according to the wavelength of light to be detected.

[0021] In some embodiments, the absorption region is silicon or similar. Silicon absorbs visible light to near-infrared light, i.e., from about 300 nm to about 1100 nm, making it suitable for both direct time-of-flight (dToF) and photon counting image sensors. Silicon SPADs may be manufactured using CMOS-compatible processing. Applications for silicon SPADs include light-detection ranging (LiDAR) and 3D imaging systems. Silicon pn junctions have reverse breakdown in the range of about 20 V to about 200 V. A suitable bias voltage for a SPAD is the reverse breakdown voltage plus an over-bias voltage. For silicon SPADs, the over-bias voltage is about 2 V to about 10 V. If the over-bias voltage is too low, the photon detection efficiency will be impaired. If the over-bias voltage is too high, the dark current may become excessive.

[0022] In some embodiments, the absorption region is germanium or similar. Germanium absorbs near-infrared and mid-infrared light, i.e., from about 800 nm to about 1500 nm, making it suitable for dToF and other LiDAR systems. Applications of germanium SPADs include long-range LiDAR and communication systems. In some embodiments, the germanium SPAD is germanium on silicon. In some embodiments, the germanium on silicon SPAD includes a heterojunction diode. For a germanium pn junction, the reverse breakdown voltage is about 5V to about 30V, and the over-bias voltage is about 1V to about 3V. For a germanium on silicon SPAD, the reverse breakdown voltage is about 10V to about 50V, and the over-bias voltage is about 2V to about 5V.

[0023] In some embodiments, the absorption region is indium gallium arsenide (InGaAs) or similar on indium phosphide (InP). Indium gallium arsenide absorbs wavelengths in the range of about 1000 nm to about 1700 nm and is suitable for dToF and photon counting systems. Applications include LiDAR, communications, and imaging systems. Although integrated circuit device 100 is illustrated as a dToF system, it can be easily adapted to any of these applications. For an InGaAs SPAD on InP, the reverse breakdown voltage is about 10V to about 50V, and the over-bias voltage is about 2V to about 6V.

[0024] The second device layer 103 includes an in-pixel circuit array 121. The in-pixel circuit array 121 has in-pixel circuits that correspond one-to-one with SPADs in the SPAD array 111. For each pixel, there is at least one electrical connection between the first device layer 101 and the second device layer 103. In some embodiments, the in-pixel circuit array 121 is within the footprint of the SPAD array 111, within the width of a single pixel. Row connectors 123 and column connectors 125 are positioned laterally to the in-pixel circuit array 121 and coupled to it through row buses and column buses (not shown). The in-pixel circuits include quench circuits and recharge circuits, as well as circuits for generating digital or other low-voltage outputs from SPAD avalanche events.

[0025] The third device layer 105 includes row driver circuits 133 and column readout circuits 135. In some embodiments, the third device layer 105 further includes one or more of a phase-locked loop (PLL) 137, a delay-locked loop (DLL) 139, and an image signal processor (ISP) 131. In some embodiments, the row driver circuits 133 and column readout circuits 135 are located below the row connectors 123 and column connectors 125, which are outside the footprint of the SPAD array 111. In some embodiments, the PLL 137, DLL 139, and ISP are located within the footprint of the SPAD array 111. This configuration efficiently utilizes the area within the third device layer 105 while limiting the connection lengths between the row driver circuits 133, the column readout circuits 135, and the circuits of the in-pixel circuit array 121.

[0026] This in-pixel circuitry includes at least a quench circuit and a recharge circuit, which are responsible for stopping avalanche events in the SPAD after photon detection and ensuring that the diode is properly recharged for subsequent detections, and includes a signal processing circuit that provides a low-voltage output signal in response to avalanche events. The quench circuit and recharge circuit can be a passive quench circuit and recharge circuit, where a high-value resistor is used to limit the current flow and restore the SPAD to its operating bias. Alternatively, the quench circuit and recharge circuit can be an active quench circuit and recharge circuit, which includes a feedback control transistor that rapidly pulls down the SPAD voltage to stop the avalanche with greater speed and control compared to passive quenching.

[0027] Figure 2 provides a circuit diagram 200 illustrating the SPAD241 and its in-pixel circuitry 201. The SPAD241 is located in the first device layer 101. The in-pixel circuitry 201 is located in the second device layer 103 (see Figure 1) and provides an active quench circuit and a recharge circuit. In particular, the in-pixel circuitry 201 includes a quench circuit and recharge circuit 237, a signal processing and output circuit 207, and a timing and control circuit 209.

[0028] The signal processing and output circuit 207 converts transient analog avalanche events into low-voltage (logic level) output signals. This circuit includes a first inverter 203, a second inverter 204, and a third inverter 205 connected in series. The first inverter 203 is V DD_comp This is a comparator powered by [the following]. The first inverter 203 converts the avalanche pulse from SPAD241 into a logic level signal. The second inverter 204 and the third inverter 205 adjust (amplify and shape) the logic level signal to V DDL This is a buffer and driver that generates clean digital pulses, which are passed to a column bus shared by multiple SPAD241s. DDL V is the operating voltage of the third device layer 105 (see Figure 1) and the operating voltage of the second device layer 103. DDH Smaller.

[0029] The timing and control circuit 209 generates control signals that drive the quench circuit and recharge circuit 237. These can interface with timing measurements (e.g., a time digital converter or an external timing line) or be selectable between internal and external timing signals. The timing and control circuit 209 may include a fourth inverter 213, a capacitor 215, a multiplexer 217, and first NAND gates 219, second NAND gates 221, and third NAND gates 223. The fourth inverter 213 receives a tap 208 from the signal processing and output circuit 207, which provides an indication that the SPAD 241 is firing. The output of the fourth inverter 213 helps shape the internal timing signal. Capacitor 215 modulates this timing. A switch 211 may be used to reset the output of the fourth inverter 213 to rearm the timing circuit between avalanche events.

[0030] Multiplexer 217 has a time mode selection (T sel)Based on the signal, select between an internal timing signal and an external timing signal (column timer). The output of the multiplexer 217 passes through further logic, and the timing and control circuit 209 controls the quenching circuit and the recharge circuit 237 using one or the other timing signal according to the operating mode. In particular, the third NAND gate 223 provides a recharge control signal 224 according to the setting of the timing signal and the active recharge enable (ARC EN ) signal. The first NAND gate 219 and the second NAND gate 221 provide a quenching activation signal 222 according to the timing signal, the avalanche signal from the tap 208, and the row selection signal (R sel ). The row selection signal R sel can come from a row bus shared by a second plurality of SPADs 241.

[0031] The quenching circuit and the recharge circuit 237 include a floating node 227, a charging node 231, an active quenching switch 225, a charging switch 229, a quenching bias transistor 233, and a recharge enable transistor 235. The floating node 227 is connected to the cathode of the SPAD 241. The active quenching switch 225 is an NMOS transistor connected between the floating node 227 and the ground. The charging switch 229 is a PMOS transistor connected between the floating node 227 and the charging node 231. The active quenching switch 225 and the charging switch 229 are both controlled by the quenching activation signal 222. These transistors together can force the floating node 227 to the ground or drive it to the voltage of the charging node 231 according to the quenching activation signal 222.

[0032] The quenching bias transistor 233 is connected between the high voltage V DDH and the charging node 231. This helps to extinguish the avalanche event in a controlled manner by the quenching bias signal (Q sel) is adjusted by the recharge enable transistor 235, high voltage V DDH It is connected between the charging node 231 and the recharge enable transistor 235. The recharge enable transistor 235 provides a high-speed recharge path controlled by the recharge control signal 224.

[0033] When a photon triggers an avalanche within SPAD241, the voltage at the floating node 227 drops rapidly (or rises depending on the polarity). The processing and output circuit 207 detects the pulse and provides a low-voltage digital output signal to the column bus. The timing and control circuit 209 detects the avalanche event and asserts the quench activation signal 222, which closes the active quenching switch 225 and causes the voltage on the floating node 227 to drop. After a short delay, the recharge control signal 224 is activated and the floating node 227 is restored to the reverse bias voltage.

[0034] Figure 3 illustrates a cross-sectional view of an integrated circuit device 300 according to several embodiments. The integrated circuit device 300 includes a first device layer 101, a second device layer 103, a third device layer 105, and a fourth device layer 373. The fourth device layer 373 includes a plurality of semiconductor devices, including transistors 353, on the surface 337F of a semiconductor substrate 337. The semiconductor devices are interconnected by a metal interconnect structure 333 to form an ASIC. The fourth device layer 373 is bonded to the third device layer 105 through a bonding structure 369.

[0035] The third device layer 105 includes a semiconductor substrate 325 having a front surface 325F and a back surface 325B. Multiple semiconductor devices, including a transistor 349, are arranged on the front surface 325F and interconnected by a metal interconnect structure 321 to provide a PLL 137, a DLL 139, and an ISP 131 (see Figure 1). A redistribution layer 329 is arranged on the back surface 325B. A silicon through-electrode 365 forms a connection between the metal interconnect structure 321 and the redistribution layer 329. The third device layer 105 is bonded to the second device layer 103 through a bonding structure 361.

[0036] The second device layer 103 includes a semiconductor substrate 313 having a front surface 313F and a back surface 313B. Multiple semiconductor devices, including a transistor 345, are arranged on the front surface 313F and interconnected by a metal interconnect structure 309, providing in-pixel circuits such as a quench circuit and a recharge circuit 237, a signal processing and output circuit 207, and a timing and control circuit 209 (see Figure 2). The metal interconnect structure 309 also provides row buses and column buses (not shown), row connectors 123, and column connectors 125 (see Figure 1). A redistribution layer 317 is arranged on the back surface 313B. Through-silicon electrodes 357 form connections between the row connectors 123 and column connectors 125 and the redistribution layer 317. The second device layer 103 is bonded to the first device layer 103 through a bonding structure 341.

[0037] The first device layer 101 includes a semiconductor substrate 301 having a front surface 301F and a back surface 301B. SPADs 241 are disposed within or on the front surface 301F and connected to the in-pixel circuits of the second device layer 103 through metal interconnect structures 305 and bonding structures 341 on the front surface 301F. Isolation structures (not shown) provide electrical isolation between SPADs 241. Microlenses, color filters, etc., may be disposed on the back surface 301B.

[0038] Figures 4-13 provide a series of cross-sectional views 400-1300 illustrating an integrated circuit device according to the present invention at various stages of manufacturing according to the process of the present invention. Although Figures 4-13 are described in relation to a series of operations, the order of operations may be changed in some cases, and it will be understood that this series of operations is applicable to structures other than those shown. In some embodiments, some of these operations may be omitted in whole or in part. Furthermore, although Figures 4-13 are described in relation to a series of operations, it will be understood that the structures shown in Figures 4-13 are not limited to the manufacturing method, but may rather exist as structures separate from the method.

[0039] As illustrated in the cross-sectional view 400 of Figure 4, the process begins with separate front-end-of-line (FEOL) and back-end-of-line (BEOL) processing of the first device layer 101, the second device layer 103, the third device layer 105, and the fourth device layer 373, respectively. At this processing stage, each of these device layers may be in wafer form.

[0040] Each of the semiconductor substrates 301, 313, 325, and 337 may be a bulk semiconductor substrate or an SOI (Silicon on Insulator) substrate. At least the upper part of each is semiconductor. The semiconductor may be silicon (Si), a III-V semiconductor (e.g., GaAs), or other binary semiconductor, ternary semiconductor (e.g., AlGaAs), a higher-order semiconductor, an analogue thereof, or any other suitable semiconductor.

[0041] The front-end-of-line processing of the first device layer 101 forms a SPAD 241 in or on the semiconductor substrate 301. The formation of the SPAD 241 may include doping the semiconductor substrate 301, embedding other semiconductors in the semiconductor substrate 301, or forming mesas of other semiconductors on the semiconductor substrate 301. The front-end-of-line processing of the first device layer 101 may also include forming contact regions and isolation structures within the semiconductor substrate 301. The isolation structures may include shallow trench isolation structures, deep trench isolation structures, or doped regions potentially containing embedding layers. The front-end-of-line processing of the first device layer 101 may be a special process sequence structure centered on the formation of the SPAD 241. In some embodiments, this special process sequence is partially characterized by the absence of a process step that forms a polysilicon gate, metal gate, or other transistor structure on the surface 301F.

[0042] Front-end-of-line processing of the second device layer 103 forms the transistor 345 and other semiconductor devices on the surface 313F of the semiconductor substrate 313. These other semiconductor devices may include diodes, capacitors, thyristors, resistors, analogues, or any combination thereof. The transistor 345 is a higher voltage transistor capable of operating at voltages of 10V or higher. In some embodiments, the transistor 345 is capable of operating at voltages of 20V or higher. In some embodiments, the transistor 345 is a planar transistor with a minimum spacing of 22nm or more, the minimum spacing being determined by their formation process. In some embodiments, the transistor 345 has a minimum spacing of 28nm or more. In some embodiments, the transistor 345 has a minimum spacing of 40nm or more. In some embodiments, the transistor 345 has a polysilicon gate. In some embodiments, the transistor 345 has a tunnel dielectric layer which is a medium k dielectric such as silicon dioxide (SiO2) or silicon nitride (SiN), silicon oxynitride (SiON), or analogues, which have a dielectric constant higher than SiO2 but less than 10. In some embodiments, transistor 345 has an SiO2 tunnel dielectric layer. Planar transistors, larger transistor spacing, polysilicon gates, and medium-k or SiO2 tunnel dielectric layers are variously associated with more mature process technologies that support higher operating voltages.

[0043] The front-end-of-line processing of the third device layer 105 forms the transistor 349 and other semiconductor devices on the surface 325F of the semiconductor substrate 325. These other semiconductor devices may include diodes, capacitors, memory cells, thyristors, resistors, similars, or any combination thereof. In some embodiments, the third device layer 105 includes memory cells while the second device layer 103 does not. The third device layer 105 has a maximum operating voltage of about 5V or less. In some embodiments, the third device layer 105 has a maximum operating voltage of about 2.8V or less.

[0044] The front-end-of-line processing of the third device layer 105 follows a different process from the front-end-of-line processing of the second device layer 103, and the difference is associated with more advanced process technology that provides higher circuit density and a lower maximum operating voltage. In some embodiments, the front-end-of-line processing of the third device layer 105 involves lithography with a shorter wavelength than that used for the front-end-of-line processing of the second device layer 103. In some embodiments, the front-end-of-line processing of the third device layer 105 uses extreme ultraviolet (EUV) lithography, while the front-end-of-line processing of the second device layer 103 uses deep ultraviolet (DUV) lithography. In some embodiments, the front-end-of-line processing of the third device layer 105 uses immersion lithography, while the front-end-of-line processing of the second device layer 103 uses lithography in air. In some embodiments, the front-end-of-line processing of the third device layer 105 uses lithography in a vacuum, while the front-end-of-line processing of the second device layer 103 uses lithography in a non-vacuum environment. In some embodiments, the front-end-of-line processing of the third device layer 105 uses a multi-patterning process such as double patterning, while the front-end-of-line processing of the second device layer 103 uses only single patterning.

[0045] In some embodiments, the transistor 349 in the third device layer 105 has a more technically advanced structure than the transistor 345 in the second device layer 103. The progression of advancements is from planar transistors to Finn field-effect transistors (FinFETs), gate-all-around (GAA) transistors, and complementary FETs (C-FETs). A C-FET is a GAA in which nMOS and pMOS nanosheets are stacked vertically to reduce footprint and improve performance. In some embodiments, transistor 349 is a Finn field-effect transistor (FinFET). In some embodiments, transistor 349 is a GAA transistor. In some embodiments, transistor 349 has a metallic gate while transistor 345 has a non-metallic gate. In some embodiments, transistor 349 has a metallic gate while transistor 345 has a non-metallic gate. In some embodiments, transistor 349 has a tunnel dielectric with a higher k than transistor 345. In some embodiments, transistor 349 has a high-k dielectric tunnel dielectric, i.e., a tunnel dielectric with a dielectric constant of 10 or more. Examples of high-k dielectrics include hafnium-based materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfO2-Al2O3) alloys, and their analogues. Additional examples of high-k dielectrics, but not limited to them, include zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium titanate (SrTiO3), and their analogues.

[0046] The transistors 349 in the third device layer 105 have a smaller minimum spacing than the transistors 345 in the second device layer 103. In some embodiments, the transistors 349 have a minimum spacing of approximately 22 nm or less. In some embodiments, the transistors 349 have a minimum spacing of approximately 12 nm or less. In some embodiments, the transistors 349 have a minimum spacing of approximately 7 nm or less.

[0047] The front-end-of-line processing of the fourth device layer 373 forms the transistor 353 and other semiconductor devices on the surface 337F of the semiconductor substrate 337. These other semiconductor devices may include diodes, capacitors, memory cells, thyristors, resistors, analogues, or any combination thereof. The front-end-of-line processing of the fourth device layer 373 may use the same or a different process sequence as that of the third device layer 105, but any comparison made between the processing used in the third device layer 105 and the processing used in the second device layer 103 may also be applied to the comparison between the processing used in the fourth device layer 373 and the processing used in the second device layer 103.

[0048] The BEOL treatment of the first device layer 101, the second device layer 103, the third device layer 105, and the fourth device layer 373 forms metal interconnect structures 305, 309, 321, and 333. These metal interconnect structures include a plurality of metallization layers separated by via layers. Each metallization layer includes conductive traces surrounded by an interlayer insulating film (ILD). Each via layer includes conductive vias that interconnect the conductive traces and are surrounded by ILDs. The conductive traces and vias may include one or more layers of copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, analogues thereof, or any other suitable conductive material. An ILD may comprise one or more layers of silicon dioxide (SiO2), a low dielectric constant interlayer insulator, or an ultra-low dielectric constant insulator. A low dielectric constant insulator has a dielectric constant lower than that of silicon dioxide (SiO2). SiO2 has a dielectric constant of about 3.9. Examples of low dielectric constant insulators include carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass (FSG)), organic polymer low dielectric constant insulators, and organosilicate glass (OSG), such as porous silicate glass. An ultra-low dielectric constant insulator is a material with a dielectric constant of about 2.1 or less. Ultra-low dielectric constant insulator materials are generally low dielectric constant insulator materials formed in a porous structure. Porosity reduces the effective dielectric constant.

[0049] In some embodiments, the metal interconnect structure 305 of the first device layer 101 has fewer metallization layers than the metal interconnect structures 309, 321, and 333 of the second device layer 103, the third device layer 105, and the fourth device layer 373. The metal interconnect structure 305 may be limited to electrode connections of the SPAD241 and associated insulating structures, and these connections are mainly of the second device layer 10 3 It may also be a vertical connection to the internal pixel circuitry. Second device layer 10 3The metal interconnect structure 309 includes at least row bus and column bus grids. The metal interconnect structures 321 and 333 of the third device layer 105 and the fourth device layer 373 provide complex electrical connections between semiconductor devices to provide functional circuits arranged in these layers.

[0050] As illustrated by the cross-sectional view 500 in Figure 5, the process continues by bonding the second device layer 103 to the first device layer 101. The bonding may be a metal-to-metal junction, or a combination of a metal-to-metal junction and a dielectric-to-dielectric junction. The bonding is a pixel-level junction in that at least one electrical connection is formed for each SPAD 241 in the SPAD array 111 (see Figure 1).

[0051] As illustrated by the cross-sectional view 600 in Figure 6, the semiconductor substrate 313 is thinned from the back surface 313B. The thinning process may include grinding, chemical mechanical polishing, plasma or wet etching, or one or more of these. Thinning can reduce the thickness of the semiconductor substrate 313 to approximately 150 μm or less.

[0052] As illustrated by the cross-sectional view 700 in Figure 7, the silicon through-electrode 357 is formed by penetrating the semiconductor substrate 313. The silicon through-electrode 357 may land on a conductive trace 701 within the metal interconnect structure 309. The silicon through-electrode 357 may be formed by etching a hole through the semiconductor substrate 313, lining the hole with a dielectric layer, an adhesive layer, and / or a diffusion barrier layer, performing anisotropic etching at the bottom of the hole to expose a contact such as the conductive trace 701, and filling the hole with a conductive material. The conductive material may be copper (Cu), tungsten (W), aluminum (Al), polysilicon, similar materials, or any other suitable material.

[0053] As shown in the cross-sectional view 800 of Figure 8, the redistribution layer 317 may be formed on the back surface 313B. The redistribution layer may include a metallization layer, a via layer, and an ILD similar to one of the metal interconnect structures.

[0054] As shown in the cross-sectional view 900 of Figure 9, the third device layer 105 is bonded to the second device layer 103. In some embodiments, the third device layer 105 is diced before bonding, so the bonding involves aligning and mounting multiple chips to the second device layer 103. The bonding may be a metal-to-metal bond, or a combination of a metal-to-metal bond and a dielectric-to-dielectric bond.

[0055] As illustrated by the cross-sectional view 1000 in Figure 10, the semiconductor substrate 325 is thinned from the back surface 325B. The thinning process may include grinding, chemical mechanical polishing, plasma or wet etching, or one or more of these. Thinning can reduce the thickness of the semiconductor substrate 325 to approximately 150 μm or less.

[0056] As shown in the cross-sectional view 1100 of Figure 11, the silicon through-electrode 365 is formed penetrating the semiconductor substrate 325. The silicon through-electrode 365 may land on a conductive trace 1101 within the metal interconnect structure 321. The composition and process for forming the silicon through-electrode 365 may be the same as those for forming the silicon through-electrode 357.

[0057] As shown in the cross-sectional view 1200 of Figure 12, the redistribution layer 329 may be formed on the back surface 325B. The redistribution layer may include a metallization layer, via layers, and ILDs similar to one of the metal interconnect structures.

[0058] As shown in the cross-sectional view 1300 of Figure 13, the fourth device layer 373 is bonded to the third device layer 105. In some embodiments, the fourth device layer 373 is diced before bonding, so the bonding involves aligning and mounting multiple chips to the third device layer 105. The bonding may be a metal-to-metal bond, or a combination of a metal-to-metal bond and a dielectric-to-dielectric bond.

[0059] After the fourth device layer 373 is bonded to the third device layer 105, the semiconductor substrate 337 is thinned from the back surface 337B to form the integrated circuit device 300 or a similar device shown in Figure 3. The thinning process may include grinding, chemical mechanical polishing, plasma or wet etching, or one or more of these. Thinning can reduce the thickness of the semiconductor substrate 337 to about 50 μm or less. In some embodiments, thinning reduces the thickness of the semiconductor substrate 337 to about 10 μm or less. After thinning, additional processes may be performed on the back surface 337B. Additional processing may form one or more of the back surface deep groove isolation structures, passivation structures, metal grids, color filters, or microlenses.

[0060] Figure 14 provides a flowchart of Method 1400 for forming an image sensing integrated circuit device according to several embodiments. Although Method 1400 is illustrated and described below as a series of operations or events, it will be understood that the illustrated order of such operations or events should not be interpreted in an restrictive sense. For example, some operations may occur in a different order and / or simultaneously with other operations or events not illustrated and / or described herein. In addition, not all illustrated operations are necessarily required to carry out one or more aspects or embodiments described herein. Furthermore, one or more operations depicted herein may be performed in one or more separate operations and / or stages.

[0061] Method 1400 begins with operation 1401, separate front-end-of-line and BEOL processing for each device layer. There are three, four, or more device layers. At least the first, second, and third device layers are formed by different process sequences. Cross-sectional view 400 in Figure 4 provides an example showing four device layers upon completion of the front-end-of-line and BEOL processing.

[0062] Operation 1403 is to bond the surface of the second device layer to the surface of the first device layer. A cross-sectional view 500 in Figure 5 provides an example.

[0063] Operation 1405 is to thin the substrate of the second device layer from the back side. Cross-sectional view 600 in Figure 6 provides an example.

[0064] Operation 1407 is to form a through-silicon electrode by penetrating the substrate of the second device layer. A cross-sectional view 700 in Figure 7 provides an example.

[0065] Operation 1409 is to form a redistribution layer on the back surface of the second device layer. A cross-sectional view 800 in Figure 8 provides an example.

[0066] Operation 1411 involves bonding the surface of the third device layer to the back surface of the second device layer. A cross-sectional view 900 in Figure 9 provides an example.

[0067] Operation 1413 involves thinning the substrate of the third device layer from the back side. Cross-sectional view 1000 in Figure 10 provides an example.

[0068] Operation 1415 is to form a through-silicon electrode by penetrating the substrate of the third device layer. A cross-sectional view 1100 in Figure 11 provides an example.

[0069] Operation 1417 is to form a redistribution layer on the back surface of the third device layer. A cross-sectional view 1200 in Figure 12 provides an example.

[0070] Operation 1419 involves bonding the surface of the fourth device layer to the back surface of the third device layer. A cross-sectional view 1300 in Figure 13 provides an example.

[0071] Operation 1421 involves thinning the substrate of the first device layer from the back side. Figure 3 provides an example of the resulting structure. Additional processes may form microlenses or other structures on the back side of the first device layer.

[0072] Some aspects of the present invention relate to an integrated circuit device comprising a first device layer, a second device layer, and a third device layer. The first device layer comprises a first semiconductor substrate and a SPAD array. The second device layer comprises a second semiconductor substrate, bonded to the first device layer, and includes intrapixel circuits, as well as row and column connectors. The intrapixel circuits include a quench circuit and a recharge circuit configured to quench avalanche events in the SPAD. The third device layer comprises a third semiconductor substrate, bonded to the second device layer, and includes a row driver circuit and a column read circuit configured to address the intrapixel circuits in the second device layer via row and column connectors.

[0073] In some embodiments, the first device layer does not include any transistors. In some embodiments, the in-pixel circuitry forms a second array, with row and column connectors oriented laterally to the second array, and row driver and column readout circuits oriented laterally to the footprint of the second array. In some embodiments, the device further includes one or more of a phase-locked loop, a delay-locked loop, and an image signal processor on a third device layer within the footprint of the second array. In some embodiments, the device includes a fourth semiconductor substrate and further includes a fourth device layer bonded to the third device layer. The fourth device layer includes an application-specific integrated circuit.

[0074] In some embodiments, the third device layer has a larger minimum transistor spacing than the second device layer. In some embodiments, the maximum operating voltage of the third device layer is 2.8V or less, while the maximum operating voltage of the second device layer is 10V or more. In some embodiments, the third device layer has a more advanced transistor structure than the second device layer. In some embodiments, the third device layer has FinFET or GAA transistors, while the second device layer has only planar transistors.

[0075] In some embodiments, each SPAD in the first device layer is electrically connected to a corresponding quench circuit and recharge circuit in the second device layer by a separate bond between the first and second device layers. In some embodiments, row and column connectors in the second device layer are electrically coupled to row driver and column readout circuits in the third device layer via through-silicon electrodes (TSVs) extending through the second semiconductor substrate. In some embodiments, the in-pixel circuitry includes a comparator configured to receive an avalanche current from the corresponding SPAD in the first device layer, the comparator configured to generate a digitized signal in response to the avalanche current, the digitized signal being at a voltage lower than the avalanche current, and provided to the third device layer.

[0076] Some aspects of the present invention relate to a method for manufacturing an integrated circuit device. This method includes forming a first device layer including a first semiconductor substrate, forming a second device layer including a second semiconductor substrate, and forming a third device layer including a third semiconductor substrate. The first device layer includes an array of single-photon avalanche diodes (SPADs). The second device layer includes in-pixel circuits corresponding to the SPADs, row connectors and column connectors, and corresponding to the row connectors and column connectors. Through-silicon electrodeThe third device layer includes TSVs. The third device layer includes row driver circuits and column read circuits. The first device layer is bonded to the second device layer, and each SPAD in the first device layer is electrically connected to the corresponding in-pixel circuit in the second device layer by individual bonds. The third device layer is bonded to the second device layer, and the row connectors and column connectors in the second device layer are electrically coupled to the row driver circuits and column read circuits in the third device layer via TSVs.

[0077] In some embodiments, the first device layer is formed without transistors. In some embodiments, the second device layer is formed by a process sequence that provides minimum transistors of at least 22 nm, and 3 The device layer is formed by different process sequences that provide transistors spaced less than 22 nm apart.

[0078] Some aspects of the present invention relate to a method for manufacturing an integrated circuit device, the method comprising: processing a first semiconductor substrate including a first front-end-of-line processing to form a SPAD array; processing a second semiconductor substrate including a second front-end-of-line processing to form an array of in-pixel circuits including a quench circuit and a recharge circuit, and a BEOL processing to form row buses and column buses for the array of in-pixel circuits; processing a third semiconductor substrate including a third front-end-of-line processing to form row driver circuits and column readout circuits; bonding the second semiconductor substrate to the first semiconductor substrate, wherein the bonding forms pixel-level electrical connections between the SPAD array and the array of in-pixel circuits; and bonding the second semiconductor substrate to the third semiconductor substrate, wherein the bonding forms electrical connections between the row driver circuits and the row buses and between the column readout circuits and the column buses.

[0079] In some embodiments, a third front-end-of-line processing provides a higher transistor density than a second front-end-of-line processing. In some embodiments, a second front-end-of-line processing provides higher voltage transistors than a second front-end-of-line processing. In some embodiments, the first front-end-of-line processing does not form transistors. In some embodiments, the method further includes processing a fourth semiconductor substrate for forming an application-specific integrated circuit and bonding the fourth semiconductor substrate to the third semiconductor substrate.

[0080] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0081] The present invention generally relates to addressing the limited space within a SPAD chip for arranging SPAD arrays, in-pixel circuits, row driver circuits, and column readout circuits. [Explanation of Symbols]

[0082] 100 Integrated Circuit Devices 101 First Device Layer 103 Second Device Layer 105 Third Device Layer 111 SPAD array 121-pixel in-pixel circuit array 123-row connector 125-row connector 131 Image signal processor 133-row driver circuit 135-column readout circuit 137 Phase-locked loop 139 Delayed Sync Loop 1400 methods 1401, 1403, 1405, 1407, 1409, 1411, 1413, 1415, 1417, 1419, 1421 operation

Claims

1. A first device layer comprising a first semiconductor substrate and an array of single-photon avalanche diodes (SPADs), A second device layer comprising a second semiconductor substrate and bonded to the first device layer, wherein the second device layer includes an in-pixel circuit comprising a quench circuit and a recharge circuit configured to quench an avalanche event in the single-photon avalanche diode, and also includes row connectors and column connectors, An integrated circuit device comprising: a third semiconductor substrate, a third device layer bonded to the second device layer, the third device layer including a row driver circuit and a column read circuit configured to address the in-pixel circuits in the second device layer through the row connector and the column connector; and a third device layer.

2. The integrated circuit device according to claim 1, wherein the first device layer does not include any transistors.

3. The aforementioned in-pixel circuit forms a second array, The row connectors and column connectors are oriented laterally to the second array, The integrated circuit device according to claim 1, wherein the row driver circuit and the column readout circuit are oriented laterally with respect to the footprint of the second array.

4. The integrated circuit device according to claim 3, further comprising one or more of a phase-locked loop, a delay-locked loop, and an image signal processor on the third device layer within the footprint of the second array.

5. The integrated circuit device according to claim 1, further comprising a fourth semiconductor substrate, a fourth device layer bonded to the third device layer, the fourth device layer comprising an application-specific integrated circuit.

6. The integrated circuit device according to claim 1, wherein the third device layer has a minimum transistor spacing smaller than that of the second device layer.

7. The integrated circuit device according to claim 1, wherein the maximum operating voltage of the third device layer is 2.8V or less, and the maximum operating voltage of the second device layer is 10V or more.

8. The integrated circuit device according to claim 1, wherein the third device layer has a more advanced transistor structure than the second device layer.

9. The integrated circuit device according to claim 1, wherein the third device layer has a fin field-effect transistor (FinFET) or a gate-all-around (GAA) transistor, while the second device layer has only a planar transistor.

10. The integrated circuit device according to claim 1, wherein each single-photon avalanche diode in the first device layer is electrically connected to a corresponding quench circuit and recharge circuit in the second device layer by a separate bond between the first device layer and the second device layer.

11. The integrated circuit device according to claim 1, wherein the row connector and column connector in the second device layer are electrically coupled to the row driver circuit and the column readout circuit in the third device layer via through-silicon electrodes (TSVs) that extend through the second semiconductor substrate.

12. Each of the pixel circuits includes a comparator configured to receive an avalanche current from a corresponding single-photon avalanche diode in the first device layer, the comparator configured to generate a digitized signal in response to the avalanche current, the digitized signal having a voltage lower than the avalanche current, and provided to the third device layer, the integrated circuit device according to claim 1.

13. A first device layer is formed, which includes a first semiconductor substrate and an array of single-photon avalanche diodes (SPADs), A second device layer is formed, comprising a second semiconductor substrate and including an in-pixel circuit including a quench circuit and a recharge circuit configured to quench an avalanche event in the single-photon avalanche diode in correspondence with the single-photon avalanche diode, row connectors and column connectors, and through-substrate vias (TSVs) corresponding to the row connectors and column connectors. The first device layer is bonded to the second device layer such that each single-photon avalanche diode in the first device layer is electrically connected to the corresponding in-pixel circuit in the second device layer by a separate bond between the first device layer and the second device layer, A third semiconductor substrate is included, and a third device layer is formed including a row driver circuit and a column readout circuit. The third device layer is joined to the second device layer such that the row connector and column connector in the second device layer are electrically coupled to the row driver circuit and column read circuit in the third device layer via the TSV, A method for manufacturing an integrated circuit device, including [a specific component].

14. The method according to claim 13, wherein the first device layer is formed without transistors.

15. The method according to claim 13, wherein the second device layer is formed by a process sequence that provides minimum transistors of at least 22 nm, and the second device layer is formed by a different process sequence that provides transistors spaced at intervals of less than 22 nm.

16. Processing a first semiconductor substrate, including a first front-end-of-line (FEOL) process for forming a single-photon avalanche diode (SPAD) array, Processing a second semiconductor substrate, which includes a second front-end obline processing for forming an array of in-pixel circuits including a quench circuit and a recharge circuit, and a back-end obline processing for forming row buses and column buses for the array of in-pixel circuits, Processing a third semiconductor substrate, including a third front-end ob-line processing that forms a row driver circuit and a column readout circuit, The second semiconductor substrate is bonded to the first semiconductor substrate so as to form a pixel-level electrical connection between the single-photon avalanche diode array and the array of in-pixel circuits, The second semiconductor substrate is bonded to the third semiconductor substrate so as to form an electrical connection between the row driver circuit and the row bus and between the column read circuit and the column bus, A method for manufacturing an integrated circuit device that includes [a specific component].

17. The method according to claim 16, wherein the third front-end-of-line processing provides a higher transistor density than the second front-end-of-line processing.

18. The method according to claim 16, wherein the second front-end-of-line processing provides a transistor with a higher voltage than the second front-end-of-line processing.

19. The method according to claim 16, wherein the first front-end-of-line processing does not form a transistor.

20. Processing a fourth semiconductor substrate to form an integrated circuit for a specific application, Bonding the fourth semiconductor substrate to the third semiconductor substrate, The method according to claim 16, further comprising:

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