Image sensor

Abstract

To provide an image sensor with improved electrical and optical characteristics. [Solution] The image sensor comprises a semiconductor substrate of a first conductivity type, an isolation structure PIS disposed within the semiconductor substrate and defining a plurality of pixel regions PR1 to 4, an element isolation film disposed within the semiconductor substrate and defining active parts ACT1 and ACT2 in each of the plurality of pixel regions, a transmission gate electrode TG1 and TG2 provided between the photoelectric conversion region and the floating diffusion regions FD1 and FD2 in each of the pixel regions, and a plurality of pixel transistors provided to each of the pixel regions, each of which includes a pixel gate electrode PG1 and PG2 disposed on the active part, and a source / drain region provided within the active part on both sides of the pixel gate electrode, the transmission gate electrodes of the plurality of pixel regions and the pixel gate electrodes of the plurality of pixel transistors include a dopant of the first conductivity type, and the source / drain region includes a dopant of the second conductivity type.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly to an image sensor with improved electrical and optical characteristics.

Background Art

[0002] An image sensor converts an optical image into an electrical signal. In recent years, with the development of the computer and communication industries, the demand for image sensors with improved performance has been increasing in various fields such as digital cameras, video cameras, PCS (Personal Communication System), game devices, security cameras, and medical micro cameras.

[0003] Examples of image sensors include charge-coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate the signal processing circuit on a single chip, making it possible to miniaturize the product. CMOS image sensors also have very low power consumption, making them easy to apply to products with limited battery capacity. In addition, CMOS image sensors can use CMOS process technologies interchangeably, which can reduce the manufacturing cost. Therefore, as CMOS image sensors can achieve higher resolutions with technological development, their use has been increasing rapidly, and improving their electrical and optical characteristics has become an everyday issue.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the problems of the above-mentioned conventional image sensors, and the object of the present invention is to provide an image sensor having improved electrical and optical characteristics. [Means for solving the problem]

[0006] To achieve the above objective, the present invention provides an image sensor comprising: a semiconductor substrate of a first conductivity type; an isolation structure disposed within the semiconductor substrate and defining a plurality of pixel regions; an element isolation film disposed within the semiconductor substrate and defining an active region in each of the plurality of pixel regions; a transmission gate electrode provided between a photoelectric conversion region and a floating diffusion region in each of the plurality of pixel regions; and a plurality of pixel transistors provided in each of the plurality of pixel regions, wherein each of the plurality of pixel transistors includes a pixel gate electrode disposed on the active region and source / drain regions provided within the active region on both sides of the pixel gate electrode, and the transmission gate electrodes of the plurality of pixel regions and the pixel gate electrodes of the plurality of pixel transistors include a dopant of the first conductivity type, and the source / drain regions include a dopant of the second conductivity type.

[0007] Furthermore, an image sensor according to the present invention made to achieve the above objective comprises: a semiconductor substrate of a first conductivity type; an isolation structure disposed within the semiconductor substrate and defining a plurality of pixel regions; an element isolation film disposed within the semiconductor substrate and defining an active portion in each of the plurality of pixel regions; a photoelectric conversion region provided within the semiconductor substrate in each of the plurality of pixel regions and containing a dopant of a second conductivity type; a floating diffusion region provided within the semiconductor substrate, separated from the photoelectric conversion region in each of the plurality of pixel regions; a transmission gate electrode disposed between the photoelectric conversion region and the floating diffusion region in each of the plurality of pixel regions; a source-follower gate electrode disposed on a first active portion among the active portions of the plurality of pixel regions; a first fin activation pattern disposed between the first active portion and the source-follower gate electrode; and a first source / drain region provided within the first active portion on both sides of the source-follower gate electrode, wherein the transmission gate electrode and the source-follower gate electrode contain the dopant of the first conductivity type.

[0008] Furthermore, the image sensor according to the present invention, made to achieve the above objective, comprises: a semiconductor substrate of a first conductivity type having a first surface and a second surface facing each other; an isolation structure disposed within the semiconductor substrate and defining first to fourth pixel regions; first to fourth photoelectric conversion regions disposed within the semiconductor substrate and provided to the first to fourth pixel regions, respectively; first to fourth floating diffusion regions separated from the first to fourth photoelectric conversion regions and provided to the first to fourth pixel regions, respectively; first to fourth transmission gate electrodes provided between the first to fourth photoelectric conversion regions and the first to fourth floating diffusion regions, respectively; each of the first to fourth transmission gate electrodes having a bottom surface at the level between the first surface and the second surface of the semiconductor substrate, adjacent to the first surface of the semiconductor substrate, and defining active portions in the first to fourth pixel regions, respectively; and the first to fourth pixels The invention comprises a plurality of pixel transistors, each provided on the active portion of a region; color filters arranged on the second surface of the semiconductor substrate corresponding to the first to fourth pixel regions; a lattice structure arranged between the color filters and superimposed on the isolation structure; and microlenses on the color filters, wherein each of the plurality of pixel transistors includes a fin active pattern protruding from the active portion of each of the first to fourth pixel regions; a pixel gate electrode crossing the fin active pattern; and source / drain regions provided within the active portion on both sides of the pixel gate electrode, wherein the pixel gate electrode and the first to fourth transmission gate electrodes of the pixel transistors include a dopant of the first conductivity type, and the source / drain regions of the pixel transistors include a dopant of the second conductivity type. [Effects of the Invention]

[0009] According to the image sensor of the present invention, the pixel gate electrode constituting the pixel transistor of a unit pixel includes a dopant of the first conductivity type, which makes it possible to increase the threshold voltage of the pixel transistor. Therefore, the threshold voltage of the pixel transistor can be secured in accordance with the miniaturization of the unit pixel. Therefore, the linearity of the output characteristics of the source-follower transistor can be improved at low light levels. Furthermore, the leakage current characteristics of the source-follower transistor can be improved. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a circuit diagram showing a unit pixel of a pixel array according to an embodiment of the present invention. [Figure 1B] This is a circuit diagram showing a unit pixel of a pixel array according to an embodiment of the present invention. [Figure 2] This is a plan view showing a unit pixel of an image sensor according to an embodiment of the present invention. [Figure 3A] This is a cross-sectional view taken along lines A-A' and D-D' in Figure 2. [Figure 3B] This is a cross-sectional view taken along the lines B-B' and E-E' in Figure 2. [Figure 3C] This is a cross-sectional view taken along the line C-C' in Figure 2. [Figure 4] These are cross-sectional views taken along lines A-A', B-B', and C-C' in Figure 2 according to another embodiment. [Figure 5] These are cross-sectional views taken along lines A-A', B-B', and C-C' in Figure 2 according to another embodiment. [Figure 6] This is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 7] These are cross-sectional views taken along lines A-A', B-B', and C-C' in Figure 6. [Figure 8] This is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 9] These are cross-sectional views taken along lines A-A', B-B', and C-C' in Figure 8. [Figure 10] This is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 11]It is a cross-sectional view taken along the lines A-A', B-B', and C-C' of FIG. 10. [Figure 12] It is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 13] It is a cross-sectional view taken along the lines A-A', B-B', and C-C' of FIG. 12. [Figure 14] It is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 15] It is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 16] It is a cross-sectional view taken along the line F-F' of FIGS. 14 and 15. [Figure 17] It is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 18] It is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 19] It is a cross-sectional view taken along the line I-I' of FIG. 18. [Figure 20] It is a cross-sectional view taken along the line I-I' of FIG. 18.

Embodiments for Carrying Out the Invention

[0011] Next, a specific example of an embodiment for implementing the image sensor according to the present invention will be described with reference to the drawings.

[0012] FIG. 1A is a circuit diagram showing a unit pixel of a pixel array according to an embodiment of the present invention, and FIG. 1B is a circuit diagram showing a unit pixel of a pixel array according to an embodiment of the present invention. Referring to FIGS. 1A and 1B, according to the present embodiment, the image sensor includes a plurality of unit pixels arranged two-dimensionally, and each unit pixel PX converts an optical signal into an electrical signal.

[0013] The unit pixel PX includes a photoelectric conversion circuit 1 and a pixel circuit 2. The photoelectric conversion circuit 1 includes multiple photoelectric conversion groups (1a, 1b, 1c, 1d). The photoelectric conversion circuit 1 may include at least four, eight, or sixteen photoelectric conversion groups (1a, 1b, 1c, 1d). Each of the photoelectric conversion groups (1a, 1b, 1c, 1d) includes at least two photoelectric conversion elements (e.g., photodiodes), a plurality of transfer transistors, and a floating diffusion region. Each of the photoelectric conversion groups (1a, 1b, 1c, 1d) may contain four, eight, or sixteen photoelectric conversion elements. As an example, the photoelectric conversion circuit 1 includes first, second, third, and fourth photoelectric conversion groups (1a, 1b, 1c, 1d).

[0014] The first photoelectric conversion group 1a includes a first photodiode PD1, a second photodiode PD2, a first transmission transistor TX1, and a second transmission transistor TX2. The first and second transfer transistors (TX1, TX2) transmit the charge accumulated in the first and second photoelectric conversion elements (PD1, PD2) to the floating diffusion region FD. The second photoelectric conversion group 1b includes a third photodiode PD3, a fourth photodiode PD4, a third transmission transistor TX3, and a fourth transmission transistor TX4. The third and fourth transfer transistors (TX3, TX4) transfer the charge accumulated in the third and fourth photoelectric conversion elements (PD3, PD4) to the floating diffusion region FD. The third photoelectric conversion group 1c includes a fifth photodiode PD5, a sixth photodiode PD6, a fifth transmission transistor TX5, and a sixth transmission transistor TX6. The fifth and sixth transfer transistors (TX5, TX6) transfer the charge accumulated in the fifth and sixth photoelectric conversion elements (PD5, PD6) to the floating diffusion region FD. The fourth photoelectric conversion group 1d includes a seventh photodiode PD7, an eighth photodiode PD8, a seventh transmission transistor TX7, and an eighth transmission transistor TX8. The seventh and eighth transfer transistors (TX7, TX8) transfer the charge accumulated in the seventh and eighth photoelectric conversion elements (PD7, PD8) to the floating diffusion region FD.

[0015] The first to fourth photoelectric conversion groups (1a, 1b, 1c, 1d) are commonly connected to the floating diffusion region (FD). In other words, the first to eighth transmission transistors (TX1 to TX8) are commonly connected to the floating diffusion region (FD). Although the figures show that each of the first to fourth photoelectric conversion groups (1a, 1b, 1c, 1d) includes two photodiodes, the present invention is not limited thereto, and each photoelectric conversion group may include four or eight photodiodes.

[0016] The transmission gate electrodes of the first to eighth transmission transistors (TX1 to TX8) are controlled by the first to eighth charge transmission signals (TG1 to TG8). In this specification, the transmission gate electrode of each transmission transistor has a dual vertical gate structure. A dual vertical gate structure means that there are two vertical transmission gates corresponding to one photodiode. The same transmission control signal is applied to each of the two vertical transmission gates contained within the dual vertical gate. The floating diffusion region FD receives and cumulatively stores the charge generated by at least one of the first to eighth photodiodes (PD1 to PD8). The source-follower transistor SF is controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0017] Pixel circuit 2 includes a reset transistor (RX), a source follower transistor (SF), a selection transistor (SX), and a dual conversion gain transistor (DCX), as shown in Figure 1A. In contrast, the pixel circuit 2 may also include a reset transistor RX, a source follower transistor SF, and a selection transistor SX, as shown in Figure 1B. In one embodiment, the number of pixel transistors in the pixel circuit 2 is not limited thereto, and the number of pixel transistors can be changed in each unit pixel PX.

[0018] In detail, the reset transistor RX periodically resets the charge accumulated in the floating diffusion region FD in response to the reset signal RG applied to the reset gate electrode. The reset transistor RX is connected between the floating diffusion region FD and the pixel power supply. Specifically, when the reset transistor RX and the double-conversion gain transistor DCX are turned on, the pixel power supply voltage VPIX is transmitted to the floating diffusion region FD. Therefore, the charge accumulated in the floating diffusion region FD is discharged, and the floating diffusion region FD is reset.

[0019] The dual-conversion gain transistor DCX is connected between the floating diffusion region FD and the reset transistor RX. The dual conversion gain transistor DCX varies the conversion gain of a unit pixel PX by varying the capacitance of a charge detection node or a floating diffusion region FD in response to a dual conversion gain control signal DCG. Specifically, during image capture, low-light and high-light conditions are applied to the pixel array, and the dual-conversion gain transistor DCX is turned on in high-light mode and turned off in low-light mode. The dual conversion gain transistor DCX provides different conversion gains for high-light and low-light modes. When the dual-conversion-gain transistor DCX is turned on, the capacitance of the floating diffusion region FD increases, and the conversion gain decreases. When the dual-conversion-gain transistor DCX is turned off, the capacitance of the floating diffusion region FD decreases, and the conversion gain increases. In one embodiment, two or more dual conversion gain transistors DCX may be connected between the reset transistor RX and the floating diffusion region FD, and the conversion gain can be varied in units of pixels PX according to the number of dual conversion gain transistors DCX.

[0020] A source follower transistor (SF) is a source follower buffer amplifier that generates a source-drain current proportional to the amount of charge in the floating diffusion region (FD) input to the source follower gate electrode. The source follower transistor SF amplifies the potential change at the charge detection node and outputs the amplified signal through the selection transistor SX to the output line Vout. The selection transistor SX selects the unit pixel PX to read out row by row. When the selection transistor SX is turned on by the selection signal SG applied to the selection gate electrode, the electrical signal output at the source terminal of the source follower transistor SF is output to the output line Vout.

[0021] Figure 2 is a plan view showing a unit pixel of an image sensor according to an embodiment of the present invention; Figure 3A is a cross-sectional view taken along the lines A-A' and D-D' in Figure 2; Figure 3B is a cross-sectional view taken along the lines B-B' and E-E' in Figure 2; and Figure 3C is a cross-sectional view taken along the line C-C' in Figure 2. Referring to Figures 2, 3A, 3B, and 3C, the image sensor according to an embodiment of the present invention includes a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and a light transmission layer 30.

[0022] When viewed in a vertical cross-section, the photoelectric conversion circuit layer 10 is positioned between the pixel circuit layer 20 and the light transmission layer 30. The photoelectric conversion circuit layer 10 includes a semiconductor substrate 100, an isolation structure PIS, an element isolation film STI, photoelectric conversion regions (110a, 110b), transmission gate electrodes (TG1, TG2, TG3, TG4), and floating diffusion regions (FD1, FD2). The pixel circuit layer 20 includes pixel circuits (e.g., MOS transistors) that are electrically connected to the floating diffusion regions (FD1, FD2). In other words, the pixel circuit layer 20 includes the reset transistor RX, the selection transistor SX, the double conversion gain transistor DCX, and the source follower transistor SF, as previously described with reference to Figures 1A and 1B, and includes wiring connected to the pixel circuit (Figure 1A and Figure 1B).

[0023] The light-transmitting layer 30 collects and filters light incident from the outside and provides it to the photoelectric conversion circuit layer 10. The light-transmitting layer 30 includes a flat insulating film 310, a lattice structure 320, a color filter 330, and a microlens 340. In detail, the semiconductor substrate 100 has a first surface 100a (or front surface) and a second surface 100b (or back surface) that face each other. The semiconductor substrate 100 is a substrate on which a first conductivity type (e.g., p-type) bulk silicon substrate has a first conductivity type epitaxial layer formed on it. In the manufacturing process of the image sensor, the bulk silicon substrate is removed, leaving only the p-type epitaxial layer. In contrast, the semiconductor substrate 100 may be a bulk semiconductor substrate containing wells of the first conductivity type.

[0024] The semiconductor substrate 100 includes multiple pixel regions (PR1, PR2, PR3, PR4) defined by the isolation structure PIS. Multiple pixel regions (PR1, PR2, PR3, PR4) are arranged in a matrix shape along the intersecting first direction D1 and second direction D2. The multiple pixel regions include first, second, third, and fourth pixel regions (PR1, PR2, PR3, PR4), where the first and second pixel regions P (PR1, PR2) are arranged adjacent to each other in the first direction D1, and the first and third pixel regions (PR1, PR3) are arranged adjacent to each other in the second direction D2. The second and fourth pixel regions (PR2, PR4) are adjacent to each other in the second direction D2, and the second and third pixel regions (PR2, PR3) are arranged diagonally with respect to the first and second directions (D1, D2). Here, the first and second directions (D1 and D2) are parallel to the first surface 100a of the semiconductor substrate 100 and intersect each other. The third direction D3 is perpendicular to the first surface 100b of the semiconductor substrate 100.

[0025] Each of the first to fourth pixel regions (PR1 to PR4) is enclosed by a separation structure PIS in a planar view. Each of the first to fourth pixel regions (PR1 to PR4) is defined by a pair of first parts Pa extending in the first direction D1 and a pair of second parts Pb extending in the second direction D2. Furthermore, the separated structure PIS includes a pair of third parts Pc in each of the first to fourth pixel regions (PR1 to PR4). The third section Pc extends from the first section Pa in the second direction D2 or from the second section Pb in the first direction D1, and is separated from each other. The isolation structure PIS penetrates the semiconductor substrate 100 vertically. In detail, the isolation structure PIS has a length in a direction perpendicular to the surface of the semiconductor substrate 100 (i.e., in the third direction D3), and the length of the isolation structure PIS is substantially the same as the thickness of the semiconductor substrate 100 in the vertical direction. As another example, the isolation structure PIS may extend perpendicularly from the first surface 100a of the semiconductor substrate 100 to the second surface 100b, and be separated from the second surface 100b of the semiconductor substrate 100.

[0026] As an example, the isolation structure PIS includes a liner insulation pattern 111, an embedded pattern 113, and a capping insulation pattern 115. The embedded pattern 113 penetrates a portion of the semiconductor substrate 100 vertically, and the liner insulating pattern 111 is provided between the embedded pattern 113 and the semiconductor substrate 100. The capping insulation pattern 115 is placed on the embedded pattern 113. The liner insulating pattern 111 and the capping insulating pattern 115 may include at least one of a silicon oxide film, a silicon oxidnitride film, and a silicon nitride film. The embedded pattern 113 includes an undoped polysilicon film or a polysilicon film doped with impurities. The embedded pattern 113 may include an air gap or a void. The capping insulation pattern 115 of the isolation structure PIS contains the same insulating material as the element isolation film STI, and in some cases, the boundary between the capping insulation pattern 115 and the element isolation film STI may not be observed.

[0027] In one embodiment, the first and second photoelectric conversion regions (110a, 110b) are provided within the semiconductor substrate 100 in each of the first to fourth pixel regions (PR1 to PR4). Light incident from an external source is converted into an electrical signal in the first and second photoelectric conversion regions (110a, 110b). The first and second photoelectric conversion regions (110a, 110b) are impurity regions doped with a dopant of the second conductivity type (e.g., n-type), which is opposite to the first conductivity type semiconductor substrate 100. The first conductivity type semiconductor substrate 100 and the first and second photoelectric conversion regions (110a, 110b) constitute a pair of photodiodes. In other words, a photodiode is formed by the junction between the first conductivity type semiconductor substrate 100 and the first or second photoelectric conversion region (110a, 110b). The first and second photoelectric conversion regions (110a, 110b) that constitute the photodiode generate and accumulate photocharge in proportion to the intensity of the incident light.

[0028] In each of the first to fourth pixel regions (PR1 to PR4), the electrical signal output in the first photoelectric conversion region 110a and the electrical signal output in the second photoelectric conversion region 110b have a phase difference. The image sensor can then measure the distance to an object by comparing the phase difference of the electrical signals output from a pair of first and second photoelectric conversion regions (110a, 110b), determine whether the image sensor is in focus on the object, and determine the degree of focus misalignment, thereby automatically correcting the focus of the image sensor. Each of the first and second photoelectric conversion regions (110a, 110b) has a first width in the first direction D1 and a first length in the second direction D2 that is greater than the first width. For example, the first length is approximately twice the first width. The first and second photoelectric conversion regions (110a, 110b) are separated from each other in the first direction D1 via a third portion Pc of the separation structure PIS. The third part Pc of the pixel separation structure PIS can reduce crosstalk between the first and second photoelectric conversion regions (110a, 110b) by physically reflecting incident light at the edges of each of the first to fourth pixel regions (PR1 to PR4).

[0029] The element isolation film STI is arranged in each of the first to fourth pixel regions (PR1 to PR4) so ​​as to be adjacent to the first surface 100a of the semiconductor substrate 100. The lower surface of the element isolation film STI is perpendicularly separated from the first and second photoelectric conversion regions (110a, 110b). The element isolation film STI is provided in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. The element isolation film (STI) can be made of an insulating material. As an example, referring to Figures 3B, 4B, and 5B, the element isolation film STI includes a liner insulating film conformally covering the surface of the trench, and a filling insulating film that fills the trench on which the liner insulating film is formed. The embedded insulating film may include, for example, at least one of a silicon oxide film, a silicon oxidnitride film, and a silicon nitride film.

[0030] In one embodiment, the element isolation film STI defines first and second active areas (ACT1, ACT2) in each of the first to fourth pixel regions (PR1 to PR4). The first and second active parts (ACT1, ACT2) are parts of the semiconductor substrate 100. In a plan view, the first and second active regions (ACT1, ACT2) are superimposed on the respective first and second photoelectric conversion regions (110a, 110b). In other words, each pixel region (PR1 to PR4) is provided with two first active parts ACT1 and two second active parts ACT2, but the present invention is not limited thereto. The first active part ACT1 and the second active part ACT2 are separated from each other in the second direction D2 by the element separation film STI and may have different sizes and shapes. Although the first active portion ACT1 is shown in a T-shape in the figure, the present invention is not limited thereto and can have a rectangular or polygonal shape of various shapes. The second active portion ACT2 has a long axis in the second direction D2 and a short axis in the first direction D1. Each of the second active parts ACT2 has a second length in the second direction D2 that is smaller than the first length of the first or second photoelectric conversion region (110a, 110b). The first and second active parts (ACT1 and ACT2) of the third and fourth pixel regions (PR3 and PR4) are arranged in mirror symmetry with the first and second active parts (ACT1 and ACT2) of the first and second pixel regions (PR1 and PR2).

[0031] First and second transmission gate electrodes (TG1, TG2) are provided in each of the first to fourth pixel regions (PR1 to PR4). The first transmission gate electrode TG1 is positioned on the first active portion ACT1 and superimposed on the first photoelectric conversion region 110a. The second transmission gate electrode TG2 is positioned on the first active portion ACT1 and superimposed on the second photoelectric conversion region 110b. Parts of the first and second transmission gate electrodes (TG1, TG2) are placed in trenches formed by recessing the first surface 100a of the semiconductor substrate 100. In one embodiment, each of the first and second transmission gate electrodes (TG1, TG2) includes a first portion P1 disposed on the first surface 100a of the semiconductor substrate 100, and a second portion P2 extending perpendicularly from the first portion P1 into the semiconductor substrate 100. Each of the first and second transmission gate electrodes (TG1, TG2) has a first bottom surface BS1 located at a level lower than the first surface 100a of the semiconductor substrate 100.

[0032] In one embodiment, each of the first and second transmission gate electrodes (TG1, TG2) has a dual gate electrode structure including a pair of first and second vertical gates (GE1, GE2) on a single first active portion ACT1. In one embodiment, the shape and position of the first and second transmission gate electrodes (TG1, TG2) can be varied in various ways. In each of the first and second transmission gate electrodes (TG1, TG2), a pair of first and second vertical gates (GE1, GE2) are electrically connected in common through a metal wiring 223. In one embodiment, the first and second transmission gate electrodes (TG1, TG2) may be made of a conductive film containing a dopant of the same conductivity type as the semiconductor substrate 100. For example, the first and second transmission gate electrodes (TG1, TG2) include polysilicon doped with a first conductivity type (e.g., p-type).

[0033] A gate insulating film of uniform thickness is interposed between the first and second transmission gate electrodes (TG1, TG2) and the semiconductor substrate 100. Insulating spacers SP are placed on both side walls of the first and second transmission gate electrodes (TG1, TG2). In each of the first to fourth pixel regions (PR1 to PR4), a first floating diffusion region FD1 is provided within the first active region ACT1 on one side of the first transmission gate electrode TG1. The second floating diffusion region FD2 is provided within the first active region ACT1 on one side of the second transmission gate electrode TG2. The first and second floating diffusion regions (FD1, FD2) are formed by doping the semiconductor substrate 100 with a dopant of a second conductivity type opposite to that of the substrate. For example, the first and second floating diffusion regions (FD1, FD2) are n-type dopant regions. The first and second floating diffuse regions (FD1, FD2) of the first to fourth pixel regions (PR1 to PR4) are electrically connected in common through the contact plug 221 and the metal wiring 223. The first and second floating diffusion regions (FD1, FD2) of the first to fourth pixel regions (PR1 to PR4) electrically share the pixel transistors (SF, DCX, RX, SX) as described with reference to Figures 1A and 1B.

[0034] In each of the first to fourth pixel regions (PR1 to PR4), the first and second pixel gate electrodes (PG1 and PG2) are respectively positioned on the second active region ACT2. In each of the first, second, and fourth pixel regions (PR1, PR2, and PR4), the first pixel gate electrode PG1 is superimposed on the first photoelectric conversion region 110a, and the second pixel gate electrode PG2 is superimposed on the second photoelectric conversion region 110b. In each of the first to fourth pixel regions (PR1 to PR4), the first and second pixel gate electrodes (PG1 and PG2) constitute one of the pixel transistors previously described with reference to Figures 1A and 1B, namely the reset, source follower, double conversion gain, and selection transistors (RX, SF, DCX, and SX).

[0035] As an example, the first pixel gate electrode PG1 of the first pixel P region PR1 is provided as the selected gate electrode of the selected transistor SX, as described with reference to Figures 1A and 1B, and the first and second pixel gate electrodes PG1(SFG) and PG21(SFG) of the third pixel region PR are provided as the source follower gate electrodes of the source follower transistor SF, as described with reference to Figures 1A and 1B. The first and second pixel gate electrodes PG1(SFG) and PG21(SFG) of the third pixel region PR are electrically connected in common via metal wiring 223. The first pixel gate electrode PG1 of the fourth pixel region PR4 is provided as the double conversion gain gate electrode of the double conversion gain transistor DCX, as described with reference to Figures 1A and 1B. The second pixel gate electrode PG2 of the fourth pixel region PR4 is provided as the reset gate electrode of the reset transistor RX, as described with reference to Figures 1A and 1B. In contrast, the first and second pixel gate electrodes (PG1, PG2) of the fourth pixel region PR4 may all be provided as reset gate electrodes of the reset transistor RX.

[0036] Furthermore, the first and second pixel gate electrodes (PG1, PG2) of the second pixel P region PR2 either constitute one of the pixel transistors that make up the unit pixel, or are provided as dummy gates. In one embodiment, the functions of the first and second pixel gate electrodes (PG1, PG2) of the first to fourth pixel regions (PR1 to PR4) can be varied. In one embodiment, in the first to fourth pixel regions (PR1 to PR4), the first and second pixel gate electrodes (PG1, PG2) are made of a conductive film containing a dopant of the same conductivity type as the semiconductor substrate 100. For example, the first and second pixel gate electrodes (PG1, PG2) contain polysilicon doped with a first conductivity type (e.g., p-type). Since the first and second pixel gate electrodes (PG1, PG2) contain a first-conductivity dopant, the threshold voltage of the pixel transistors (SF, RX, DCX, SX) is increased. Therefore, the linearity of the output characteristics of the source-follower transistor FD can be improved at low light levels, and the leakage current characteristics of the source-follower transistor FD can be improved.

[0037] Insulating spacers SP are placed on both side walls of the first and second pixel gate electrodes (PG1, PG2). The insulating spacer SP may include, for example, silicon oxide, silicon nitride, silicon oxidnitride, silicon carbon nitride (SiCN), or silicon carbon oxidnitride (SiCON). A first source / drain region SD1 is provided within the second active region ACT2 on one side of each of the first and second pixel gate electrodes (PG1, PG2), and a second source / drain region SD2 is provided within the second active region ACT2 on the other side of each of the first and second pixel gate electrodes (PG1, PG2). The first and second source / drain regions (SD1, SD2) are formed by doping the semiconductor substrate 100 with a dopant of the second conductivity type opposite to that of the substrate. For example, the first and second source / drain regions (SD1, SD2) are n-type dopant regions.

[0038] In one embodiment, at least one of the pixel transistors (SF, DCX, RX, SX) constituting the unit pixel PX shown in Figures 1A and 1B includes a fin activity pattern FP between the first and second pixel gate electrodes (PG1, PG2) and the second active portion ACT2. As an example, in the third pixel region PR3, a source follower transistor (SF in Figures 1A and 1B) is provided on the second active region ACT2, and the fin active pattern FP protrudes perpendicularly from each of the second active regions ACT2. The fin-active pattern FP is formed as part of the semiconductor substrate 100 by patterning a portion of the semiconductor substrate 100. In detail, the upper surface of the fin-active pattern FP is located at substantially the same level as the first surface 100a of the semiconductor substrate 100. The fin activation pattern FP is located between the first and second source drain regions (SD1, SD2). The fin activity pattern FP has a bar shape extended in the second direction D2.

[0039] The first and second pixel gate electrodes (PG1(SFG) and PG2(SFG)) of the third pixel region PR3 each surround the side walls and top surface of the fin-active pattern FP, respectively. A gate insulating film is interposed between the first and second pixel gate electrodes (PG1, PG2) and the fin active pattern FP, respectively. In the third pixel region PR3, by providing a fin active pattern FP on the second active portion ACT2, it is possible to secure an effective channel width in the first direction D1 and an effective channel length in the second direction D2 of the pixel transistor (e.g., a source-follower transistor). Therefore, even if the area of ​​each pixel region PR is reduced, the electrical characteristics of the pixel transistor can be optimized.

[0040] In one embodiment, the fin activity pattern FP includes a channel region CH doped with a second conductivity type dopant. The channel region CH is provided between the first and second source / drain regions (SD1, SD2). In the channel region (CH), the dopant concentration of the second conductivity type is lower than the dopant concentration of the second conductivity type in the first and second source / drain regions (SD1, SD2). On the other hand, a dopant of the second conductivity type may be undoped within the channel region CH of the fin active pattern FP, and the pixel transistor may have a channel of the first conductivity type in the third pixel region PR3. Because the channel region CH and the first and second source / drain regions (SD1, SD2) have the same conductivity type, the pixel transistor formed by the first and second pixel gate electrodes (PG1, PG2) and the fin active pattern FP constitutes a junctionless transistor. Therefore, it is possible to prevent junction leakage current from occurring between the channel region CH and the first and second source / drain regions (SD1, SD2).

[0041] Furthermore, the first and second pixel gate electrodes (PG1(SFG) and PG2(SFG)) of the third pixel region PR3 have a second bottom surface BS2 at a level lower than the first surface 100a of the semiconductor substrate 100, between the fin active pattern FPs. Furthermore, the second bottom surface BS2 of the first and second pixel gate electrodes (PG1(SFG) and PG2(SFG)) is located at a higher level than the first bottom surface BS1 of the first and second transmission gate electrodes (TG1 and TG2). In other words, the first and second pixel gate electrodes (PG1(SFG) and PG2(SFG)) of the third pixel region PR3 have a second bottom surface BS2 at a level between the first surface 100a and the first bottom surface of the semiconductor substrate 100. Furthermore, with respect to the first surface 100a of the semiconductor substrate 100, the vertical length d1 of the first and second transmission gate electrodes (TG1, TG2) is greater than the vertical length d2 of the first and second pixel gate electrodes (PG1(SFG), PG2(SFG)).

[0042] In one embodiment, the first and second pixel gate electrodes (PG1, PG2) provided to the first, second, and fourth pixel regions (PR1, PR2, PR4), excluding the third pixel region PR3, have a bottom surface parallel to the first surface 100a of the semiconductor substrate 100. In other words, the pixel transistors provided in the first, second, and fourth pixel regions (PR1, PR2, PR4) are planar-type MOS transistors. The first and second pixel gate electrodes (PG1, PG2) on the first, second, and fourth pixel regions (PR1, PR2, PR4) are located on the channel region CH which contains a second-conductivity dopant. In contrast, the pixel transistors on the first, second, and fourth pixel regions (PR1, PR2, PR4) may be provided on a semiconductor substrate 100 of the first conductivity type. In other words, the pixel transistors on the first, second, and fourth pixel regions (PR1, PR2, PR4) include a channel region of the first conductivity type.

[0043] Furthermore, in each of the first to fourth pixel regions (PR1 to PR4), a ground impurity region GR is provided between the first and second photoelectric conversion regions (110a, 110b). The grounded impurity region GR is provided between the third part Pc of the separation structure PIS. The ground impurity region GR is formed by doping the semiconductor substrate 100 with a dopant of the same first conductivity type. An interlayer insulating film 210 is laminated on the first surface 100a of the semiconductor substrate 100, and the interlayer insulating film 210 covers the pixel transistors (RX, SF, DCX, SX) and the first and second transmission gate electrodes (TG1, TG2) that constitute the readout circuit. The interlayer insulating film 210 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. Wiring structures (221, 223) connected to the readout circuit are placed within the interlayer insulating film 210. The wiring structure (221, 223) includes metal wiring 223 and contact plugs 221 that connect them.

[0044] Next, referring to Figures 3A, 3B, and 3C, the light-transmitting layer 30 is placed on the second surface 100b of the semiconductor substrate 100. The flat insulating film 310 covers the second surface 100b of the semiconductor substrate 100. The flat insulating film 310 is made of a transparent insulating material and includes multiple layers. The flat insulating film 310 is made of an insulating material having a different refractive index than the semiconductor substrate 100. The flat insulating film 310 contains a metal oxide and / or a silicon oxide. The lattice structure 320 is placed on the flat insulating film 310. The lattice structure 320, similar to the separation structure PIS, has a lattice shape in a plan view. In a plan view, the grid structure 320 is superimposed on the separation structure PIS. That is, the lattice structure 320 includes a first portion extending in a first direction D1 and a second portion extending in a second direction D2 across the first portion. The width of the grid structure 320 is substantially the same as, or smaller than, the minimum width of the separation structure PIS. The lattice structure 320 includes conductive patterns and / or low-refractive-index patterns. The conductive pattern may include metallic materials such as titanium, tantalum, or tungsten. Low-refractive-index patterns are created using materials with a lower refractive index than conductive patterns. Low refractive index patterns are produced by organic materials and have a refractive index of approximately 1.1 to 1.3. For example, the lattice structure is a polymer layer containing silica nanoparticles.

[0045] A color filter 330 is formed corresponding to each pixel region (PR1 to PR4). The color filter 330 fills the space defined by the grid structure 320. The color filter 330 includes a red, green, or blue color filter, or a magenta, cyan, or yellow color filter, depending on the unit pixel. As another example, some of the color filters 330 may include white color filters or infrared filters. The microlens 340 is positioned on the color filter 330. The microlens 340 has a convex shape and a predetermined radius of curvature. The microlens 340 can be formed from a light-transmitting resin. Microlenses 340 are positioned on the color filter 330, corresponding to each pixel area PR. As another example, at least one of the microlenses 340 may be commonly located on at least two pixel regions PR.

[0046] Figures 4 and 5 are cross-sectional views of an image sensor according to another embodiment of the present invention, showing cross-sections cut along lines A-A', B-B', and C-C' in Figure 2. For simplicity, we will omit explanations of the same technical features as those described earlier with reference to Figures 2, 3A, 3B, and 3C, and instead explain the differences.

[0047] Referring to Figure 4, unlike the embodiments described above, the first bottom surface BS1 of the first and second transmission gate electrodes (TG1, TG2) and the second bottom surface BS2 of the first and second pixel gate electrodes (PG1(SFG), PG2(SFG)) provided to the third pixel region PR3 are located at substantially the same level. In other words, the first and second bottom surfaces (BS1, BS2) are located at the same distance from the first surface 100a of the semiconductor substrate 100. In other words, with respect to the first surface 100a of the semiconductor substrate 100, the vertical length d1 of the first and second transmission gate electrodes (TG1, TG2) of the third pixel region PR3 is substantially the same as the vertical length d2 of the first and second pixel gate electrodes (PG1(SFG), PG2(SFG)). The first and second transmission gate electrodes (TG1, TG2) and the first and second pixel gate electrodes (PG1, PG2) of the first to fourth pixel regions (PR1 to PR4) are formed simultaneously and contain the same conductive material. In one embodiment, the first and second transmission gate electrodes (TG1, TG2) and the first and second pixel gate electrodes (PG1, PG2) of the first to fourth pixel regions (PR1 to PR4) include polysilicon doped with a first conductivity type (e.g., p-type). Furthermore, a channel region CH is provided in which a second conductivity type (e.g., n-type) dopant is doped beneath the first and second pixel gate electrodes (PG1, PG2) of the first to fourth pixel regions (PR1 to PR4).

[0048] Referring to Figure 5, the pixel transistor in the third pixel region PR3 includes first and second pixel gate electrodes (PG1, PG2) located on a channel region CH doped with a second conductivity type (e.g., n-type). Planar pixel transistors are provided in the first, second, and fourth pixel regions (PR1, PR2, PR4), and the pixel transistors in the first, second, and fourth pixel regions (PR1, PR2, PR4) use a semiconductor substrate 100 of first conductivity type as a channel. That is, in the first, second, and fourth pixel regions (PR1, PR2, PR4), the first and second pixel gate electrodes (PG1, PG2) have a bottom surface that is parallel to the first surface 100a of the semiconductor substrate 100.

[0049] Figure 6 is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention, and Figure 7 is a cross-sectional view of an image sensor according to another embodiment of the present invention, showing a cross section cut along lines A-A', B-B', and C-C' in Figure 6. For simplicity, we will omit explanations of the same technical features as those described earlier with reference to Figures 2, 3A, 3B, and 3C, and instead explain the differences.

[0050] Referring to Figures 6 and 7, all pixel transistors in the first to fourth pixel regions (PR1 to PR4) are fin-type MOS transistors. In detail, in each of the first to fourth pixel regions (PR1 to PR4), a fin-activated F pattern FP is provided between the second active portion ACT2 and the first and second pixel gate electrodes (PG1, PG2). The fin activity F pattern FP protrudes perpendicularly from each second active region ACT2. Each of the first and second pixel gate electrodes (PG1, PG2) has a bottom surface at a level lower than the first surface 100a of the semiconductor substrate 100, between the fin-active F patterns FP. In at least one of the first to fourth pixel regions (PR1 to PR4), a dopant of the second conductivity type is doped into the fin-active F pattern FP.

[0051] As an example, in all of the first to fourth pixel regions (PR1 to PR4), a second-type conductive dopant is doped into the fin-active F pattern FP. As another example, the second conductivity type dopant is undoped within the fin-active F pattern FP of the third pixel region PR3, and the second conductivity type dopant is undoped within the fin-active F pattern FP of the first, second, and fourth pixel regions (PR1, PR2, PR4). In other words, the pixel transistors in the third pixel region PR3 include a channel region of the second conductivity type, while the pixel transistors in the first, second, and fourth pixel regions (PR1, PR2, PR4) include a channel region of the first conductivity type. As another example, the fin-active F pattern FP of the third pixel region PR3 is undoped with a second-type dopant, and the fin-active F pattern FP of the first, second, and fourth pixel regions (PR1, PR2, PR4) is doped with a second-type dopant. In other words, the pixel transistors in the third pixel region PR3 include a channel region of the first conductivity type, while the pixel transistors in the first, second, and fourth pixel regions (PR1, PR2, PR4) include a channel region of the second conductivity type.

[0052] Figure 8 is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention, and Figure 9 is a cross-sectional view taken along lines A-A', B-B', and C-C' in Figure 8. To simplify the explanation, we will omit the explanation of technical features that are the same as those of the image sensor described earlier with reference to Figures 6 and 7, and instead explain the differences.

[0053] Referring to Figures 8 and 9, all pixel transistors in the first to fourth pixel regions (PR1 to PR4) are fin-type MOS transistors, and the width of the fin-activated F patterns (FP1, FP2) differs depending on the pixel transistors provided in the first to fourth pixel regions (PR1 to PR4). As an example, in the third pixel region PR3, a first fin-activated F pattern FP1 is provided between the second active part ACT2 and the first and second pixel gate electrodes (PG1, PG2), and in the first, second, and fourth pixel regions (PR1, PR2, PR4), a second fin-activated F pattern FP2 is provided between the second active part ACT2 and the first and second pixel gate electrodes (PG1, PG2). In the third pixel region PR3, each of the first and second pixel gate electrodes (PG1, PG2) is positioned across the first fin activation F pattern FP1. In each of the first, second, and fourth pixel regions (PR1, PR2, PR4), each of the first and second pixel gate electrodes (PG1, PG2) is positioned across the second fin-activated F pattern FP2. In one embodiment, in the first direction D1, the width of each of the first fin-activating F patterns FP1 is smaller than the width of each of the second fin-activating F patterns FP2.

[0054] Figure 10 is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention, and Figure 11 is a cross-sectional view taken along lines A-A', B-B', and C-C' in Figure 10. Referring to Figures 10 and 11, as previously described, in each of the first to fourth pixel regions (PR1 to PR4), first and second transmission gate electrodes (TG1, TG2) are provided on the first active portion ACT1, and each of the first and second transmission gate electrodes (TG1, TG2) includes a vertical portion extended into the semiconductor substrate 100.

[0055] In each of the first, second, and fourth pixel regions (PR1, PR2, PR4), the first and second pixel gate electrodes (PG1, PG2) are respectively positioned on the second active region ACT2. In the third pixel region PR3, one pixel gate electrode PG (SFG) is positioned across the second active region ACT2. In the third pixel region PR3, the pixel gate electrode PG (SFG) is longer in the first direction D1 than the first and second pixel gate electrodes (PG1, PG2). In other words, the pixel gate electrode PG (SFG) overlaps with a portion of the first and second photoelectric conversion regions (110a, 110b) of the third pixel region PR3. In the third and fourth pixel regions (PR3, PR4), a fin-active F pattern FP is provided between the pixel gate electrode PG (SFG) and the second active region ACT2. The second type of dopant is undoped within the fin-active F pattern FP of the third pixel region PR3, and the second type of dopant is undoped within the fin-active F pattern FP of the fourth pixel region PR4. In contrast, the channel region of the pixel transistors in the first to fourth pixel regions (PR1 to PR4) can be undoped with a dopant of the second conductivity type. In other words, the pixel transistors in the first to fourth pixel regions (PR1 to PR4) include a channel region of the first conductivity type.

[0056] Figure 12 is a plan view showing a unit pixel of an image sensor according to another embodiment of the present invention, and Figure 13 is a cross-sectional view taken along lines A-A', B-B', and C-C' in Figure 12. Referring to Figures 12 and 13, all pixel transistors in the first to fourth pixel regions (PR1 to PR4) are planar-type MOS transistors, and the first and second pixel gate electrodes (PG1, PG2) of the pixel transistors contain polysilicon with a first-conductivity dopant. Therefore, the threshold voltage of the pixel transistors in the first to fourth pixel regions (PR1 to PR4) increases. Furthermore, the channel region CH between the first and second source / drain regions (SD1, SD2) contains a dopant of the second conductivity type. In the channel region (CH), the threshold voltage of each pixel transistor can be adjusted according to the concentration of the second conductivity type dopant.

[0057] Figures 14 and 15 are plan views showing a unit pixel of an image sensor according to another embodiment of the present invention, and Figure 16 is a cross-sectional view taken along the F-F' line in Figures 14 and 15. To simplify the explanation, we will omit descriptions of technical features that are identical to those of the image sensor described earlier, and instead focus on the differences. Referring to Figures 14 and 16, the image sensor includes multiple pixel groups PGX.

[0058] Each pixel group PGX contains at least four, eight, nine, or sixteen pixel regions (PR1 to PR4). In each pixel group GPX, the pixel regions (PR1 to PR4) are arranged in a matrix shape along the intersecting first direction D1 and second direction D2. In one embodiment, the first to fourth pixel regions (PR1 to PR4) constitute a single pixel group GPX. In one embodiment, a single pixel group GPX is shown in the figure as containing four pixel regions, but the present invention is not limited thereto. The first to fourth pixel regions (PR1 to PR4) are each provided with the first to fourth photoelectric conversion regions (110a to 110d). The first to fourth photoelectric conversion regions (110a to 110d) are impurity regions doped with a second-type conductivity dopant.

[0059] On the first surface 100a of the semiconductor substrate 100, a first active portion ACT1 and a second active portion ACT2 are provided in each of the first to fourth pixel regions (PR1 to PR4) by an element isolation film STI. The first and second active parts (ACT1, ACT2) are defined by an element isolation film STI adjacent to the first surface 100a of the semiconductor substrate 100. The first to fourth pixel regions (PR1 to PR4) are each provided with the first to fourth transmission gate electrodes (TG1, TG2, TG3, TG4). Each of the first to fourth transmission gate electrodes (TG1 to TG4) has a dual vertical gate electrode structure that includes two vertical portions that extend into the semiconductor substrate 100, as described above. In the first to fourth pixel regions (PR1 to PR4), the first to fourth transmission gate electrodes (TG1, TG2, TG3, TG4) contain polysilicon doped with a first-conductivity dopant, as explained earlier.

[0060] The first to fourth floating diffusion regions (FD1 to FD4) are each provided within the first active region ACT1 on one side of the first to fourth transmission gate electrodes (TG1 to TG4). The first to fourth floating diffuse regions (FD1 to FD4) are arranged adjacent to each other and are located in the central part of each pixel group PGX. In each of the first to fourth pixel regions (PR1 to PR4), a pixel transistor is provided on the second active region ACT2. The first to fourth pixel gate electrodes (PG1, PG2, PG3, PG4) are each provided on the second active portion ACT2 of the first to fourth pixel regions (PR1 to PR4). The first to fourth pixel gate electrodes (PG1 to PG4) contain polysilicon doped with a first-type conductivity dopant, as explained earlier. At least one of the pixel transistors in the first to fourth pixel regions (PR1 to PR4) is a fin-type transistor. In other words, the fin activity pattern FP is positioned between the second active portion ACT2 and the first to fourth pixel gate electrodes (PG1 to PG4). On the other hand, as explained earlier, some of the pixel transistors in the first to fourth pixel regions (PR1 to PR4) may be m-planar transistors. Furthermore, in one embodiment, a channel region may be included between the source / drain regions of the pixel transistor, and the channel region may include a dopant of a second conductivity type.

[0061] Referring to Figure 15, a common active area ACT is provided for the first to fourth pixel regions (PR1 to PR4), and a second active area ACT2 is provided for each pixel region (PR1 to PR4). In the first to fourth pixel regions (PR1 to PR4), the first to fourth transmission gate electrodes are each provided on the common active portion ACT. For each pixel group GPX, one common floating diffusion region CFD is provided within the common active region ACT. As an example, a common floating diffuse region CFD is provided in common to at least four pixel regions (PR1 to PR4).

[0062] The first portion Pa of the separation structure PIS is separated in the first direction D1 via a common floating diffusion region CFD, and the second portion Pb is separated in the second direction D2 via a common floating diffusion region CFD. The common floating diffusion region FD is provided within the semiconductor substrate 100 so as to be adjacent to the first to fourth transmission gate electrodes (TG1 to TG4). The first to fourth pixel gate electrodes (PG1, PG2, PG3, PG4) are each provided on the second active portion ACT2 of the first to fourth pixel regions (PR1 to PR4). The first to fourth transmission gate electrodes (TG1 to TG4) and the first to fourth pixel gate electrodes (PG1 to PG4) of the first to fourth pixel regions (PR1 to PR4) contain polysilicon doped with a first-conductivity type dopant, as described earlier.

[0063] Figure 17 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to Figure 17, the image sensor according to this embodiment includes first to third pixel groups (GPX1, GPX2, GPX3) arranged two-dimensionally along a first direction D1 and a second direction D2. In odd-numbered rows, the first and second pixel groups (GPX1 and GPX2) are arranged alternately and repeatedly. In even-numbered rows, the second and third pixel groups (GPX2, GPX3) are arranged alternately and repeatedly. Each of the first to third pixel groups (GPX1, GPX2, GPX3) contains a 2x2 pixel region PR. The separation structure PIS separates the first to third pixel groups (GPX1, GPX2, GPX3) from each other. In a planar view, the separation structure PIS is inserted into each pixel group (GPX1, GPX2, GPX3) to separate the pixel region PR. However, the separation structure PIS is cut at the center of each pixel group (GPX1, GPX2, GPX3), and the pixel regions PR belonging to one pixel group are connected to each other.

[0064] The first pixel group GPX1 is covered by the first color filter CF1. The second pixel group, GPX2, is covered by the second color filter, CF2. The third pixel group, GPX3, is covered by the third color filter, CF3. The first color filter CF1 has one of the following colors, for example, red, green, and blue. The second color filter CF2 has one other color from among red, green, and blue. The third color filter CF3 has one other color from among red, green, and blue. Microlenses (ML) are positioned on the first to third color filters (CF1, CF2, CF3). The microlenses ML correspond to and superimpose the pixel regions PR. In other words, one microlens ML is placed on one pixel PX. A 2x2 array of microlenses (ML) is arranged on each pixel group (GPX1, GPX2, GPX3). Such an arrangement of microlenses (ML) can enhance the light-gathering efficiency in each pixel area (PR), resulting in a sharper image.

[0065] Figure 18 is a plan view showing a schematic configuration of an image sensor according to another embodiment of the present invention, and Figures 19 and 20 are cross-sectional views taken along the line I-I' in Figure 18. Referring to Figures 18 and 19, the image sensor includes a sensor chip C1 and a logic chip C2. The sensor chip C1 includes a pixel array region R1 and a pad region R2. The pixel array region R1 includes a plurality of unit pixels P arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect each other. Each unit pixel P includes a photoelectric conversion element and a readout element. In each unit pixel P of the pixel array region R1, an electrical signal generated by incident light is output.

[0066] The pixel array region R1 includes the light-receiving region AR and the light-shielding region OB. The light-blocking region OB surrounds the light-receiving region AR in a planar view. In other words, the light-shielding area OB is positioned above, below, and to the left and right of the light-receiving area AR in a plan view. A reference pixel is provided in the light-shielding region OB, where no light is incident. The size of the electrical signal sensed by the unit pixel P is calculated by comparing the amount of charge sensed by the reference pixel with the amount of charge sensed by the unit pixel P in the light-receiving region AR. Multiple conductive pads CP, used for inputting and outputting control signals and photoelectric signals, are arranged in the pad area R2. The pad region R2 surrounds the pixel array region R1 in a plan view, facilitating electrical connections with external elements. The conductive pad CP inputs and outputs electrical signals generated at a unit pixel P to an external device.

[0067] In the light-receiving area (AR), the sensor chip C1 includes the same technical features as the image sensor described earlier. In other words, as described earlier, the sensor chip C1 includes a photoelectric conversion circuit layer 10 between the pixel circuit layer 20 and the light transmission layer 30 in the vertical direction. As previously described, the photoelectric conversion circuit layer 10 of the sensor chip C1 includes a semiconductor substrate 100, an isolation structure PIS that defines a pixel region, and a photoelectric conversion region 110 provided within the pixel region. The separation structure PIS has substantially the same structure in the light-receiving region AR and the light-shielding region OB. The isolation structure PIS is placed within the semiconductor substrate 100 in the light-shielding region OB. The embedded pattern 113 within the isolation structure PIS is electrically connected to the rear contact plug PLG in the light-shielding area OB. A predetermined bias is applied to the embedded pattern 113 through the rear contact plug PLG. The rear contact plug PLG has a width greater than the width of the isolation structure PIS. The rear contact plug PLG contains metal and / or metal nitride. For example, the back contact plug PLG contains titanium and / or titanium nitride.

[0068] The contact pattern CT is embedded in the contact hole where the rear contact plug PLG is formed. The contact pattern CT contains a different material than the back contact plug PLG. For example, contact pattern CT contains aluminum (Al). The contact pattern CT and the rear contact plug PLG are electrically connected to the embedded pattern 113 of the isolation structure PIS. A positive bias is applied to the embedding pattern 113 of the separation structure PIS via the contact pattern CT, and the positive bias is transmitted to the light-receiving region AR in the light-shielding region OB. Therefore, the dark current generated at the interface between the isolation structure PIS and the semiconductor substrate 100 can be reduced.

[0069] The light-transmitting layer 30 is a light-shielding region OB and includes a light-shielding pattern OBP, a filtering film 335, and an organic film 345. In one embodiment, the separation structure PIS is continuously extended from the light-receiving region AR to the light-shielding region OB. In the light-shielding region OB, the light-shielding pattern OBP is positioned on the upper surface of the flat insulating film 310. The light-shielding pattern OBP contains the same material as the conductive pattern of the lattice structure 320 of the light-receiving region AR. In other words, the light-shielding pattern OBP includes metal patterns and metal oxide patterns. For example, the light-shielding pattern OBP includes titanium nitride and titanium oxynitride. The light-shielding pattern OBP does not need to be extended to the light-receiving area AR. The light-shielding pattern OBP blocks light from entering the photoelectric conversion region PD provided in the light-shielding region OB. In the reference pixel area of ​​the light-shielding area OB, the photoelectric conversion area PD does not output a photoelectric signal, but instead outputs a noise signal. Noise signals are generated by electrons produced by heat generation or dark current, etc.

[0070] The filtering film 335 covers the light-shielding pattern OBP in the light-shielding region OB. The filtering film 335 blocks light of a different wavelength than the color filter 330. For example, the filtering film 335 blocks infrared rays. The filtering film 335 may, but is not limited to, include a blue color filter. The organic film 345 and the passivation film are provided on the protective film in the light-shielding region OB and the pad region R2. The organic film 345 contains the same material as the microlens 340.

[0071] In the light-shielding region OB, the first through-conductive pattern 511 penetrates the semiconductor substrate 100 and is electrically connected to the metal wiring of the pixel circuit layer 20 and the wiring structure 1111 of the logic chip C2. The first through-conductive pattern 511 has a first bottom surface and a second bottom surface located at different levels from each other. The first embedded pattern 521 is provided inside the first through-conductive pattern 511. The first embedded pattern 521 contains a low refractive index material and has insulating properties. In the pad region R2, a conductive pad CP is provided on the second surface 100b of the semiconductor substrate 100. The conductive pad CP is embedded within the second surface 100b of the semiconductor substrate 100. As an example, the conductive pad CP is provided in a pad trench formed on the second surface 100b of the semiconductor substrate 100 in the pad region R2. The conductive pad CP may contain metals such as aluminum, copper, tungsten, titanium, tantalum, or alloys thereof. In the image sensor mounting process, bonding wires are bonded to conductive pads CP. The conductive pad CP is electrically connected to an external device via bonding wires.

[0072] In the pad region R2, the second through-conductive pattern 520 penetrates the semiconductor substrate 100 and is electrically connected to the wiring structure 1111 of the logic chip C2. The second through-conductive pattern 520 extends onto the second surface 100b of the semiconductor substrate 100 and is electrically connected to the conductive pad CP. A portion of the second through-conductive pattern 520 covers the bottom surface and side walls of the conductive pad CP. The second embedded pattern 510 is provided inside the second through-conductive pattern 520. The second embedded pattern 510 contains a low refractive index material and has insulating properties. In the pad region R2, the isolation structure PIS is provided around the second through-conductive pattern 520. The logic chip C2 includes a logic semiconductor substrate 1000, a logic circuit TR, a wiring structure 1111 connected to the logic circuit TR, and a logic interlayer insulating film 1100. The uppermost layer of the logic interlayer insulating film 1100 is bonded to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 is electrically connected to the sensor chip C1 through the first through-hole conductive pattern 511 and the second through-hole conductive pattern 520. In one example, the sensor chip C1 and the logic chip C2 have been described as being electrically connected to each other through first and second through-hole conductive patterns (511, 520), but the present invention is not limited thereto.

[0073] According to the embodiment shown in Figure 20, the first and second through-conductive patterns shown in Figure 19 are omitted, and the sensor chip C1 and logic chip C2 are electrically connected by directly bonding the bonding pads provided on the uppermost metal layers of the sensor chip C1 and logic chip C2 to each other. In detail, on the sensor chip C1, the embedded pattern 113 of the isolation structure PIS, which extends from the light-receiving area AR to the light-shielding area OB, is connected to the rear contact plug PLG in the light-shielding area OB. In addition, the sensor chip C1 includes a first bonding pad BP1 provided on the top metal layer of the pixel circuit layer 20, and the logic chip C2 includes a second bonding pad BP2 provided on the top metal layer of the wiring structure 1111.

[0074] The first and second bonding pads (BP1, BP2) may include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN). The first bonding pad BP1 of sensor chip C1 and the second bonding pad BP2 of logic chip C2 are directly electrically connected to each other using a hybrid bonding method. Hybrid bonding refers to a type of bonding in which two components containing the same type of material fuse together at their interface. For example, if the first and second bonding pads (BP1, BP2) are made of copper (Cu), they are physically and electrically connected by copper (Cu)-copper (Cu) bonding. Furthermore, the insulating film surface of sensor chip C1 and the insulating film surface of logic chip C2 are joined by dielectric-dielectric bonding.

[0075] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0076] 10 Photoelectric conversion circuit layer 20 pixel circuit layers 30 Light transmission layer 100 semiconductor substrates 110a, 110b (1st, 2nd) Photoelectric Conversion Regions 111 Liner Insulation Pattern 113 Embedding Patterns 115 Capping Insulation Pattern 210 Interlayer insulating film 221 Contact Plug 223 Metal wiring 310 Flat insulating film 320 Lattice Structure 330 Color Filters 340 Microlens ACT1, ACT2 (1st, 2nd) active part CH Channel Area FD1, FD2 (first, second) floating diffusion regions GR ground impurity region P1, P2 (1st, 2nd) parts PG1, PG2 (first and second) pixel gate electrodes PIS separation structure PR1, PR2, PR3, PR4 (1st to 4th) pixel regions SD Source / Drain Area STI device isolation membrane TG1, TG2, TG3, TG4 (1st to 4th) transmission gate electrodes

Claims

1. A first-type conductive semiconductor substrate and A separation structure is disposed within the semiconductor substrate and defines a plurality of pixel regions, A device isolation film disposed within the semiconductor substrate and defining an active area in each of the plurality of pixel regions, In each of the plurality of pixel regions, a transmission gate electrode is provided between the photoelectric conversion region and the floating diffusion region, The plurality of pixel transistors provided in each of the plurality of pixel regions, Each of the aforementioned plurality of pixel transistors is A pixel gate electrode disposed on the active portion, The pixel gate electrode includes source / drain regions provided within the active portion on both sides of the pixel gate electrode, The transmission gate electrodes of the plurality of pixel regions and the pixel gate electrodes of the plurality of pixel transistors include a dopant of the first conductivity type. The image sensor is characterized in that the source / drain region includes a second-type conductivity dopant.

2. At least one of the plurality of pixel transistors includes a channel region between the source / drain regions, The image sensor according to claim 1, characterized in that the channel region includes the second conductivity type dopant.

3. The image sensor according to claim 1, characterized in that the first pixel transistor among the plurality of pixel transistors further includes a fin activity pattern between the active portion and the pixel gate electrode.

4. The image sensor according to claim 3, characterized in that the fin activation pattern includes a dopant of the first conductivity type or the second conductivity type.

5. The image sensor according to claim 3, characterized in that the upper surface of the fin activation pattern is located at substantially the same level as the first surface of the semiconductor substrate.

6. The transmission gate electrode includes a vertical portion that vertically penetrates a part of the semiconductor substrate. The vertical portion of the transmission gate electrode has a first bottom surface at a level lower than the upper surface of the semiconductor substrate. The image sensor according to claim 3, characterized in that the pixel gate electrode of the first pixel transistor has a second bottom surface at a level between the first surface and the first bottom surface of the semiconductor substrate.

7. The first pixel transistor among the plurality of pixel transistors further includes a fin active pattern disposed between the active portion and the gate electrode, The pixel gate electrode of the first pixel transistor is positioned across the fin activation pattern, The image sensor according to claim 1, characterized in that the pixel gate electrode of the second pixel transistor among the plurality of pixel transistors has a bottom surface that is parallel to the first surface of the semiconductor substrate.

8. The image sensor according to claim 1, characterized in that the transmission gate electrode includes a vertical portion that vertically penetrates a part of the semiconductor substrate.

9. The vertical portion of the transmission gate electrode has a first bottom surface at a level lower than the upper surface of the semiconductor substrate. The image sensor according to claim 8, characterized in that the pixel gate electrode has a second bottom surface at a level between the first surface and the first bottom surface of the semiconductor substrate.

10. The image sensor according to claim 1, characterized in that the transmission gate electrode includes a first vertical gate and a second vertical gate that extend into the semiconductor substrate.

11. In each of the plurality of pixel regions, the photoelectric conversion region includes a first photoelectric conversion region and a second photoelectric conversion region. In each of the plurality of pixel regions, the floating diffusion region includes a first floating diffusion region and a second floating diffusion region. The image sensor according to claim 1, characterized in that in each of the plurality of pixel regions, the transmission gate electrode includes a first transmission gate electrode between the first photoelectric conversion region and the first floating diffusion region, and a second transmission gate electrode between the second photoelectric conversion region and the second floating diffusion region.

12. The image sensor according to claim 11, characterized in that the pixel gate electrodes of the plurality of pixel transistors include a first pixel gate electrode and a second pixel gate electrode that are superimposed on the first photoelectric conversion region and the second photoelectric conversion region, respectively.

13. A first-type conductive semiconductor substrate and A separation structure is disposed within the semiconductor substrate and defines a plurality of pixel regions, A device isolation film disposed within the semiconductor substrate and defining an active area in each of the plurality of pixel regions, In each of the plurality of pixel regions, a photoelectric conversion region is provided within the semiconductor substrate and includes a second-conductivity dopant, In each of the plurality of pixel regions, a floating diffusion region is provided within the semiconductor substrate, separated from the photoelectric conversion region. In each of the plurality of pixel regions, a transmission gate electrode is disposed between the photoelectric conversion region and the floating diffusion region, A source follower gate electrode is disposed on the first active portion among the active portions of the plurality of pixel regions, A first fin activation pattern is disposed between the first active portion and the source-follower gate electrode, The source follower gate electrode has a first source / drain region provided within the first active portion on both sides of the gate electrode, The image sensor is characterized in that the transmission gate electrode and the source follower gate electrode include the first conductivity type dopant.

14. The image sensor according to claim 13, characterized in that the first source / drain region includes the second conductivity type dopant.

15. The image sensor according to claim 13, characterized in that the bottom surface of the transmission gate electrode and the bottom surface of the source follower gate electrode are located at a level lower than the top surface of the semiconductor substrate.

16. The first fin activation pattern includes a first channel region between the first source / drain region, The image sensor according to claim 13, characterized in that the first channel region includes the second conductivity type dopant.

17. A pixel gate electrode is disposed on the second active portion of the active portion of the plurality of pixel regions, The present invention further comprises a second source / drain region provided within the second active portion on both sides of the pixel gate electrode, The image sensor according to claim 13, characterized in that the pixel gate electrode includes the first conductivity type dopant.

18. The second fin activation pattern is further disposed between the second active portion and the pixel gate electrode, The image sensor according to claim 17, characterized in that the bottom surface of the pixel gate electrode is located at substantially the same level as the bottom surface of the source-follower gate electrode.

19. A semiconductor substrate of a first conductivity type having a first surface and a second surface facing each other, A separation structure is disposed within the semiconductor substrate and defines the first to fourth pixel regions, Displaced within the semiconductor substrate, the first to fourth photoelectric conversion regions are provided to the first to fourth pixel regions, respectively. The first to fourth floating diffuse regions are separated from the first to fourth photoelectric conversion regions and provided to the first to fourth pixel regions, respectively. The first to fourth transmission gate electrodes are provided between the first to fourth photoelectric conversion regions and the first to fourth floating diffusion regions, respectively. Each of the first to fourth transmission gate electrodes has a bottom surface at a level between the first and second surfaces of the semiconductor substrate. An element isolation film adjacent to the first surface of the semiconductor substrate, defining active areas in the first to fourth pixel regions, A plurality of pixel transistors provided on the active portion of the first to fourth pixel regions, A color filter is arranged on the second surface of the semiconductor substrate, corresponding to the first to fourth pixel regions, A grid structure is arranged between the color filters and superimposed on the separation structure, The color filter has microlenses, Each of the aforementioned plurality of pixel transistors is Fin activity patterns protruding from the active portion of each of the first to fourth pixel regions, A pixel gate electrode that crosses the aforementioned fin activation pattern, The pixel gate electrode includes source / drain regions provided within the active portion on both sides of the pixel gate electrode, The pixel gate electrode and the first to fourth transmission gate electrodes of the pixel transistor include the first conductivity type dopant. The image sensor is characterized in that the source / drain region of the pixel transistor includes a second-conductivity dopant.

20. At least one of the plurality of pixel transistors includes a channel region provided within the fin activation pattern between the source / drain regions, The image sensor according to claim 19, characterized in that the channel region includes the second conductivity type dopant.

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