Evaluation method for metal oxide films

Abstract

To provide a metal oxide film with high electrical properties. To provide a highly reliable metal oxide film , . 【Solution means】The metal oxide film contains indium, M (M is aluminum, gallium, yttrium um, or tin), and zinc. Also, the distribution of the interplanar spacing d determined by electron diffraction in which an electron beam is irradiated from a direction perpendicular to the film surface of the metal oxide film has a first peak and a second peak. The apex of the first peak is located at 0.25 nm or more and​​​​​​​​​​

Description

Technical Field

[0001] One aspect of the present invention relates to a metal oxide film. One aspect of the present invention relates to a semiconductor device using a metal oxide film. One aspect of the present invention relates to a method for evaluating a metal oxide film.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

[0003]

Background Art

Prior Art Documents

[0004]

Patent Documents

Patent Document 1

Summary of the Invention

[0005]

Problems to be Solved by the Invention

[0006] Furthermore, one aspect of the present invention provides a semiconductor device to which a metal oxide film is applied and which has high electrical properties. One of the objectives is to achieve a highly reliable metal oxide film. One aspect of the present invention involves applying a metal oxide film to a metal oxide film. One of the objectives is to provide semiconductor devices.

[0007] Furthermore, one aspect of the present invention relates to a novel method for analyzing, evaluating, or interpreting metal oxide films. One of the objectives is to provide [this].

[0008] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title can be extracted from descriptions such as the specification, drawings, and claims. [Means for solving the problem]

[0009] One aspect of the present invention is indium, M (where M is aluminum, gallium, yttrium, etc.) It is a metal oxide film containing tin and zinc. The metal oxide film is the surface of the metal oxide film. The distribution of interplanar spacing d, determined by electron diffraction irradiated from a direction perpendicular to the plane, is the first P It has a first peak and a second peak. The peak of the first peak is 0.25 nm or more and 0.30 nm or more. It is located below m, and the peak of the second peak is located between 0.15 nm and 0.20 nm. The distribution of interplanar spacing d is determined from multiple electron diffraction patterns in multiple regions of the metal oxide film. This is what can be obtained. Furthermore, electron diffraction is performed with a beam diameter of 0.3 nm to 10 nm. This is done using electron beams.

[0010] Furthermore, in the above, the height of the first peak is greater than the height of the second peak. A high value is preferable. Alternatively, in the above, the height of the peak of the first peak is equal to the height of the second peak. It is preferable that it be lower than the height of the vertex of the curve.

[0011] Another aspect of the present invention includes a semiconductor layer, a gate electrode, and a gate insulating layer. A semiconductor device wherein the semiconductor layer includes the metal oxide film described in any one of the above descriptions.

[0012] Another aspect of the present invention involves a metal oxide film with respect to multiple regions of the metal oxide film. An electron beam with a beam diameter of 0.3 nm to 10 nm is irradiated from a direction perpendicular to the surface. Multiple electron diffraction patterns are acquired, and multiple spots observed in the multiple electron diffraction patterns are analyzed. For each sample, the interplanar spacing d is calculated, and the crystal structure of the metal oxide film is determined from the shape of the frequency distribution of the interplanar spacing d. This is a method for evaluating metal oxide films to assess their properties.

[0013] Another aspect of the present invention involves a metal oxide film with respect to multiple regions of the metal oxide film. An electron beam with a beam diameter of 0.3 nm to 10 nm is irradiated from a direction perpendicular to the surface. Multiple electron diffraction patterns are acquired, and multiple spots observed in the multiple electron diffraction patterns are analyzed. For each element, the angle θ from the reference line is calculated, and from the shape of the distribution of angle θ, the metal oxide film is... This is a method for evaluating metal oxide films, specifically for assessing their crystallinity. [Effects of the Invention]

[0014] According to one aspect of the present invention, a metal oxide film with high electrical properties can be provided. Or, reliability It can provide a metal oxide film with high performance, or a novel metal oxide film.

[0015] According to one aspect of the present invention, a semiconductor device with high electrical properties is provided, to which a metal oxide film is applied. Yes, it is possible. Alternatively, a metal oxide film can be applied to provide a highly reliable semiconductor device.

[0016] According to one aspect of the present invention, a novel method for analyzing, evaluating, or interpreting metal oxide films. We can provide this.

[0017] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0018] [Figure 1] Figure 1A is a schematic diagram of a metal oxide film. Figures 1B and 1C are schematic diagrams of electron diffraction patterns. Figures 1D and 1E are schematic diagrams of histograms. [Figure 2] Figures 2A and 2C are schematic diagrams of histograms. [Figure 3] Figures 3A and 3B are schematic diagrams of electron diffraction patterns. [Figure 4] Figure 4A shows the electron diffraction pattern. Figure 4B shows the histogram of the lattice plane spacing. [Figure 5] Figure 5A shows the electron diffraction pattern. Figure 5B shows the histogram of the lattice plane spacing. [Figure 6] Figure 6A shows the electron diffraction pattern. Figure 6B shows the histogram of the lattice plane spacing. [Figure 7] Figure 7A shows the electron diffraction pattern. Figure 7B shows the histogram of the lattice plane spacing. [Figure 8] Figure 8A shows the electron diffraction pattern. Figure 8B shows the histogram of the lattice plane spacing. [Figure 9] Figure 9A shows the electron diffraction pattern. Figure 9B shows the histogram of the lattice plane spacing. [Figure 10] Figure 10 shows the ratio of electron diffraction peak frequencies. [Figure 11] Figure 11A shows the change in grid plane spacing for each frame. Figure 11B shows the change in spot angle for each frame. [Figure 12] Figure 12A shows the change in grid plane spacing for each frame. Figure 12B shows the change in spot angle for each frame. [Figure 13] Figures 13A, 13B, and 13C show the XRD spectra. [Figure 14] Figures 14A, 14B, and 14C show the XRD spectra. [Figure 15] Figures 15A, 15B, and 15C show the XRD spectra. [Figure 16] Figures 16A, 16B, and 16C show the XRD spectra. [Figure 17] Figure 17 shows the angle of the peak of the X-ray diffraction. [Figure 18] Figures 18A to 18E show the computational model. [Figure 19] Figures 19A to 19E show the computational model. [Figure 20] Figure 20A shows the relationship between temperature and average energy. Figure 20B shows the relationship between temperature and the difference in average energy. [Figure 21] Figure 21 is a diagram illustrating the generation energy of defects. [Figure 22]Figure 22A illustrates the classification of IGZO crystal structures. Figure 22B illustrates the XRD spectrum of quartz glass. Figure 22C illustrates the XRD spectrum of crystalline IGZO. Figure 22D illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 23] Figure 23A is a top view of the semiconductor device. Figures 23B and 23C are cross-sectional views of the semiconductor device. [Figure 24] Figures 24A and 24B are cross-sectional views of a semiconductor device. [Figure 25] Figure 25A is a top view of the semiconductor device. Figures 25B and 25C are cross-sectional views of the semiconductor device. [Figure 26] Figure 26A is a top view of the semiconductor device. Figures 26B and 26C are cross-sectional views of the semiconductor device. [Figure 27] Figures 27A and 27B are cross-sectional views of a semiconductor device. [Figure 28] Figures 28A to 28C show examples of display device configurations. [Figure 29] Figure 29 shows an example of a cross-sectional configuration of a display device. [Figure 30] Figure 30 shows an example of a cross-sectional configuration of a display device. [Figure 31] Figure 31 shows an example of a cross-sectional configuration of a display device. [Figure 32] Figure 32A is a block diagram of the display device. Figures 32B and 32C are circuit diagrams of the display device. [Figure 33] Figures 33A, 33C, and 33D are circuit diagrams of the display device. Figure 33B is a timing chart. [Figure 34] Figures 34A and 34B show examples of the display module configuration. [Figure 35] Figures 35A to 35C show examples of electronic device configurations. [Figure 36] Figures 36A to 36E show examples of the configuration of electronic equipment. [Figure 37] Figures 37A to 37G show examples of the configuration of electronic equipment. [Figure 38] Figures 38A to 38D show examples of electronic device configurations. [Figure 39] Figures 39A to 39D show the Id-Vg characteristics of a transistor. [Figure 40] Figure 40 shows the results of the transistor reliability evaluation. [Figure 41] Figures 41A to 41D show the Id-Vg characteristics of a transistor. [Figure 42] Figure 42 shows the HAADEF-STEM image and EDX mapping image. [Figure 43] Figures 43A to 43D show the results of quantitative analysis of the composition of the metal oxide film. [Figure 44] Figures 44A to 44C are histograms of the composition of the metal oxide film. [Modes for carrying out the invention]

[0019] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0020] In the configuration of the invention described below, the same part or part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to the function of [this], the hatch pattern is the same, and sometimes no specific symbol is assigned.

[0021] In each figure described herein, the size, layer thickness, or area of ​​each component is not specified. This may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. I can't.

[0022] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0023] A transistor is a type of semiconductor device that amplifies current and voltage, and controls conductivity or non-conductivity. It is possible to realize controlled switching operations, etc. Transistors in this specification are , IGFET(Insulated Gate Field Effect Trans istors and thin-film transistors (TFTs) ) includes.

[0024] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. For example, the direction of the current may change during circuit operation. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably. It is assumed that this is possible.

[0025] Furthermore, in this specification, the terms "membrane" and "layer" are interchangeable. It is possible to change them. For example, the terms "conductive layer" and "insulating layer" can be replaced with "conductive film" or In some cases, the term "insulating film" can be used interchangeably.

[0026] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0027] Furthermore, in this specification, the substrate of the display panel may be, for example, FPC (Flexible Printed Circuit). (inted Circuit) or TCP (Tape Carrier Packa A connector such as a ge is attached, or the circuit board has a COG (Chip On A display panel module or display module is a device on which an IC is mounted using a glass or similar method. It may be called a display panel, or simply a display board.

[0028] In this specification, a touch panel, which is one form of a display device, displays images, etc. on its display surface. The display function detects when a finger, stylus, or other object touches, presses, or comes near the display surface. It has the function of a touch sensor that detects things like touching. Therefore, touch panel This is one form of an input / output device.

[0029] A touch panel is, for example, a display panel (or display device) with a touch sensor. It can also be called a display panel (or display device) with a touch function. It can also be configured to have a panel and a touch sensor panel. Alternatively, the display panel The configuration can also include a touch sensor functioning either internally or on its surface.

[0030] Furthermore, in this specification, etc., a touch panel circuit board with connectors and ICs mounted on it is considered to be a touch panel circuit board. It may be called a touch panel module, display module, or simply a touch panel. be.

[0031] (Embodiment 1) This embodiment relates to a metal oxide film according to one aspect of the present invention, and a method for evaluating the metal oxide film. I will explain.

[0032] [Metal oxide film] Figure 1A shows a schematic diagram of the metal oxide film 11 formed on the substrate 10.

[0033] A metal oxide film 11 in one aspect of the present invention is made of indium, M (where M is aluminum, gallium The oxide film contains yttrium or tin, and zinc. It has semiconductor properties. The metal oxide film 11 is formed by sputtering. It is preferable that the film is made of polycrystalline metal acid. In particular, as a sputtering target, It is preferable to use a monster target.

[0034] The metal oxide film 11 is made up of extremely minute particles that are randomly oriented (or have no orientation). It contains multiple crystalline regions (smaller than a few nanometers). Metal oxide film 1 having such crystalline properties 1 is extremely reliable compared to amorphous metal oxide films. Also, the metal oxide film 11 is The film may be a mixture of crystalline regions that do not have orientation and crystalline regions that do have orientation. .

[0035] A metal oxide film 11 according to one aspect of the present invention can be applied to a semiconductor device. For example, It can be applied to semiconductors in which the transistor channel is formed.

[0036] The metal oxide film 11 is particularly an oxide film containing indium, gallium, and zinc. It is preferable that the metal oxide film 11 contains the metal elements. Of these, it is preferable to use a material with a high indium content. In particular, a gallium content It is preferable to use a material with a higher indium content than the indium content. By applying the material film 11 to the semiconductor layer of the transistor, a transistor with high field-effect mobility can be created. It is possible to achieve this.

[0037] The crystallinity of the metal oxide film 11 can be controlled by varying the film formation conditions. For example, by increasing the proportion of oxygen gas in the deposition gas (also called the oxygen flow rate ratio) when depositing a film. This allows for the formation of a highly crystalline film. On the other hand, by reducing the proportion of oxygen gas in the film-forming gas... Alternatively, by using a film-forming gas that does not contain oxygen gas, a film with low crystallinity can be formed. This can be done. Alternatively, the higher the substrate temperature during film formation, the more crystalline the film can be. By lowering the substrate temperature or depositing the film without heating the substrate, the crystallinity is reduced. A film can be formed. The higher the crystallinity of the metal oxide film 11, the better the film's stability. On the other hand, the lower the crystallinity, the more the field-effect mobility is increased when applied to a transistor. It is possible.

[0038] [Electron diffraction] A metal oxide film 11 according to one aspect of the present invention is obtained by irradiating the film surface with an electron beam from a direction perpendicular to the film surface. The following characteristics appear in the electron diffraction pattern of this film.

[0039] One electron diffraction method is nanobeam electron diffraction, which focuses an electron beam and irradiates the sample with it. Using the NBED (Nano Beam Electron Diffraction) method It is preferable to do so. Alternatively, a parallel electron beam is used, and the irradiation area is narrowed to illuminate a minute region with the electron beam. Selected Area Electron Diffraction (SAED) The Diffraction method may also be used.

[0040] For a metal oxide film 11 having extremely minute crystalline regions, the beam diameter of the electron beam is set to an extremely small size. Under reduced conditions (e.g., 0.3 nm or more and 10 nm or 5 nm or less), electron beam rotation When the folding pattern is measured, multiple spots are found to be discretely distributed in the circumferential direction (also called the θ direction). The condition is confirmed. On the other hand, under conditions with a larger beam diameter (for example, 50 nm or more, or 100 nm), In electron diffraction patterns at wavelengths of 1 nm or more, a ring-shaped (also called annular) pattern can be observed. It is measured.

[0041] Figures 1B and 1C show an electric beam with a diameter of several nanometers, projected from a direction perpendicular to the surface of the metal oxide film 11. A schematic diagram of the electron diffraction pattern obtained by irradiating with a sub-beam is shown. The electron diffraction pattern shown in Figure 1B Turn 20a is the electron diffraction pattern in region 12a shown in Figure 1A, and is shown in Figure 1C. The electron diffraction pattern 20b shown is an electron diffraction pattern in region 12b that is different from region 12a. It's a pattern.

[0042] As shown in Figure 1B, the electron diffraction pattern 20a of the metal oxide film 11 shows that the sample is transmitted through it. The spot of the incident electron beam (direct spot 20) and the area near the direct spot 20 On the other side is the first spot 21, and further away from the direct spot 20 than the first spot 21 is A second spot, spot 22, is observed on the other side.

[0043] The first spot 21 is located at a radial distance r from the direct spot 20, and the distance r1 is equal to the distance r1. It is observed within the first ring-shaped region 31 located near it. Also, the second spot 22 This is when the radial distance r from the direct spot 20 is at or near distance r2. It is observed within the annular second region 32. The second region 32 is outside the first region 31. It is located at a distance of r2, that is, the distance r2 is greater than the distance r1.

[0044] Furthermore, as shown in Figure 1A, the electron beam irradiation position is parallel to the direction of the metal oxide film 11. When scanning and observing the electron diffraction pattern of a region different from region 12a (region 12b), As shown in Figure 1C, the first spot 21 is located at a different position within the first region 31, and the second spot 21 is located at a different position within the first region 31. A second spot 22 is observed at different locations within region 32.

[0045] From this, it can be seen that the metal oxide film 11 contains extremely minute crystalline regions. Furthermore, the positions of the first spot 21 and the second spot 22 differ in different regions. From this, it can be seen that the minute crystalline regions contained in the metal oxide film 11 do not have orientation.

[0046] In this way, the electron beam irradiation position is measured while scanning parallel to the direction of the metal oxide film 11. By doing so, multiple electron diffraction patterns can be observed. From each of the electron diffraction patterns, the first spot 21 and the second spot 22 The location and detection intensity information can be obtained. The location information for spot 22 includes the distance r from direct spot 20 and an arbitrarily determined value. There is an angle θ from the reference line. From the information obtained from multiple electron diffraction patterns, the distance A histogram (also called a distribution map or frequency distribution map) is obtained for the distance r, angle θ, detection intensity, etc. It is possible.

[0047] A method for evaluating metal oxide films according to one aspect of the present invention will be described. First, multiple metal oxide films For the region, a beam with a diameter of 0.3 nm or more is applied from a direction perpendicular to the surface of the metal oxide film. Multiple electron diffraction patterns are obtained by irradiating with an electron beam smaller than nm. Subsequently, acquisition For multiple spots observed in multiple electron diffraction patterns, the interplanar spacing d is calculated. Then, the crystallinity of the metal oxide film is evaluated from the shape of the frequency distribution of the calculated interplanar spacing d. It is possible.

[0048] Furthermore, for multiple spots observed in multiple electron diffraction patterns obtained in the same manner The angle θ from the reference line is calculated, and the crystallinity of the metal oxide film is determined from the shape of the distribution of this angle θ. It can be evaluated.

[0049] In addition, the brightness of multiple spots observed in multiple electron beam patterns acquired in the same manner (detection) The crystallinity of a metal oxide film can also be evaluated from information about its intensity (for example, the shape of its distribution). .

[0050] A larger number of electron diffraction patterns obtained is preferable because it increases the accuracy of the information. For example, the electron diffraction pattern has 50 or more, preferably 100 or more, more preferably 1000. It is preferable to obtain the above. There is no particular upper limit, but it should be 10,000 or less, or 5,000 or less. But we can still obtain information with sufficient accuracy.

[0051] The following provides more specific examples.

[0052] Figure 1D shows the number (frequency) of spots observed in the electron diffraction pattern of the metal oxide film 11. Here is an example of a histogram 30r showing the relationship between the distance r from the direct spot 20 and the data point. As shown in Figure 1D, the histogram 30r shows that the peaks are located within the first region 31. The first spot 21 has a peak, and the second has a peak apex within the second region 32. Each of the 22 spots has its own peak.

[0053] In electron diffraction, the distance r from the center of the direct spot to the target spot is used. Then, according to the following formula (1), the value of the surface spacing d corresponding to the spot (hereinafter referred to as the d value) It is possible to calculate (u).

[0054] [Mathematics 1] d = Lλ / r····(1) In equation (1), L is the camera distance and λ is the wavelength of the electron beam.

[0055] The histogram 30 created using the d-values ​​calculated in this way is shown in Figure 1E.

[0056] The histogram of d values ​​obtained from the electron diffraction pattern of a metal oxide film 11 according to one embodiment of the present invention As shown in Figure 1E, Lamb has two peaks (from the side with the larger d value, the first peak 41, It has a second peak (42).

[0057] As shown in Figure 1E, the metal oxide film 11 has a frequency distribution shape for d values ​​of 0.25 The peak of the first peak 41 is located in the range of 0.30 nm to 0.15 nm, and the d value is 0.15 nm. It is preferable that the film has a second peak 42 located in the range of m to 0.20 nm. It's nice.

[0058] Multiple first spots 21 constituting the first peak 41 are contained in the metal oxide film 11 The spots include scattered electrons originating from the medium-range ordered structure of tiny crystalline clusters. The first spot 21 is due to diffraction with different interplanar spacings in the crystalline cluster. Because it includes scattered electrons and scattered electrons from crystalline clusters with different structures, the scattering angle is important. This causes stuttering, and as a result, the width of the region where the d value of the first spot 21 can be observed becomes larger. Therefore, the full width at half maximum of the first peak 41 is larger than the full width at half maximum of the second peak 42. There is a tendency for this to happen.

[0059] Furthermore, the first spot 21 is rotated by minute crystalline regions contained in the metal oxide film 11. It may include spots caused by diffracted electrons.

[0060] Multiple second spots 22 constituting the second peak 42 are contained within the metal oxide film 11. These are spots caused by diffracted electrons diffracted by tiny crystalline regions. For example, the crystalline region However, if it has a crystal structure similar to that of an InGaZnO4 crystal, the second spot 22 is It is presumed that this is due to diffracted electrons from the (110) plane and equivalent crystal planes.

[0061] The shape and height of the first peak 41 and the second peak 42 in histogram 30 are related to metal. The shape reflects the crystallinity of the oxide film 11. Therefore, the frequency distribution of the histogram 30 is... The shape of the metal oxide film 11 makes it possible to evaluate its crystallinity.

[0062] As an example, Figures 2A, 2B, and 2C show metal oxide films 11 having different crystalline properties. Histogram 30 is shown for each.

[0063] The histogram 30a shown in Figure 2A is an example of a metal oxide film 11 with low crystallinity. Figure 2 In A, the peak value P1 is the value at the top of the first peak 41, and the peak value is the value at the top of the second peak 42. The peak value P2 is shown as a value. Note that the height of the peak value P1 and the peak value P2 are also shown. The position changes according to the division width (class width) of the data in histogram 30a, therefore The class width can be set to an appropriate width. Typically, the number of classes is approximately the square root of the total number of data points. It is preferable to do so.

[0064] In histogram 30a, the peak value P1 of the first peak 41 is lower than the peak value P1 of the second peak 42. The peak value P2 is lower. Furthermore, in the metal oxide film 11 with even lower crystallinity, In some cases, the second peak, 42, may hardly be observed.

[0065] The histogram 30b shown in Figure 2B is an example of a metal oxide film 11 with higher crystallinity than that shown in Figure 2A. Therefore, as the crystallinity improves, the number of second spots 22 originating from diffracted electrons increases. As a result, the peak value P2 of the second peak 42 becomes higher than that in Figure 2A. On the other hand, metal oxidation The proportion of low-order regions in the material film 11 decreases, resulting in a decrease in the number of first spots 21. The peak value P1 of the first peak 41 is slightly lower. As a result, compared to Figure 2A, The difference between the peak value P1 of the first peak 41 and the peak value P2 of the second peak 42 becomes smaller.

[0066] The histogram 30c shown in Figure 2C represents a metal oxide film with even higher crystallinity than that shown in Figure 2B. This is an example of 1. As the crystallinity improves, the number of second spots 22 increases further, and As the number of spots 21 decreases, the peak value P1 of the first peak 41 and the second The relative magnitude of peak 42 and peak value P2 is reversed, with peak value P2 being larger than peak value P1. It's getting better.

[0067] The above is an example of a histogram. According to the evaluation method shown here, the degree of the histogram The shape of the number distribution makes it possible to evaluate the crystallinity of the metal oxide film 11. The shape of the frequency distribution of the histogram was compared for the metal oxide film 11 deposited under the specified deposition conditions. This allows us to compare their crystallinity.

[0068] The metal oxide film 11 is a film in which regions with low crystallinity and regions with high crystallinity are mixed. Alternatively, an electron beam can be applied to such a metal oxide film 11 parallel to the film surface direction, as described above. When the electron diffraction pattern is measured while scanning, electrons originating from regions with low crystallinity are detected. The electron diffraction pattern originating from the highly crystalline region appears alternately. There are cases where this occurs.

[0069] Figure 3A shows the electron diffraction pattern when measuring the region of the metal oxide film 11 with low crystallinity. An example of n20c is shown.

[0070] In the electron diffraction pattern 20c, multiple first spots 21 were observed within the first region 31. The first spot 21 is located in the radial direction (specifically, the direct spot 2 There is variation in the distance from 0 to the first spot 21. Also, although not shown here, Furthermore, there is variability in the detection intensity of the first spot 21.

[0071] Furthermore, in the electron diffraction pattern 20c, a second spot 22 was observed within the second region 32. The second spot 22 has radial variation compared to the first spot 21. It is small. Also, because it is a region with low crystallinity, in many cases the observation of the second spot 22 The number of detections will be fewer than that of the first spot 21. The detection intensity will also be relatively lower. There are cases where this is the case.

[0072] Figure 3B shows the electron diffraction pattern when measuring the highly crystalline region of the metal oxide film 11. This shows an example of n20d.

[0073] In the electron diffraction pattern 20d, six first spots 21 are observed within the first region 31. It is being measured. Centered around direct spot 20, two adjacent first spots 2 The angle θ1 formed by 1 is approximately 60 degrees. That is, the six first spots 21 are direct It is observed that the 6-fold symmetry is satisfied around spot 20. Also, the first spot The radial position and detection intensity of pot 21 are compared with the electron diffraction pattern 20c described above. This reduces the variability.

[0074] Furthermore, in the electron diffraction pattern 20d, there are six second spots 2 within the second region 32. 2 has been observed. The second spot 22, like the first spot 21, exhibits six-fold symmetry. Observations satisfy this condition, and the angle θ2 between two adjacent second spots 22 is approximately 60 degrees. That is the case.

[0075] Also, centered around Direct Spot 20, there is the first Spot 21 and the second Spot The angle θ3 formed by 22 is approximately 30 degrees. From this, the crystallinity of the metal oxide film 11 The high-density region exhibits six-fold symmetry with respect to an axis perpendicular to the film surface.

[0076] The crystalline regions contained in the metal oxide film 11 have a crystalline structure similar to that of an InGaZn2O5 crystal. If present, the first spot 21 has diffraction due to the (100) plane and equivalent crystal planes. It is presumed to originate from the child. Furthermore, the crystalline region has a crystalline structure similar to that of InGaZnO4 crystals. If present, the (100) plane satisfies the extinction rule, and therefore, in principle, diffracted electrons are not observed. However, even if it has a crystal structure similar to that of an InGaZnO4 crystal, The entire crystal region is not a perfect crystal, but rather an imperfect state containing lattice distortion, which causes it to disappear. When the rule is broken, diffracted electrons from the (100) plane, which should not be observed, are sometimes observed. ru.

[0077] Furthermore, if the crystal structure of the crystalline region contained in the metal oxide film 11 is classified as a hexagonal system... The electron diffraction pattern 20d obtained by irradiating the film surface perpendicularly with an electron beam was obtained six times. Because it has symmetry, the crystal orientation of the crystal region contained in the metal oxide film 11 is the c axis. It can be inferred that the film is oriented in the direction of film thickness.

[0078] [Method for forming metal oxide films] The following describes a method for forming a metal oxide film according to one aspect of the present invention.

[0079] A metal oxide film according to one aspect of the present invention is formed by heating the substrate or by not heating the substrate. It can be formed by the sputtering method.

[0080] When forming a film by heating the substrate, the substrate temperature should preferably be between room temperature and 250°C. The temperature should be between room temperature and 200°C, more preferably between room temperature and 140°C. For example, a substrate Maintaining a temperature between room temperature and 140°C is preferable as it increases productivity.

[0081] When depositing a film without heating the substrate, the substrate temperature is initially at or near room temperature. This is the temperature. Furthermore, the energy imparted to the substrate by sputtering particles during film formation is also a factor. In some cases, the substrate may be heated. Also, when a metal oxide film is deposited in an apparatus, the substrate is heated. Because it does not require a specific mechanism, the device can be simplified and costs can be reduced.

[0082] During film formation, an oxygen-containing atmosphere may be used. For example, the film to be deposited into the deposition chamber of the film deposition apparatus. The ratio of the oxygen flow rate to the total gas flow rate (hereinafter referred to as the oxygen flow rate ratio) should be 0% or more and 10% or more. An appropriate value can be set within the range of 0% or less. By adjusting the oxygen flow rate, the film deposition process can be controlled. The crystallinity of the metal oxide film can be controlled. Specifically, the higher the oxygen flow rate ratio, the better. A highly crystalline metal oxide film can be formed, and the lower the oxygen flow rate ratio, the lower the crystallinity. It can form a metal oxide film. Other gases besides oxygen included in the film-forming gas include, for example, Noble gases such as argon can be used. By forming a film in an oxygen-containing atmosphere... This can reduce oxygen vacancies in the metal oxide film. Also, in an oxygen-free atmosphere and You may do so.

[0083] Examples of oxide targets that can be used for depositing metal oxide films include In- M-Zn oxides (where M is Al, Ga, Y, or Sn) can be used. It is preferable to use an In-Ga-Zn oxide.

[0084] Furthermore, as oxide targets that can be used for depositing metal oxide films, In-M type Oxides and In-Zn oxides can also be used. In particular, In-Ga oxides are oxygen This is preferable because it is less likely to form defects.

[0085] Here, the metal oxide contained in the oxide target is preferably one with a high proportion of In. For example, if the sum of the compositions of In, M, and Zn is 1 (100%), Metal oxide in which the proportion of In is 33% or more and 60% or less, preferably 40% or more and 50% or less. It is preferable to use a material target. Typically, In:Ga:Zn=1:1:1 and The oxides in the vicinity, In:Ga:Zn=4:2:3 and the oxides in the vicinity, In:Ga: Zn=4:2:4.1 and its vicinity oxides, In:Ga:Zn=5:1:3 and its vicinity Nearby oxides, In:Ga:Zn=5:3:4 and its neighboring oxides, or In:Ga Zn = 10:1:3 and similar oxides can be used.

[0086] This results in a metal oxide film with a high In content. This can be done. Here, the composition of the deposited metal oxide film and the oxide target are not necessarily the same. This may not always be the case. In particular, the deposited metal oxide film is Z compared to the oxide target. The content of n tends to decrease easily.

[0087] As described above, a metal oxide film can be formed.

[0088] The above is not the only method for forming metal oxide films. Other film formation methods include: Plasma chemical vapor deposition (PECVD), thermal CVD (Chemical Vapor Deposition) eposition) method, ALD (Atomic Layer Deposition) method Methods include vacuum deposition, pulsed laser deposition (PLD), and liquid phase methods (spin coating, spray coating). Examples of thermal CVD methods include MOCVD (Metal Organic Chemicals). Examples include the nic Chemical Vapor Deposition method.

[0089] The above is a description of the method for forming metal oxide films.

[0090] [Examples of evaluation of metal oxide films] In the following, a metal oxide film according to one embodiment of the present invention will be evaluated using the evaluation method exemplified above. I will now explain the results of the analysis.

[0091] For metal oxide films produced using different methods, nanobeam electron diffraction analysis and X-ray diffraction (X) analysis were performed. Crystallinity was evaluated by performing RD (X-Ray Diffraction) analysis. This includes a sample in which a metal oxide film with a thickness of 40 nm is formed on a silicon wafer. Samples A1 to A6 were used. In-Ga-Zn oxide was used as the metal oxide film. The film deposition conditions for the metal oxide film were varied between samples.

[0092] [Sample preparation] Metal oxide film deposition is performed using an In-Ga-Zn oxide target (In:Ga:Zn=4: It was formed by sputtering using a 2:4.1 [atomic ratio]. Note that In:Ga A sample film structure formed using a target with a composition of Zn=4:2:4.1 [atomic ratio] The composition is approximately In:Ga:Zn = 4:2:3 [atomic ratio].

[0093] The film deposition conditions for samples A1 to A6 are shown in Table 1. In Table 1, the substrate temperature during metal oxide film formation is Tsub, and the oxygen flow rate ratio is O2. The formula is represented as / (Ar+O2), pressure as "Pressure," and power as "Power."

[0094] [Table 1]

[0095] Sample A1 uses room temperature (hereinafter also referred to as RT) as the substrate temperature during metal oxide film deposition. (This was done.) A mixed gas of oxygen and argon was used as the film-forming gas, and the oxygen flow rate ratio was set to 1. The value was set to 0%. The pressure during film deposition was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0096] For sample A2, the substrate temperature during metal oxide film deposition was set to room temperature (RT). A mixture of oxygen and argon gas was used as the membrane gas, with an oxygen flow rate ratio of 30%. The membrane pressure was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0097] For sample A3, the substrate temperature during metal oxide film deposition was set to room temperature (RT). A mixed gas of oxygen and argon was used as the membrane gas, with an oxygen flow rate ratio of 40%. The membrane pressure was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0098] For sample A4, the substrate temperature during metal oxide film deposition was set to room temperature (RT). A mixture of oxygen and argon gas was used as the membrane gas, with an oxygen flow rate ratio of 50%. The membrane pressure was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0099] For sample A5, the substrate temperature during metal oxide film deposition was set to 100°C. A mixed gas of oxygen and argon was used as the buffer, with an oxygen flow rate ratio of 10%. The pressure was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0100] For sample A6, the substrate temperature during metal oxide film deposition was set to 100°C. A mixed gas of oxygen and argon was used as the buffer, with an oxygen flow rate ratio of 30%. The pressure was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0101] [Nanobeam electron diffraction] Samples A1 to A6 were placed flat on the surface to which the metal oxide film was to be formed. The sample was thinned in the longitudinal direction to a thickness of approximately 20 nm to 30 nm. The thinned sample was then treated with a metal acid. This includes the surface of the metal oxide film when an oxide film is formed.

[0102] Next, an electron beam with an accelerating voltage of 200kV (wavelength: approximately 2.51pm) and a beam diameter of 1nm is used. Multiple electron diffraction patterns were obtained by incidenting electron beams from a direction perpendicular to the surface on which the metal oxide film was formed. By moving the electron beam irradiation site and capturing the electron diffraction pattern in video, multiple images can be obtained. The electron diffraction pattern was obtained. The video shows the electron beam irradiation area at approximately 0.08 n per frame. Images were captured while moving the sample by m to 0.10 nm, yielding approximately 3700 frames for each sample. Electron diffraction patterns are captured using a 200x200 pixel imaging plate. The magnitude (q) of the scattering vector for one pixel is 0.082426 / nm / pixel. It was l.

[0103] Next, we performed a spot analysis on each frame of the video.

[0104] The nanobeam electron diffraction results for sample A1 are shown in Figures 4A and 4B. The nanobeam electron diffraction results for sample A2 are shown in Figures 5A and 5B. The nanobeam electron diffraction results are shown in Figures 6A and 6B. The nanobeam electron diffraction results for sample A4 are shown. The diffraction results are shown in Figures 7A and 7B. The nanobeam electron diffraction results for sample A5 are shown below. The nanobeam electron diffraction results for sample A6 are shown in Figures 8A and 8B. Shown in B.

[0105] Figures 4A, 5A, 6A, 7A, 8A, and 9A are shown in the video of each sample. The electron diffraction pattern of the final frame is shown. In each figure, the upper horizontal axis and the right side On the vertical axis, the coordinates of the pixels of the imaging plate (denoted as pixels) are shown, with the bottom left as the reference point. This is shown. Furthermore, the horizontal axis at the bottom and the vertical axis on the left show the magnitude of the scattering vector (q[ / nm). ]) is shown. Also, each point shown in each figure represents the spot intensity (detection intensity (Intens Higher intensity indicates darker colors, while lower intensity indicates lighter colors.

[0106] Spots observed in the region between 30 and 90 pixels from the center of the electron diffraction pattern. For (the first spot), the position and intensity values ​​of each spot were obtained. Figure 4A. In Figures 5A, 6A, 7A, 8A, and 9A, the region is 30 pixels from the center, and from the center The area of ​​90 pixels is shown by a solid circle. From the center of the electron diffraction pattern, within 30 pixels... In the region below the top 90 pixels, the grid plane spacing (d) is between 0.13348 nm and 0.4044 nm. This corresponds to the following. Also, the spot intensity (0 to 255) is 64 or higher, and the area is Only spots with two or more pixels were included in the evaluation. (Figures 4A, 5A, 6A, 7A, 8) In Figures A and 9A, the center of the electron diffraction pattern and each spot are connected by a solid line. The center of the electron diffraction pattern is the spot of the incident electron beam that passed through the sample without diffracting (d). It was centered around an electrifying spot.

[0107] Figures 4B, 5B, 6B, 7B, 8B, and 9B were obtained for each sample, respectively. This is a histogram (frequency distribution) of the grid plane spacing (d) for all frames of the video. In each figure, the horizontal axis shows the lattice plane spacing (d [nm]), and the vertical axis shows the frequency (Frequenc This shows y[count]). Note that in this embodiment, the data interval (class) of the histogram is shown. The width was set to a lattice plane spacing (d) of 0.002 nm.

[0108] As shown in Figures 4B, 5B, 6B, 7B, 8B, and 9B, under all conditions Therefore, the vertex of the lattice plane spacing (d) is in the range of 0.25 nm to 0.30 nm. The first peak and the peak having a peak in the range of 0.15 nm to 0.20 nm. It has a second peak (a "k").

[0109] Here, for samples A1 to A4, the peak of the first peak is The ratio of the value at the peak of the second peak (peak value P2) to the value (peak value P1) (P2 / P 1) is shown in Figure 10. In Figure 10, the horizontal axis is the oxygen flow rate ratio (O) during metal oxide film formation. The graph shows 2 / (Ar+O2)[%]), with the vertical axis representing the ratio of peak value P2 to peak value P1. The P2 / P1 values ​​are shown. Note that in Figure 10, the frequency at d=0.278nm is shown as the peak value P1. The frequency is shown using the peak value P2 at d=0.168nm.

[0110] Comparing samples A1 to A4, the higher the oxygen flow rate ratio, the higher the oxygen flow rate ratio. A tendency for the peak of 2 to increase is observed. Also, sample A1 to sample A3 Then, the value at the peak of the first peak (peak value P1) is equal to the value at the peak of the second peak (peak value P 2) is higher. On the other hand, in sample A4, which has the highest oxygen flow rate ratio, these The relative magnitudes are reversed, and the value at the peak of the second peak (peak value P2) is equal to the value at the peak of the first peak. The value (peak value P1) is exceeded, and the P2 / P1 value shown in Figure 10 is also greater than 1. It is.

[0111] Similarly, comparing sample A5 and sample A6, the lower oxygen flow rate ratio In sample A5, the value at the peak of the first peak is greater than the value at the peak of the second peak. In contrast to the high oxygen flow rate, in sample A6, under conditions of a high oxygen flow rate ratio, the peak of the second peak is The value exceeds the peak value of the first peak. This suggests that the higher the oxygen flow rate ratio, the greater the result. It can be confirmed that the crystallinity has improved.

[0112] Furthermore, sample A1 and sample A5, which were deposited under the same oxygen flow rate conditions, were compared. In comparison, sample A5 has a larger second peak. Also, sample A2 and The same applies to sample A6. This suggests that under the same oxygen flow rate conditions... However, it can be confirmed that the higher the substrate temperature during film formation, the better the crystallinity.

[0113] In one aspect of the present invention, the evaluation method involves not only a histogram, but also the position of the detected spots. Information regarding the crystallinity of the metal oxide film can also be obtained from frame-by-frame data on position and brightness. It is possible.

[0114] Figure 11A shows the change in the grid plane spacing (d) for each frame of sample A1. In A, the horizontal axis shows the frame number (Frame No.), and the vertical axis shows the grid plane spacing (d The [nm] indicates the spot intensity. Also, each point shown in Figure 11A represents the spot intensity. The higher the intensity, the darker the color; the lower the intensity, the lighter the color.

[0115] Figure 1 also shows the change in the spot angle for each frame of sample A1. As shown in 1B. In Figure 11B, the horizontal axis shows the frame number, and the vertical axis shows the vertical axis. The axis indicates the angle (Angle[°]) of the spot. Also, each point shown in Figure 11B is a spot The higher the intensity, the darker the color; the lower the intensity, the lighter the color. ru.

[0116] As shown in FIG. 11A, in sample A1, the first spot is observed in the region where the lattice plane spacing (d) is from 0.25 nm to 0.35 nm, and the second spot is observed in the region where the lattice plane spacing (d) is from 0.15 nm to 0.20 nm. As shown in FIG. 11A, the first spot is continuously observed regardless of the measurement position, while the second spot is discretely observed. The position where the second spot is observed is inferred to be a region with relatively high crystallinity compared to other positions. From this, it can be confirmed that the metal oxide film does not have uniform crystallinity, but rather a mixture of regions with relatively high crystallinity and regions with relatively low crystallinity. As shown in FIG. 11B, in sample A1, it can be seen that there is almost no angular dependence of the spots. From this, it is inferred that most of the crystal regions contained in sample A1 are randomly oriented without orientation. Subsequently, FIG. 12A shows the change in the lattice plane spacing (d) for each frame of sample A6, and FIG. 12B shows the change in the angle (Angle) of the spots for each frame. In FIG. 12A, since the second spot observed in the region where the lattice plane spacing (d) is from 0.15 nm to 0.20 nm is continuously observed regardless of the position (frame), it can be confirmed that sample A6 has extremely high crystallinity compared to sample A1. Also, focusing on the first spot observed in the region where the lattice plane spacing (d) is from 0.25 nm to 0.35 nm, there are regions with small variations (for example, in the range from frame 0 to frame 200), and

[0117]

[0118]

[0119]

[0120] Areas with significant stuttering (for example, the range from 300 to 500 frames) appear alternately. It can be confirmed that this is the case. Also, in areas where the variation of the first spot is small, the second spot The variation in size also tends to be small. This suggests that large sizes of bonds are present in the metal oxide film. It is inferred that a crystalline region exists.

[0120] Furthermore, according to Figure 12B, in the region where the variation of the first spot is small in Figure 12A, It can be confirmed that spots are observed discretely at intervals of approximately 30 degrees. Also, look at Figure 9A. Then, the six first spots and the six second spots outside of them form regular hexagons. It was observed to be located at the vertices of the shape and showed an electron diffraction pattern with six-fold symmetry. This shows that the variation of the first spot in Figures 12A and 12B In regions where the value is small, it is inferred that a single crystal region with six-fold symmetry has been observed. ru.

[0121] Thus, according to one embodiment of the present invention, the crystallinity of a metal oxide film can be evaluated with high accuracy. The value can be compared.

[0122] [X-ray diffraction] Next, X-ray diffraction (XRD) analysis was performed on samples A1 through A6. .

[0123] XRD analysis is a type of out-of-plane method called GIXRD (Grazing - The Incidence XRD method was used. The GIXRD method is a thin-film method or Seema Also known as the nn-Bohlin method. The GIXRD method fixes the incident angle of X-rays to a very shallow angle. This method involves changing the angle of a detector positioned opposite the X-ray source to measure the X-ray diffraction intensity. Yes. In this embodiment, the incident angle was set to 0.70 degrees. Also, the X-ray source had a wavelength of 0.15 Using a 418nm CuKα line, the scanning range is 2θ = 15 to 70 degrees, and the step size is 0. It was set to 0.1 degrees.

[0124] The XRD measurement results for samples A1 to A3 are shown in Figures 13A to 13. Figure C shows the XRD measurement results for samples A4 to A6. A to Figure 14C are shown.

[0125] In Figures 13A to 14C, the horizontal axis represents 2θ, and the vertical axis represents intensity. ) is shown. Also, in Figures 13A to 14C, 2θ = 33 degrees (deg.) is shown as an auxiliary line. Note) and 2θ = 55 degrees are shown with a dashed line.

[0126] As shown in Figures 13A to 14C, in all samples, around 2θ = 33 degrees, A diffraction peak was observed around 2θ = 55 degrees. The diffraction peak around 2θ = 33 degrees was observed on the lattice plane. The interval (d) corresponds to approximately 0.27 nm and corresponds to the first peak in the electron diffraction described above. It is thought that this is the case. Furthermore, a peak has also been observed around 2θ = 55 degrees. The sharp peak observed around 51 degrees is due to diffraction from the silicon wafer substrate. This is the resulting peak.

[0127] For the diffraction peaks observed around 2θ=33 degrees in each sample, the Lorentz function fit was applied. The angle (2θ) of the diffraction peak peak was calculated using a Lorentz function filter. The least squares method was used for the setting. Enlarged views of Figures 13A, 13B, and 13C are shown in Figure 1. Figures 5A, 15B, and 15C are shown. Enlarged views of Figures 14A, 14B, and 14C are also shown in Figure 5A. Shown in FIGS. 16A, 16B, and 16C. Also, the angle (2 θ) of the peak of the diffraction peak in each sample is shown in FIG. 17. In FIG. 17, the oxygen flow rate ratio (O 2 / (Ar + O2) [%]) during the formation of the metal oxide film is shown on the horizontal axis, and the angle (2θ [deg.] ) of the peak of the diffraction peak is shown on the vertical axis. Also, in FIG. 17, a sample with a substrate temperature of room temperature (denoted as Tsub = RT) is plotted with a circle mark, and a sample with a substrate temperature of 100 ° C (denoted as Tsub = 100 ° C) is plotted with a triangle mark, respectively .

[0128] As shown in FIGS. 15A to 16C and FIG. 17, when the oxygen flow rate ratio during the formation of the metal oxide film increases, the 2θ of the peak of the diffraction peak tends to decrease. Also, when the substrate temperature during the formation of the metal oxide film increases, the​​​​​​​​​​​​​​​​​​​​​​​​​​​Furthermore, in order to explain the stability of the nc film, two computational models (computational model 1A and computation) are used. Model 2A) was prepared. Calculation model 1A is a calculation model that has a crystalline region, nc This is a computational model that mimics a film. Furthermore, computational model 2A is a computational model that does not have a crystalline region. This is a computational model that mimics an amorphous film. The crystalline region will be discussed later.

[0132] [How to create calculation model 1A] The following section describes how to create calculation model 1A.

[0133] First, let's look at In-Ga-Zn acid with an atomic ratio of In:Ga:Zn:O=1:1:1:4. From the crystalline structure of the ion, a hexagonal prismatic region (called the crystalline region) is cut out, and this crystalline region is It is placed at the center of the computational model. The number of atoms in this crystal region is 87. From this point forward, atoms located in the crystalline region refer to the 87 atoms arranged within the crystalline region. Yes. Also, one or more of the atoms located in the crystal region will be determined by the calculations performed later. In some cases, it may move to the outer edge of the crystal region.

[0134] Next, in the outer periphery of the above crystal region, multiple In atoms, multiple Ga atoms, multiple Zn atoms, and multiple oxygen atoms are randomly arranged. Note that the number of in atoms placed on the outer periphery The number of Ga atoms, the number of Zn atoms, and the number of O atoms, as well as the size of the outer periphery, The atomic ratio of atoms arranged in the above crystal region and its outer periphery is In:Ga:Zn:O=1: The ratio becomes 1:1:4, and the density of the computational model is 6.1 g / cm³. 3 Adjust it so that it becomes It is included. Furthermore, the number of atoms placed on the outer periphery is 291. Therefore, it is included in the calculation model. The number of atoms present is 378. In addition, any one of the atoms arranged on the outer periphery or Multiple elements may move into the crystalline region as a result of subsequent calculations.

[0135] Next, the coordinates of the atoms located in the above crystal region are fixed, and a plan for melting the outer periphery is calculated. Perform the calculation. Specifically, set the temperature to 3500K, the time step size to 1fs, and the number of steps to 6000. Set to the number of times. From here on, calculations will be performed by setting the temperature, time step size, and number of steps. This is sometimes called first-principles molecular dynamics calculation, or quantum molecular dynamics calculation.

[0136] The calculations were performed using the first-principles calculation software VASP (The Vienna Academy). The tio simulation package was used. The calculation conditions are shown in Table 2. In the above first-principles molecular dynamics calculation, the calculation conditions are set to Condition 1 shown in Table 2. Set it.

[0137] [Table 2]

[0138] The pseudopotential of the electronic state is Projector Augmented Wave(P The potential generated by the AW method is given the functional GGA / PBE (General ized-Gradient-Approximation / Perdew-Burke -Ernzerhof) was used.

[0139] In this embodiment, first-principles molecular dynamics calculations and the calculation model described later are performed. In calculations to optimize the structure of the material (also called optimization calculations), In, Ga, and In the Zn potential, the 3d or 4d states are not considered as part of the valence band. Furthermore, the lattice vectors (axis lengths and angles between axes) of the computational model are fixed. In other words, first-principles molecular dynamics calculations assume that the number of particles (N), volume (V), and temperature (T) are constant. The simulation is performed under specific conditions (NVT ensemble). Furthermore, in first-principles molecular dynamics calculations, temperature control is applied. A nose-hoover thermostat is used as a method for controlling this. .

[0140] Next, calculations are performed to cool the molten outer periphery to a temperature of 500K. Note that the cooling rate The temperature will be set to 500 K / ps. Specifically, first, the coordinates of the atoms located in the crystal region will be fixed. Condition 1, with a time step size of 1 fs, 1000 steps, and other calculation conditions shown in Table 2. Set to this. Then, for the calculation model obtained from the calculation for melting the outer perimeter, First-principles molecular dynamics calculations are performed with the temperature set to 3500K. Next, the results obtained after the calculations are... For the calculation model, first-principles molecular dynamics calculations are performed with the temperature set to 3000K. Next Then, for the calculation model obtained after the calculation, the temperature is set to 2500K and the first-principles calculation is performed. Perform a dynamics calculation. Next, apply the temperature to the calculation model obtained after the calculation, set to 2000. Set to K and perform first-principles molecular dynamics calculations. Next, the computational model obtained after the calculation is used. In contrast, first-principles molecular dynamics calculations are performed with the temperature set to 1500K. Next, after the calculation... For the computational model obtained, first-principles molecular dynamics calculations were performed with the temperature set to 1000K. Next, for the calculation model obtained after the calculation, set the temperature to 500K and perform the first A molecular dynamics calculation is performed. This completes the calculation for cooling the outer periphery.

[0141] Next, calculations are performed to relax the structure of the cooled outer periphery. Specifically, the outer periphery is cooled For the computational model obtained from the calculations to achieve this, the coordinates of atoms located in the crystal region are fixed. The temperature is set to 300K, the time step size to 1fs, the number of steps to 5000, and other calculation conditions are as follows: First-principles molecular dynamics calculations are performed under the conditions shown in Table 2, Condition 1.

[0142] Next, the calculation conditions were set to condition 2 shown in Table 2, and the calculation to relax the structure of the outer perimeter was obtained. For the computational model, the coordinates of atoms located in the crystal region are fixed, and the structure of the outer periphery is minimized. Calculations are performed to optimize the model. Subsequently, the outer perimeter is applied to the calculation model obtained after these calculations. By fixing the coordinates of the atom located at and the coordinates of a single In atom located at the center of the crystal region, Calculations are performed to optimize the structure of the crystal region. Subsequently, the calculation model obtained after these calculations... For the given atom, the coordinates are fixed, and the entire calculation model (crystal region and outer periphery) is analyzed. Calculations are performed to optimize the structure of ). After that, the calculation conditions are set to condition 3 shown in Table 2. Furthermore, for the calculation model obtained after the calculation, the coordinates of only the In atom are fixed, and the calculation model Perform calculations to optimize the overall structure of Dell.

[0143] Using the method described above, calculation model 1A is created. The created calculation model 1A is shown in Figure 18A. This is shown in Figure 18D. Figures 18A and 18C show the overall structure of computational model 1A. Furthermore, Figures 18B and 18D show the crystal region of computational model 1A. Figures 18A and 18B are side views of the hexagonal prism-shaped region, and Figures 18C and 18B are side views. Figure 18D is a view of the hexagonal prism-shaped region from above.

[0144] [Method for creating calculation model 2A] The following describes how to create calculation model 2A. The calculations for this purpose use the calculation conditions shown in Table 2.

[0145] First, we will perform calculations to melt the crystalline region and outer periphery of computational model 1A. Specifically... Specifically, we prepared calculation model 1A, without fixing the coordinates of all atoms, and set the temperature to 3500K and time. Set the step size to 1 fs, the number of steps to 6000, and the other calculation conditions to Condition 1 shown in Table 2. Then, first-principles molecular dynamics calculations are performed.

[0146] Next, calculations are performed to cool the entire melted computational model down to a temperature of 500K. The cooling rate will be 500 K / ps. Specifically, first, without fixing the coordinates of all atoms, Set the step size to 1 fs, the number of steps to 1000, and the other calculation conditions to Condition 1 shown in Table 2. Determine. Then, the computational model obtained from the calculations for melting the crystalline region and the outer periphery is used. Next, the temperature is set to 3500K and first-principles molecular dynamics calculations are performed. Then, after the calculations are performed... First-principles molecular dynamics calculations were performed on the resulting computational model with the temperature set to 3000K. Next, for the calculation model obtained after the calculation, set the temperature to 2500K and perform the first We perform a molecular dynamics calculation in principle. Next, we apply the temperature to the calculation model obtained after the calculation. Set to 000K and perform first-principles molecular dynamics calculations. Next, the calculation obtained after the calculation is... For Dell, first-principles molecular dynamics calculations are performed with the temperature set to 1500K. Next, the For the computational model obtained after the calculation, first-principles molecular dynamics are performed by setting the temperature to 1000K. Perform the calculation. Next, set the temperature to 500K for the calculation model obtained after the calculation. First-principles molecular dynamics calculations are then performed. This completes the calculations required to cool the entire computational model. Completed.

[0147] Next, we perform calculations to relax the overall structure of the cooled computational model. Specifically, the calculations For the computational model obtained from calculations to cool the entire model, the coordinates of all atoms are fixed. Without specifying the temperature, set the time step size to 300K, the number of steps to 5000, and other calculation conditions. The items are set to condition 1 as shown in Table 2, and first-principles molecular dynamics calculations are performed.

[0148] Next, the calculation conditions are set to condition 2 as shown in Table 2, and the calculation is performed to relax the entire calculation model. For the resulting computational model, the overall structure of the computational model is optimized without fixing the coordinates of all atoms. Perform the calculations to convert it. Then, set the calculation conditions to condition 3 shown in Table 2, and after the calculation... For the resulting computational model, the overall structure of the computational model is optimized without fixing the coordinates of all atoms. Perform calculations to convert it.

[0149] Using the method described above, we create computational model 2A. The overall structure of computational model 2A is shown in Figure 18E. vinegar.

[0150] For each of the calculation models 1A and 2A created using the method described above, total energy Energy was calculated and compared. Specifically, the calculation conditions were set to condition 3 shown in Table 2, and the calculation was performed. For Model 1A, the coordinates of only one In atom located at the center of the crystal region are fixed, Point calculations are performed, and for calculation model 2A, single-point calculations are performed without fixing the coordinates of all atoms. The total energy calculated in the said calculation is compared.

[0151] Based on the above calculations, the total energy value of calculation model 1A is equal to the total energy of calculation model 2A. It was smaller than the negative value, specifically 6.83 eV smaller. Therefore, it has a crystalline region. It was found that computational model 1A, which does not have a crystalline region, is more stable than computational model 2A. Therefore, it is suggested that the nc film is stabilized by having crystalline regions.

[0152] Next, we prepare calculation model 3A for comparison with calculation model 1A. The structure of L3A is a single crystal structure.

[0153] First, we have a single crystal structure of InGaZnO4 (space group is R-3m), and the original The atom ratio is In:Ga:Zn:O = 1:1:1:4, and the density is 6.36 g / cm³. 3 dea Next, prepare a calculation model containing 112 atoms. Then, set the k-point grid to 2x2x3. Then, set the other calculation conditions to condition 3 shown in Table 2, and optimize the coordinates of the atoms in the calculation model. Perform calculations to convert the model. Based on the above, create calculation model 3A.

[0154] For the calculation model 3A created using the method described above, we will calculate the total energy. Specifically, Set the grid of points k to 2x2x3, and set the other calculation conditions to condition 3 shown in Table 2. Then, perform a single-point calculation. The total energy calculated in this calculation is 3.375 (=378 / 112) The value obtained by multiplying by ) is taken as the total energy value of the single-crystal structure calculation model.

[0155] Based on the above calculations, the total energy value of the single-crystal structure calculation model is the total energy of calculation model 1A. It was smaller than the energy value, specifically 54.88 eV smaller. In other words, in the membrane It can be seen that the film becomes more energetically stable as its crystallinity improves.

[0156] From the above, although the calculation model 1A has a higher energy than the single-crystal structure calculation model, Since it is more stable than computational model 2A, the presence of crystalline regions contributes to the stabilization of the nc film. This suggests that they are doing so.

[0157] The above explains the stability of the NC film.

[0158] [Thermal stability of nc films] This section explains the thermal stability of NC films using the results of first-principles calculations. The thermal stability of the nc film is evaluated using the internal energy described later.

[0159] Here, we will explain internal energy. In this specification, internal energy U is given by the following equation It is calculated using [this method].

[0160]

number

[0161] Here, M I m is the mass of the Ith nucleus (where I is a natural number), and m is the mass of the electron. It is. Also, v I is the velocity of the first atomic nucleus. In other words, the first term on the right-hand side of the above equation is the The first term represents the kinetic energy of the electron nucleus, and the third term on the right-hand side of the above equation represents the kinetic energy of the electron.

[0162] Also, Z I is the charge of the first nucleus, and e is the charge of the electron. Also, r IJ teeth, It is the distance between the first atomic nucleus and the jth atomic nucleus (where J is an integer greater than I). , r ij This involves the i-th electron (where i is a natural number) and the j-th electron (where j is an integer greater than i). This is the distance between the electrons of the nucleus and the nucleus. In other words, the second term on the right side of the above equation is the distance between the nucleus and the nucleus. This is the potential energy related to the interaction, and the fourth term on the right-hand side of the above equation is the phase between electrons. This is the potential energy related to the interaction, and the fifth term on the right-hand side of the above equation is the potential energy of the nucleus and electrons. This is the potential energy related to the interaction.

[0163] From the above, the internal energy U is the sum of the kinetic energy and the potential energy. It is calculated as follows.

[0164] Furthermore, the stability of the phase in equilibrium is determined by the Helmholtz free energy F. It is described as follows: Here, the Helmholtz free energy F is derived from the internal energy U by temperature It is the value obtained by subtracting the product of T and entropy S (F = U - TS). However, entropy Since evaluating S is difficult, this specification uses internal energy U to determine thermodynamic phase stability. We will conduct an examination of sexuality.

[0165] The above explains the internal energy. Next, we will discuss the method for evaluating the thermal stability of the nc film. I will explain the physical method.

[0166] For calculation models 1A and 2A described above, the temperature was set to 300K, 6 Set the temperature to 73K, 1000K, 1500K, or 2000K, and use a first-principles molecular dynamics instrument. Perform the calculation. Note that when using calculation model 1A, one In atom located at the center of the crystal region The coordinates are fixed and the first-principles molecular dynamics calculation is performed. Also, when using calculation model 2A... In addition, the first-principles molecular dynamics calculation is performed without fixing the coordinates of all atoms. In molecular dynamics calculations, the time step is 1 fs, the number of steps is 10,000, and other calculation conditions are set. Set the item to condition 2 as shown in Table 2.

[0167] Next, for each of the calculation models 1A and 2A described above, the temperature is set For each of the 10 calculation models after first-principles molecular dynamics calculations were performed The internal energy is calculated. Specifically, the steps range from 9001 to 10000 times. The average internal energy is calculated. Note that for calculation model 1A, the temperature is set to 300K. The average internal energy obtained by performing first-principles molecular dynamics calculations with the settings configured is used as the basis. The average value of the internal energy when it is set to (0.0 eV) is called the average energy.

[0168] Figure 20A shows the relationship between temperature and the average energy calculated using the method described above. The horizontal axis represents temperature [K], and the vertical axis represents average energy [eV]. Also, in Figure 20A, the black... The diamond-shaped plot represents the average energy when using computational model 1A. The white square plot represents the average energy when using calculation model 2A. be.

[0169] Next, we perform first-principles molecular dynamics calculations for computational model 1A, setting each temperature. For each of the five calculation models obtained, the calculation conditions are set to Condition 2 shown in Table 2. Then, calculations are performed to optimize the structure of the computational model. The optimization calculation is performed by fixing the coordinates of a single In atom located at the center of the crystal region. For each of the five calculation models obtained by performing this process, the calculation conditions are shown in Table 2. Set to item 3 and perform calculations to optimize the structure of the computational model.

[0170] Some of the calculation models (a total of 5 types) obtained from the above calculations are shown in Figures 19A to 19E. In Figures 19A to 19E, the calculation model shows atoms placed on the outer periphery of the crystal region. Before that, we show the arrangement of 87 atoms placed in the crystalline region. Figure 19A shows the arrangement at a temperature of 300K. The computational model obtained by performing first-principles molecular dynamics calculations and optimization calculations set to the following parameters Figure 19B shows the results of a first-principles molecular dynamics calculation with the temperature set to 673K, and the most... This is a calculation model obtained by performing optimization calculations, and Figure 19C shows the model with the temperature set to 1000K. This computational model is obtained by performing first-principles molecular dynamics calculations and optimization calculations. Figure 19D shows the first-principles molecular dynamics calculation and optimization with the temperature set to 1500K. This is a calculation model obtained by performing calculations, and Figure 19E shows the result when the temperature is set to 2000K. This computational model is obtained by performing first-principles molecular dynamics calculations and optimization calculations.

[0171] Figures 19A to 19D show a first-principles molecular dynamics instrument set to a temperature of 1500K or less. In the computational model obtained by performing calculations and optimization calculations, the lattice arrangement of the crystal region is preserved. Furthermore, Figure 19E shows the results of a first-principles molecular dynamics calculation with a temperature set to 2000K. Furthermore, the computational model obtained by performing optimization calculations has a broken crystal structure. Figure 19D shows the first-principles molecular dynamics calculation and optimization with the temperature set to 1500K. In the computational model obtained by performing the calculation, the lattice arrangement of the crystal region is preserved, By performing first-principles molecular dynamics calculations and optimization calculations with the temperature set to 1000K Compared to the obtained computational model, the atomic arrangement is highly disordered, and there are signs that the crystal structure is beginning to break down. I can see it.

[0172] Here, the difference between the average energy of calculation model 1A and the average energy of calculation model 2A. The thermal stability of calculation model 1A and calculation model 2A will be compared by calculating the thermal stability of each temperature. The relationship between the degree and the average energy of calculation model 1A and calculation model 2A is shown in Figure 20A. That is correct.

[0173] The temperature and the average energy of calculation model 2A are subtracted from the average energy of calculation model 1A. The relationship with the value (also called the difference in average energy) is shown in Figure 20B. In Figure 20B, the horizontal The axis represents temperature [K], and the vertical axis represents the difference in average energy [eV].

[0174] As shown in Figure 20B, when the temperature is set to 2000K, the difference in average energy is close to zero. , the average energy when using calculation model 1A and the average energy when using calculation model 2A It can be seen that it is almost equal to energy. On the other hand, when the temperature is set to 1500K or below At any temperature, the difference in average energy is a negative value, and when using calculation model 1A... The average energy is smaller than the average energy obtained using calculation model 2A. This can be understood. In other words, at temperatures where the lattice arrangement of the crystalline region is preserved, the computational model having a crystalline region The model is estimated to be more thermally stable than the computational model that does not have a crystalline region. This suggests that, except in the high-temperature range, the presence of crystalline regions improves the thermal stability of the film. It can be done.

[0175] The above explains the thermal stability of NC films.

[0176] [H in nc film O [Ease of generation] This section uses the results of first-principles calculations to describe the ease with which defects are generated in NC films. will be described. Specifically, the generation energy of a defect in which hydrogen enters an oxygen deficiency (hereinafter referred to as V O H or H O is called the case where there is.) is calculated from first-principles calculations.

[0177] H O may generate electrons that serve as carriers. Therefore, when H is generated in the channel formation region in the oxide semiconductor, the transistor tends to have normally-on characteristics, O and the electrical characteristics of the transistor fluctuate. Therefore, it is preferable that the generation of H is suppressed in the channel formation region in the oxide semiconductor. Here, the generation energy of the defect will be described. In this specification, the generation energy of the defect O is calculated using the following formula. The smaller the generation energy of the defect, the easier it is to say that the defect is generated.

[0178] Here, the generation energy of the defect will be described. In this specification, the generation energy of the defect is calculated using the following formula. The smaller the generation energy of the defect, the easier it is to say that the defect is generated. can be said to be generated.

[0179]

Equation

[0180] Here, E form (defect) is the generation energy of the defect (defect), where E(defect) is the total energy of the calculation model containing one defect, E(no d efect) is the total energy of the calculation model not containing the defect, the atom X is the atom whose increase or decrease is caused by generating the defect, μ(X) is the chemical potential of the atom X, and n is the increase or decrease number of the atom X X. For example, when the defect is H O , X is an oxygen atom (O) or a hydrogen atom O (H), n is -1, and n O is +1, and n H is +1.

[0181] Furthermore, the chemical potential μ(O) of an oxygen atom and the chemical potential μ(H) of a hydrogen atom The following formula is used to calculate it.

[0182]

number

[0183] Here, E(O2) is the total energy of an oxygen molecule (O2), and E(H2O) is the total energy of water. This is the total energy of the molecule (H2O).

[0184] Note that E(O2) is defined as one O2 molecule being 1 nm 3 Place them within the grid, and the calculation conditions are shown in Table 2. Set the conditions to condition 2 shown and perform calculations to optimize the structure of the O2 molecule, and then the calculations will be performed. It is calculated by performing a single-point calculation on the calculation model obtained after the calculation. Also, E(H2 O) is one H2O molecule at 1 nm 3 Place them within the grid, and set the calculation conditions to Condition 2 shown in Table 2. The settings are configured, calculations are performed to optimize the structure of the H2O molecule, and then the results obtained after the calculations are... It is calculated by performing a single-point calculation on the given computational model.

[0185] The above explains the energy required to create defects.

[0186] To calculate the energy of defect generation, we prepared computational model 3A. Below, we will discuss the calculations. This section explains how to create Model 3A. Note that the calculations required to create Model 3A are as follows: The calculation conditions shown in Table 2 are used.

[0187] First, we prepare computational model 1A, and then we relax the structure of the outer perimeter of computational model 1A. Perform the calculation. Specifically, prepare calculation model 1A and fix the coordinates of atoms located in the crystal region. Set the temperature to 1000K, the time step size to 1fs, the number of steps to 10000, and other settings. The calculation conditions are set to Condition 2 as shown in Table 2, and a first-principles molecular dynamics calculation is performed.

[0188] Next, keeping the calculation conditions set to Condition 2 as shown in Table 2, we will calculate the measures to relax the structure of the outer perimeter. For the computational model obtained by calculation, the coordinates of atoms located in the crystal region are fixed, and the outer periphery We perform calculations to optimize the structure. Then, we apply the computational model obtained after these calculations to the computational model. The coordinates of the atoms located on the outer periphery and the coordinates of a single In atom located at the center of the crystal region are fixed. Then, calculations are performed to optimize the structure of the crystal region. Subsequently, the results obtained after these calculations are... For the computational model, the coordinates of a single In atom located at the center of the crystal region are fixed, and the computational model Perform calculations to optimize the overall structure of Dell. Then, set the calculation conditions to Condition 3 shown in Table 2. Set and, for the calculation model obtained after the calculation, one In exists at the center of the crystal region We fix the coordinates of the atoms and perform calculations to optimize the overall structure of the computational model.

[0189] Using the method described above, we create calculation model 3A.

[0190] Using the calculation model 3A created by the above method, H O Calculate the energy of generation. In essence, by substituting one oxygen atom with one hydrogen atom in computational model 3A, H O of Prepare a calculation model that includes one. Note that the number of oxygen atoms in calculation model 3A is 216. Therefore, H O 216 computational models are provided that include one of the following: O Calculations that do not include Dell is the very embodiment of the 3A calculation model.

[0191] H O Computational models including one and H O For each of the computational models that does not include computation, The conditions are set to Condition 3 as shown in Table 2, and calculations are performed to optimize the overall structure of the computational model. U. The H obtained after the calculation O The total energy of a computational model containing one of these is E(defec Let t) and the result obtained after the calculation, H O The total energy of the calculation model that does not include E(no (Sequence) Note that H O Perform the calculation on a computation model that includes one of the following: So, H O This can sometimes be replaced by other defects (such as oxygen deficiencies and hydrogen deficiencies).

[0192] Using E(defect) and E(no defect) calculated using the method described above H O The energy of formation is calculated. O The energy of production is shown in Figure 21. In step 21, the horizontal axis represents the optimization of the overall structure of the computational model, starting from the In atom located at the center of the crystal region. H is placed in the computational model before performing the calculations for which the calculations are performed. O Distance to [ [Å], and the vertical axis is H O Formation energy [e V]. Note that the plotted black squares (■) in Figure 21 represent the region near In within the crystal region. H located in the region (also called the crystal core region) O This is the energy of production, shown in Figure 21. The white squares (□) shown represent regions within the crystal region other than the core region (crystal shell). Also called the l region. OThis is the energy of formation, as shown by the X mark (×) in Figure 21. The plot shows H located on the outer edge. O This is the energy of formation. Note that this is the core region of the crystal. There are 12 oxygen atoms located in the region, and 38 oxygen atoms located in the shell region of the crystal. It is an individual.

[0193] H located in the core region of the crystal O H located in the shell region of the crystal O , on the outer circumference H located O The average values ​​of the energy produced are 2.75 eV, 2.60 eV, and 2 eV, respectively. The voltage became 0.14 eV.

[0194] From Figure 21, compared to the core region of the crystal, the shell region of the crystal has H O Generation The energy variation is large, H O H with a small energy of formation value O There was this. Even within the crystalline region, the structure is distorted in the region near the interface between the crystalline region and the outer periphery. It is presumed that this is the reason.

[0195] Furthermore, compared to the crystalline region (the core region of the crystal and the shell region of the crystal), the outer In the surrounding area, H O The variation in the energy of formation is large, H O The value of the energy of formation is small. iH O It can be seen that there are many of them. This is because the outer periphery, which has lower crystallinity, is more prone to bonding compared to the crystalline region. This is presumed to be because there are many oxygen atoms with large fluctuations in total length, resulting in weaker bonding forces with metal atoms. It will be done.

[0196] From the above, the crystalline region is H O In regions where crystallinity is low (the outer periphery mentioned above), H OThis suggests that it is easily formed. Therefore, the presence of a crystalline region means that H O The generation of is suppressed. Therefore, by using nc film in transistors, This can suppress fluctuations in the electrical characteristics.

[0197] The above explains H in nc films. O This is an explanation of how easily it can be generated.

[0198] [Structure of metal oxides] Oxide semiconductors (metal oxides) include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It can be divided into conductors and non-single-crystal oxide semiconductors, for example, CAAC-OS(c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide IDE semiconductor, pseudo-amorphous oxide semiconductor (a-like OS (amorphous-like oxide semiconductor), and Examples include amorphous oxide semiconductors.

[0199] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, the grid arrangement This refers to the point where the orientation has changed.

[0200] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Furthermore, the distortion may have a grid arrangement such as a pentagon or heptagon. In CAAC-OS, even near strain, clear grain boundaries are present. It is also said that it is difficult to confirm the grain boundaries. In other words, due to the distortion of the lattice arrangement, It can be seen that the formation is suppressed. This is because CAAC-OS is in the ab plane direction The arrangement of oxygen atoms is not dense, and the bond distance between atoms changes due to the substitution of metal elements. This is because distortion can be tolerated by processes such as transformation. Crystal structures in which grain boundaries can be observed are known as polycrystalline structures. It is called a stal. The grain boundary becomes a recombination center, and carriers are trapped and the transition This is likely to cause a decrease in the on-current or a decrease in the field-effect mobility. Therefore, CAAC-OS, which lacks clearly defined grain boundaries, is a suitable crystal for the semiconductor layer of transistors. It is one of the crystalline oxides that has a structure. Note that Zn is required to constitute CAAC-OS. A configuration having the following is preferred. For example, In-Zn oxide and In-Ga-Zn oxide are It is preferable because it can suppress the generation of grain boundaries more effectively than in oxides.

[0201] Furthermore, CAAC-OS consists of a layer containing indium and oxygen (hereinafter referred to as the In layer), and A layered crystal in which layers containing element M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers) are stacked. It tends to have a structure (also called a layered structure). Note that indium and element M are relative to each other. It is interchangeable, and if element M in the (M,Zn) layer is replaced with indium, then (In,M,Zn It can also be represented as a layer. Furthermore, if the indium in the In layer is replaced by element M, (In, It can also be represented as layer M.

[0202] CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS has a clear bond. Because it is difficult to confirm grain boundaries, a decrease in electron mobility caused by grain boundaries is less likely to occur. It can be said that... Also, the crystallinity of metal oxides decreases due to the inclusion of impurities and the formation of defects. Because this can sometimes occur, CAAC-OS is a metal oxide with few impurities or defects (such as oxygen deficiencies). It can also be said that metal oxides containing CAAC-OS have stable physical properties. Therefore, metal oxides containing CAAC-OS are heat-resistant and highly reliable.

[0203] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. Also, nc-OS has different na No regularity is observed in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body.

[0204] Furthermore, In- is a type of metal oxide containing indium, gallium, and zinc. Ga-Zn oxide (hereinafter referred to as IGZO) adopts a stable structure when formed into the nanocrystals described above. In some cases, IGZO tends to have difficulty growing crystals in the atmosphere, so large bonds may form. Crystals smaller than crystals (here, crystals of several millimeters or several centimeters) (for example, as mentioned above) In some cases, forming the material into nanocrystals can result in a more structurally stable material.

[0205] a-like OS is a metallic acid having a structure between nc-OS and amorphous oxide semiconductors. It is a monster. a-like OS has porous or low-density regions. That is, a-li ke OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0206] Oxide semiconductors (metal oxides) can take on diverse structures, each possessing different properties. An oxide semiconductor according to one aspect of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and a-li It may have two or more of the following: ke OS, nc-OS, and CAAC-OS.

[0207] Furthermore, as a non-single-crystal oxide semiconductor, CAC (Cloud-Aligned Comp osite)-OS may also be used. Note that CAC-OS refers to the material composition.

[0208] [Composition of metal oxides] CAC-OS refers to a material that possesses both conductive and insulating properties in some parts. It possesses the properties of a semiconductor as a whole. Furthermore, CAC-OS is a transistor. When used in the active layer of a device, its conductive function is to allow electrons (or holes) that act as carriers to flow. The function of insulation is the function of preventing the flow of electrons, which act as carriers. The function of conductivity is... By having the insulating function and the other function work complementaryly, a switching function is achieved. The function to turn CAC-OS on / off can be added to CAC-OS. By separating each function, it is possible to maximize the performance of both.

[0209] Furthermore, CAC-OS has conductive regions and insulating regions. The conductive regions are as described above. It has conductive properties, and the insulating region has the aforementioned insulating properties. Furthermore, conductive and insulating regions may be separated at the nanoparticle level. Conductive and insulating regions may be unevenly distributed within the material. The affected area may appear blurred around the edges, creating a cloud-like, connected appearance.

[0210] Furthermore, in CAC-OS, the conductive region and the insulating region are each 0.5 nm or less. The particles are dispersed in the material with a size of 10 nm or less, preferably between 0.5 nm and 3 nm. There are cases where this is the case.

[0211] Furthermore, CAC-OS is composed of components with different band gaps. For example, CAC-OS has components with a wide gap due to the insulating region and components with a conductive region. It consists of a component having a resulting narrow gap, and a carrier. When flowing, the carrier mainly flows in the component with a narrow gap. - Components with a gap act complementaryly with components with a wide gap, and narrow gap In conjunction with the component having a gap, the carrier also flows to the component having a wide gap. Therefore, when the above CAC-OS is used in the channel formation region of a transistor, the transistor In the ON state, a high current driving force, i.e., a large ON current, and high field effect mobility are obtained. It is possible.

[0212] In other words, CAC-OS is a matrix composite ), or metal matrix composite It can also be called that.

[0213] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from those mentioned above. Here, we will explain the classification of crystal structures in oxide semiconductors using Figure 22A. To proceed. Figure 22A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). This is a diagram illustrating the classification of the crystal structures of metal oxides.

[0214] As shown in Figure 22A, IGZO can be broadly divided into Amorphous and, They are classified into Crystalline and Crystal. Amorphous includes completely amorphous molecules. Furthermore, Crystalline includes CAAC, nc, and CAC. Oh, the classification of crystallines includes single crystal, polycrystalline rystal and completely amorphous are excluded. Also, Cr ystal contains single crystal and poly crystal. It is included.

[0215] The structures within the thick frame shown in Figure 22A are Amorphous and Crystal. It is an intermediate state between al (crystal) and a new boundary region (New crystallin This structure belongs to the e phase. This structure is Amorphous and Cryst It lies in the boundary region between al and Amor. In other words, this structure is energetically unstable. To put it another way, it's a structure that is completely different from phous (amorphous) or crystal (crystalline). It is possible.

[0216] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using an ion image. Here, quartz glass and Crystal XRD of IGZO (also called crystalline IGZO) having a crystal structure classified as ine The vectors are shown in Figures 22B and 22C. Figure 22B shows quartz glass, and Figure 22C shows crystalline glass. This is the XRD spectrum of IGZO. Note that the composition of crystalline IGZO shown in Figure 22C is I The ratio of n:Ga:Zn is approximately 4:2:3 [atomic ratio]. Also, the crystalline IG shown in Figure 22C The thickness of ZO is 500 nm.

[0217] As shown by the arrow in Figure 22B, the shape of the peak in the XRD spectrum of quartz glass is approximately It is symmetrical. On the other hand, as shown by the arrow in Figure 22C, crystalline IGZO has XRD spectrum The peak shape of the clef is asymmetrical. The peak shape of the XRD spectrum is asymmetrical. The fact that it is named indicates the presence of a crystal. In other words, the peak of the XRD spectrum A shape cannot be considered amorphous unless it is symmetrical. Note that Figure 22C shows , 2θ=31° or near that, IGZO crystal phase It is clearly stated. The reason why the peaks in the XRD spectrum are asymmetrical is as follows. This is presumed to be due to the crystalline phase (microcrystals).

[0218] Specifically, in the XRD spectrum of crystalline IGZO shown in Figure 22C, 2θ=3 It has a peak at 4° or nearby. Also, the microcrystals have a peak at 2θ=31° or nearby. It has a peak. When evaluating an oxide semiconductor film using X-ray diffraction patterns, as shown in Figure 22C... In other words, the spectral width is wider at angles lower than the peak at 2θ=34° or its vicinity. This is because the oxide semiconductor film contains microcrystals having a peak at or near 2θ = 31°. This suggests that it is inherent.

[0219] Furthermore, the crystalline structure of the film is determined by nano-beam electron diffraction (NBED). Diffraction patterns observed by tron ​​diffraction (micro-electron diffraction) It can be evaluated using the pattern (also called a pattern). IGZ film deposited at room temperature. The diffraction pattern of the O film is shown in Figure 22D. Note that the IGZO film shown in Figure 22D is In:Ga Using an oxide target with an atomic ratio of Zn=1:1:1, the sputtering method is applied to Therefore, a film is formed. In addition, in the ultra-micro electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm. It was carried out.

[0220] As shown in Figure 22D, the diffraction pattern of an IGZO film deposited at room temperature does not show a halo, A spot-like pattern is observed. Therefore, the IGZO film deposited at room temperature is in a crystalline state. It is neither amorphous nor non-crystalline, but an intermediate state, and therefore it cannot be concluded that it is amorphous. It is presumed that there is none.

[0221] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0222] (Embodiment 2) In this embodiment, an example of the configuration of a semiconductor device to which a metal oxide film according to one aspect of the present invention is applied is provided. I will explain using transistors as an example.

[0223] [Configuration Example 1] [Configuration Example 1-1] Figure 23A is a top view of transistor 300, and Figure 23B is a single-point chain shown in Figure 23A. Figure 23C corresponds to a cross-sectional view of the cross-section along line A1-A2, and shows the dashed line B shown in Figure 23A. This corresponds to the cross-sectional view of the section in 1-B2. The dashed line A1-A2 direction is the channel length direction. The dashed line B1-B2 corresponds to the channel width direction. Note that in Figure 23A, Some components of the inverter 300 (such as the gate insulating layer) are omitted from the illustration. Regarding the top view of the transistor, in subsequent drawings, as with Figure 23A, one of the components is shown. The diagram omits some parts.

[0224] The transistor 300 is provided on the substrate 302, and consists of a conductive layer 304, an insulating layer 306, and a semiconductor It has layers 308, conductive layer 312a, and conductive layer 312b, etc. The insulating layer 306 is conductive layer 30 It is provided covering 4. The semiconductor layer 308 has an island-like shape and is provided on the insulating layer 306. The conductive layer 312a and conductive layer 312b are in contact with the upper surface of the semiconductor layer 308. Furthermore, they are spaced apart on the semiconductor layer 308. Also, the insulating layer 306, conductive layer 3 An insulating layer 314 is provided covering 12a, the conductive layer 312b, and the semiconductor layer 308, and the insulating layer An insulating layer 316 is provided on 314.

[0225] The metal oxide film exemplified in Embodiment 1 can be applied to the semiconductor layer 308.

[0226] There are no major restrictions on the material of the substrate 302, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, a single crystal made of silicon or silicon carbide. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI groups Plates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used as substrate 302. It is also acceptable to have semiconductor elements mounted on these substrates as substrate 302. You may use it.

[0227] Furthermore, a flexible substrate is used as the substrate 302, and a semiconductor device is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 302 and the semiconductor device. The release layer is After partially or completely completing the semiconductor device on top of it, it is separated from the substrate 302 and placed on another substrate It can be used for reproduction. In this case, the semiconductor device may be a substrate with poor heat resistance or a flexible substrate. It can also be mounted on the circuit board.

[0228] The conductive layer 304 functions as a gate electrode. Part of the insulating layer 306 is a gate insulating layer. It functions as follows: The conductive layer 312a functions as either the source electrode or the drain electrode. The conductive layer 312b functions as the other. The region of the semiconductor layer 308 that overlaps with the conductive layer 304 is It functions as a channel formation region. Transistor 300 is formed more than semiconductor layer 308. This is a so-called bottom-gate type transistor, where the gate electrode is located on the face side. The side of the semiconductor layer 308 opposite to the conductive layer 304 is called the back channel side. Yes. Transistor 300 is located on the back channel side of semiconductor layer 308, and the source electrode and This is a transistor with a so-called channel etch structure, which does not have a protective layer between the rain electrode and the transistor. ru.

[0229] The semiconductor layer 308 may have a stacked structure of two or more layers. The semiconductor film constituting 8 preferably contains a metal oxide. The semiconductor layer 308 has a two-layer structure. In this case, the semiconductor film located on the back channel side is the semiconductor located on the conductive layer 304 side. It is preferable that the film has higher crystallinity than the film. This is because the conductive layer 312a and the conductive layer During the processing of 312b, a portion of the semiconductor layer 308 is etched and lost. It can be controlled.

[0230] For example, semiconductor layer 308 is made of indium and M (where M is gallium, aluminum, and silica). N, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium (One or more elements selected from luminous, tantalum, tungsten, or magnesium), It is preferable that it contains zinc. In particular, M is aluminum, gallium, yttrium, or Tin is preferred.

[0231] In particular, an oxide containing indium, gallium, and zinc is used as the semiconductor layer 308. It is preferable.

[0232] The conductive layer 312a and the conductive layer 312b are, in order from the side to be formed, the conductive layer 313a It has a laminated structure in which a conductive layer 313b is laminated.

[0233] The conductive layer 313b is made of a low-resistance conductive material, such as copper, silver, gold, or aluminum. It is preferable to use it. In particular, it is preferable that the conductive layer 313b contains copper or aluminum. This makes the conductive layer 312a and conductive layer 312b extremely low-resistance. It is possible.

[0234] Furthermore, the conductive layer 313a can be made of a different conductive material than the conductive layer 313b. For example, the conductive layer 313a is titanium, tungsten, molybdenum, chromium, tantalum, It is preferable to use a conductive material containing zinc, indium, platinum, or ruthenium. .

[0235] Thus, between the conductive layer 313b containing copper, aluminum, etc. and the semiconductor layer 308, By providing the conductive layer 313a, the metal elements contained in the conductive layer 313b become semiconductor layer 308 This prevents diffusion inside, enabling the creation of a highly reliable transistor 300. Furthermore, the conductive layer 313a prevents oxygen in the semiconductor layer 308 from diffusing into the conductive layer 313b. It is preferable that it functions as a barrier layer.

[0236] Furthermore, the structure of conductive layers 312a and 312b is not limited to a two-layer structure, and can also be made of copper, silver, gold, Alternatively, it may be a three-layer or four-layer structure including a conductive layer containing aluminum. , conductive layer 312a and conductive layer 312b are the same as conductive layer 313a on conductive layer 313b A three-layer structure may be formed by laminating conductive layers containing the conductive material. To suppress oxidation of the upper surface of b, and to prevent metal elements contained in the conductive layer 313b from scattering into the surroundings. This prevents this from happening, enabling the creation of highly reliable transistors.

[0237] The conductive layer 304 is the same conductive layer that can be used in conductive layer 313a or conductive layer 313b. An electrical material can be used as appropriate. In particular, it is preferable to use a conductive material containing copper. .

[0238] The insulating layer 306 and insulating layer 314 that are in contact with the semiconductor layer 308 contain an insulating material containing an oxide. It is preferable to use the following. Also, when the insulating layer 306 and insulating layer 314 are made into a laminated structure Furthermore, an insulating material containing an oxide is used in the layer that is in contact with the semiconductor layer 308.

[0239] Furthermore, even if a nitride insulating film such as silicon nitride or aluminum nitride is used for the insulating layer 306, Good. When using an insulating material that does not contain oxides, oxygen is added to the top of the insulating layer 306. It is preferable to perform a process to form an oxygen-containing region. For example, heating or plasma treatment in an oxygen-containing atmosphere, or ion doping There are processes such as grading.

[0240] The insulating layer 316 functions as a protective layer to protect the transistor 300. These include silicon nitride, silicon oxide nitride, silicon oxide, silicon oxide nitride, and aluminum oxide. Inorganic insulating materials such as aluminum nitride can be used. In particular, insulating layer 316 By using materials that do not easily diffuse oxygen, such as silicon nitride and aluminum oxide, During the manufacturing process, heat generated can cause the semiconductor layer 308 and insulating layer 314 to move through the insulating layer 316. This is preferable because it prevents oxygen from escaping to the outside.

[0241] Alternatively, an organic insulating material that functions as a planarization film may be used as the insulating layer 316. Alternatively, a laminated film comprising a film containing an inorganic insulating material and a film containing an organic insulating material is used as the insulating layer 316. It's okay to be there.

[0242] Furthermore, the semiconductor layer 308 has portions that are in contact with the conductive layer 312a and the conductive layer 312b and portions that are in close proximity thereto. A pair of low-resistance regions are formed adjacent to each other, functioning as a source region and a drain region. It may be present. This region is part of the semiconductor layer 308 and has lower resistance than the channel formation region. This is a region. Furthermore, the low-resistance region is a region with high carrier concentration, or a region that is n-type, etc. This can be rephrased as follows. Also, in the semiconductor layer 308, sandwiched between a pair of low-resistance regions, Furthermore, the region overlapping with the conductive layer 304 functions as a channel-forming region.

[0243] [Configuration Example 1-2] The following describes a transistor configuration example that differs in some aspects from the above configuration example 1-1. Yes. Note that in the following, explanations may be omitted for parts that overlap with the above configuration example 1-1.

[0244] Figure 24A is a cross-sectional view of transistor 300A in the channel length direction, and Figure 24B is a cross-sectional view of transistor 300A in the channel length direction. This is a cross-sectional view in the channel width direction.

[0245] Transistor 300A has a conductive layer 320 on an insulating layer 314, as in Configuration Example 1-1. It differs primarily from the above.

[0246] The conductive layer 320 has a region that overlaps with the semiconductor layer 308 via the insulating layer 314.

[0247] In transistor 300A, the conductive layer 304 is the first gate electrode (bottom gate electrode The conductive layer 320 functions as a second gate electrode (also called a top gate electrode), and the conductive layer 320 has the function of a second gate electrode (top gate electrode). It functions as a pole (also called a pole). In addition, a part of the insulating layer 314 is the second gate insulating layer It functions as such.

[0248] Furthermore, as shown in Figure 24B, the conductive layer 320 is provided on the insulating layer 314 and the insulating layer 306. It may be electrically connected to the conductive layer 304 through the opening 342. Therefore, the same potential can be applied to the conductive layer 320 and the conductive layer 304, and the on current is high. It is possible to implement Rangista.

[0249] Furthermore, as shown in Figure 24B, in the channel width direction, conductive layer 304 and conductive layer 320 However, it is preferable that it extends outward beyond the edge of the semiconductor layer 308. In this case, see Figure 24. As shown in B, the entire channel width direction of the semiconductor layer 308 is connected to the conductive layer 304 and the conductive layer 3 The structure will be covered by 20.

[0250] With this configuration, the semiconductor layer 308 is protected from the electric field generated by the pair of gate electrodes. And it can be electrically surrounded. In particular, the conductive layer 304 and the conductive layer 320 are the same It is preferable to apply an electric potential. This induces a channel in the semiconductor layer 308. Because the electric field can be effectively applied, the on-current of the 300A transistor can be increased. Yes, it is possible. Therefore, it is also possible to miniaturize the 300A transistor.

[0251] Furthermore, the conductive layer 304 and the conductive layer 320 may be configured without being connected. In this case, one pair A constant potential is applied to one gate electrode, and a signal is applied to the other to drive transistor 300A. A voltage may be given. At this time, the potential applied to one of the gate electrodes determines the transistor 30 The threshold voltage when driving 0A with the other gate electrode can be controlled.

[0252] Alternatively, the conductive layer 320 is electrically connected to either the conductive layer 312a or the conductive layer 312b. A connected configuration is also possible. In particular, among the conductive layer 312a and conductive layer 312b, the constant potential is It is preferable to electrically connect the supplied conductive layer (e.g., source electrode) and the conductive layer 320. It seems so.

[0253] The above is an explanation of Configuration Example 1.

[0254] [Configuration Example 2] The following describes a transistor configuration example different from the above-mentioned Configuration Example 1.

[0255] [Configuration Example 2-1] Figure 25A is a top view of transistor 350, and Figure 25B is a single-point chain shown in Figure 25A. Figure 25C corresponds to a cross-sectional view of the cross-section along line A3-A4, and is shown along the dashed line B in Figure 25A. This corresponds to the cross-sectional view of the section in 3-B4. The dashed line A3-A4 direction indicates the channel length. The dashed line B3-B4 corresponds to the channel width direction.

[0256] The transistor 350 is provided on the substrate 352 and has an insulating layer 353, a semiconductor layer 358, and an insulating layer 350. It has an edge layer 360, a metal oxide layer 364, a conductive layer 362, an insulating layer 368, etc. The body layer 358 is provided on the insulating layer 353. The insulating layer 360 is on the upper surface, half of the insulating layer 353. The metal oxide layer 364 and conductive layer 362 are provided in contact with the upper and side surfaces of the conductive layer 358. These are arranged in this order on the insulating layer 360 and have a portion that overlaps with the semiconductor layer 358. The insulating layer 368 is located on the upper surface of the insulating layer 360, the side surface of the metal oxide layer 364, and the conductive layer 36 It is provided covering the upper surface of 2.

[0257] The metal oxide film exemplified in Embodiment 1 can be applied to the semiconductor layer 358.

[0258] Furthermore, as shown in Figures 25A and 25B, the transistor 350 is connected to the insulating layer 368. It may also have an electrical layer 370a and a conductive layer 370b. b functions as either a source electrode or a drain electrode. Conductive layer 370a and conductive layer 370 b is an opening 391a or opening provided in the insulating layer 368 and the insulating layer 360, respectively. It is electrically connected to the low-resistance region 358n via section 391b.

[0259] A portion of the conductive layer 362 functions as a gate electrode. A portion of the insulating layer 360 functions as a gate insulating It functions as a marginal layer. Transistor 350 has a gate electrode provided on semiconductor layer 358. It is a so-called top-gate type transistor.

[0260] The conductive layer 362 and the metal oxide layer 364 are processed so that their upper surface shapes are roughly identical to each other. It is being done.

[0261] In this specification, "approximately matching top surface shape" means that there is a small difference between the stacked layers. This refers to the overlapping of parts of the outlines. For example, the upper layer and the lower layer may have the same mask pattern. , or including cases where part of it is processed with the same mask pattern. However, strictly speaking, ring The walls do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case as well, it is said that "the top surface shape is roughly the same."

[0262] The metal oxide layer 364 located between the insulating layer 360 and the conductive layer 362 is in the insulating layer 360. It functions as a barrier film that prevents the contained oxygen from diffusing to the conductive layer 362. The oxide layer 364 allows hydrogen and water contained in the conductive layer 362 to diffuse towards the insulating layer 360. It also functions as a barrier film to prevent this. The metal oxide layer 364 is, for example, at least the insulating layer 36 It is preferable to use a material that is less permeable to oxygen and hydrogen than 0.

[0263] The metal oxide layer 364 makes it easier for oxygen such as aluminum and copper to be attracted to the conductive layer 362. Even when using a metal material, oxygen diffuses from the insulating layer 360 to the conductive layer 362. This can prevent the conductive layer 362 from containing hydrogen. This prevents hydrogen from diffusing from the insulating layer 360 to the semiconductor layer 358. As a result, the carrier density in the channel formation region of the semiconductor layer 358 is made extremely low. It is possible.

[0264] As the metal oxide layer 364, an insulating material or a conductive material can be used. If the metal oxide layer 364 has insulating properties, the metal oxide layer 364 is part of the gate insulating layer. It functions as follows. On the other hand, if the metal oxide layer 364 is conductive, the metal oxide layer 3 64 functions as part of the gate electrode.

[0265] As the metal oxide layer 364, an insulating material with a higher dielectric constant than silicon oxide is used. This is preferred. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminum film is preferred. Using a film or similar material is preferable because it allows for a reduction in the driving voltage.

[0266] For example, the metal oxide layer 364 may be indium oxide or indium tin oxide (ITO). or conductive oxides such as silicon-containing indium tin oxide (ITSO) It can also be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. .

[0267] Furthermore, the metal oxide layer 364 is an oxide material containing one or more of the same elements as the semiconductor layer 358. It is preferable to use a material. In particular, an oxide semiconductor material applicable to the semiconductor layer 358 is preferable. It is preferable to use the same material as the semiconductor layer 358 as the metal oxide layer 364. By applying a metal oxide film formed using a puttering target, the equipment can be standardized. This is preferable because it allows for this.

[0268] Furthermore, the metal oxide layer 364 is preferably formed using a sputtering apparatus. When forming an oxide film using a sputtering apparatus, the film is formed in an atmosphere containing oxygen gas. This allows for the appropriate addition of oxygen to the insulating layer 360 and the semiconductor layer 358.

[0269] The semiconductor layer 358 consists of a region superimposed on the conductive layer 362 and a pair of low-resistance regions flanking that region. It has 358n. The region of the semiconductor layer 358 that overlaps with the conductive layer 362 is transistor 3 It functions as a channel formation region of 50. On the other hand, the low-resistance region 358n is used by transistor 3 It functions as either a source area or a drain area.

[0270] Furthermore, the low-resistance region 358n is a region with lower resistance than the channel-forming region, and the carrier concentration is higher. This region is also known as the n-type region, the region with high oxygen defect density, the region with high impurity concentration, or the n-type region. It is possible.

[0271] The low-resistance region 358n of the semiconductor layer 358 is a region containing impurity elements. Examples of elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Examples include noble gases. Representative examples of noble gases include helium and neon. These include argon, krypton, and xenon. In particular, they may contain boron or phosphorus. This is preferable. Furthermore, it may contain two or more of these elements.

[0272] The process of adding impurities to the low-resistance region 358n is performed using the conductive layer 362 as a mask, and the insulating layer This can be done via 360. The process of adding impurities to the low-resistance region 358n is as follows: Plasma ion doping and ion implantation methods can be suitably used.

[0273] In the low resistance region 358n, the impurity concentration is 1 × 10⁻⁶. 19atoms / cm 3 The above is 1 x 1 0 23 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The above 5x 10 22 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 That's all. , 1 x 10 22 atoms / cm 3 Preferably, the region includes the following:

[0274] The concentration of impurities in the low-resistance region 358n can be determined, for example, by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry, and X-ray photoelectric X-ray Photoelectron Spectroscopy (XPS) It can be analyzed by analytical methods such as y). When using XPS analysis, the surface side or By combining ion sputtering from the back side with XPS analysis, the concentration in the depth direction can be determined. It is possible to know the degree distribution.

[0275] Furthermore, in the low-resistance region 358n, impurity elements exist in an oxidized state. Preferred. For example, boron, phosphorus, magnesium, aluminum, and silica as impurity elements. It is preferable to use easily oxidizable elements such as ammonium. Such easily oxidizable elements are semi-ammonium. Because it can exist stably in an oxidized state by bonding with oxygen in the conductive layer 358, high in subsequent processes When exposed to high temperatures (for example, 400°C or higher, 600°C or higher, or 800°C or higher) Even if this occurs, the desorption is suppressed. Also, impurity elements do not remove oxygen from the semiconductor layer 358. As a result, many oxygen vacancies are generated in the low-resistance region 358n. These oxygen vacancies and the water in the membrane Because it becomes a carrier source when it combines with other elements, the low-resistance region 358n has extremely low resistance. This is the state it is in.

[0276] For example, when boron is used as an impurity element, the boron contained in the low resistance region 358n It can exist in a state bound to oxygen. This means that in XPS analysis, the B2O3 bond... This can be confirmed by observing the resulting spectral peak. Furthermore, in XPS analysis, The spectral peaks caused by the element boron existing in its elemental form are not observed, or are not measured. The peak intensity becomes extremely small, to the point where it is buried in the background noise below a certain limit.

[0277] The insulating layer 360 is in contact with the channel formation region of the semiconductor layer 358, i.e., the conductive layer 3 It has a region that overlaps with 62. In addition, the insulating layer 360 has a low-resistance region 35 of the semiconductor layer 358. It has a region that is in contact with 8n and does not overlap with the conductive layer 362.

[0278] The region of the insulating layer 360 that overlaps with the low-resistance region 358n contains the aforementioned impurity elements. In this case, the impurity elements in the insulating layer 360 may be present, similar to the low-resistance region 358n. It is preferable that it exists in a state of being bonded with oxygen. Such easily oxidized elements are insulating. Because it can exist stably in an oxidized state by bonding with oxygen in layer 360, it can be subjected to high temperatures in subsequent processes. Even if heat is applied, detachment is suppressed. In particular, detachment in the insulating layer 360 due to heating If the mixture contains oxygen that can be released (also called excess oxygen), the excess oxygen and the impurity elements will In order to bond and stabilize, oxygen is supplied from the insulating layer 360 to the low-resistance region 358n. This can suppress the oxidized state of impurity elements in the insulating layer 360. Because the part is in a state where oxygen does not easily diffuse, the insulating layer 360 is above the insulating layer 36 By supplying oxygen to the low-resistance region 358n via 0, it also prevents the resistance from increasing. It is possible.

[0279] The insulating layer 368 functions as a protective layer to protect the transistor 350. Insulating layer 368 For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon oxide, silicon oxide nitride, silicon nitride, and silicon oxide nitride. Aluminum oxide, aluminum nitride oxide, aluminum nitride, hafnium oxide, haf Inorganic insulating materials such as nium aluminate can be used.

[0280] [Configuration Example 2-2] Figure 26A is a top view of transistor 350A, and Figure 26B is a top view of transistor 350 Figure 26C is a cross-sectional view of transistor A in the channel length direction, and Figure 26C is a cross-sectional view of transistor 350A in the channel width direction. This is a cross-sectional view of the opposite side.

[0281] Compared to transistor 350 illustrated in Configuration Example 2-1, transistor 350A has the following characteristics: The main differences lie in the different configuration of the margin layer 360 and the presence of an insulating layer 366.

[0282] The insulating layer 360 is designed so that its upper surface shape is roughly consistent with that of the conductive layer 362 and the metal oxide layer 364. The insulating layer 360 is processed by, for example, processing the conductive layer 362 and the metal oxide layer 364. It can be formed by processing using a resist mask.

[0283] The insulating layer 366 consists of the conductive layer 362, the metal oxide layer 364, and the insulating layer 3 of the semiconductor layer 358. It is provided in contact with the top and side surfaces that are not covered by 60. The insulating layer 366 is an insulating layer The upper surface of layer 353, the side surface of insulating layer 360, the side surface of metal oxide layer 364, and conductive layer 362 It is provided to cover the top and sides.

[0284] The insulating layer 366 has the function of reducing the resistance of the low-resistance region 358n. As for layer 366, by heating during or after the deposition of the insulating layer 366, low resistance is achieved. An insulating film that can supply impurities into region 358n can be used. Alternatively, By heating during or after the deposition of the insulating layer 366, acid is introduced into the low-resistance region 358n. An insulating film capable of causing elementary defects can be used.

[0285] For example, as an insulating layer 366, it can be used as a source to supply impurities to the low-resistance region 358n. An insulating film capable of this can be used. In this case, the insulating layer 366 releases hydrogen upon heating. It is preferable that the film is such that an insulating layer 366 is formed in contact with the semiconductor layer 358. By doing so, impurities such as hydrogen are supplied to the low-resistance region 358n, and the low-resistance region 358n is made low-resistance It can be made resistant.

[0286] The insulating layer 366 is formed using a gas that contains impurity elements such as hydrogen in the film formation gas. It is preferable that the film is formed using [a specific method]. Furthermore, it is preferable to increase the film formation temperature of the insulating layer 366. This allows for the effective supply of many impurity elements to the semiconductor layer 358. Insulating layer 366 The film deposition temperature is, for example, 200°C to 500°C, preferably 220°C to 450°C. The temperature can be below ℃, more preferably between 250℃ and 400℃.

[0287] Furthermore, by forming the insulating layer 366 under reduced pressure and heating, the semiconductor layer 358 This can promote the desorption of oxygen in the low-resistance region of 358n. By supplying impurities such as hydrogen to the formed semiconductor layer 358, the low-resistance region 358n The carrier density increases, making it possible to more effectively reduce the resistance of the low-resistance region 358n. ru.

[0288] Examples of insulating layer 366 include silicon nitride, silicon nitride oxide, and silicon oxide nitride. Preferably, an insulating film containing nitrides, such as aluminum nitride or aluminum oxide nitride, is used. This is possible. In particular, silicon nitride has blocking properties for hydrogen and oxygen, To prevent both the diffusion of hydrogen from the outside into the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside. This makes it possible to create highly reliable transistors.

[0289] Furthermore, the insulating layer 366 has the function of drawing oxygen from the semiconductor layer 358 and creating an oxygen deficiency. It may also be an insulating film. In particular, it is especially preferable to use a metal nitride for the insulating layer 366. It seems so.

[0290] Furthermore, when using metal nitrides, aluminum, titanium, tantalum, tungsten, and It is preferable to use chromium or ruthenium nitride. In particular, aluminum or tungsten is preferable. It is particularly preferable to include tan. For example, if aluminum is used as the sputtering target. i. Nitride formed by a reaction sputtering method using a gas containing nitrogen as the film deposition gas. The luminium film is formed by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas, This film possesses both extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen. Therefore, an insulating film containing such a metal nitride is provided in contact with the semiconductor layer. This not only makes it possible to reduce the resistance of the semiconductor layer, but also causes oxygen to be removed from the semiconductor layer. Furthermore, it is possible to effectively prevent hydrogen from diffusing into the semiconductor layer.

[0291] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the layer thickness be 5 nm or more. Even with such a thin film, hydrogen and acid This material can achieve both high blocking properties for the element and low resistance of the semiconductor layer. The thickness of the insulating layer can be any thickness, but considering productivity, it is preferably 500 nm or less. It is preferable that the wavelength be 200 nm or less, and more preferably 50 nm or less.

[0292] When an aluminum nitride film is used for the insulating layer 366, the composition formula is AlN x (x is greater than 0) A film is used that satisfies the condition x is a real number less than or equal to 2, preferably a real number greater than 0.5 and less than or equal to 1.5. It is preferable to have this. This makes it possible to create a film with excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the heat dissipation of the heat generated when driving the 350A transistor. Cut.

[0293] By providing such an insulating layer 366 in contact with the low-resistance region 358n, the insulating layer 366 By drawing oxygen from the low-resistance region 358n, an oxygen deficiency is formed in the low-resistance region 358n. This can be achieved. Furthermore, by performing a heat treatment after forming such an insulating layer 366, low resistance The anti-region 358n can form more oxygen deficiencies, promoting resistance reduction. Yes, it is possible. Also, if a film containing a metal oxide is used for the insulating layer 366, the insulating layer 366 becomes a semiconductor. As a result of drawing oxygen from layer 358, the insulating layer between insulating layer 366 and low-resistance region 358n When a layer containing oxides of metal elements (e.g., aluminum) included in 366 is formed be.

[0294] Here, when a metal oxide film containing indium is used as the semiconductor layer 358, low resistance A region where indium oxide is deposited near the interface of region 358n on the insulating layer 366 side, or In some cases, regions with high indium concentration may be formed. This results in extremely low resistance. A resistive region 358n can be formed. The presence of such a region is useful, for example, in X-ray photoelectric fields. X-ray Photoelectron Spectroscopy (XPS) It may be possible to observe this using analytical methods such as y).

[0295] [Configuration Example 2-3] Figure 27A shows a cross-sectional view of transistor 350B. In Figure 27A, the dashed line... Furthermore, the cross-section in the channel length direction is shown on the left, and the cross-section in the channel width direction is shown on the right, side by side for clarity. ru.

[0296] The transistor 350B has a conductive layer 356 between the substrate 352 and the insulating layer 353. Therefore, it differs mainly from configuration example 2-1. The conductive layer 356 is composed of semiconductor layer 358 and conductive layer 362. It has an overlapping region.

[0297] In transistor 350B, the conductive layer 362 is the second gate electrode (top gate electrode). The conductive layer 356 functions as a first gate electrode (also called a bottom gate electrode), and the conductive layer 356 has the function of a first gate electrode (bottom gate electrode). It functions as a pole (also called a pole). In addition, a part of the insulating layer 360 is the second gate insulating layer It functions as such, and a portion of the insulating layer 353 functions as the first gate insulating layer.

[0298] The portion of the semiconductor layer 358 that overlaps with at least one of the conductive layer 362 and the conductive layer 356 is It functions as a channel formation region. For the sake of simplicity, semiconductor layer 358 will be referred to below. The portion that overlaps with the conductive layer 362 is sometimes called the channel formation region, but in reality the conductive layer 3 In addition to the portion that does not overlap with 62, there is also a portion that overlaps with the conductive layer 356 (the portion that includes the low-resistance region 358n). A channel can be formed.

[0299] Furthermore, as shown in Figure 27A, the conductive layer 356 consists of a metal oxide layer 364 and an insulating layer 360. and electrically connected to the conductive layer 362 through an opening 392 provided in the insulating layer 353. This may be done. This allows the conductive layer 356 and the conductive layer 362 to be given the same potential. can.

[0300] The conductive layer 356 is electrically connected to either the conductive layer 370a or the conductive layer 370b. A continuation of this configuration is also acceptable.

[0301] The conductive layer 356 is made of the same material as conductive layer 362, conductive layer 370a, or conductive layer 370b. This can be used. In particular, if a material containing copper is used for the conductive layer 356, the wiring resistance can be reduced. It is preferable for this reason.

[0302] In Figure 27A, the insulating layer 353 is, from the conductive layer 356 side, the insulating layer 353a and the insulating layer 35 This shows a case where 3b and have a laminated structure. In this case, the conductive layer 356 side The insulating layer 353a to be placed uses an insulating film that does not easily diffuse the metal elements contained in the conductive layer 356. It is preferable that they be present. For example, silicon nitride film, silicon nitride oxide film, aluminum oxide film It is preferable to use an inorganic insulating film such as a hafnium oxide film. Also, the semiconductor layer 358 and It is preferable to use an insulating film containing oxygen for the insulating layer 353b that comes into contact with it. For example, silica oxide It is preferable to use a condensate film or a silicon oxidizing nitride film.

[0303] Furthermore, as shown in Figure 27A, in the channel width direction, conductive layer 362 and conductive layer 35 It is preferable that 6 protrudes outward beyond the edge of the semiconductor layer 358. In this case, see Figure 2. As shown in 7A, the entire channel width direction of the semiconductor layer 358 is connected to the insulating layer 360 and the insulating layer 3 The structure is covered by conductive layers 362 and 356 via 53.

[0304] With this configuration, the semiconductor layer 358 is protected from the electric field generated by the pair of gate electrodes. And it can be electrically surrounded. In particular, the conductive layer 356 and the conductive layer 362 are the same It is preferable to apply an electric potential. This induces a channel in the semiconductor layer 358. Because the electric field can be effectively applied, the on-current of transistor 350B can be increased. Yes, it is possible. Therefore, it becomes possible to miniaturize the 350B transistor.

[0305] Furthermore, the conductive layer 362 and the conductive layer 356 may be configured not to be connected. In this case, one pair A constant potential is applied to one of the gate electrodes, and a signal to drive transistor 350B is applied to the other. You may also give it. At this time, the potential applied to one gate electrode will affect transistor 350 The threshold voltage when driving B with the other gate electrode can also be controlled.

[0306] [Configuration Example 2-4] Figure 27B shows a cross-sectional view of transistor 350C. In Figure 27B, the dashed line... Furthermore, the cross-section in the channel length direction is shown on the left, and the cross-section in the channel width direction is shown on the right, side by side for clarity. ru.

[0307] Transistor 350C is the same as transistor 350A as exemplified in Configuration Example 2-2. This is an example of a case where a conductive layer 356, which functions as a second gate electrode, is provided, as illustrated in -3. .

[0308] This configuration allows for the creation of transistors with high on-current. This can be a transistor capable of controlling the threshold voltage.

[0309] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0310] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0311] (Embodiment 3) In this embodiment, a semiconductor device having a metal oxide film according to one aspect of the present invention is used for fabrication. This section describes an example configuration for a display device.

[0312] Figure 28A is a schematic top view of the display device 700. The display device 700 is flexible. It has a circuit board 762. The circuit board 762 has a display unit 702, a pair of circuit units 763, and a circuit unit 76 4. Wiring 704, connection terminal 703a, and connection terminal 703b are provided.

[0313] Circuit sections 763 and 764 have the function of driving the display section 702. There are two 3s, flanking the display unit 702. The circuit unit 764 is wired to the display unit 702. It is located between 704 and 763. The circuit section 763 functions, for example, as a gate driver. The circuit section 764 has, for example, a source driver, or functions as part thereof. For example, circuit section 764 may include a buffer circuit or a demultiplexer circuit. .

[0314] The display elements provided in the display unit 702 include, for example, liquid crystal elements or light-emitting elements. The various display elements described above can be applied. In particular, organic EL elements can be used as display elements. preferable.

[0315] The circuit board 762 is the portion where the wiring 704, connection terminal 703a and connection terminal 703b are provided. However, it has a top surface shape that protrudes more than other parts. In other words, the part of the substrate 762 The width is smaller than the width of the portion where the display unit 702 is provided.

[0316] Furthermore, the protruding portion of the substrate 762 can be curved in the area where it overlaps with the wiring 704. It has a curved region (curved portion 761a). The substrate 762 also has a region on which the display unit 702 is provided. The region has a pair of regions (curved portion 761b) that can be curved. Figure 28A As shown, the substrate 762 has a protruding shape, which affects the curvature of the curved portion 761a. The direction and the curvature direction of the curved portion 761b can be in intersecting directions.

[0317] The connection terminal 703a is for FPC (Flexible Printed Circuit) It functions as a terminal to be connected, and terminal 703b functions as the terminal to which the IC is connected. .

[0318] Figures 28B and 28C show that in the curved portion 761a and curved portion 761b, opposite to the display surface side. Figure 28B shows a perspective view of the display device 700 when the substrate 762 is curved on the opposite side. Figure 1 is a perspective view including the display side, while Figure 28C is a perspective view including the side opposite to the display side. Also, in Figure 28C, the FPC 706 is connected to connection terminal 703a, and the FPC 706 is connected to connection terminal 703b. The connected IC707 is clearly indicated.

[0319] As shown in Figure 28B, by curving both sides of the display unit 702, the electronic device When incorporating the display device 700 into the device, curved display sections are provided on both sides of the electronic device. Yes, it's possible. This will enable the creation of highly functional electronic devices.

[0320] Furthermore, as shown in Figures 28B and 28C, the curved portion 761a is used to define a part of the substrate 762. It can be folded back to the opposite side from the display side. Specifically, so that wiring 704 is on the outside. The protruding portion of the substrate 762 can be folded back. This allows the connection terminal 703a and the connection The connection terminal 703b can be positioned on the opposite side from the display side, and furthermore, the FPC 706 It can be positioned on the opposite side from the display surface. This allows the display device 700 to be connected to an electronic device. When integrating the system, it becomes possible to reduce the area of ​​the non-displayed parts.

[0321] Furthermore, the substrate 762 is provided with a notch 765. The notch 765 is, for example, Camera lenses, optical sensors and other various sensors, lighting devices, or designs of electronic devices This is the part where the following can be placed. By cutting out a part of the display unit 702, This enables the creation of electronic devices with a more aesthetically pleasing design. Furthermore, it reduces the screen's occupancy on the casing surface. The success rate can be increased.

[0322] [Example of cross-sectional configuration] The following describes an example of a cross-sectional configuration of a display device.

[0323] [Configuration Example 1] Figure 29 shows a schematic cross-sectional view of the display device 700. Figure 29 is the display device shown in Figure 28A. The 700 consists of a display unit 702, a circuit unit 763, a curved unit 761a, and a connection terminal 703a. The cross-section is shown. The display unit 702 is equipped with a transistor 750 and a capacitive element 790. It is being installed. A transistor 752 is provided in circuit section 763.

[0324] Transistors 750 and 752 have an acid in the semiconductor layer where the channel is formed. This is a transistor that uses a synthetic semiconductor. However, it is not limited to this; the semiconductor layer can also be silicon (Amorphous silicon, polycrystalline silicon, or single-crystal silicon) and organic semiconductors The transistor used can also be applied.

[0325] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can significantly reduce the off-current. Therefore, Pixels to which such transistors are applied can have a longer retention time for electrical signals such as image signals, and the image The writing interval for image signals, etc., can also be set to be longer. Therefore, the frequency of refresh operations can be reduced. Therefore, power consumption can be reduced.

[0326] Furthermore, the transistor used in this embodiment is capable of obtaining a relatively high field-effect mobility. Therefore, high-speed operation is possible. For example, a transistor capable of such high-speed operation can be used in a display device. By using it in place, the pixel switching transistor and the driver transistor used in the circuit section are used. The inverter can be formed on the same substrate, that is, formed on a silicon wafer or the like. A configuration that does not apply the specified drive circuit is also possible, which reduces the number of components in the display device. It is possible. Furthermore, by using transistors capable of high-speed operation in the pixels, high image quality can be achieved. I can provide images.

[0327] Capacitive element 790 is made from the same film as the first gate electrode of transistor 750. A lower electrode formed by processing a metal oxide film identical to the semiconductor layer, and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. The upper electrode has the same characteristics as the source and drain regions of transistor 750. The resistance has been reduced. Also, between the lower electrode and the upper electrode, the first of transistor 750 A portion of the insulating film, which functions as the gate insulating layer, is provided. That is, the capacitive element 790 is It has a multilayer structure in which an insulating film, which functions as a dielectric film, is sandwiched between a pair of electrodes. Furthermore, the upper electrode was processed with the same film as the source and drain electrodes of transistor 750. The resulting wiring is connected.

[0328] Furthermore, on transistors 750, 752, and 790, planarization An insulating layer 770 that functions as a film is provided.

[0329] The display unit 702 has a transistor 750, and the circuit unit 763 has a transistor 75 2. A transistor with a different structure may be used. For example, one of them may have a top-gear This configuration uses a T-type transistor on one side and a bottom-gate transistor on the other. This is also acceptable. Furthermore, the same applies to circuit section 764 as to circuit section 763.

[0330] The configuration of transistors 750 and 752 is as described in the above embodiment. We can use point 2.

[0331] The connection terminal 703a has part of the wiring 704. Also, as shown in Figure 29, the connection terminal If 703a has a laminated structure in which multiple conductive films are stacked, the conductivity of the connection terminal 703a This is preferable because it increases mechanical strength. The connection terminal 703a is connected via the connection layer 780 to FP It is electrically connected to C706. The connecting layer 780 is, for example, an anisotropic conductive material. It can be used.

[0332] The display device 700 includes a substrate 762 and a substrate 740, which each function as a support substrate. It has. Substrates 762 and 740 may be, for example, glass substrates or plastic substrates. A flexible substrate such as a plate can be used.

[0333] Transistors 750, 752, and capacitive elements 790 are provided on the insulating layer 744. The substrate 762 and the insulating layer 744 are bonded together by the adhesive layer 742.

[0334] Furthermore, the display device 700 includes a light-emitting element 782, a colored layer 736, a light-shielding layer 738, and the like.

[0335] The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive layer 788. 772 is electrically connected to the source or drain electrode of transistor 750. The conductive layer 772 is provided on the insulating layer 770 and functions as a pixel electrode. An insulating layer 730 is provided covering the end of layer 772, and E is applied to the insulating layer 730 and the conductive layer 772. The L layer 786 and the conductive layer 788 are laminated together.

[0336] The conductive layer 772 can be made of a material that is reflective to visible light. For example, Materials containing aluminum, silver, etc. can be used. In addition, the conductive layer 788 may contain visible Materials that are translucent to light can be used. For example, indium, zinc, tin It is preferable to use an oxide material containing such materials. Therefore, the light-emitting element 782 is on the opposite side from the surface to be formed. This is a top-emission type light-emitting element that emits light towards the substrate 740 side.

[0337] The EL layer 786 contains organic compounds or inorganic compounds such as quantum dots. 86 contains a light-emitting material that emits light when an electric current flows through it.

[0338] Examples of luminescent materials include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (Thermally A ctivated delayed fluorescence (TADF) materials, inorganic Compounds (such as quantum dot materials) can be used. The materials that can be used include colloidal quantum dot materials, alloy quantum dot materials, and core-shell type quantum dot materials. Examples include quantum dot materials and core-type quantum dot materials.

[0339] The light-shielding layer 738 and the colored layer 736 are provided on one side of the insulating layer 746. 736 is located in a position that overlaps with the light-emitting element 782. Also, the light-shielding layer 738 is In section 702, it is provided in an area that does not overlap with the light-emitting element 782. Also, the light-shielding layer 73 8 may also be provided on top of the circuit section 763, etc.

[0340] The substrate 740 is bonded to the other side of the insulating layer 746 by an adhesive layer 747. Furthermore, substrate 740 and substrate 762 are bonded together by a sealing layer 732.

[0341] Here, the EL layer 786 of the light-emitting element 782 is a light-emitting material that exhibits white light emission. This is applied. The white light emitted by the light-emitting element 782 is colored by the colored layer 736. It is then emitted to the outside. The EL layer 786 is provided across pixels exhibiting different colors. A colored layer 7 that transmits either red (R), green (G), or blue (B) is provided in part 702. By arranging the pixels with 36 in a matrix, the display device 700 displays full color It is possible to display this.

[0342] Furthermore, a conductive film having transparency and reflectivity may be used as the conductive layer 788. This enables the realization of a microcavity structure between conductive layer 772 and conductive layer 788. Furthermore, it is possible to configure it to intensify and emit light of a specific wavelength. Also, in this case, the conductive layer 7 An optical adjustment layer is placed between 72 and the conductive layer 788 to adjust the optical distance, and the optical adjustment By varying the thickness of the layer between pixels of different colors, the light emitted from each pixel... A configuration that enhances color purity is also acceptable.

[0343] Furthermore, the EL layer 786 is formed in an island-like pattern for each pixel or in a striped pattern for each row of pixels, i.e., color separation. When formed by this method, the colored layer 736 and the optical adjustment layer described above are not provided. That is also acceptable.

[0344] Here, insulating layer 744 and insulating layer 746 each function as a barrier film with low moisture permeability. It is preferable to use an inorganic insulating film. Between such insulating layer 744 and insulating layer 746 By having a configuration in which the light-emitting element 782 and transistor 750 are sandwiched, these inferior This suppresses degradation and enables the realization of highly reliable display devices.

[0345] [Configuration Example 2] Figure 30 shows a cross-sectional view of the display device 700, which has some configuration differences from Figure 29. Furthermore, in Figure 30, a part of the display device 700 is curved at the curved portion 761a, and the display surface side is curved. It clearly shows the form that has been folded back on the opposite side.

[0346] The display device 700 shown in Figure 30 is located between the adhesive layer 742 and the insulating layer 744 shown in Figure 29. A resin layer 743 is provided. In addition, a protective layer 749 is provided instead of the substrate 740.

[0347] The resin layer 743 is a layer containing organic resins such as polyimide and acrylic. Insulating layer 744 This includes an inorganic insulating film such as silicon oxide, silicon oxide nitride, and silicon nitride. Resin layer 74 3 and the substrate 762 are bonded together by an adhesive layer 742. The resin layer 743 is the substrate It is preferable that it be thinner than 762.

[0348] The protective layer 749 is bonded to the sealing layer 732. The protective layer 749 is made of glass. A substrate or resin film can be used. Also, as the protective layer 749, a polarizing plate (circular Optical components such as polarizing plates, scattering plates, input devices such as touch sensor panels, or A configuration in which two or more of these are stacked may also be applied. In addition, the protective layer 749 is the casing of the electronic device. It may include components that constitute a part of the body (for example, the part that becomes the screen).

[0349] Furthermore, the EL layer 786 of the light-emitting element 782 has islands on the insulating layer 730 and the conductive layer 772. It is arranged in a certain manner. The EL layer 786 is made so that the light-emitting color differs for each sub-pixel. Therefore, color display can be achieved without using the colored layer 736.

[0350] Furthermore, a protective layer 741 is provided covering the light-emitting element 782. The protective layer 741 emits light. The element 782 has a function to prevent impurities such as water from diffusing into it. The protective layer 741 is conductive. Insulating layer 741a, insulating layer 741b, and insulating layer 741c are laminated in this order from the layer 788 side. It has a laminated structure. At this time, the insulating layer 741a and insulating layer 741c are filled with water, etc. An inorganic insulating film with high barrier properties against impurities is used, and the insulating layer 741b functions as a planarization film. It is preferable to use organic insulating films for each. Also, the protective layer 741 is the circuit section 763 It is preferable that it extends to the following areas as well.

[0351] Furthermore, inside the sealing layer 732, transistors 750 and 752, etc. It is preferable that the organic insulating film covering the is formed in an island-like manner. In other words, the organic insulating film The end is located inside the sealing layer 732, or in a region that overlaps with the end of the sealing layer 732. Preferred. In Figure 30, insulating layer 770, insulating layer 730, and insulating layer 741b are added in an island-like manner. An example of the construction is shown. For example, in the part that overlaps with the sealing layer 732, the insulating layer 741c and An insulating layer 741a is provided in contact with the transistor 750 and the transistor The surface of the organic insulating film covering the sta 752 is configured so that it is not exposed to the outside of the sealing layer 732. As a result, water can enter transistors 750 and 752 from the outside through the organic insulating film. This effectively prevents hydrogen from diffusing. This improves the electrical characteristics of the transistor. This suppresses fluctuations and enables the creation of an extremely reliable display device.

[0352] Furthermore, in Figure 30, the curved portion 761a has an insulating layer in addition to the substrate 762 and adhesive layer 742. It has portions where inorganic insulating films such as 744 are not provided. Also, in the curved portion 761a, To prevent the wiring 704 from being exposed, an insulating layer 770 containing organic material covers the wiring 704. It has the following configuration. In the configuration shown in Figure 30, the curved portion 761a is made up of a resin layer 743 and wiring 7 It has a laminated structure in which 04 and an insulating layer 770 are stacked.

[0353] The curved portion 761a should have as little inorganic insulating film as possible, and should contain a conductive material including metal or alloy. By constructing a structure consisting only of layers and layers containing organic materials, cracks will occur when bent. This can prevent this. Also, by not providing the substrate 762 on the curved portion 761a, it is possible to make it extremely small The radius of curvature allows a portion of the display device 700 to be bent.

[0354] Furthermore, in the region overlapping with the connection terminal 703a, the resin layer 743 is connected via an adhesive layer 748. The support 720 is then bonded to it. The support 720 has higher rigidity than the substrate 762, etc. Materials can be used. Alternatively, the support 720 may be part of the housing of an electronic device, or an electric device. It may be part of a component located inside a sub-device.

[0355] Furthermore, in Figure 30, a conductive layer 761 is provided on the protective layer 741. 61 can be used as wiring or an electrode.

[0356] Furthermore, the conductive layer 761 is used when a touch sensor is placed on top of the display device 700. Electrostatic shielding to prevent electrical noise generated during the operation of the element from being transmitted to the touch sensor. It can function as a protective film. At this time, a predetermined constant potential is applied to the conductive layer 761. It should be configured in such a way.

[0357] Alternatively, the conductive layer 761 can be used, for example, as an electrode for a touch sensor. This allows the display device 700 to function as a touch panel. For example, conductive layer 761 can be used as an electrode or wiring for a capacitive touch sensor. At that time, the conductive layer 761 is connected to the wiring or electrodes to which the detection circuit is connected, and to which the sensor signal is input. It can be used as wiring or electrodes that touch the light-emitting element 782. By developing sophisticated sensors, the number of parts can be reduced, thereby lowering the manufacturing costs of electronic devices and other equipment. It is possible.

[0358] The conductive layer 761 is preferably provided in a portion that does not overlap with the light-emitting element 782. The conductive layer 761 can be provided in a position that overlaps with the insulating layer 730. As layer 761, there is no need to use a transparent conductive film with relatively low conductivity, and a highly conductive metal is used instead. Because materials such as alloys can be used, the sensitivity of the sensor can be increased.

[0359] Furthermore, the types of touch sensors that can be constructed using the conductive layer 761 include electrostatic Not limited to capacitive methods, but also include resistive, surface acoustic wave, infrared, optical, and pressure-sensitive methods. Various methods can be used. Alternatively, two or more of these can be combined. stomach.

[0360] [Configuration Example 3] Figure 31 shows a schematic cross-sectional view of the display device 700a when a liquid crystal element is used as the display element. This is shown. Figure 31 includes the circuit section 763, the display section 702, and the connection terminal 703a. This shows a cross-sectional view of the region.

[0361] The display device 700a shown in Figure 31 has a transistor 7 between substrate 701 and substrate 705. It has 21, transistor 722, liquid crystal element 710, etc. Substrate 701 and substrate 705 are, It is bonded by a sealing layer 732.

[0362] Here, transistors 721 and 722 are bottom-gate type transistors. This shows the case when ZISTA is applied.

[0363] The liquid crystal element 710 has a conductive layer 711, liquid crystal 712, and a conductive layer 713. 13 is provided on the substrate 701. One or more insulating layers are provided on the conductive layer 713, and the insulating layer A conductive layer 711 is provided on the edge layer. The liquid crystal 712 is connected to the conductive layer 711 and the substrate 7 It is located between 05. The conductive layer 713 is electrically connected to the wiring 723 and serves as a common electrode. It works. The conductive layer 711 is electrically connected to the transistor 721 and functions as a pixel electrode. It is possible. A common potential is applied to wiring 723.

[0364] The liquid crystal element 710 shown in Figure 31 is a liquid crystal to which a transverse electric field method (for example, FFS mode) is applied. It is a crystalline element. The conductive layer 711 has a comb-like or slit-like upper surface shape. The crystal element 710 reacts to the electric field generated between the conductive layer 711 and the conductive layer 713, causing the liquid crystal 712 to form. The orientation state is controlled.

[0365] Furthermore, the laminated structure of conductive layer 711, conductive layer 713, and one or more insulating layers sandwiched therebetween them Due to the construction, a capacitive element 790 that functions as a holding capacitance is formed. Therefore, a separate volume This eliminates the need for a quantitative element and allows for a higher aperture ratio.

[0366] The conductive layer 711 and the conductive layer 713 are made of a material that is transparent to visible light, or a material that is transparent to visible light. Translucent materials can be used. Examples of translucent materials include indium, zinc, It is preferable to use oxide materials containing tin, etc. For example, aluminum is a good reflective material. It is advisable to use materials containing silver, etc.

[0367] A reflective material is used in either the conductive layer 711 or the conductive layer 713, or in both. Thus, the display device 700a becomes a reflective liquid crystal display device. Meanwhile, conductive layer 711 and conductive layer 7 If light-transmitting materials are used for both of 13, the display device 700a becomes a transmissive liquid crystal display device. In the case of reflective liquid crystal display devices, a polarizing plate is provided on the viewing side. On the other hand, transmissive liquid crystal display devices In this case, a pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0368] Figure 31 shows an example of a transmissive liquid crystal display device. Polarized light is located outside the substrate 701. A plate 755 and a light source 757 are provided, and a polarizing plate 756 is provided outside the substrate 705. The light source 757 functions as a backlight.

[0369] A light-shielding layer 738 and a colored layer 736 are provided on the surface of the substrate 705 that faces the substrate 701. Furthermore, an insulating layer 734 covers the light-shielding layer 738 and the colored layer 736 and functions as a planarizing layer. A spacer 727 is provided on the substrate 701 side of the insulating layer 734. Yes, they are.

[0370] Furthermore, the liquid crystal 712 includes an alignment film 725 covering the conductive layer 711 and an alignment film covering the insulating layer 734. It is located between 726. Note that the alignment film 725 and alignment film 726 can be omitted if they are not needed. You don't have to.

[0371] Also, although not shown in Figure 31, a phase difference film and an anti-reflective film are placed outside the substrate 705. Appropriately provide optical components such as films (optical films), protective films, anti-fouling films, etc. It is possible. Anti-reflective films include AG (Anti Glare) film, A Examples include R (Anti-Reflection) film.

[0372] Liquid crystal 712 includes thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, and polymer dispersed liquid crystals. (PDLC: Polymer Dispersed Liquid Crystal), Polymer Network Liquid Crystal (PNLC) Crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When employing an electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0373] Furthermore, the liquid crystal element mode is TN (Twisted Nematic) mode. VA (Vertical Alignment) mode, IPS (In-Plane-S) witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optically Compensated Biref ringence) mode, ECB (Electrically Controlled) You can use modes such as Birefringence mode and Guest Host mode. .

[0374] Furthermore, the liquid crystal 712 uses polymer dispersed liquid crystals, polymer network liquid crystals, etc. A randomly shaped liquid crystal can also be used. In this case, a structure that displays in black and white without providing a colored layer 736 can be used. Alternatively, the structure may be configured to display color using a colored layer 736.

[0375] Furthermore, as a method for driving liquid crystal elements, color display is performed based on the time additive color mixing method. A split-screen display method (also known as a field-sequential drive method) may be applied. In addition, a configuration without a colored layer 736 is possible. When using a time-division display method, For example, it is necessary to provide subpixels that exhibit the respective colors R (red), G (green), and B (blue). Because it lacks certain features, it offers advantages such as improved pixel aperture ratio and increased resolution.

[0376] The display device 700a shown in Figure 31 includes a conductive layer 711 that functions as a pixel electrode, and a common electrode. An organic insulating film, which functions as a planarizing layer, is provided on the side of the conductive layer 713 that is formed. It has a configuration that does not exist. Also, as transistors 721 etc. in the display device 700a, A bottom-gate transistor is used, which allows for a relatively short manufacturing process. Also, wiring 7 04. Connection terminals 703a, etc., can be used to connect transistors, liquid crystal elements, etc. without adding any special processes. It can be manufactured using the same process as the manufacturing process. It can reduce stress, increase manufacturing yield, and provide a reliable display device at a low cost. It will become possible to provide it.

[0377] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0378] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0379] (Embodiment 4) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figure 32A. Further explanation will be provided using Figure 32C.

[0380] The display device shown in Figure 32A comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0381] Transistors in the pixel section 502 and the drive circuit section 504 are configured according to one aspect of the present invention. A transistor can be applied. Also, a transistor according to one aspect of the present invention can be applied to the protection circuit 506. You may apply this.

[0382] The pixel section 502 is arranged in X rows and Y columns (where X and Y are independent natural numbers greater than or equal to 2). It has several pixel circuits 501. Each pixel circuit 501 is a circuit that drives a display element. To possess.

[0383] The drive circuit section 504 outputs a scanning signal to the gate lines GL_1 to GL_X. Source driver 504a, which supplies data signals to data lines DL_1 to DL_Y. It has a drive circuit such as 04b. The gate driver 504a has at least a shift register The configuration should include, for example, multiple analog switches. It is constructed using switches, etc. Furthermore, it uses shift registers, etc., to configure the source driver 504 You may also construct b.

[0384] The terminal section 507 inputs power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0385] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires. The protection circuit 506 shown in Figure 32A is, for example, For example, the gate line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, or - Various wirings such as data lines DL, which are the wiring between driver 504b and pixel circuit 501. It continues. Note that in Figure 32A, in order to distinguish between the protection circuit 506 and the pixel circuit 501, protection Circuit 506 is hatched.

[0386] Furthermore, the gate driver 504a and the source driver 504b are connected to the pixel section 502 and They may be provided on the same board, or the gate driver circuit or source driver circuit may be A separately formed substrate (for example, a drive circuit base formed of a single-crystal semiconductor or polycrystalline semiconductor) The board is made into a circuit board using COG or TAB (Tape Automated Bonding). It may also be implemented in this configuration.

[0387] Figures 32B and 32C show one of the pixel circuit configurations that can be applied to the pixel circuit 501. Here is an example.

[0388] The pixel circuit 501 shown in Figure 32B consists of a liquid crystal element 570, a transistor 550, and a capacitance element. It has a sub-unit 560 and a gate line GL_m. The pixel circuit 501 also has a data line DL_n and a gate line GL_m The potential supply line VL and other connections are connected.

[0389] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 in each row One of the electrodes may be given a different potential.

[0390] Furthermore, the pixel circuit 501 shown in Figure 32C includes transistor 552 and transistor 554 It also has a capacitive element 562 and a light-emitting element 572. The pixel circuit 501 also has data Line DL_n, gate line GL_m, potential supply line VL_a, and potential supply line VL_b are connected. It is being done.

[0391] Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied to the gate of transistor 554. Depending on the potential, the current flowing through the light-emitting element 572 is controlled, thereby controlling the light-emitting element 5 The luminescence is controlled from 72 onwards.

[0392] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0393] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0394] (Embodiment 5) Below, we have a pixel circuit equipped with memory for correcting the gradation displayed in the pixel, and this The display device having the metal oxide film exemplified in Embodiment 1 will be described. ZISTA can be applied to transistors used in the pixel circuits exemplified below.

[0395] [Circuit Configuration] Figure 33A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 consists of transistor M1, It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 also has wiring S1, wiring S2, wiring G1, and wiring G2 are connected.

[0396] Transistor M1 has its gate connected to wiring G1, and one of its sources or drains connected to wiring S1. The other end is connected to one electrode of capacitance C1. Transistor M2 has a gate that is wired G2, one of the source and drain is connected to wiring S2, the other electrode is connected to capacitance C1, and rotation It connects to Route 401, respectively.

[0397] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While children can be used, typical examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystals. Device, or MEMS (Micro Electro Mechanical System) EMS elements and the like can be applied.

[0398] The node connecting transistor M1 and capacitor C1 is node N1, and the node connecting transistor M2 and... Let node N2 be the node connecting to path 401.

[0399] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. It can be maintained. Also, by turning off transistor M2, the power of node N2 can be controlled. It can maintain its position. Also, with transistor M2 in the OFF state, By writing a predetermined potential to node N1 via station M1, capacitive coupling via capacitor C1 is achieved. This allows the potential of node N2 to be changed in accordance with the potential displacement of node N1.

[0400] Here, in the embodiment, one or both of transistors M1 and M2 are The transistor using oxide semiconductors, as exemplified in 1, can be applied. Therefore, the extremely low off-current maintains the potential of nodes N1 and N2 for a long period of time. This is possible. However, if the period for which the potential of each node is maintained is short (specifically, the frame When the frequency is 30Hz or higher, a transistor using a semiconductor such as silicon is used. You may also use "ta".

[0401] [Example of driving method] Next, an example of how the pixel circuit 400 operates will be explained using Figure 33B. This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and transistors The effects of the threshold voltage of the staccato are not considered.

[0402] In the operation shown in Figure 33B, one frame period is divided into period T1 and period T2. Period T1 Period T2 is the period during which the potential is written to node N2, and period N1 is the period during which the potential is written to node N1. That is the case.

[0403] [Period T1] During period T1, a potential is applied to both wire G1 and wire G2 that turns the transistor ON. Also, the wiring S1 has a constant potential V ref The first data is supplied to wiring S2. Potential V w To supply.

[0404] Node N1 receives a potential V from wiring S1 via transistor M1. ref It is given. Furthermore, node N2 receives the first data potential V from wiring S2 via transistor M2. w is given Therefore, a potential difference V can be obtained across capacitance C1. w -V ref This state is maintained.

[0405] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and The wire G2 is given a potential that turns off transistor M2. Also, the wiring S1 is supplied with the second diode DATA potential V data It supplies a predetermined constant potential to the wiring S2, or a floating It may also be in a ling state.

[0406] Node N1 receives a second data potential V from wiring S1 via transistor M1. data but Given. At this time, the second data potential V is generated by capacitive coupling with capacitance C1. data in response Then the potential of node N2 changes by a potential of dV. That is, circuit 401 receives the first data Potential V w The input will be the sum of the potential dV and the potential dV. Note that in Figure 33B, the potential dV Although it is shown to be a positive value, it may also be a negative value. That is, the second data potential. V data The potential is V ref It can be lower.

[0407] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second dV. DATA potential V data The potential will be close to that.

[0408] Thus, the pixel circuit 400 combines two types of data signals to form a display element. Since it is possible to generate the potential supplied to path 401, grayscale correction can be performed within the pixel circuit 400. It becomes possible to do so.

[0409] Furthermore, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to wiring S1 and wiring S2. It also becomes possible to achieve this. For example, when using light-emitting elements, high dynamic range ( It can display HDR (High Dynamic Range) and other functions. Furthermore, when using liquid crystal elements, overdrying can be performed. It can implement features such as drive mechanisms.

[0410] [Examples of application] [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 33C has circuit 401LC. Circuit 401LC is It has a liquid crystal element LC and a capacitance C2.

[0411] In a liquid crystal element (LC), one electrode is the electrode of node N2 and capacitance C2, and the other electrode is Potential V com2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Connect to the provided wiring.

[0412] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed. Cut.

[0413] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example High-speed display is achieved through overdrive operation, and high-voltage liquid crystal materials are applied. It is possible to do things like this. Also, by supplying a correction signal to wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the degradation state of the liquid crystal elements (LC).

[0414] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 33D has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0415] Transistor M3 has a gate that connects to one electrode of node N2 and capacitance C2, and a source and a dot. One side of Rain has a potential of V H One is a wire that is given, and the other is one electrode of the light-emitting element EL, and They are connected. Capacitor C2 is connected when the other electrode is at potential V com Connect to the provided wiring. In the light-emitting element (EL), the other electrode is at potential V. L Connect to the provided wiring.

[0416] Transistor M3 has the function of controlling the current supplied to the light-emitting element EL. Capacitor C2 This functions as a holding capacity. Capacity C2 can be omitted if it is not needed.

[0417] Note that this configuration shows the anode side of the light-emitting element EL connected to transistor M3. However, transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0418] The pixel circuit 400EL generates light by applying a high potential to the gate of transistor M3. Because it can supply a large current to the sub-EL, it can enable features such as HDR display. It can be done. Also, by supplying a correction signal to wiring S1 or wiring S2, transistor M3 and It is also possible to correct for variations in the electrical characteristics of light-emitting elements (ELs).

[0419] Note that the circuits are not limited to those illustrated in Figures 33C and 33D, and may also include transistors, capacitors, etc. This could also be considered an added configuration.

[0420] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0421] (Embodiment 6) In this embodiment, a display module that can be manufactured using one aspect of the present invention is provided. I will explain.

[0422] The display module 6000 shown in Figure 34A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006, frame 6009, and print, with the FPC6005 connected. It has a circuit board 6010 and a battery 6011.

[0423] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of an extremely low-power display module. It is possible.

[0424] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as needed.

[0425] The display device 6006 may also have the functionality of a touch panel.

[0426] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0427] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It has a processing circuit, a battery control circuit, etc.

[0428] Figure 34B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. ru.

[0429] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0430] The display device 6006 connects to the printed circuit board 6010 and the battery via the frame 6009. - It is installed overlapping with 6011. The display device 6006 and frame 6009 are connected to the light guide section 6 017a is fixed to the light guide section 6017b.

[0431] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 600. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or a stand Touch operation is detected when light 6018 is blocked by an object to be detected, such as an illustration. It is possible.

[0432] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0433] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0434] The light-emitting section 6015 and the light-emitting section 6015 are separated by the light-transmitting light-emitting section 6017a and light-transmitting section 6017b. The light receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light receiving unit 601 Reaching 6 can suppress the malfunction of the touch sensor. In particular, it absorbs visible light and infrared light. Using a resin that allows light to pass through can more effectively suppress malfunctions in touch sensors.

[0435] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0436] (Embodiment 7) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0437] The electronic device 6500 shown in Figure 35A is a portable device that can be used as a smartphone. It is a news terminal device.

[0438] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0439] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0440] The display unit 6502 has a notch, and the camera 6507 engages with the notch. And a light source 6508 is provided. With this configuration, the housing 6501 This allows for a larger occupied area of ​​the display unit 6502.

[0441] Furthermore, Figure 35B shows that the display unit 6502 has an opening, and inside the opening is the camera 6507 and This shows an example where a ring-shaped light source 6509 is arranged around camera 6507. Also, The speaker 6505 is provided so as to engage with the notch of the display unit 6502. The display unit 6502 may also be used as a light source to illuminate the subject. This allows the display unit 6502 to occupy a larger area relative to the housing 6501.

[0442] Figure 35C is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0443] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0444] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0445] Furthermore, in the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is done. Furthermore, the FPC6515 is connected to the folded portion. IC6516 is mounted on the 6515. Also, the FPC6515 is printed circuit board 6 It is connected to the terminal provided at 517.

[0446] A flexible display panel according to one aspect of the present invention is applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 651 Because it is extremely thin, it allows for a reduction in the thickness of electronic devices while incorporating a large-capacity 6518 battery. It is also possible to fold back a portion of the display panel 6511 and place an FPC on the back of the pixel area. By positioning the connection point with 6515, it is possible to realize electronic devices with narrow bezels.

[0447] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0448] (Embodiment 8) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0449] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0450] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0451] Examples of electronic devices include television equipment, notebook personal computers, Equipped with relatively large screens such as monitors, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and portable devices are also available. Examples include mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0452] An electronic device to which one aspect of the present invention is applied includes the interior or exterior walls of houses and buildings, the interior of automobiles, etc. It can be incorporated along the flat or curved surfaces of the fittings or exterior.

[0453] Figure 36A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. That is the case.

[0454] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0455] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0456] Camera 8000 can be operated by pressing the shutter button 8004, or by using the touch panel function. Image capture can be performed by touching the display unit 8002.

[0457] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, it also has a strobe It can be connected to devices such as power supply units.

[0458] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0459] The housing 8101 engages with the mount of the camera 8000 via a mount, and the camera 800 It is attached to the 0. The viewfinder 8100 receives images and other data from the camera 8000. This can be displayed on the display unit 8102.

[0460] Button 8103 functions as a power button, etc.

[0461] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied. Note that a camera with a built-in viewfinder can also be used. It could also be 8000.

[0462] Figure 36B shows the external appearance of the head-mounted display 8200.

[0463] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0464] Cable 8205 supplies power from battery 8206 to main unit 8203. Unit 203 is equipped with a wireless receiver and can display the received video information on the display unit 8204. It can do that. Furthermore, the main unit 8203 is equipped with a camera that inputs information about the user's eyeball and eyelid movements. It can be used as a step.

[0465] Furthermore, the attachment part 8201 is positioned in a location that touches the user, and the flow follows the movement of the user's eyeballs. Multiple electrodes capable of detecting currents may be provided, and the device may also have a function to recognize line of sight. Furthermore, the device may have a function to monitor the user's pulse rate based on the current flowing through the electrode. Furthermore, the mounting section 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It is also possible to have a function that displays the user's biometric information on the display unit 8204, and the user's head The display unit 8204 may also have a function to change the image displayed in accordance with the movement.

[0466] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0467] Figures 36C, 36D, and 36E show the appearance of the head-mounted display 8300. This is a diagram. The head-mounted display 8300 consists of a housing 8301 and a display unit 8302. It comprises a band-shaped fastener 8304 and a pair of lenses 8305.

[0468] The user can view the display on the display unit 8302 through the lens 8305. Furthermore, by arranging the display unit 8302 in a curved shape, the user can experience a high level of realism. This is preferable. Also, another image displayed in a different area of ​​the display unit 8302 is displayed by the lens 8 By viewing through the 305, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one display unit 8302, but can also have two display units 8302, allowing one of the users to... One display unit may be placed for each eye.

[0469] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. A display device having a semiconductor device according to one embodiment has extremely high resolution, as shown in Figure 36E. Even when magnified using lens 8305, the user cannot see the individual pixels, resulting in a more detailed view. It can display highly realistic images.

[0470] The electronic equipment shown in Figures 37A to 37G consists of a housing 9000, a display unit 9001, and a speaker 9 003, Operation key 9005 (including power switch or operation switch), Connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, Magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity (Including functions for measuring degrees, inclines, vibrations, odors, or infrared radiation), Microphone 900 8, etc.

[0471] The electronic devices shown in Figures 37A to 37G have various functions. For example, various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function that displays the date or time, etc., through various software (programs) Functions that control processing, wireless communication functions, programs or data recorded on recording media It can have functions such as reading and processing data. Furthermore, the functions of electronic devices are related to these. It is not limited and can have a variety of functions. Even if an electronic device has multiple display units Good. Also, an electronic device can be equipped with a camera, etc., to take still images and videos, and the recording medium (external or It has features such as saving to the camera (built-in), and displaying the captured image on the display unit. That's good too.

[0472] Details of the electronic equipment shown in Figures 37A to 37G will be explained below.

[0473] Figure 37A is a perspective view showing the television equipment 9100. 0 is a display unit 9001 with a large screen, for example, 50 inches or larger, or 100 inches or larger. It is possible to insert it.

[0474] Figure 37B is a perspective view showing the personal digital assistant 9101. The personal digital assistant 9101 is, for example, For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speed A connector (9003), connection terminal (9006), sensor (9007), etc. may be provided. Also, a portable information terminal may be provided. The 9101 can display text and image information on its multiple surfaces. Figure 37B shows three of them. This shows an example of displaying icon 9050. Also, information 9051, indicated by a dashed rectangle, is shown. The information can also be displayed on other sides of the display unit 9001. An example of information 9051 is electronic data. Notifications for incoming calls, SNS messages, and phone calls; subject, sender name, and date / time for emails and SNS messages. This includes the time, battery level, and antenna signal strength. Alternatively, information 9051 is displayed. You may display an icon such as 9050 in the indicated location.

[0475] Figure 37C is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is a table The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where information 9053 and information 9054 are displayed on different sides. For example, the user With the mobile information terminal 9102 stored in the breast pocket of his clothing, the mobile information terminal 9102 Information 9053, displayed in a position visible from above, can also be viewed. The user can, You can check the display without taking the 9102 personal digital assistant out of your pocket, for example, to answer a phone call. It is possible to determine whether or not to do so.

[0476] Figure 37D is a perspective view showing a wristwatch-type personal information terminal 9200. Personal information terminal 92 00 can be used, for example, as a smartwatch. Also, the display unit 9001 is The display surface is curved, allowing the display to follow the curved surface. The personal information terminal 9200 communicates with, for example, a wireless communication headset. It also allows for hands-free calling. Furthermore, the 9200 mobile information terminal has a connection terminal 9 006 allows for mutual data transmission with other information terminals and also enables charging. Charging may also be performed via wireless power supply.

[0477] Figures 37E, 37F, and 37G are perspective views showing a foldable portable information terminal 9201. Figure 37E shows the mobile information terminal 9201 in its unfolded state, and Figure 37G shows it in its folded state. Figure 37F is a perspective view of the state in the process of changing from one of Figures 37E and 37G to the other. The 9201 personal digital assistant offers excellent portability when folded and seamless when unfolded. The wide display area without visible pixels provides excellent readability of the display. (Display features of the 9201 mobile information terminal) The section 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. .

[0478] Figure 38A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0479] The television device 7100 shown in Figure 38A is operated by the operation switches provided on the housing 7101. This can be done by using the remote control unit 7111 or by using the display unit 7500. A touch panel can be applied to it, allowing the television device 7100 to be operated by touching it. The remote control unit 7111 may have a display unit in addition to the operation buttons.

[0480] The television equipment 7100 is a television broadcast receiver and for network connectivity. It may have a communication device.

[0481] Figure 38B shows the 7200 notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0482] Figures 38C and 38D show digital signage. An example of a sign is shown.

[0483] The digital signage 7300 shown in Figure 38C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0484] Figure 38D shows a digital signage 7400 mounted on a cylindrical column 7401. Yes. The digital signage 7400 has a display unit 75 that is installed along the curved surface of the column 7401. It has 00.

[0485] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0486] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows for use not only in advertising but also in route information, traffic information, and commercial facility information. It can also be used to provide information that users are seeking.

[0487] Furthermore, as shown in Figures 38C and 38D, the Digital Signage 7300 or Digital The Signage 7400 communicates wirelessly with the user's smartphone or other information terminal 7311. It is preferable that communication is possible. For example, the advertisement displayed on the display unit 7500 To display information on the screen of the information terminal 7311, and to operate the information terminal 7311. This allows you to switch the display on the 7500 display unit.

[0488] Additionally, information terminals can be connected to the Digital Signage 7300 or Digital Signage 7400. It is also possible to run games using the 7311 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0489] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 38A to 38D. It is possible.

[0490] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied. [Examples]

[0491] In this example, a transistor is fabricated using a metal oxide film according to one aspect of the present invention, and We will now explain the results of the evaluation of the electrical characteristics.

[0492] [Sample preparation] The configuration of the fabricated transistor is illustrated in Configuration Example 2-3 of Embodiment 2 and in Figure 27A. A 350B transistor can be used.

[0493] First, a tungsten film with a thickness of approximately 100 nm is formed on a glass substrate using the sputtering method. This was then processed to obtain the first gate electrode. Subsequently, as the first gate insulating layer, nitrogen A laminated film with a thickness of approximately 300 nm, consisting of a silicon oxide film and a silicon oxidizide film, is used in Plasma Formed by the CVD method.

[0494] Next, a metal oxide film with a thickness of approximately 30 nm is formed on the first gate insulating layer, and this is then processed. A semiconductor layer was obtained by processing. The metal oxide film had an atomic ratio of metal elements of In:Ga:Zn=4: The shape is formed by sputtering using a metal oxide target with an atomic ratio of 2:4.1. Success. A mixed gas of argon and oxygen was used as the film deposition gas. Here, metal Four samples (Sample B1 to Sample B) with different oxide film deposition conditions. 4) was created.

[0495] The metal oxide film of Sample B1 is formed as a percentage of the oxygen gas flow rate relative to the total flow rate of the film-forming gas. The film was deposited under conditions where the oxygen flow rate ratio was 10%. Furthermore, the film deposition was performed without heating the substrate. went.

[0496] The metal oxide film of Sample B2 was deposited under conditions where the oxygen flow rate ratio was 30%. The film deposition was performed without heating the substrate.

[0497] The metal oxide film of Sample B3 was deposited under conditions where the oxygen flow rate ratio was 40%. The film deposition was performed without heating the substrate.

[0498] The metal oxide film of Sample B4 was deposited under conditions where the oxygen flow rate ratio was 50%. The film deposition was performed without heating the substrate.

[0499] The metal oxide films of Sample B1 to Sample B4 are, respectively, in the form described above. Under the same conditions as the metal oxide films of samples A1 to A4 shown in state 1, the shape It was accomplished.

[0500] After the semiconductor layer is formed, it is heated at 350°C for 1 hour under a nitrogen gas atmosphere, and then nitrogen The sample was heated at 350°C for 1 hour in a mixed atmosphere of elementary gas and oxygen gas.

[0501] Next, a silicon oxide nitride film with a thickness of approximately 150 nm is used as the second gate insulating layer. The film was deposited using the CVD method.

[0502] Next, a metal oxide layer approximately 20 nm thick is applied to the second gate insulating layer by sputtering. A metal film was deposited. For metal oxide film deposition, the atomic ratio of the metal elements is In:Ga:Zn=4: The process was carried out using a metal oxide target with an atomic ratio of 2:4.1 under an oxygen-containing atmosphere. Subsequently, the material was heat-treated at 350°C for 1 hour in a nitrogen-containing atmosphere.

[0503] Next, a molybdenum film with a thickness of approximately 100 nm is applied to the metal oxide film by sputtering. The film was formed. Subsequently, the molybdenum film and a portion of the metal oxide film were removed by etching, and the second A gate electrode and a metal oxide layer were obtained.

[0504] Next, using the second gate electrode as a mask, boron was added as an impurity element. The addition of impurities was performed using a plasma ion doping device. B2H6 gas was used as the gas.

[0505] Next, a silicon oxide-nitride layer approximately 300 nm thick is used as a protective insulating layer covering the transistor. The film was deposited by plasma CVD. Subsequently, a protective insulating layer and a second gate insulating layer were formed. After opening the area by etching and depositing a molybdenum film by sputtering, The material was processed to obtain the source electrode and drain electrode. Then, a planarization layer with a thickness of approximately 1.5 μm was applied. An acrylic film of thickness m was formed and subjected to heat treatment at 250°C for 1 hour under a nitrogen atmosphere.

[0506] Through the above process, Sam has transistors formed on a glass substrate. Sample B1 to Sample B4 were obtained.

[0507] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated as described above were measured.

[0508] The measurement conditions for the Id-Vg characteristics of a transistor are as follows: gate electrode (first gate electrode and The voltage applied to the gate (and second gate electrode) (also called the gate voltage (Vg)) is set from -15V to The voltage applied was increased in 0.25V increments up to +20V. Also, the voltage applied to the source electrode (source voltage) was measured. (Also called Vs) is set to 0V, and the voltage applied to the drain electrode (drain voltage (Vd) and The voltages (also known as) were set to 0.1V and 10V.

[0509] Furthermore, the measured transistor had a design value of a channel length of 2 μm and a channel width of 3 μm. I made it a 'njista'.

[0510] Figures 39A to 39D show the Id-Vg characteristics of Sample B1 to Sample B4. This shows the properties. In each figure, the horizontal axis is the gate voltage (Vg) and the vertical axis is the drain current (Id The figures also show the Id-Vg characteristics when the drain voltage (Vd) is 10V. The dashed line shows the field-effect mobility (μFE) calculated from the above.

[0511] As shown in Figures 39A to 39D, good electrical characteristics were obtained for all samples. It was confirmed that this is possible. From this, it can be concluded that a transient using a metal oxide film according to one embodiment of the present invention Even if there are variations in the film deposition conditions (especially the oxygen flow rate ratio) for the metal oxide film, the electrical characteristics The impact on quality was suggested to be minimal, and it was confirmed that it is highly productive for mass production.

[0512] [Reliability Assessment] Next, we will evaluate the reliability of Sample B1 to Sample B4 mentioned above. To evaluate reliability, a gate bias stress test (GBT test) was performed. The T test involves keeping the substrate on which the transistor is formed at 60°C, and the source of the transistor... Apply 0V to the drain and 20V or -20V to the gate, and maintain this state for one hour. The results were maintained. Here, in particular, the results of the PBTS and NBTIS trials are presented. In NBTIS, the illumination was provided using white LED light with an output of approximately 3400 lux. The transistor measured was a transistor with a design specification of channel length 2 μm and channel width 3 μm. That's what I decided.

[0513] Figure 40 shows the PBTS test and N in Samples B1 to B4. The change in threshold voltage (ΔVth) before and after the BTIS test is shown. As an example, Figure Figures 41A to 41D show the GBT in Sample B1 and Sample B4. This shows the changes in Id-Vg characteristics before and after the test. Figure 41A is PB of Sample B1. TS test, Figure 41B is the PBTS test of Sample B4, Figure 41C is Sample B Figure 41D shows the results of the NBTIS test for Sample B4. They are shown respectively.

[0514] As shown in Figures 40 and 41A to 41D, for each sample, the threshold The transistor exhibited minimal voltage fluctuations, confirming its high reliability.

[0515] From the above results, a transistor to which a metal oxide film according to one aspect of the present invention is applied has a short channel. It exhibits good transistor characteristics even with a short cable length, and is a highly reliable transistor. It was confirmed that this was the case. [Examples]

[0516] This example describes the results of an investigation into the composition of a metal oxide film according to one embodiment of the present invention. I will reveal it.

[0517] [Sample preparation] The sample used in this example had a metal oxide film deposited on a glass substrate by sputtering. This is the result. The deposition of metal oxide films is performed when the atomic ratio of the metal elements is In:Ga:Zn=4: A metal oxide target with an atomic ratio of 2:4.1 was used. As the deposition gas, aluminum was used. A mixture of gases (GON and oxygen) was used. Furthermore, the metal oxide film was deposited by heating the substrate. This was done without any problems. Here, three samples were prepared using different conditions for depositing the metal oxide film (Sampl Models e (C1 to Sample C3) were prepared.

[0518] The metal oxide film of Sample C1 was formed as a percentage of the oxygen gas flow rate relative to the total flow rate of the film-forming gas. The film was deposited under conditions where the oxygen flow rate ratio was 10%. The metal oxide film of Sample C2 was The film was deposited under conditions where the oxygen flow rate ratio was 30%. The metal oxide film of Sample C3 was acid The film was deposited under conditions where the raw flow rate ratio was 50%.

[0519] [HAADF-STEM observation and EDX analysis] The three prepared samples were examined using high-angle scattering annular dark-field scanning transmission electron microscopy (HAADF). -STEM:High-Angle Annular Dark Field Scan (Ning Transmission Electron Microscopy) Observation and energy-dispersive X-ray spectroscopy (EDX) Compositional analysis was performed using X-ray spectroscopy.

[0520] Figure 42 shows the HAADF-STEM images for each sample and their relative values ​​for In, Ga, and Zn. The EDX mapping images are shown for each sample. For each sample, the HAADF-STEM image and the ED X-mapping images are the result of observing the same region.

[0521] In HAADF-STEM images, contrast proportional to the square of the atomic number is obtained. Therefore, brighter regions suggest the presence of heavier atoms. Also, ED In X-mapped images, bright areas correspond to regions where the corresponding element is abundant, while dark areas... The areas of light color correspond to regions where the corresponding element is scarce.

[0522] As shown in the EDX mapping image in Figure 42, Sample C1, Sample C2 In both Sample C3 and In It was confirmed that Ga and Zn were not uniformly present in the range of several nanometers. .

[0523] [Quantitative analysis of composition] Next, for each sample, the bright region in the above In EDX mapping image (In- Rich regions, dark regions (In-poor regions), and Ga EDX mappers Bright regions (Ga-rich regions) and dark regions (Ga-poor regions) in the image. Quantitative analysis was performed on In, Ga, and Zn for each of the regions. This was done for each of the 5 points.

[0524] Figures 43A to 43D show the results of the quantitative analysis of Sample C1. Figure 43A is I n-rich region, Figure 43B is the in-poor region, Figure 43C is the Ga-rich region, Figure Figure 43D shows the analysis results for the Ga-poor region. In each figure, horizontal The axes represent the proportions of each element when the sum of the compositions of In, Ga, and Zn is set to 100%, and there are five axes. The measurement points are shown in a bar graph.

[0525] Focusing on Figures 43B and 43C, we can see that Ga is detected in greater quantities than In, and also, Compared to the composition of GET (In:Ga:Zn=4:2:4.1), the proportion of Ga is higher. It can be seen that a region exists. Note that In was detected in the In-poor region in Figure 43B. This indicates that the thickness of the measurement sample is approximately 30 nm, and In present in the depth direction is detected. This is considered to be the result of the process.

[0526] Furthermore, looking at Figures 43A and 43D, we can see that the Ga composition is extremely small, or Ga is Areas where Ga was not detected were also observed. In the areas where Ga was not detected, indium oxide or i It is suspected that a state similar to zinc oxide exists.

[0527] From these results, it can be seen that the metal oxide film actually deposited is uniform in that it reflects the composition of the target. It was confirmed that the film was not a single, uniform membrane, but rather a membrane with regions of different compositions distributed throughout.

[0528] Note that only the results for Sample C1 are shown here, but Sample C2 and Sa A similar trend was observed with mple C3.

[0529] [Analysis using histograms] Next, quantitative analysis was performed on each EDX mapping image shown in Figure 42, and the obtained I Histogram-based analysis was performed for the compositions of n, Ga, and Zn.

[0530] Figures 44A, 44B, and 44C show Sample C1 and Sample C1, respectively. Histograms for C2 and Sample C3 are shown. In each figure, the horizontal axis represents the composition. The vertical axis shows the frequency. Also, to make each element easier to see, each figure shows the peak. The element names are clearly indicated near the vertices.

[0531] As shown in Figures 44A to 44C, there is a significant difference in the compositional distribution of each sample. It was confirmed that it was not present. Furthermore, Ga was not detected in any of the samples. We were also able to confirm the existence of a region (a region where the Ga composition is 0). From the above, we can conclude that oxygen In multiple metal oxide films with different crystalline properties formed by varying the flow rate ratio, the composition It was confirmed that there were no significant differences in the distribution.

[0532] From the above results, the metal oxide film according to one aspect of the present invention is not a uniform film, but rather a metal oxide film It is a film in which the constituent metallic elements are unevenly distributed, and it is observed to be like a composite. This was confirmed. [Explanation of symbols]

[0533] 10: Substrate, 11: Metal oxide film, 12a, 12b: Region, 20: Direct spot, 20a, 20b, 20c, 20d: Electron diffraction patterns, 21: First spot, 22: Second spot, 30, 30a, 30b, 30c, 30r: histogram, 31: first Region, 32: Second region, 41, 42: Peak, 300, 300A: Transistor, 30 2: Substrate, 304: Conductive layer, 306: Insulating layer, 308: Semiconductor layer, 312a, 312b, 313a, 313b: conductive layer, 314, 316: insulating layer, 320: conductive layer, 342: opening Parts 350, 350A, 350B, 350C: Transistors, 352: Circuit board, 353, 3 53a, 353b: insulating layer, 356: conductive layer, 358: semiconductor layer, 358n: low-resistance region 360: insulating layer, 362: conductive layer, 364: metal oxide layer, 366, 368: insulating layer, 370a, 370b: conductive layer, 391a, 391b, 392: opening

Claims

[Claim 1] Multiple regions of a metal oxide film are irradiated with an electron beam having a beam diameter of 0.3 nm to 10 nm from a direction perpendicular to the film surface of the metal oxide film, and multiple electron diffraction patterns are obtained. For multiple spots observed in multiple electron diffraction patterns, the interplanar spacing d is calculated. A method for evaluating a metal oxide film, comprising evaluating the crystallinity of the metal oxide film from the shape of the frequency distribution of the interplanar spacing d.

Images