Silicon carbide semiconductor device and power converter

Abstract

The objective is to provide a technology that can suppress bipolar-preferential operation in boundary regions. [Solution] The silicon carbide semiconductor device comprises a semiconductor layer made of silicon carbide, which has defined active regions, peripheral regions, and boundary regions, and a source electrode provided on the upper side of the semiconductor layer. The semiconductor layer includes a first-conductivity drift layer and a second-conductivity well layer, and the drift layer in the boundary region includes a high-point defect density layer that overlaps with at least a portion of the well layer in a plan view and is spaced apart from the well layer in a cross-sectional view and provided on the lower side of the well layer.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device and a power conversion device.

Background Art

[0002] As a silicon carbide semiconductor device, a technique has been proposed in which an SBD (Schottky barrier diode), which is a unipolar diode, is provided in a unit cell of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Regardless of whether the energization region during the reflux operation is the SBD region or the channel region of the MOSFET, due to the structure, a unipolar diode cannot be densely arranged in the boundary region between these active regions and the outer peripheral region, and there is a location where a parasitic pn diode exists. Therefore, a bipolar priority operation in which a bipolar current preferentially flows through the parasitic pn diode in the boundary region is performed, and as a result, for example, heat generation due to current concentration may occur.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of suppressing the bipolar priority operation in the boundary region.

Means for Solving the Problems

[0006] The silicon carbide semiconductor device according to this disclosure comprises a semiconductor layer made of silicon carbide, which has defined active regions through which a main current flows, an outer peripheral region surrounding the active region, and a boundary region between the active region and the outer peripheral region, and a source electrode provided on the upper side of the semiconductor layer, wherein the semiconductor layer includes a drift layer of a first conductivity type and a well layer of a second conductivity type provided on the drift layer in the boundary region and connected to the source electrode, the drift layer in the boundary region includes a high point defect density layer which overlaps with at least a part of the well layer in a plan view and is spaced apart from the well layer in a cross-sectional view and provided below the well layer, and the point defect density of the high point defect density layer is higher than the point defect density of the drift layer other than the high point defect density layer. [Effects of the Invention]

[0007] According to this disclosure, the drift layer in the boundary region includes a high-point defect density layer that overlaps with at least a portion of the well layer in a plan view and is spaced apart from the well layer and located below the well layer in a cross-sectional view. With such a configuration, bipolar-preferential operation in the boundary region can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic plan view showing the configuration of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 1. [Figure 3] Figure 3 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 1. [Figure 4] Figure 4 is a schematic plan view showing the configuration of a silicon carbide semiconductor device according to Embodiment 1. [Figure 5] Figure 5 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 1. [Figure 6] Figure 6 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 1. [Figure 7]Figure 7 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 2. [Figure 8] Figure 8 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 2. [Figure 9] Figure 9 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 3. [Figure 10] Figure 10 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 4. [Figure 11] Figure 11 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to Embodiment 5. [Figure 12] Figure 12 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 6 is applied. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily coincide with the positions and directions in actual implementation. Furthermore, a higher concentration in one part than in another part may mean, for example, that the average or peak concentration of one part is higher than the average or peak concentration of the other part. Conversely, a lower concentration in one part than in another part may mean, for example, that the average or peak concentration of one part is lower than the average or peak concentration of the other part. Also, in the following descriptions, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0010] <Related technologies> A well-known reliability problem exists with pn diodes made of silicon carbide: when a forward current, i.e., bipolar current, is continuously passed through them, stacking faults occur in the silicon carbide crystal, causing a shift in the forward voltage. This is thought to be because minority carriers injected through the pn diode recombine with majority carriers, generating recombination energy. This recombination energy then expands the stacking faults, which are planar defects, starting from basal plane dislocations in the silicon carbide substrate. In other words, the stacking faults are thought to obstruct the flow of current, thereby increasing the forward voltage.

[0011] Such forward voltage shifts also occur in switching elements such as transistors made of silicon carbide. Furthermore, forward voltage shifts occur in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), also known as SiC-MOSFETs, which are a type of switching element made of silicon carbide. The reason for this forward voltage shift is that, although the MOSFET itself is a unipolar transistor, it has a bipolar parasitic pn diode as a body diode between the source and drain. As a result, when a bipolar current flows through the MOSFET's body diode, reliability degradation similar to that of a pn diode occurs.

[0012] Generally, Schottky barrier diode (SBD) chips with low forward voltage are used as freewheel diodes in switching circuits, and the SBD chip is connected in parallel with a MOSFET chip that is provided separately from the SBD chip. However, even if the SBD chip and MOSFET chip are provided separately, the above-mentioned degradation of the MOSFET characteristics will occur as long as the body diode of the SiC-MOSFET functions as a freewheel diode.

[0013] On one hand, if a unipolar diode such as a MOSFET is built-in with a unipolar diode as a freewheeling diode, it is possible to suppress the body diode from functioning as a freewheeling diode. As an example of the configuration, a configuration in which an SBD is built-in into a unit cell of a MOSFET as a unipolar diode has been proposed. In this configuration, an n-type drift layer partially exposed from a p-type well layer among the lower part of the source electrode in the active region contacts a Schottky electrode, thereby realizing an SBD region that functions as an SBD.

[0014] In a unipolar transistor with a built-in unipolar diode in an active region such as a unit cell, the diffusion potential of the unipolar diode, that is, the voltage at which the energization operation starts, can be designed to be lower than that of the pn junction. Therefore, it is possible to suppress the flow of bipolar current through the body diode during actual use, and suppress the deterioration of the characteristics of the active region.

[0015] However, when the unipolar current of the built-in SBD increases and the potential around the SBD exceeds the pn junction potential of the body diode, the body diode turns on and a bipolar current flows. Therefore, there is a limit to the maximum unipolar current that can flow through the SBD built-in MOSFET chip. In order to reduce the chip cost under such a limit of the maximum unipolar current, it is required to increase the current density as much as possible and increase the maximum unipolar current density that can flow through the chip.

[0016] As a method for increasing the maximum unipolar current density of the SBD built-in MOSFET, for example, a method of forming a recombination layer with a high point defect density by injecting hydrogen or helium under the body region (well layer) in the active region can be considered. According to such a structure, holes injected from the body region (well layer) are more likely to recombine with electrons, and the hole concentration accumulated directly under the body region (well layer) decreases, so that the bipolar current is less likely to flow, and the maximum unipolar current density can be increased.

[0017] Incidentally, due to structural (layout) constraints, there are areas in the boundary region between the active region and the outer region where unipolar diodes cannot be densely packed. Therefore, even in unipolar transistors that incorporate unipolar diodes in the active region, parasitic pn diodes may form around the areas in the boundary region where unipolar diodes cannot be densely packed.

[0018] For example, in boundary regions such as near the gate pad, due to structural considerations such as the routing of the gate electrode to the gate wiring, there are generally regions where the SBD region is not provided in part, i.e., regions where the area ratio (area density) of the SBD region is smaller than that of the active region. Also, generally in boundary regions, from the perspective of maintaining breakdown voltage, at least a part of the drift layer is in contact with the well layer, and there are places where parasitic pn diodes exist, similar to the active region. As a result, in MOSFETs with built-in SBDs, bipolar-preferential operation, where bipolar current flows preferentially, may occur more easily in the active region than in the boundary region.

[0019] When a large current flows through the chip, if bipolar-preferential operation occurs in the boundary region, the concentration of current in the boundary region can lead to increased localized heat generation, potentially causing thermal degradation of performance. Furthermore, if a basal plane dislocation or other origin exists in a location where the bipolar current density is higher than expected, the stacking fault can expand, causing leakage current to occur when the transistor is off, which can degrade the transistor's breakdown voltage.

[0020] In a MOSFET with an integrated SBD, where unipolar current generally flows, if there are areas where the bipolar current resistance is lower than the unipolar current resistance, current concentration is likely to occur at those points. For this reason, current concentration at boundary regions is more likely to occur in MOSFETs with integrated SBDs than in MOSFETs without integrated SBDs.

[0021] As mentioned above, in MOSFETs with integrated SBDs, a recombination layer with a high point defect density is sometimes provided below the body region (well layer) in the active region in order to increase the maximum unipolar current density in the active region. In this case, the difference between the maximum unipolar current density in the active region and the maximum unipolar current density in the boundary region widens, which presents a problem as bipolar-preferential operation becomes even more likely to occur in the boundary region.

[0022] Furthermore, in a configuration where the channel region of the MOSFET is formed by a thin second conductivity region on the first conductivity region, a unipolar freewheeling current flows through the MOSFET's channel region during freewheeling operation. With such a configuration, it is possible to suppress the flow of bipolar current to the parasitic pn diode (body diode) between the source and drain. However, even with such a configuration, similar to the MOSFET with an SBD built into the active region, there are areas in the boundary region where unipolar diodes cannot be densely arranged due to structural constraints. Therefore, the problem of bipolar-preferential operation occurring in the boundary region remains unresolved.

[0023] In contrast, as will be explained below, the silicon carbide semiconductor device according to this embodiment 1 makes it possible to suppress bipolar-preferential operation in the boundary region.

[0024] <Embodiment 1> The following description will mainly focus on an example where the silicon carbide semiconductor device according to Embodiment 1 is an n-channel silicon carbide MOSFET, specifically a silicon carbide MOSFET with a built-in SBD (Schottky barrier diode), i.e., an SBD-integrated SiC-MOSFET. However, the silicon carbide semiconductor device according to Embodiment 1 is not limited to this, and may also be an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting IGBT). Furthermore, silicon carbide semiconductor devices offer more stable operation at high temperatures and high voltages, as well as faster switching speeds, compared to semiconductor devices made of ordinary silicon.

[0025] The following description shows the potential differences when the first conductivity type is n-type and the second conductivity type is p-type. Therefore, the potential differences when the first conductor is p-type and the second conductivity type is n-type will be the opposite of what is described below.

[0026] Figure 1 is a schematic plan view of the silicon carbide semiconductor device according to this first embodiment, as seen from above. In Figure 1, a gate pad 81, an adjacent source electrode 80, and gate wiring 82 connected to the gate pad 81 and surrounding the source electrode 80 are provided on a part of the top surface of the SiC-MOSFET. A high-point defect density layer 104 is shown in Figure 1, which will be described later.

[0027] Figures 2 and 3 are schematic cross-sectional diagrams showing the configuration of a silicon carbide semiconductor device according to this first embodiment. Figure 2 is a schematic cross-sectional diagram along the line a-a' spanning the source electrode 80 and gate wiring 82 in Figure 1, where the boundary region 102 is a schematic cross-sectional diagram of the portion that does not include the routing of the gate electrode 60 from the active region 101 to the outer peripheral region 103. Figure 3 is a schematic cross-sectional diagram along the line b-b' spanning the source electrode 80 and gate wiring 82 in Figure 1, where the boundary region 102 is a schematic cross-sectional diagram of the portion that includes the routing of the gate electrode 60 from the active region 101 to the outer peripheral region 103.

[0028] The silicon carbide semiconductor device according to this first embodiment comprises a semiconductor layer made of silicon carbide, including a drift layer 20. In the example shown in Figures 2 and 3, the semiconductor layer is provided on a semiconductor substrate 10, but the semiconductor substrate 10 may also be included. The semiconductor layer is defined as having an active region 101, a boundary region 102, and an outer peripheral region 103. Here, an overview of each region will be described, and the details of each region will be described later.

[0029] The active region 101 is the region through which the main current flows, and unit cells are arranged periodically. The active region 101 may include a MOSFET region through which the main current flows and an SBD region through which the freewheel current flows as unit cells, or it may include a MOSFET region through which the main current flows and which conducts in the reverse direction during freewheel operation as unit cells.

[0030] The outer peripheral region 103 is the region surrounding the active region 101 and is located at the edge of the silicon carbide semiconductor device. The outer peripheral region 103 may include an electric field relaxation layer such as a JTE (Junction Termination Extension).

[0031] The boundary region 102 is the region between the active region 101 and the outer peripheral region 103, and connects the active region 101 and the outer peripheral region 103.

[0032] <Active area 101> Next, the configuration of the active region 101 will be described. The semiconductor layer of the active region 101 according to this embodiment 1 includes an n-type drift layer 20, a p-type first well layer 30, a p-type contact layer 32, and an n-type first source layer 40.

[0033] The drift layer 20 is provided on an n-type semiconductor substrate 10. A first well layer 30 is selectively provided on the drift layer 20. The p-type impurity in the first well layer 30 is, for example, aluminum (Al). In cross-sectional view, the first well layer 30 is divided by a first separation region 21 and a second separation region 22, which are both parts of the drift layer 20.

[0034] The first source layer 40 is located inside the upper part of the first well layer 30 in a cross-sectional view. The n-type impurity in the first source layer 40 is, for example, nitrogen (N). The lower end of the first source layer 40 is located above the lower end of the first well layer 30.

[0035] In a cross-sectional view, the contact layer 32 is located in the upper part of the first well layer 30, sandwiched between the first source layer 40 and the first separation region 21, and is provided in a region separated from the first separation region 21. The p-type impurities in the contact layer 32 are, for example, aluminum (Al), and are at a higher concentration than the p-type impurities in the first well layer 30.

[0036] A gate insulating film 50, made of, for example, silicon oxide, is provided spanning the second separation region 22, the first well layer 30, and a portion of the first source layer 40. A gate electrode 60 is provided on the gate insulating film 50, facing the ends of the second separation region 22, the first well layer 30, and the first source layer 40, via the gate insulating film 50. The region of the first well layer 30 sandwiched between the second separation region 22 and the first source layer 40, facing the gate electrode 60 via the gate insulating film 50, and where an inversion layer is formed during ON operation, is called the channel region.

[0037] An interlayer insulating film 55 made of silicon oxide is provided on the gate insulating film 50, covering the gate electrode 60. Ohmic electrodes 70 are provided on the upper surface of the portion of the first source layer 40 not covered by the gate insulating film 50 and on the upper surface of the portion of the contact layer 32 that contacts the first source layer 40, in order to reduce contact resistance with silicon carbide. As a result, the first well layer 30 is ohmic-connected to the source electrode 80 via the contact layer 32 and the ohmic electrodes 70, and electrons and holes can be easily exchanged between the ohmic electrodes 70 and the first well layer 30 via the low-resistance contact layer 32.

[0038] A first Schottky electrode 71 is provided on the upper surface of the first separation region 21, and the first Schottky electrode 71 is connected to the first separation region 21 via a Schottky connection. The first Schottky electrode 71 and the first separation region 21 are in contact with each other to form a Schottky barrier (SBD), and the diffusion potential of the SBD is lower than the diffusion potential of the pn junction. It is desirable that the first Schottky electrode 71 be provided on the upper surface of the first separation region 21, but it is not required.

[0039] A source electrode 80 is provided on the ohmic electrode 70, the first Schottky electrode 71, and the interlayer insulating film 55. The source electrode 80 is connected to the ohmic electrode 70 and the first Schottky electrode 71 via a first contact hole 90 provided in the gate insulating film 50 and the interlayer insulating film 55, thereby electrically short-circuiting the ohmic electrode 70 and the first Schottky electrode 71. As a result, the ohmic electrode 70 and the first Schottky electrode 71 are electrically connected.

[0040] The source electrode 80 is provided on the upper side of the semiconductor layer not only in the active region 101 but also in the boundary region 102. The drain electrode 84 is provided on the lower surface of the semiconductor substrate 10 not only in the active region 101 but also in the boundary region 102 and the outer peripheral region 103.

[0041] <Outer area 103> Next, the configuration of the outer peripheral region 103 will be described. The semiconductor layer of the outer peripheral region 103 according to this embodiment 1 includes an n-type drift layer 20, a p-type second well layer 31, and a p-type JTE layer 37.

[0042] The drift layer 20 is provided on an n-type semiconductor substrate 10. A second well layer 31 is selectively provided on the drift layer 20. The p-type impurity in the second well layer 31 is, for example, aluminum (Al).

[0043] As shown in Figure 3, the gate electrode 60 is provided from the active region 101 through the boundary region 102 to the outer peripheral region 103, and is provided on the second well layer 31 via the gate insulating film 50 and the field insulating film 51. An interlayer insulating film 55 is provided on the gate electrode 60, and the interlayer insulating film 55 has gate contact holes 95 that expose a part of the gate electrode 60 on the field insulating film 51. Gate wiring 82 provided on the interlayer insulating film 55 is connected to a part of the gate electrode 60 via the gate contact holes 95.

[0044] The outer peripheral region 103 includes not only the gate wiring 82 but also the gate pad 81 shown in Figure 1. It is preferable that the second well layer 31 be provided in such a way as to shield the high voltage from the drain electrode 84 so as to suppress the application of the high voltage from the drain electrode 84 to the field insulating film 51, which is provided below the gate wiring 82, which has a significantly lower potential than the drain voltage. To achieve this, in this embodiment 1, as shown in Figures 2 and 3, the gate wiring 82 overlaps with the second well layer 31 in a plan view, and although not shown, the gate pad 81 also overlaps with the second well layer 31 in a plan view. A JTE layer 37 connected to the second well layer 31 is provided on the outer peripheral side of the second well layer 31, and the concentration of p-type impurities in the JTE layer 37 is lower than that of p-type impurities in the second well layer 31.

[0045] The second well layer 31 of the boundary region 102, described later, is connected to the source electrode 80 via the second contact hole 91 shown in Figure 2, which is provided in the gate insulating film 50 and the interlayer insulating film 55. The gate electrode 60 in Figure 3 is provided from the active region 101 to the outer peripheral region 103, but the gate electrode 60 in Figure 2 is removed at the location where the second contact hole 91 is made in order to avoid contact with the source electrode 80.

[0046] <Border area 102> Next, the configuration of the boundary region 102 will be described. The boundary between the boundary region 102 and the active region 101 is defined, for example, by whether or not the main current flows. The boundary between the boundary region 102 and the outer peripheral region 103 is defined, for example, by whether or not the source electrode 80 is connected to the semiconductor layer.

[0047] The semiconductor layer of the boundary region 102 according to this embodiment 1 includes an n-type drift layer 20, a p-type second well layer 31 which is a well layer, a p-type contact layer 32, and an impurity layer similar to the n-type first source layer 40.

[0048] The drift layer 20 is provided on an n-type semiconductor substrate 10. A second well layer 31 is selectively provided on the drift layer 20, similar to the outer peripheral region 103. The second well layer 31 is ohmic connected to the source electrode 80. In cross-sectional view, the second well layer 31 is divided by a third separation region 24, which is part of the drift layer 20.

[0049] A second Schottky electrode 73 is provided on the upper surface of the third separation region 24. The second Schottky electrode 73 is Schottky connected to the source electrode 80, thereby providing a Schottky contact through which a unipolar current flows during recirculation operation, and an SBD is provided.

[0050] The configuration of the active region 101, boundary region 102, and outer peripheral region 103 is not limited to those described above. For example, the gate electrode 60 does not need to be provided in the outer peripheral region 103, nor do the second well layer 31 and JTE layer 37 need to be provided in the outer peripheral region 103.

[0051] Now, in the boundary region 102 of Figure 3, the gate electrode 60 is routed to connect the active region 101 and the outer peripheral region 103. In this configuration, there are areas where Schottky contacts, or SBDs, cannot be provided. For this reason, due to structural constraints, there are areas in the boundary region 102 where the SBD area density is smaller compared to the active region 101.

[0052] In regions with a small SBD area density, the unipolar current density that can flow around it is also small. Therefore, when a large freewheel current flows through the MOSFET chip with an integrated SBD, bipolar current preferentially flows through this region. The area of ​​the region within the boundary region 102 where bipolar current preferentially flows is small compared to the entire area of ​​the active region 101, and the bipolar current flowing through the boundary region 102 has lower resistance than the unipolar current flowing through the active region 101.

[0053] Therefore, in the region of the boundary region 102 where bipolar current preferentially flows, the bipolar current density becomes higher than expected, raising concerns about crystal defect expansion and thermal degradation. The above describes the case where the area density of the SBD region in the boundary region 102 cannot be increased due to the routing of the gate electrode 60. However, there are other cases where the area density of the SBD region in the boundary region 102 cannot be increased, such as by the formation of a contact layer in the second well layer 31.

[0054] <High-point defect density layer 104> In this embodiment 1, to solve these problems, as shown in Figures 2 and 3, at least a portion of the drift layer 20 in the boundary region 102 includes a high-point defect density layer 104, which is a low-lifetime layer. In a plan view, the high-point defect density layer 104 overlaps with at least a portion of the second well layer 31, and in a cross-sectional view, it is spaced apart from the second well layer 31 and located below the second well layer 31. The point defect density of the high-point defect density layer 104 is higher than the point defect density of the other drift layers 20.

[0055] Herein, an example of a method for manufacturing a silicon carbide semiconductor device according to this embodiment 1 will be briefly described. First, semiconductor layers, such as the drift layer 20, are formed on the semiconductor substrate 10 by epitaxial growth. Then, using a patterning mask, n-type and p-type impurities are selectively ion-implanted into the semiconductor layers to form the first well layer 30, the second well layer 31, the contact layer 32, and the first source layer 40.

[0056] Next, using a patterning mask, hydrogen (H) or helium (He), for example, is selectively ion-implanted into at least a portion of the drift layer 20 in the boundary region 102. Subsequently, by heat treatment at a high temperature, the hydrogen or helium is thermally diffused, and a high-point defect density layer 104 is formed at the locations where they were implanted. After heat treatment, various insulating films and various electrodes are formed, and the silicon carbide semiconductor device according to this embodiment 1 is completed.

[0057] In such a silicon carbide semiconductor device, when the parasitic pn diode operates, holes flowing from the second well layer 31 and electrons flowing from the semiconductor substrate 10 are more easily recombined in the high-point defect density layer 104, making it difficult for holes to flow towards the semiconductor substrate 10. As a result, bipolar current is less likely to flow in and around this high-point defect density layer 104, suppressing bipolar-preferential operation. This suppresses, for example, degradation due to current concentration in the boundary region 102 and degradation of characteristics due to the expansion of stacking faults.

[0058] Furthermore, a pn diode that operates bipolar preferentially is formed between the second well layer 31 and the drift layer 20, in a region that is ohmic-connected to the source electrode 80 via a contact layer 32 or the like. For this reason, in a plan view, it is more preferable that the high-point defect density layer 104 overlaps at least a portion of the contact layer 32. However, in regions where a sufficient unipolar current can flow, such as regions adjacent in a plan view to a region where SBDs are densely arranged, the high-point defect density layer 104 may be narrower or not provided at all.

[0059] Furthermore, in a pn diode consisting of a second well layer 31 and a drift layer 20, the resistance in the current path increases the further away from the contact layer 32 on the second well layer 31, and the less likely it is to perform bipolar-preferential operation. For this reason, the high-point defect density layer 104 does not need to be provided in regions far from the contact layer 32. Also, in Figures 2 and 3, the high-point defect density layer 104 is provided throughout the entire boundary region 102, but the high-point defect density layer 104 may be provided only on the active region 101 side and not on the outer peripheral region 103 side.

[0060] In order to obtain a good ohmic connection, it is preferable that the contact layer 32 on the second well layer 31 is connected to the source electrode 80 via the ohmic electrode 70, but this is not the only option. For example, the ohmic electrode 70 may be omitted, and the contact layer 32 may be directly ohmic-connected to the source electrode 80.

[0061] Furthermore, in the examples shown in Figures 2 and 3, an SBD is provided in the boundary region 102 by connecting the third separation region 24 to the source electrode 80 in the second contact hole 91 via the second Schottky electrode 73, but this is not the only configuration. In a configuration in which an SBD is provided in the boundary region 102, the high-point defect density layer 104 may be provided intermittently (discretely) by not providing the high-point defect density layer 104 directly below the third separation region 24 where the SBD is provided. This makes it possible to reduce leakage current when a high electric field is generated at the lower end of the second well layer 31 and below the second Schottky electrode 73.

[0062] Furthermore, when fabricating the high-point defect density layer 104 according to this embodiment 1, hydrogen (H) or helium (He) ions may be implanted after heat treatment. Also, the dose of ion implantation is 1 × 10⁻⁶. 12 cm -2 From 1 x 10 16 cm -2 It is desirable to set the dose within this range. The reason for this is that if the dose is too small, the effect of suppressing the bipolar-preferential operation described above will be reduced, and if the dose is too large, the semiconductor layer may warp during ion implantation, potentially causing adverse effects on subsequent processes and device characteristics.

[0063] Note that the high-point defect density layer 104 is not located on the uppermost surface of the silicon carbide semiconductor device, and therefore is not actually visible from the top side of the silicon carbide semiconductor device. However, for convenience, the high-point defect density layer 104 is shown in plan views such as Figure 1 to clarify the planar positional relationship. In the example in Figure 1, the high-point defect density layer 104 is located in the boundary region 102 around the gate pad 81. With this configuration, the effect of suppressing bipolar-preferential operation can be obtained even around the gate pad 81.

[0064] The high-point defect density layer 104 may be continuously provided around the active region 101 as shown in Figure 1, or it may be provided intermittently as shown in Figure 4. For example, if there is a process in another injection process that uses a patterning mask with intermittently open holes, forming the high-point defect density layer 104 with that mask can be expected to simplify the patterning process.

[0065] In the example shown in Figure 2, the distance between the high-point defect density layer 104 and the lower end of the drift layer 20, that is, the distance between the high-point defect density layer 104 and the semiconductor substrate 10, is smaller than the distance between the high-point defect density layer 104 and the second well layer 31. With this configuration, since the high-point defect density layer 104 is provided in a region where the hole density is high when the SBD is energized, the hole density can be effectively reduced, and the effect of suppressing bipolar-preferential operation can be enhanced.

[0066] As shown in the example in Figure 5, the distance between the high-point defect density layer 104 and the second well layer 31 may be smaller than the distance between the high-point defect density layer 104 and the lower end of the drift layer 20. The bipolar current from the second well layer 31 in the boundary region 102 flows not only along the shortest path in the vertical direction of the cross-sectional view toward the drain electrode 84, but also to some extent in the horizontal direction of the cross-sectional view as shown in Figure 5. For this reason, in a configuration in which the high-point defect density layer 104 is located near the second well layer 31, the current path of the bipolar current flowing in the horizontal direction can be made longer or have higher resistance, thereby enhancing the effect of suppressing current concentration due to bipolar-preferential operation in the boundary region 102.

[0067] Furthermore, if the high-point defect density layer 104 is in contact with the second well layer 31, there is a concern that the leakage current through point defects present at the interface between the second well layer 31 and the drift layer 20 will increase, potentially lowering the breakdown voltage of the semiconductor device, which is undesirable. The inventors have also confirmed that in a configuration where the high-point defect density layer 104 is provided within the third separation region 24, the bipolar-preferential operation of the boundary region 102 cannot be effectively suppressed. In this embodiment 1, taking the above into consideration, the high-point defect density layer 104 is provided below the second well layer 31, separated from it in a cross-sectional view.

[0068] In the example shown in Figure 2, the width of the high-point defect density layer 104, which corresponds to the lateral length in the cross-sectional view, is the same as the width of the boundary region 102. However, the width of the high-point defect density layer 104 may be smaller than the width of the boundary region 102 so as to fit within the boundary region 102. However, if the width of the high-point defect density layer 104 is made too small, the above effect of suppressing bipolar priority operation will be reduced, so it is preferable to set the width of the high-point defect density layer 104 according to the specifications of the silicon carbide semiconductor device.

[0069] Furthermore, if a contact layer 32 connected to the source electrode 80 via an ohmic contact exists on the second well layer 31 of the boundary region 102, the unipolar current flowing from the SBD in the active region 101 cannot reach it, and bipolar-preferential operation is likely to occur. For this reason, in a plan view, it is preferable that the high-point defect density layer 104 overlaps with at least a portion of the contact layer 32, and consequently with at least a portion of the second well layer 31.

[0070] As shown in Figure 6, the high-point defect density layer 104 may extend beyond the boundary between the boundary region 102 and the active region 101 and be provided in a part of the active region 101. In a plan view, the high-point defect density layer 104 may overlap with at least a part of the SBD region of the active region 101. With such a configuration, it is possible to block a part of the current path of the bipolar current flowing laterally, or to make the current path longer or increase its resistance, thereby suppressing bipolar-preferential operation in the active region 101. However, if the high-point defect density layer 104 is provided throughout the entire active region 101, it will strengthen the tendency for bipolar-preferential operation to occur in the boundary region 102, so it is preferable that the high-point defect density layer 104 be provided in a part of the active region 101.

[0071] Furthermore, the point defect density in the drift layer 20 of the active region 101 may be smaller than the point defect density in the drift layer 20 of the boundary region 102. With such a configuration, the maximum unipolar current of the boundary region 102 can be increased, and malfunctions due to current concentration during overcurrent application and SBD conduction degradation can be suppressed.

[0072] Furthermore, the point defect density in the drift layer 20 of the outer peripheral region 103 may be smaller than the point defect density in the drift layer 20 of the boundary region 102. With such a configuration, a decrease in the breakdown voltage and an increase in the leakage current of the silicon carbide semiconductor device can be suppressed.

[0073] Although not shown in the diagram, by providing a high point defect density layer 104 below the gate pad 81, the point defect density in the drift layer 20 below the gate pad 81 may be greater than the point defect density in the drift layer 20 of the active region 101. With such a configuration, the maximum unipolar current below the gate pad 81 can be increased, and malfunctions due to current concentration during overcurrent application and SBD conduction degradation can be suppressed.

[0074] <Embodiment 2> Figure 7 is a schematic cross-sectional diagram showing the configuration of a silicon carbide semiconductor device according to this second embodiment, and is a schematic cross-sectional diagram corresponding to Figure 2. In this second embodiment, a plurality of high-point defect density layers 104 are arranged from the second well layer 31 toward the lower end of the drift layer 20. According to this second embodiment, the total length (thickness) of the high-point defect density layers 104 in the depth direction within the drift layer 20 is increased, so the effect of suppressing bipolar priority operation can be enhanced compared to the first embodiment.

[0075] Furthermore, by performing ion implantation in multiple stages while gradually changing the implantation energy, for example, even if a single high-point defect density layer 104 with a large thickness is formed, the same effects as described above can be enjoyed. However, due to the characteristics of ion implantation, it is extremely difficult to make the peak concentration values ​​of hydrogen or helium after implantation (i.e., the peak value of point defect density) exactly the same while only changing the thickness. In contrast, in this embodiment 2, multiple high-point defect density layers 104 with different peak values ​​and peak positions can be easily formed.

[0076] In the following explanation, the high-point defect density layer 104 on the second well layer 31 side will be referred to as the first high-point defect density layer 104a, and the high-point defect density layer 104 on the lower end side of the drift layer 20, that is, on the semiconductor substrate 10 side, will be referred to as the second high-point defect density layer 104b.

[0077] The peak point defect densities of the first high-point defect density layer 104a and the second high-point defect density layer 104b may be the same. Alternatively, the peak point defect densities of the second high-point defect density layer 104b may be higher than that of the first high-point defect density layer 104a, so the peak values ​​of the two may be different. During freewheeling operation, the hole density increases in the region close to the semiconductor substrate 10. Therefore, in a configuration in which the peak point defect density of the second high-point defect density layer 104b is increased, the hole density can be effectively reduced, and the effect of suppressing bipolar priority operation can be enhanced.

[0078] Furthermore, as shown in Figure 8, the first high-point defect density layer 104a may be provided in the boundary region 102, while the second high-point defect density layer 104b may be provided throughout the entire area from the active region 101 to the outer peripheral region 103. With such a configuration, it is possible to increase the unipolar current in the active region 101 during recirculation operation while obtaining bipolar-preferential operation and suppression of current concentration in the boundary region 102.

[0079] In the example shown in Figure 8, the second high-point defect density layer 104b is provided throughout the entire region, but it may also be provided in the active region 101 and the boundary region 102, excluding the outer peripheral region 103. Furthermore, at least one of the multiple high-point defect density layers 104 may be provided straddling the boundary between the active region 101 and the boundary region 102. Even with such a configuration, it is possible to increase the unipolar current in the active region 101 during recirculation operation while obtaining the effect of bipolar-preferential operation and suppression of current concentration in the boundary region 102. However, if the second high-point defect density layer 104b is provided throughout the entire region, the process of patterning the second high-point defect density layer 104b can be omitted, thereby reducing manufacturing costs.

[0080] <Embodiment 3> Figure 9 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this third embodiment, and is a schematic cross-sectional view corresponding to Figure 2. In this third embodiment, a second Schottky electrode 73 is provided on the upper surface of a third separation region 24 that divides the second well layer 31 of the boundary region 102. An SBD is provided by Schottky connecting the second Schottky electrode 73 to a source electrode 80. A pn ​​diode consisting of the second well layer 31 and the drift layer 20 adjacent to the third separation region 24 and the SBD are connected in parallel, thereby providing a junction barrier Schottky diode (JBS diode) in the boundary region 102.

[0081] By providing a JBS diode in the boundary region 102, the effect of suppressing bipolar-preferential operation around the boundary region 102 can be obtained. Furthermore, by providing a high-point defect density layer 104 in the boundary region 102, the effect of suppressing bipolar-preferential operation in the boundary region 102 can be obtained more effectively.

[0082] As shown in Figure 9, an ohmic contact with the source electrode 80 may be provided by providing a high-density p-type contact layer 32 on the inside of the upper surface of the second well layer 31 of the JBS diode, or the contact layer 32 may be omitted. In addition, a sufficient unipolar current density can flow in the region around the third separation region 24 of the JBS diode region, making bipolar preferential operation less likely. For this reason, the high-point defect density layer 104 may not be provided directly below the third separation region 24 that constitutes the JBS diode, but rather intermittently in the lateral direction in the cross-sectional view as shown in Figure 9.

[0083] Furthermore, the JBS diode may be placed in the region of the active region 101 that is closest to the boundary region 102. Since the unipolar current flowing from the SBD in the active region 101 also flows in the lateral direction in the cross-sectional view, by placing the JBS diode within the active region 101, it is possible to obtain the effect of suppressing the bipolar-preferential operation of the boundary region 102.

[0084] <Embodiment 4> Figure 10 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment 4, and is a schematic cross-sectional view corresponding to Figure 2. In this embodiment 4, a source contact layer 106 with a high n-type impurity concentration rather than a p-type impurity concentration is provided on the second well layer 31 of the boundary region 102, and an ohmic electrode 70 is provided on the source contact layer 106. Normally, a p-type contact layer 32 is provided on the p-type second well layer 31 to reduce contact resistance, but in this embodiment 4, the second well layer 31 is connected to the source electrode 80 via the n-type source contact layer 106 and the ohmic electrode 70.

[0085] With this configuration, during recirculation operation, a forward bias is less likely to be applied to the pn junction consisting of the second well layer 31 of the boundary region 102 and the drift layer 20. As a result, bipolar current is less likely to flow through the second well layer 31 of the boundary region 102 and the outer peripheral region 103, and the effect of suppressing bipolar-preferential operation can be obtained.

[0086] In the example shown in Figure 10, the n-type source contact layer 106 is provided in the boundary region 102, but it may also be provided in the outer peripheral region 103 instead of the boundary region 102. In this case, the second well layer 31 is connected to the source electrode 80 via the source contact layer in the outer peripheral region 103.

[0087] <Embodiment 5> Figure 11 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment 5, and is a schematic cross-sectional view corresponding to Figure 2. In this embodiment 5, a third Schottky electrode 107, which is a Schottky electrode, is provided on the second well layer 31 of the boundary region 102, instead of a contact layer 32 with a high concentration of p-type impurities. The second well layer 31 is connected to the source electrode 80 via the third Schottky electrode 107. As a result, the second well layer 31 and the source electrode 80 form a Schottky contact, not an ohmic contact.

[0088] With this configuration, similar to Embodiment 4, during recirculation operation, a forward bias is less likely to be applied to the pn junction consisting of the second well layer 31 of the boundary region 102 and the drift layer 20. As a result, bipolar current is less likely to flow through the second well layer 31 of the boundary region 102 and the outer peripheral region 103, and the effect of suppressing bipolar priority operation can be obtained.

[0089] In the example shown in Figure 11, the third Schottky electrode 107 is located in the boundary region 102, but it may also be located in the outer peripheral region 103 instead. In this case, the second well layer 31 is connected to the source electrode 80 via the third Schottky electrode 107 in the outer peripheral region 103.

[0090] <Embodiment 6> The power converter according to this embodiment 6 has the silicon carbide semiconductor device according to embodiments 1 to 5 described above. The power converter according to this embodiment 6 is not limited to a specific power converter, but the following describes the case in which the power converter according to this embodiment 6 is applied to a three-phase inverter.

[0091] Figure 12 is a block diagram showing the configuration of a power conversion system to which the power conversion device 200 according to this embodiment 6 is applied. The power conversion system shown in Figure 12 consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various power sources, for example, a DC grid, a solar cell, or a storage battery, or a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 100 may be composed of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0092] The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300. The power converter 200 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Figure 12, the power converter 200 includes a main conversion circuit 201, which is a conversion circuit that converts DC power into AC power and outputs it; a drive circuit 202, which outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203, which outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0093] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is a motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0094] The details of the power converter 200 are described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). The freewheeling diodes are built into the switching elements. By switching the switching elements, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Various specific circuit configurations can be envisioned for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment 6 is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. Silicon carbide semiconductor devices according to any of the embodiments 1 to 5 described above are used as the switching elements of the main conversion circuit 201. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0095] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit 202 outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element, according to the control signals from the control circuit 203, which will be described later. When the switching element is kept in the ON state, the drive signal is a voltage signal greater than the threshold voltage of the switching element (ON signal), and when the switching element is kept in the OFF state, the drive signal is a voltage signal less than the threshold voltage of the switching element (OFF signal).

[0096] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state, based on the power to be supplied to the load 300. For example, the control circuit 203 calculates the time so that the main converter circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0097] In the power conversion device according to this embodiment 6, since the silicon carbide semiconductor device according to embodiments 1 to 5 is used in the main conversion circuit 201, a power conversion device with low loss and improved reliability of high-speed switching can be realized.

[0098] In this embodiment 6, an example of applying the silicon carbide semiconductor device according to embodiments 1 to 5 to a two-level three-phase inverter was described. However, embodiment 6 is not limited to this and can be applied to various power conversion devices. Although the power conversion device according to embodiment 6 is described as a two-level power conversion device, it may also be a three-level or multi-level power conversion device, and when supplying power to a single-phase load, the power conversion device may be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, it is also possible to apply the power conversion device to a DC / DC converter or an AC / DC converter.

[0099] Furthermore, the power conversion device according to this embodiment 6 is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0100] In the above description, the silicon carbide semiconductor devices in each embodiment were described as planar type silicon carbide semiconductor devices, but trench type silicon carbide semiconductor devices may also be used. For example, in the active region 101 of the configuration in Figure 1, a stripe-shaped gate trench structure in which transistors are formed and a stripe-shaped Schottky trench structure in which Schottky electrodes are embedded may be provided parallel to each other and alternately.

[0101] In this disclosure in English, the articles 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0102] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0103] The various aspects of this disclosure are summarized below as an appendix.

[0104] (Note 1) A semiconductor layer made of silicon carbide, having defined active regions through which the main current flows, outer peripheral regions surrounding the active regions, and boundary regions between the active regions and the outer peripheral regions, A source electrode provided on the upper side of the semiconductor layer and Equipped with, The aforementioned semiconductor layer is A first conductive drift layer, A second conductivity type well layer is provided on the drift layer in the boundary region and connected to the source electrode. Includes, The drift layer in the boundary region is In a plan view, it overlaps with at least a portion of the well layer, and in a cross-sectional view, it includes a high-point defect density layer that is spaced apart from the well layer and located below the well layer. A silicon carbide semiconductor device wherein the point defect density of the high-point defect density layer is higher than the point defect density of the drift layers other than the high-point defect density layer.

[0105] (Note 2) A silicon carbide semiconductor device as described in Appendix 1, The silicon carbide semiconductor device comprises an active region including a MOSFET region through which the main current flows and an SBD region through which a freewheeling current flows.

[0106] (Note 3) A silicon carbide semiconductor device as described in Appendix 1, The silicon carbide semiconductor device comprises an active region which includes a MOSFET region through which the main current flows and which conducts in the reverse direction during recirculation operation.

[0107] (Note 4) A silicon carbide semiconductor device described in any one of the items 1 to 3 of the appendix, A silicon carbide semiconductor device wherein the point defect density in the drift layer of the active region is smaller than the point defect density in the drift layer of the boundary region.

[0108] (Note 5) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 4, A silicon carbide semiconductor device wherein the point defect density in the drift layer of the outer peripheral region is smaller than the point defect density in the drift layer of the boundary region.

[0109] (Note 6) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 5, A gate pad is provided in the outer peripheral region. A silicon carbide semiconductor device wherein the point defect density in the drift layer beneath the gate pad is greater than the point defect density in the drift layer in the active region.

[0110] (Note 7) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 6, A silicon carbide semiconductor device wherein the distance between the high-point defect density layer and the well layer is smaller than the distance between the high-point defect density layer and the lower end of the drift layer.

[0111] (Note 8) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 6, A silicon carbide semiconductor device wherein the distance between the high-point defect density layer and the lower end of the drift layer is smaller than the distance between the high-point defect density layer and the well layer.

[0112] (Note 9) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 6, A silicon carbide semiconductor device in which a plurality of the high-point defect density layers are arranged from the well layer toward the lower end of the drift layer.

[0113] (Note 10) A silicon carbide semiconductor device as described in Appendix 9, A silicon carbide semiconductor device in which at least one of the plurality of high-point defect density layers is provided straddling the boundary between the active region and the boundary region.

[0114] (Note 11) A silicon carbide semiconductor device described in any one of the appendices 1 to 10, The active region includes the SBD region. In a plan view, the high-point defect density layer overlaps with at least a portion of the SBD region, in a silicon carbide semiconductor device.

[0115] (Note 12) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 11, A silicon carbide semiconductor device is provided in the boundary region, wherein a junction barrier Schottky diode is provided.

[0116] (Note 13) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 11, The semiconductor layer further includes the first conductivity type source contact layer provided on the well layer, A silicon carbide semiconductor device wherein the well layer is connected to the source electrode via the source contact layer.

[0117] (Note 14) A silicon carbide semiconductor device described in any one of the items from Appendix 1 to Appendix 11, The Schottky electrode provided on the well layer further comprises A silicon carbide semiconductor device wherein the well layer is connected to the source electrode via the Schottky electrode.

[0118] (Note 15) A silicon carbide semiconductor device described in any one of the appendices 1 to 14, and a conversion circuit that converts the input power and outputs it, A drive circuit that outputs a drive signal to the silicon carbide semiconductor device to drive the silicon carbide semiconductor device, A control circuit that outputs a control signal to the drive circuit to control the drive circuit, A power conversion device equipped with the following features. [Explanation of Symbols]

[0119] 20 Drift layer, 31 Second well layer, 80 Source electrode, 101 Active region, 102 Boundary region, 103 Outer region, 104 High defect density layer, 106 Source contact layer, 107 Third Schottky electrode, 200 Power converter, 201 Main converter circuit, 202 Drive circuit, 203 Control circuit.

Claims

1. A semiconductor layer made of silicon carbide, having defined active regions through which the main current flows, outer peripheral regions surrounding the active regions, and boundary regions between the active regions and the outer peripheral regions, A source electrode provided on the upper side of the semiconductor layer and Equipped with, The aforementioned semiconductor layer is A first conductive drift layer, A second conductivity type well layer is provided on the drift layer in the boundary region and connected to the source electrode. Includes, The drift layer in the boundary region is In a plan view, it overlaps with at least a portion of the well layer, and in a cross-sectional view, it includes a high-point defect density layer that is spaced apart from the well layer and located below the well layer. A silicon carbide semiconductor device wherein the point defect density of the high-point defect density layer is higher than the point defect density of the drift layers other than the high-point defect density layer.

2. A silicon carbide semiconductor device according to claim 1, The silicon carbide semiconductor device comprises an active region including a MOSFET region through which the main current flows and an SBD region through which a reflux current flows.

3. A silicon carbide semiconductor device according to claim 1, The silicon carbide semiconductor device comprises an active region which includes a MOSFET region through which the main current flows and which conducts in the reverse direction during recirculation operation.

4. A silicon carbide semiconductor device according to any one of claims 1 to 3, A silicon carbide semiconductor device wherein the point defect density in the drift layer of the active region is smaller than the point defect density in the drift layer of the boundary region.

5. A silicon carbide semiconductor device according to any one of claims 1 to 3, A silicon carbide semiconductor device wherein the point defect density in the drift layer of the outer peripheral region is smaller than the point defect density in the drift layer of the boundary region.

6. A silicon carbide semiconductor device according to any one of claims 1 to 3, A gate pad is provided in the outer peripheral region. A silicon carbide semiconductor device wherein the point defect density in the drift layer beneath the gate pad is greater than the point defect density in the drift layer in the active region.

7. A silicon carbide semiconductor device according to any one of claims 1 to 3, A silicon carbide semiconductor device wherein the distance between the high-point defect density layer and the well layer is smaller than the distance between the high-point defect density layer and the lower end of the drift layer.

8. A silicon carbide semiconductor device according to any one of claims 1 to 3, A silicon carbide semiconductor device wherein the distance between the high-point defect density layer and the lower end of the drift layer is smaller than the distance between the high-point defect density layer and the well layer.

9. A silicon carbide semiconductor device according to any one of claims 1 to 3, A silicon carbide semiconductor device in which a plurality of the high-point defect density layers are arranged from the well layer toward the lower end of the drift layer.

10. A silicon carbide semiconductor device according to claim 9, A silicon carbide semiconductor device in which at least one of the plurality of high-point defect density layers is provided straddling the boundary between the active region and the boundary region.

11. A silicon carbide semiconductor device according to claim 1, The active region includes an SBD region. In a plan view, the high-point defect density layer overlaps with at least a portion of the SBD region, in a silicon carbide semiconductor device.

12. A silicon carbide semiconductor device according to any one of claims 1 to 3, A silicon carbide semiconductor device is provided in the boundary region, wherein a junction barrier Schottky diode is provided.

13. A silicon carbide semiconductor device according to any one of claims 1 to 3, The semiconductor layer further includes the first conductivity type source contact layer provided on the well layer, A silicon carbide semiconductor device wherein the well layer is connected to the source electrode via the source contact layer.

14. A silicon carbide semiconductor device according to any one of claims 1 to 3, The Schottky electrode provided on the well layer further comprises A silicon carbide semiconductor device wherein the well layer is connected to the source electrode via the Schottky electrode.

15. A silicon carbide semiconductor device according to any one of claims 1 to 3, comprising a conversion circuit that converts input power and outputs it, A drive circuit that outputs a drive signal to the silicon carbide semiconductor device to drive the silicon carbide semiconductor device, A control circuit that outputs a control signal to the drive circuit to control the drive circuit, A power conversion device equipped with the following features.

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