Serial-to-Parallel Converter

Abstract

This invention provides a parallel-enabled serial-parallel converter that effectively prevents data overflow without sacrificing high-speed operation. [Solution] The device consists of multiple stages of conversion, each having a data transfer circuit from the first stage to the final stage. Each data transfer circuit has one input terminal, two output terminals, and a flip-flop placed between the input terminal and each of the two output terminals. In each of the multiple stages of conversion, the flip-flop performs a data transfer operation for input data to the input terminal in synchronization with a clock of a different frequency, thereby outputting 2 bits of data in parallel from the two output terminals. At least some of the flip-flops in the conversion stage with a lower clock frequency than the other conversion stages have a relatively larger data transfer delay than the flip-flops in the other conversion stages.

Description

Technical Field

[0001] The present invention relates to a serial-parallel converter that converts serial data into parallel data.

Background Art

[0002] For the purpose of sequentially transferring (shifting) data in synchronization with a clock, a plurality of serially-connected flip-flops are frequently used. For each clock edge, data transfer for one stage of the flip-flop operates normally. However, as disclosed in paragraph 0009 of Patent Document 1, when the delay from the previous flip-flop to the next flip-flop is "data transfer delay < clock distribution delay", an incorrect operation in which data is transferred for multiple stages with respect to one clock edge, so-called data breakthrough, may occur. With the increase in the clock speed (shortening of the clock period), shortening of the data transfer delay is essential. On the other hand, precise distribution of the clock is difficult due to manufacturing variations, etc., and the tolerance for time deviation (skew) tends to narrow. In particular, when the clock waveform becomes dull, a halfway time zone where the potential is neither "H" nor "L" becomes prolonged, and delicate skew control cannot be expected. As a result, data breakthrough can occur not only at the boundary between flip-flops but also at the boundary between the master latch and the slave latch that constitute one flip-flop.

[0003] As serial-parallel converters, there are a method consisting of one shift register (a simple configuration in which only one type of frequency clock is input to a column of flip-flops connected in multiple stages in series) (hereinafter referred to as a single type), and a method in which a large number of flip-flops are configured by combining serial connection and parallel connection (hereinafter referred to as a parallel combination type). The parallel combination type includes a configuration that combines serial connection and parallel connection of small-scale shift registers. Generally, the single type is suitable for a small chip area, and the parallel combination type is suitable for high speed. One of the reasons why the parallel combination type is suitable for high speed is that when a plurality of serial-parallel converters are arranged in parallel and operated simultaneously (hereinafter referred to as a multi-lane type), it is easy to reduce the skew of the clock and data output between lanes.

[0004] Furthermore, a parallel-type serial-parallel converter has the advantage of being easily applicable to a system where serial data is input synchronized with both the rising and falling edges of the input clock (let's call this the double-edge type).

[0005] In a parallel-type serial-parallel converter, the first stage of the serial input uses one or a few parallel-connected flip-flops driven by a clock at the original frequency (before frequency division). The limit to which the serial data input timing can have sufficient margin both ahead (setup time) and behind (hold time) the input clock edge to these first-stage flip-flops determines the limit to how fast the serial-parallel converter itself can be made. Therefore, distributing the original clock to the first-stage flip-flops in a way that does not slow down the original clock is well worthwhile, even if it increases chip area and power consumption.

[0006] On the other hand, the data input timing for the second and subsequent stages of a serial-parallel converter corresponds to the output timing of the preceding flip-flop, and is therefore largely determined by the clock input timing to the preceding stage. Furthermore, the clock input for the second and subsequent stages of the flip-flop is the slower frequency after the original oscillator clock has been divided. In other words, the setup time and hold time for the second and subsequent stages of the serial-parallel converter are both largely determined by the clock input timing, resulting in relatively small skew and much greater time leeway than the first stage. Consequently, the impact on the speed limit for the second and subsequent stages is small, and there is not much significance in distributing the clock so that the divided clock does not become sluggish. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 10-153641 [Summary] From the perspective of preventing data overflow in serial-parallel converters, it is crucial to distribute the clock so that it does not slow down. However, since the second stage and beyond of a serial-parallel converter have little adverse effect on the speed limit, thoroughly implementing clock slowdown countermeasures to the same extent as the first stage is not advisable in terms of miniaturizing chip area and reducing power consumption. In particular, in ultra-high-speed devices, the acceptable level of clock slowdown is strict, making it difficult to thoroughly implement slowdown countermeasures.

[0008] Furthermore, in a parallel-type serial-to-parallel converter, the number of flip-flops arranged in parallel increases towards the later stages, resulting in a much larger load capacitance that the divided clock signal must drive, making it more difficult to suppress clock slack.

[0009] Naturally, the more stages a parallel-type serial-to-serial converter has, the more the number of signals in the divided clock also increases (divided by 2, 4, 8, etc.), making it more difficult to suppress all clock slowdowns.

[0010] A common method for driving large load capacitances without degradation is to increase the size of the signal output driver. However, adopting more miniaturized, advanced manufacturing technologies suitable for high-speed serial-parallel converters tends to increase the parasitic resistance of the signal wiring. In this case, the driving capability of the large driver is offset, making it difficult to completely suppress the degradation of the divided clock, even if area and power are disregarded.

[0011] To mitigate the negative effects of wiring resistance, techniques such as widening the wiring width or hierarchically structuring the clock distribution system in a tree-like structure can be considered, but these would lead to further increases in area and power consumption.

[0012] Therefore, the object of the present invention is to provide a parallel-type serial-parallel converter that can effectively prevent data overflow without sacrificing high-speed operation. Here, "effective" means suppressing the increase in chip area and power consumption within a range that does not contradict the increase in speed, and in particular, the object of the present invention is to suppress the area and power spent on the driver of the divided clock and the distribution of that clock.

[0013] The purpose is to prevent data clipping, especially when using manufacturing techniques that result in high wiring resistance, or when the number of serial-to-parallel conversion stages increases, leading to a larger number of flip-flops driven by divided clocks of the same frequency (e.g., two divided by 2, two divided by 4, etc.), and when the sloppiness of the divided clock waveform cannot be completely eliminated.

[0014] The serial-parallel converter of the present invention consists of multiple stages of conversion units, each having a data transfer circuit, the data transfer circuit having one input terminal, two output terminals, and a flip-flop provided between the input terminal and each of the two output terminals, and in each of the multiple stages of conversion units, the flip-flop performs a data transfer operation for input data to the input terminal in synchronization with a clock of a different frequency, thereby outputting 2 bits of data in parallel from the two output terminals, and in the adjacent preceding and succeeding stages of the multiple stages of conversion units, the number of data transfer circuits in each of the multiple stages of conversion units is equal to the number of output terminals of the preceding stage of conversion unit A serial-to-parallel converter that corresponds to a number of such converters, wherein each of the output terminals of the preceding data transfer circuit is connected to the input terminal of the subsequent data transfer circuit, serial data is input to the input terminal of the data transfer circuit of the first stage of the multi-stage converter, and parallel data is output from the output terminals of each of the data transfer circuits of the final stage of the multi-stage converter, characterized in that at least some of the flip-flops of the converter in which the clock frequency is lower than that of the other converters have a relatively larger data transfer delay than the flip-flops of the other converters. [Brief explanation of the drawing]

[0015] [Figure 1] This is a circuit diagram showing the configuration of a serial-parallel converter according to Embodiment 1 of the present invention. [Figure 2] This is a circuit diagram showing the configuration of the flip-flops in a serial-to-parallel converter. [Figure 3]This waveform diagram shows the degradation of each clock signal used in a serial-to-parallel converter. [Figure 4] This is a comparative waveform diagram showing data breakout in a serial-parallel converter to which the present invention is not applied. [Figure 5] This waveform diagram shows the data overflow prevention state in a serial-parallel converter to which the present invention is applied. [Figure 6] This is a circuit diagram showing the configuration of a serial-parallel converter according to Embodiment 2 of the present invention. [Figure 7] This is a circuit diagram showing another configuration of the flip-flops in a serial-parallel converter as Embodiment 3 of the present invention. [Detailed Description] Embodiments of the present invention will be described in detail below with reference to the drawings. [Example 1]

[0016] Figure 1 shows the configuration of a serial-parallel converter 10 to which the present invention is applied. The serial-parallel converter 10 is a so-called parallel combined type with one input and eight outputs, consisting of one lane. The data is of the complementary data input type, and the clock is of the complementary clock input type. The input terminals of the serial-parallel converter 10 are the serial data input terminal SD and the inverting serial data input terminal SDN. The output terminals of the serial-parallel converter 10 are the 8-bit parallel output terminals PD0 to PD7. The serial-parallel converter 10 consists of three stages: the first stage conversion unit 11 to the third stage conversion unit 13.

[0017] The first stage conversion unit 11 is provided with a clock input terminal C1IN and an inverting clock input terminal C1NIN, and the primary oscillator clock C1 and the inverting primary oscillator clock C1NIN are supplied to the clock input terminal C1IN and the inverting clock input terminal C1NIN as clock signals, respectively. The second stage conversion unit 12 is provided with a clock input terminal C2IN and an inverting clock input terminal C2NIN, and the clock input terminal C2IN and the inverting clock input terminal C2NIN are supplied with a 2-division clock C2 and an inverting 2-division clock C2N as clock signals. The third stage conversion unit 13 is provided with a clock input terminal C4IN and an inverting clock input terminal C4NIN, and the clock input terminal C4IN and the inverting clock input terminal C4NIN are supplied with a 4-division clock C4 and an inverting 4-division clock C4N as clock signals.

[0018] The primary vibration clock C1 and the inverting primary vibration clock C1N are complementary to each other, with the inverting primary vibration clock C1N being the clock with the opposite phase to the primary vibration clock C1. The primary vibration clock C1 and the inverting primary vibration clock C1N are generated based on the primary vibration clock C1S, which is shown as a waveform in Figure 3.

[0019] The 2-division clock C2 and the inverting 2-division clock C2N are complementary to each other, with the inverting 2-division clock C2N being the clock with the opposite phase to the 2-division clock C2. Furthermore, the 2-division clock C2 and the inverting 2-division clock C2N are obtained by dividing the original oscillator clock C1 and the inverting original oscillator clock C1N by half, respectively. Similarly, the 4-division clock C4 and the inverting 4-division clock C4N are complementary to each other, with the inverting 4-division clock C4N being the clock with the opposite phase to the 4-division clock C4. Furthermore, the 4-division clock C4 and the inverting 4-division clock C4N are obtained by dividing the original oscillator clock C1 and the inverting original oscillator clock C1N by four, respectively. Although not shown in the diagram, the serial-parallel converter 10 is equipped with frequency divider circuits for 1 / 2 and 1 / 4 division.

[0020] The serial - parallel converter 10 has 21 flip - flops FF1 to FF21 and inverters INV0 to INV7. Three flip - flops FF1 to FF3 constitute the first - stage conversion unit 11, six flip - flops FF4 to FF9 constitute the second - stage conversion unit 12, and twelve flip - flops FF10 to FF21 and inverters INV0 to INV7 constitute the third - stage conversion unit 13.

[0021] In the first - stage conversion unit 11, flip - flops FF1 to FF3 constitute one data transfer circuit 11a. In the second - stage conversion unit 12, flip - flops FF4, FF5, FF8 constitute a data transfer circuit 12a, and flip - flops FF6, FF7, FF9 constitute another data transfer circuit 12b. In the third - stage conversion unit 13, the parts of flip - flops FF10, FF11, FF18 and inverters INV0, INV4, the parts of flip - flops FF12, FF13, FF19 and inverters INV1, INV5, the parts of flip - flops FF14, FF15, FF20 and inverters INV2, INV6, and the parts of flip - flops FF16, FF17, FF21 and inverters INV3, INV7 each constitute data transfer circuits 13a to 13d.

[0022] Flip - flops FF1 to FF21 have the same configuration, having a data input terminal D, an inverted data input terminal DN, a data output terminal Q, an inverted data output terminal QN, and also having a clock input terminal CK and an inverted clock input terminal CKN (see Figure 2).

[0023] In Figure 1, among flip - flops FF1 to FF21, the flip - flops marked as "Pos" (hereinafter sometimes referred to as Pos flip - flops) FF1, FF5, FF7 - 9, FF11, FF13, FF15, FF17 - FF21 capture data at the rising edge of the non - inverted clock, and the remaining flip - flops marked as "Neg" (hereinafter sometimes referred to as Neg flip - flops) FF2, FF3, FF4, FF6, FF10, FF12, FF14, FF16 capture data at the falling edge of the non - inverted clock.

[0024] The connection relationships between the flip-flops FF1 through FF21 are as follows:

[0025] In the first stage conversion unit 11, the clock input terminal CK of the Pos flip-flop FF1 is connected to the clock input terminal C1IN, and the inverting clock input terminal CKN is connected to the inverting clock input terminal C1NIN. On the other hand, the clock input terminal CK of the Neg flip-flops FF2 and FF3 is connected to the inverting clock input terminal C1NIN, and the inverting clock input terminal CCKN is connected to the clock input terminal C1IN.

[0026] Furthermore, in the first stage conversion unit 11, the serial data input terminal SD and the inverting serial data input terminal SDN are connected to the data input terminal D and the inverting data input terminal DN of the Pos flip-flop FF1 and Neg flip-flop FF3, respectively. The data output terminal Q and the inverting data output terminal QN of the Pos flip-flop FF1 are connected to the data input terminal D and the inverting data input terminal DN of the Neg flip-flop FF2, respectively. The data output terminal Q and the inverting data output terminal QN of the Neg flip-flops FF2 and FF3 are the output terminals of the first stage conversion unit 11.

[0027] In the second stage conversion section 12, the clock input terminal CK of the Pos flip-flops FF5, FF7~FF9 is connected to the clock input terminal C2IN, and the inverting clock input terminal CKN is connected to the inverting clock input terminal C2NIN. On the other hand, the clock input terminal CK of the Neg flip-flops FF4, FF6 is connected to the inverting clock input terminal C2NIN, and the inverting clock input terminal CCKN is connected to the clock input terminal C2IN.

[0028] Furthermore, in the second stage conversion unit 12, the data input terminal D and inverted data input terminal DN of the Neg flip-flop FF4 and POS flip-flop FF8 are connected to the data output terminal Q and inverted data output terminal QN of the Neg flip-flop FF2 in the first stage conversion unit 11, respectively. The data output terminal Q and inverted data output terminal QN of the Neg flip-flop FF4 are connected to the data input terminal D and inverted data input terminal DN of the Pos flip-flop FF5, respectively. Similarly, the data input terminal D and inverted data input terminal DN of the Neg flip-flop FF6 and POS flip-flop FF9 are connected to the data output terminal Q and inverted data output terminal QN of the Neg flip-flop FF3 in the first stage conversion unit 11, respectively. The data output terminal Q and inverted data output terminal QN of the Neg flip-flop FF6 are connected to the data input terminal D and inverted data input terminal DN of the Pos flip-flop FF7, respectively. The data output terminal Q and inverted data output terminal QN of the POS flip-flops FF5, FF7, and FF9 are the output terminals of the second stage conversion unit 12.

[0029] In the third stage conversion section 13, the clock input terminal CK of the Pos flip-flops FF11, FF13, FF115, and FF17-FF9 is connected to the clock input terminal C4IN, and the inverting clock input terminal CKN is connected to the inverting clock input terminal C4NIN. On the other hand, the clock input terminal CK of the Neg flip-flops FF10, FF12, FF14, and FF16 is connected to the inverting clock input terminal C4NIN, and the inverting clock input terminal CCKN is connected to the clock input terminal C4IN.

[0030] Furthermore, in the third stage conversion unit 13, the data input terminal D and inverting data input terminal DN of the Neg flip-flop FF10 and POS flip-flop FF18 are connected to the data output terminal Q and inverting data output terminal QN of the Pos flip-flop FF5 in the second stage conversion unit 12, respectively. The data output terminal Q and inverting data output terminal QN of the Neg flip-flop FF10 are connected to the data input terminal D and inverting data input terminal DN of the Pos flip-flop FF11, respectively. The inverting data output terminal QN of the POS flip-flop FF10 is connected to the data output terminal PD0 via inverter INV0, and the inverting data output terminal QN of the POS flip-flop FF18 is connected to the data output terminal PD4 via inverter INV4.

[0031] Similarly, the data input terminal D and inverted data input terminal DN of the Neg flip-flop FF12 and the POS flip-flop FF19 are connected to the data output terminal Q and inverted data output terminal QN of the Pos flip-flop FF7 of the second stage conversion unit 12, respectively.

[0032] The data input terminal D and inverted data input terminal DN of the Neg flip-flop FF14 and POS flip-flop FF20 are connected to the data output terminal Q and inverted data output terminal QN of the Pos flip-flop FF8 in the second stage conversion unit 12, respectively.

[0033] The data input terminal D and inverted data input terminal DN of the Neg flip-flop FF16 and POS flip-flop FF21 are connected to the data output terminal Q and inverted data output terminal QN of the Pos flip-flop FF9 of the second stage conversion unit 12, respectively.

[0034] The same connection relationships as described above for Neg flip-flop FF10, POS flip-flops FF10 and FF18, and inverters INV0 and INV4 are formed in the section consisting of Neg flip-flop FF12, POS flip-flops FF13 and FF19, and inverters INV1 and INV5; the section consisting of Neg flip-flop FF14, POS flip-flops FF15 and FF20, and inverters INV2 and INV6; and the section consisting of Neg flip-flop FF16, POS flip-flops FF17 and FF21, and inverters INV3 and INV7. The data output terminals PD0 to PD7 connected to inverters INV0 to INV7 are the parallel output terminals of the serial-parallel converter 10.

[0035] The three flip-flops FF1 to FF3 in the first stage conversion unit 11 are composed only of low threshold voltage transistors. The six flip-flops FF4 to FF9 in the second stage conversion unit 12 are composed only of standard threshold voltage transistors. The twelve flip-flops FF10 to FF21 in the third stage conversion unit 13 are composed only of standard threshold voltage transistors. The eight inverters INV0 to INV7 in the third stage conversion unit 13 are composed of low threshold voltage transistors. Here, there is a relationship where low threshold voltage < standard threshold voltage.

[0036] Next, the general operation of the serial-to-parallel converter 10 having the above-described configuration will be explained. Assume that 8-bit serial data D0, D1, ..., D7 are supplied to the serial data input terminal SD in that order, and that inverted serial data DN0, DN1, ..., DN7 of serial data D0, D1, ..., D7 are supplied to the inverted serial data input terminal SDN in that order.

[0037] In the first stage conversion unit 11, three flip-flops FF1 to FF3 are driven by the primary oscillator clock C1 and the inverting primary oscillator clock C1N. First, on the rising edge of the primary oscillator clock C1 (the falling edge of the inverting primary oscillator clock C1N), D0 and DN0 are taken in from the data input terminal D and the inverting data input terminal DN of the Pos flip-flop FF1, respectively, and D0 and DN0 are output from the data output terminal Q and the inverting data output terminal QN of the Pos flip-flop FF1, respectively.

[0038] On the next falling edge of the primary oscillator clock C1 (rising edge of the inverting primary oscillator clock C1N), D0 and DN0 output from the Pos flip-flop FF1 are taken in by the data input terminal D and inverting data input terminal DN of the Neg flip-flop FF2, and D0 and DN0 are output from the data output terminal Q and inverting data output terminal QN of the Neg flip-flop FF2. At the same time, D1 and DN1 are taken in by the data input terminal D and inverting data input terminal DN of the Neg flip-flop FF3, and D1 and DN1 are output from the data output terminal Q and inverting data output terminal QN of the Neg flip-flop FF3.

[0039] In this way, the first-stage conversion unit 11 outputs data sequentially in 2-bit units (4-bit units if the inverted bit is included) based on the rising and falling edges of the original oscillator clock C1 (the falling and rising edges of the inverted original oscillator clock C1N). That is, [(D0, DN0), (D1, DN1)] is output, followed by [(D2, DN2), (D3, DN3)], ... [(D6, DN6), (D7, DN7)] in order.

[0040] In the second stage conversion section 12, six flip-flops FF4 to FF9 are driven by a 2-division clock C2 and an inverting 2-division clock C2N. First, on the falling edge of the 2-division clock C2 (the rising edge of the inverting 2-division clock C2), D0 and DN0 are taken in from the data input terminal D and the inverting data input terminal DN of the Neg flip-flop FF4, respectively, and D0 and DN0 are output from the data output terminal Q and the inverting data output terminal QN of the Neg flip-flop FF4, respectively. At the same time, D1 and DN1 are taken in from the data input terminal D and the inverting data input terminal DN of the Neg flip-flop FF6, respectively, and D1 and DN1 are output from the data output terminal Q and the inverting data output terminal QN of the Neg flip-flop FF6, respectively.

[0041] On the rising edge of the next 2-division clock C2 (falling edge of the inverted 2-division clock C2), D0 and DN0 output from Neg flip-flop FF4 are taken in by the data input terminal D and inverted data input terminal DN of Pos flip-flop FF5, and D0 and DN0 are output from the data output terminal Q and inverted data output terminal QN of Pos flip-flop FF5, respectively. At the same time, D1 and DN1 output from Neg flip-flop FF6 are taken in by the data input terminal D and inverted data input terminal DN of Pos flip-flop FF7, and D0 and DN0 are output from the data output terminal Q and inverted data output terminal QN of Pos flip-flop FF7, respectively.

[0042] Furthermore, simultaneously with the rising edge of the 2-division clock C2 (the falling edge of the inverted 2-division clock C2), the output bits D2 and DN2 of the Neg flip-flop FF2 are taken in from the data input terminal D and inverted data input terminal DN of the Pos flip-flop FF8, and D2 and DN2 are output from the data output terminal Q and inverted data output terminal QN of the Pos flip-flop FF8. At the same time, the output bits D3 and DN3 of the Neg flip-flop FF3 are taken in from the data input terminal D and inverted data input terminal DN of the Pos flip-flop FF9, and D3 and DN3 are output from the data output terminal Q and inverted data output terminal QN of the Pos flip-flop FF9.

[0043] In this way, the second stage conversion unit 12 outputs data sequentially in 4-bit units (8-bit units if the inverted bit is included) based on the falling and rising edges of the 2-division clock C2 (the rising and falling edges of the inverted 2-division clock C2). That is, [(D0, DN0), (D1, DN1), (D2, DN2), (D3, DN3)] are output simultaneously, followed by [(D4, DN4), (D5, DN5), (D6, DN6), (D7, DN7)] are output simultaneously.

[0044] In the third stage conversion unit 13, twelve flip-flops FF10 to FF21 are driven by a 4-division clock C4 and an inverting 4-division clock C4N. The operation of the flip-flops FF10 to FF21 is the same as in the second stage conversion unit 12, so it is omitted here.

[0045] In the third stage conversion unit 13, the falling and rising edges of the 4-division clock C4 (the rising and falling edges of the inverted 4-division clock C4) sequentially output parallel data in 8-bit units (16-bit units including the inverted bits) from the data output terminal Q and inverted data output terminal QN of the Pos flip-flops FF11, FF13, FF15, FF17~FF21. That is, parallel data [(D0, DN0), (D1, DN1), (D2, DN2), (D3, DN3), (D4, DN4), (D5, DN5), (D6, DN6), (D7, DN7)] are output simultaneously. The inverted parallel data DN0~DN7 are inverted by inverters INV0~INV7, so parallel data D0~D7 are output from parallel output terminals PD0~PD7.

[0046] The flip-flops FF1 to FF21 shown in Figure 1 consist of transfer gates I0 to I3, inverters I4, I5, I10, and I11, and two-input NAND gates I9, I13 to I15, as shown in Figure 2.

[0047] The preceding transfer gates I0 and I3, NAND circuits I13 and I14, and inverters I4 and I5 constitute the master latch, while the following transfer gates I1 and I2, NAND circuits I9 and I15, and inverters I10 and I11 constitute the slave latch. The input terminal of transfer gate I0 of the master latch is connected to data input terminal D, and the input terminal of transfer gate I3 is connected to inverting data input terminal DN. The output terminal of inverter I10 of the slave latch is connected to data output terminal Q, and the output terminal of inverter I11 is connected to inverting data output terminal QN.

[0048] Each of the transfer gates I0 to I3 is turned on when the inverting control terminal marked with a circle is at a low level "L" and the opposing control terminal is at a high level "H", and is turned off when the inverting control terminal is at a high level "H" and the opposing control terminal is at a low level "L".

[0049] One input terminal of NAND circuit I13 is connected to the output terminal of NAND circuit I14, and d0 of these terminals represents the master latch hold data. One input terminal of NAND circuit I14 is connected to the output terminal of NAND circuit I13, and d0n of these terminals represents the inverted data of the master latch hold data d0.

[0050] One input terminal of NAND circuit I9 is ​​connected to the output terminal of NAND circuit I15, and q0 on these terminals represents the slave latch hold data. One input terminal of NAND circuit I15 is connected to the output terminal of NAND circuit I9, and q0n on these terminals represents the inverted data of the slave hold data q0.

[0051] The high level "H" supplied to the other input terminals of NAND circuits I14 and I15 is fixed at the power supply potential. The rstn supplied to the other input terminals of NAND circuits I13 and I9 is ​​the initialization input, which is low level "L" only when the power is turned on, and high level "H" at all other times.

[0052] As described above, the clock input terminal CK and the inverting clock input terminal CKN are directly connected to the clock input terminal C1IN and the inverting clock input terminal C1NIN in the first stage conversion unit 11 of Figure 1, directly connected to the clock input terminal C2IN and the inverting clock input terminal C2NIN in the second stage conversion unit 12, and directly connected to the clock input terminal C4IN and the inverting clock input terminal C4NIN in the third stage conversion unit 13.

[0053] In the flip-flop dependency connections shown in Figure 1, using the flip-flops shown in Figure 2, the data output terminal Q and inverted data output terminal QN of the preceding flip-flop are directly connected to the data input terminal D and inverted data input terminal DN of the following flip-flop.

[0054] When the flip-flops in Figure 2 are used in the first stage conversion unit 11, flip-flops FF1 to FF3 are all composed of low threshold voltage transistors. When they are used in the second stage conversion unit 12 and the third stage conversion unit 13, flip-flops FF4 to FF21 are all composed of standard threshold voltage transistors. The design parameters of the flip-flops in each stage (e.g., gate length and gate width of the transistors) are all the same except for the threshold voltage.

[0055] In the flip-flop shown in Figure 2, for example, the inverter that layers the clock within the flip-flop as shown in Figure 4 of Japanese Patent Publication No. 2001-368079 can be omitted, thereby enabling a smaller chip area and lower power consumption.

[0056] Figure 3 is a waveform diagram showing the blunting of each complementary clock when the serial-parallel converter 10 of Embodiment 1 of the present invention shown in Figure 1 is parallelized with 4 lanes. Here, the X axis represents time, and the Y axis represents the potential of each clock.

[0057] As can be seen from Figures 1 and 2, in the case of a total of 4 lanes, the load capacity of the original oscillator clocks C1 and C1N supplied to the first stage conversion unit 11 is equivalent to 12 transfer gates, the load capacity of the 2-division clocks C2 and C2N supplied to the second stage conversion unit 12 is equivalent to 24 transfer gates, and the load capacity of the 4-division clocks C4 and C4N supplied to the third stage conversion unit 13 is equivalent to 48 transfer gates.

[0058] As can be seen from Figure 3, the load capacitance increases with each subsequent stage, causing the clock waveform to become sluggish. As the number of serial-to-parallel conversion stages increases further, the sluggishness inevitably increases even more.

[0059] In this invention, the clock distribution to the flip-flops in the first stage (first stage conversion unit 11), which determines the speed limit of the serial-parallel converter, prioritizes suppressing clock throttling over minimizing area and low power consumption. Therefore, although not shown in Figure 1, the primary oscillator clocks C1 and C1N are not shared among the four lanes, but are complementary (i.e., hierarchical) for each lane.

[0060] Figure 4 is a comparative waveform diagram showing data breakout when all flip-flops FF1 to FF21 in the first stage conversion section 11 to the third stage conversion section 13 of the serial-parallel converter 10 shown in Figure 1 are composed only of low threshold voltage transistors. In other words, it is a waveform diagram for a serial-parallel converter to which the present invention is not applied.

[0061] The waveform names in Figure 4 basically correspond to d0, d0n, q0, and q0n in Figure 2, but they correspond to the flip-flops FF10 to FF21 of the third stage conversion unit 13 in Figure 1. Therefore, the complementary clock inputs are the clock input terminals CK and CKN in Figure 2, and the 4-division clocks C4 and C4N in Figure 1 are supplied to the clock input terminals CK and CKN.

[0062] At the left end of Figure 4, CK="H" and CKN="L" are present, meaning that transfer gates I0 and I3 in Figure 2 are off, while transfer gates I1 and I2 are on. Also at the left end of Figure 4, d0=q0="L" and d0n=q0n="H" are held by the master latch and slave latch, respectively. Although not shown, the complementary data inputs in Figure 2 are pre-set to D="H" and DN="L".

[0063] Next, as shown in Figure 4, as time progresses, the 4-division clock C4 falls and the inverting-division clock C4N rises, causing transfer gates I0 and I3 to turn on. This propagates D="H" to d0 and DN="L" to d0n. Simultaneously, transfer gates I1 and I2 turn off, which is normal operation, so q0="L" and q0n="H" should be maintained.

[0064] However, in Figure 4, the 4-division clocks C4 and C4N are significantly slowed down, causing a malfunction where the input values ​​propagated to d0 and d0n pass through to q0 and q0 respectively before the transfer gates I1 and I2 are completely turned off. Similarly, at the rising edge of the 4-division clock C4, the values ​​of d0 and d0n may pass through q0 and q0 to d0 and d0n of the next stage flip-flop.

[0065] Figure 5 shows the waveform of the serial-parallel converter 10 of Embodiment 1 of the present invention, where the flip-flops FF4 to FF21 of the second stage converter 12 and the third stage converter 13 are composed of transistors with higher threshold voltages than the flip-flops FF1 to FF3 of the first stage converter 11, as shown in Figure 1.

[0066] The other conditions in Figure 5 are the same as in Figure 4. Also, the drivers and distribution systems (wiring width, length, etc.) for the 4-division clocks C4 and C4N are the same as in Figure 4, so the waveform distortion of the 4-division clocks C4 and C4N is the same as in Figure 4.

[0067] In Figure 2, the threshold voltages of the transfer gate transistors I0 and I3 are higher than in Figure 4, which slows down the signal transitions of d0 and d0n, and increases the transfer delay from d0 and d0n to q0 and q0n.

[0068] Therefore, as shown in Figure 5, when data leakage to q0 and q0n begins, the transfer gates I1 and I2 in Figure 2 are completely turned off, allowing q0="L" and q0n="H" to be maintained, thereby preventing data leakage and avoiding malfunctions caused by it.

[0069] If the transistor threshold voltage is high, even if the clock is significantly slowed down, the time when all transfer gates I0 to I3 are on decreases and the time when they are all off increases, thus preventing data overflow.

[0070] For example, as disclosed in Japanese Patent Application Publication No. 2003-168960, increased delay in data transfer of flip-flops hinders speed increases. However, as shown in Figure 1, in the parallel-type serial-parallel converter, the clock frequencies of the second-stage converter 12 and the third-stage converter 13 are half to one-quarter of those of the first-stage converter 11, so there is no adverse effect on the speed limit, and the acceptable range of clock blunting can be expanded. [Example 2]

[0071] Figure 6 shows the configuration of a serial-parallel converter 20 to which the present invention is applied. Similar to the serial-parallel converter 10 of Example 1, the serial-parallel converter 20 is a parallel-type 1-input 8-output 1-lane converter, with complementary data input and complementary clock input.

[0072] The serial-parallel converter 20, like the serial-parallel converter 10, has flip-flops FF1 to FF21 and inverters INV0 to INV7.

[0073] In the serial-parallel converter 20, all the transistors in the flip-flops FF1 to FF3 that make up the first stage conversion unit 11 are low threshold voltage transistors, all the transistors in the flip-flops FF4 to FF9 that make up the second stage conversion unit 12 are standard threshold voltage transistors, and all the transistors in the flip-flops FF10 to FF21 that make up the third stage conversion unit 13 are high threshold voltage transistors. The serial-parallel converter 20 differs from the serial-parallel converter 10 in that the flip-flops FF10 to FF21 that make up the third stage conversion unit 13 are composed only of high threshold voltage transistors.

[0074] Therefore, the serial-parallel converter 20 has the same configuration as the serial-parallel converter 10.

[0075] In the waveform shown in Figure 5, if the flip-flops FF10 to FF21 of the third stage conversion unit 13, as in the serial-parallel converter 10, are configured with transistors with standard threshold voltages, it is possible to prevent data skipping from d0 and d0n to q0 and q0n even if the 4-division clocks C4 and C4N are blunted. However, as shown in Figure 5, there are signs that q0 is beginning to rise slightly, while q0n is beginning to fall slightly. Therefore, if there are extreme manufacturing variations, etc., there is a risk that the 4-division clocks C4 and C4N may become even more blunted (from the waveforms in Figures 3 to 5) to the limit of the tolerance range for clock waveform blunting.

[0076] In contrast, in the serial-parallel converter 20 of Embodiment 2 shown in Figure 6, the transfer delay of the third-stage converter 13 is further increased by the high threshold voltage, thus expanding the acceptable range for clock waveform degradation. At the same time, since the clock frequency is half that of the second-stage converter 12, adverse effects on the high-speed operation limit can be prevented. [Example 3]

[0077] The flip-flops FF4-FF21 of the second-stage converter 12 and the third-stage converter 13 of the serial-parallel converter 10 shown in Figure 1 may be composed only of low-threshold voltage transistors, similar to the flip-flops FF1-FF3 of the first-stage converter 11. In this case, in order to increase the data transfer delay of each of the flip-flops FF4-FF21 of the second-stage converter 12 and the third-stage converter 13, each of the flip-flops FF4-FF21 can be configured as the flip-flop FF30 shown in Figure 7.

[0078] The flip-flop FF30 shown in Figure 7 includes the transfer gates I0-I3, inverters I4, I5, I10, and I11 shown in Figure 2, as well as the two-input NAND gates I9, I13-I15, and buffers I21-I24.

[0079] Buffers I21 to I24 are inserted directly before inverters I4, I5, I10, and I11, respectively. That is, the output data d0n of the NAND circuit I13, which constitutes the master latch, is supplied to inverter I4 via buffer I21; the output data d0 of the NAND circuit I14 is supplied to inverter I5 via buffer I22; the output data q0n of the NAND circuit I9, which constitutes the slave latch, is supplied to inverter I10 via buffer I23; and the output data q0 of the NAND circuit I15 is supplied to inverter I11 via buffer I24. Each of the buffers I21 to I24 is composed of, for example, two-stage inverters, which introduce a delay to the data transfer.

[0080] In each of the flip-flops FF30 shown in Figure 7, buffers I23 and I24 prevent data from passing through between flip-flops, and buffers I21 and I22 are also provided, which prevents data from passing through from the master latch to the slave latch.

[0081] This increases the transfer delay compared to the first stage converter 11, similar to the flip-flops FF4-FF21, which consist of transistors with higher threshold voltages in the second stage converter 12 and the third stage converter 13 in Figure 1. It also expands the tolerance range for clock waveform blunting in the 2-division clocks C2, C2N and the 4-division clocks C4, C4N, thereby improving data breach tolerance.

[0082] In Figure 7, the threshold voltage of the transistors constituting the flip-flop FF30 is set to be the same as the threshold voltage of the transistors constituting the flip-flops FF1 to FF3 of the first stage conversion unit 11. However, it may be set to be higher than the threshold voltage of the transistors of the flip-flops FF1 to FF3 of the first stage conversion unit 11.

[0083] Alternatively, the transistors constituting the flip-flops in the first-stage conversion unit 11 and the second-stage conversion unit 12 may be set to the same threshold voltage, and the flip-flop in the second-stage conversion unit 12 may be configured with the flip-flop FF30 shown in Figure 7. In the third-stage conversion unit 13, the transistors constituting the flip-flops may be set to a high threshold voltage as shown in Figure 1, and the flip-flop in the third-stage conversion unit 13 may be configured with the flip-flop FF30 shown in Figure 7.

[0084] Furthermore, in the flip-flop FF30 shown in Figure 7, buffers I21~I24 were added as logic gates immediately before inverters I4, I5, I10, and I11 to increase the data transfer delay. However, instead of buffers, a transfer gate that is always on can be added to increase the data transfer delay. In this case, the always-on transfer gate can be configured by fixing the clock input terminal on the side marked with a circle to a low level "L" and the clock input terminal on the opposite side to a high level "H".

[0085] Furthermore, when a MOS (Metal-Oxide-Semiconductor) transistor is used as the transistor constituting the flip-flop, the threshold voltage of the transistor can be increased by (1) changing the impurity concentration in the semiconductor substrate or well under the gate insulating film of the transistor using manufacturing techniques including ion implantation, (2) increasing the gate length of the transistor, (3) decreasing the gate width of the transistor, (4) applying a substrate bias to the semiconductor substrate or well of the transistor and adjusting the potential of the substrate bias, or (5) increasing the thickness of the gate insulating film of the transistor.

[0086] Furthermore, although the above-described examples 1 and 2 show serial-parallel converters with multiple stages as one lane, multiple lanes may also be provided in parallel.

[0087] In the serial-parallel converter of the present invention, multiple stages are treated as one lane, and the maximum data transfer rate per lane is 1.5 GPS or higher.

[0088] Therefore, in the serial-parallel converters of Examples 1 to 3, at least some of the flip-flops in the lower-clock-frequency stage of the multi-stage conversion unit have a relatively larger data transfer delay than the flip-flops in the higher-clock-frequency stage of the multi-stage conversion unit. This makes it possible to prevent data overflow without sacrificing high-speed operation and while suppressing increases in chip area and power consumption. [Explanation of Symbols]

[0089] 10 Serial-to-Parallel Converters 11. First stage conversion section 11a, 12a, 12b, 13a~13d Data transfer circuits 12 Second stage conversion section 13. Third stage conversion section 20 Serial-Parallel Converters FF1-FF21, FF30 Flip-flop I0~I3 Transfergate I4, I5, I10, I11, INV0~INV7 Inverters I9, I13~I15 NAND circuits I21~I24 Buffers

Claims

1. It consists of multiple conversion stages, each having its own data transfer circuit. The data transfer circuit has one input terminal, two output terminals, and flip-flops provided between the input terminal and each of the two output terminals, and each of the multiple stages of the conversion unit operates in synchronization with a clock of a different frequency, and the flip-flops perform a data transfer operation for the input data to the input terminal, thereby outputting 2 bits of data in parallel from the two output terminals. In the preceding and succeeding stages of the multi-stage conversion unit, the number of data transfer circuits in each of the multi-stage conversion units corresponds to the number of output terminals in the preceding stage conversion unit, and each of the output terminals of the preceding stage data transfer circuit is connected to the input terminal of the succeeding stage data transfer circuit. A serial-to-parallel converter in which serial data is input to the input terminal of the data transfer circuit of the first stage of the multi-stage conversion unit, and parallel data is output from the output terminals of each of the data transfer circuits of the final stage of the multi-stage conversion unit, A serial-parallel converter characterized in that at least some of the flip-flops in one of the multiple stages of conversion where the clock frequency is lower than that of the other conversion stages have a relatively larger data transfer delay than the flip-flops in the other conversion stages.

2. The serial-parallel converter according to claim 1, characterized in that the flip-flop comprises first and second flip-flops connected in series between the input terminal and one of the two output terminals, and a third flip-flop directly connected between the input terminal and the other output terminal of the two output terminals.

3. The serial-parallel converter according to claim 1, characterized in that the flip-flop has a master latch and a slave latch, and the large data transfer delay is present in both the master latch and the slave latch.

4. The serial-parallel converter according to claim 1, characterized in that the frequency of the clock is lower the later the stage is among the multiple stages.

5. The serial-parallel converter according to claim 1, characterized in that the number of data transfer circuits in the nth stage of the plurality of stages is 2 to the power of n-1 (where n is an integer of 1 or more).

6. The serial-parallel converter according to claim 1, characterized in that the aforementioned multiple stages are the third stage or more.

7. The serial-parallel converter according to claim 1, characterized in that the large data transfer delay is achieved by raising the threshold voltage of all transistors constituting the flip-flop.

8. The aforementioned transistor consists of a MOS (Metal-Oxide-Semiconductor) transistor. The serial-parallel converter according to claim 7, characterized in that (1) the impurity concentration in the semiconductor substrate or well beneath the gate insulating film of the transistor is changed by a manufacturing technique including ion implantation, (2) the gate length of the transistor is increased, (3) the gate width of the transistor is decreased, (4) a substrate bias is applied to the semiconductor substrate or well of the transistor and the potential of the substrate bias is adjusted, or (5) the threshold voltage of the transistor is increased by increasing the thickness of the gate insulating film of the transistor.

9. The serial-parallel converter according to claim 2, characterized in that the large data transfer delay is achieved by increasing the threshold voltage of all transistors constituting the first to third flip-flops.

10. The serial-parallel converter according to claim 1, characterized in that the aforementioned large data transfer delay is achieved by providing a logic gate in the data transfer circuit.

11. The serial-parallel converter according to claim 1, characterized in that the aforementioned large data transfer delay is achieved by providing a transfer gate in the data transfer circuit.

12. The serial-parallel converter according to claim 2, characterized in that each of the first to third flip-flops has a data input terminal and an inverting data input terminal, and a data output terminal and an inverting data output terminal, and the data input and output are in a complementary format.

13. The serial-parallel converter according to claim 2, characterized in that each of the first to third flip-flops has a clock input terminal and an inverting clock input terminal, and the clock inputs are in a complementary format.

14. The serial-parallel converter according to claim 2, characterized in that adjacent stages of the multiple stages are directly connected to each other, and the input terminal of the second flip-flop is directly connected to the output terminal of the first flip-flop in the data transfer circuit.

15. The serial-parallel converter according to claim 2, characterized in that the first flip-flop acquires data on the rising edge of the clock, and the second and third flip-flops acquire data on the falling edge of the clock, or the first flip-flop acquires data on the falling edge of the clock, and the second and third flip-flops acquire data on the rising edge of the clock.

16. The serial-parallel converter according to claim 1, characterized in that it has multiple lanes in parallel, with the multiple stages being treated as one lane.

17. The serial-parallel converter according to claim 1, characterized in that the multiple stages are treated as one lane, and the maximum data transfer rate per lane is 1.5 GPS or more.

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