Voltage-controlled oscillator circuit
The voltage-controlled oscillator circuit addresses the issues of increased size and prolonged testing times by using inverter elements with an operating current adjustment mechanism to correct frequency errors, enhancing efficiency and reducing circuit complexity.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2025-01-16
- Publication Date
- 2026-07-29
AI Technical Summary
Existing voltage-controlled oscillator circuits require a frequency detector and variable capacitor for calibration, leading to increased circuit size and prolonged testing times during product shipment.
A voltage-controlled oscillator circuit that includes an odd number of inverter elements connected in a loop, with an operating current adjustment mechanism to correct frequency errors due to manufacturing variations and temperature fluctuations by detecting and adjusting the threshold voltage of transistors.
Reduces circuit size and shortens testing time by eliminating the need for a frequency detector and variable capacitor, while effectively correcting frequency errors through dynamic current adjustments.
Smart Images
Figure 2026122657000001_ABST
Abstract
Description
Technical Field
[0006] , , , , , , , ,
[0005]
[0001] The present disclosure relates to a voltage-controlled oscillator circuit.
Background Art
[0002] In a digital circuit, in order to obtain a clock signal having a desired frequency, a PLL (Phase Locked Loop) circuit including a voltage-controlled oscillator (VCO: Voltage Controlled Oscillator) that generates a clock signal having a frequency corresponding to a control voltage is used.
[0003] The PLL circuit generates a clock signal having a desired frequency phase-locked to a reference clock signal by supplying, as a control voltage, a voltage corresponding to a phase difference between a divided clock signal obtained by dividing the frequency of the clock signal and the reference clock signal to the VCO.
[0004] In addition, as such a PLL circuit, an oscillator circuit has been proposed in which charging and discharging of a capacitor are repeatedly performed in synchronization with each cycle of a divided clock signal, and a difference between a voltage of the capacitor and a reference voltage is obtained as the phase difference (see, for example, FIG. 8 of Patent Document 1). Incidentally, this oscillator circuit is equipped with a circuit 190 that suppresses a frequency error associated with manufacturing variations and temperature fluctuations by performing calibration. The circuit 190 includes a frequency detector that compares the magnitudes of the frequencies of the divided clock signal and the reference clock signal, and performs calibration that repeatedly adjusts to increase or decrease the capacitance of the capacitor according to the comparison result until the two match.
Prior Art Documents
Patent Documents
[0005]
Patent Document 1
[0006] [Summary] Therefore, the oscillation circuit described in Patent Document 1 requires a frequency detector, variable capacitor, etc., for calibration, which increases the circuit size. In addition, during product shipment testing, calibration testing takes a relatively long time, which increases testing costs.
[0007] The voltage-controlled oscillator circuit according to this disclosure is a voltage-controlled oscillator that receives a control voltage and generates an oscillation signal with a frequency corresponding to the magnitude of the control voltage, and includes an odd number of inverter elements connected in a loop, each of which operates with an operating current corresponding to the magnitude of the control voltage, and outputs the output of one of the odd number of inverter elements as the oscillation signal; and includes a diode-connected first transistor and a first resistor, one end of which is connected to the drain of the first transistor and a predetermined voltage is applied to its other end, and detects the voltage at the drain of the first transistor as the threshold voltage of the first transistor, and the voltage-controlled oscillator includes an adjustment circuit that adjusts the operating current to increase or decrease when the threshold voltage exceeds a predetermined voltage range. [Brief explanation of the drawing]
[0008] [Figure 1] This is a block diagram showing the configuration of a PLL circuit 100 including a voltage-controlled oscillator circuit in this disclosure. [Figure 2] This is a circuit diagram showing the internal configuration of the threshold detection and determination circuit 140. [Figure 3] This is a circuit diagram showing the internal configuration of the VCO141. [Figure 4] This is a circuit diagram showing the internal configuration of each of the inversion delay cells CE1 to CE3. [Figure 5] This figure shows the control voltage versus frequency characteristic of the VCO141, representing the relationship between the control voltage Vctrl and the frequency of the output clock signal CLK. [Figure 6] This diagram illustrates the operation of the threshold detection and determination circuit 140 and the operating current adjustment circuit CAC.
[0009] [Detailed explanation] [Example 1] Figure 1 is a block diagram showing the configuration of a PLL circuit 100 including the voltage-controlled oscillator circuit of this disclosure.
[0010] The PLL circuit 100 receives a reference clock signal REF, generates a binary oscillation signal of a predetermined frequency that is phase-synchronized with the reference clock signal REF, and outputs this as the output clock signal CLK.
[0011] As shown in Figure 1, the PLL circuit 100 includes a phase comparator (PFD) 11, a charge pump circuit 12, a loop filter (LPF) 13, a voltage-controlled oscillator circuit 14 and a frequency divider 15 as described herein.
[0012] The phase comparator 11 detects the phase difference between the rising edges of the reference clock signal REF and the divided oscillation signal FV supplied from the frequency divider 15.
[0013] If the detected phase difference indicates that the rising edge of the divided oscillation signal FV lags behind the rising edge of the reference clock signal REF, the phase comparator 11 generates a phase difference signal UP with a pulse width corresponding to that phase difference. On the other hand, if the detected phase difference indicates that the rising edge of the divided oscillation signal FV leads the rising edge of the reference clock signal REF, the phase comparator 11 generates a phase difference signal DN with a pulse width corresponding to that phase difference.
[0014] The phase comparator 11 supplies the generated phase difference signals UP and DN to the charge pump circuit 12.
[0015] When the charge pump circuit 12 receives a phase difference signal UP, it generates a charge pump current with a predetermined current value and supplies it to node n0. This increases the voltage value at node n0. On the other hand, when it receives a phase difference signal DN, the charge pump circuit 12 withdraws the charge pump current from node n0. This decreases the voltage value at node n0.
[0016] By the operation of the charge pump circuit 12 described above, a control voltage Vctrl having a voltage value corresponding to the phase difference between the reference clock signal REF and the divided oscillation signal FV is generated at the node n0.
[0017] The loop filter 13 smoothes the voltage at the node n0, that is, the control voltage Vctrl. As a result, the control voltage Vctrl smoothed by the loop filter 13 is supplied to the voltage-controlled oscillator circuit 14.
[0018] The voltage-controlled oscillator circuit 14 receives the control voltage Vctrl via the node n0, generates an oscillation signal having a frequency corresponding to the voltage value of the control voltage Vctrl as an output clock signal CLK, and outputs this.
[0019] The frequency divider 15 receives the output clock signal CLK output from the voltage-controlled oscillator circuit 14, and supplies a signal obtained by dividing the output clock signal CLK according to a predetermined division ratio or a specified division ratio to the phase comparator 11 as the above-described divided oscillation signal FV.
[0020] Next, the configuration of the voltage-controlled oscillator circuit 14 will be described in detail.
[0021] As shown in FIG. 1, the voltage-controlled oscillator circuit 14 includes a threshold detection determination circuit 140 and a VCO (Voltage controlled oscillator) 141. Note that the threshold detection determination circuit 140 and the VCO 141 are formed on the same semiconductor substrate.
[0022] FIG. 2 is a circuit diagram showing the internal configuration of the threshold detection determination circuit 140. As shown in FIG. 2, the threshold detection determination circuit 140 includes a threshold detection circuit 41 and a threshold determination circuit 42.
[0023] The threshold detection circuit 41 includes a resistor RX and an N-channel transistor N1.
[0024] Resistor RX is a high resistance, for example, 100 kilohms or more, with the power supply voltage VD applied to one end and the other end connected to the drain of transistor N1.
[0025] Transistor N1 is a so-called diode-connected transistor, with its drain and gate connected, and the ground voltage VSS is applied to its source. Furthermore, transistor N1 is a MOS (metal oxide semiconductor) transistor with the same structure and characteristics as the transistors (described later) that constitute the oscillation circuit within VCO141.
[0026] With the above configuration, the voltage generated at the drain of transistor N1 is detected as the threshold voltage Vtn of transistor N1, and this is supplied to the threshold determination circuit 42.
[0027] Furthermore, the threshold voltage Vtn of transistor N1 fluctuates due to manufacturing variations and temperature changes.
[0028] The threshold determination circuit 42 includes resistors R1 to R3, a bandgap reference (BGR) circuit 400, and comparators 401 and 402.
[0029] The BGR circuit 400 generates a reference voltage Vref (or current) of, for example, 1.25 volts, which is independent of the power supply voltage, temperature, and manufacturing process, and applies this to one end of resistor R1.
[0030] Resistors R1 to R3 are connected in series, and a ground voltage VSS is applied to one end of resistor R3. Resistors R1 to R3 divide the reference voltage Vref according to their respective resistance ratios. As a result, resistors R1 to R3 supply the voltage generated at the connection node n1 between resistors R1 and R2 to comparator 401 as an upper limit voltage refH, which represents the upper limit of the voltage range of the allowable threshold voltage Vtn according to the specifications (hereinafter referred to as the allowable voltage range). Furthermore, resistors R1 to R3 supply the voltage generated at the connection node n2 between resistors R2 and R3 to comparator 401 as a lower limit voltage refL, which represents the lower limit of the allowable voltage range described above.
[0031] Comparator 401 receives a threshold voltage Vtn and an upper limit voltage refH. If the threshold voltage Vtn is higher than the upper limit voltage refH, it generates a detection signal VtH of logic level 1. If the threshold voltage Vtn is less than or equal to the upper limit voltage refH, it generates a detection signal VtH of logic level 0. Comparator 401 then supplies this detection signal VtH to VCO 141.
[0032] Comparator 402 receives a threshold voltage Vtn and a lower limit voltage refL, and generates a detection signal VtL of logic level 1 if the threshold voltage Vtn is lower than the lower limit voltage refL, and a detection signal VtL of logic level 0 if the threshold voltage Vtn is equal to or greater than the lower limit voltage refL. Comparator 402 then supplies this detection signal VtL to VCO 141.
[0033] Therefore, with the above configuration, the threshold determination circuit 42 determines whether the threshold voltage Vtn detected by the threshold detection circuit 41 is within the allowable voltage range (refL~refH), and outputs the determination result as detection signals VtL and VtH. In other words, if the threshold voltage Vtn is within the allowable voltage range, the threshold determination circuit 42 supplies detection signals VtL and VtH, both of logic level 0, to the VCO 141.
[0034] On the other hand, if the threshold voltage Vtn exceeds the allowable voltage range, especially if the threshold voltage Vtn is higher than the upper limit voltage refH, the threshold determination circuit 42 supplies a logic level 0 detection signal VtL and a logic level 1 detection signal VtH to the VCO 141 to indicate this. Furthermore, if the threshold voltage Vtn is lower than the lower limit voltage refL, the threshold determination circuit 42 supplies a logic level 1 detection signal VtL and a logic level 0 detection signal VtH to the VCO 141 to indicate this.
[0035] The VCO141 generates an oscillation signal having a frequency corresponding to the voltage value of the control voltage Vctrl as the output clock signal CLK. Furthermore, the VCO141 has an adjustment function that adjusts the frequency of the output clock signal CLK based on the detection signals VtH and VtL supplied from the threshold voltage detection circuit 140.
[0036] Figure 3 is a circuit diagram showing the internal configuration of VCO141. As shown in Figure 3, VCO141 includes inverter elements IV1 and IV2 and inversion delay cells CE1 to CE3.
[0037] The inversion delay cells CE1 to CE3 have the same internal configuration, namely including the inverter element INV and the operating current adjustment circuit CAC shown in Figure 3.
[0038] As shown in Figure 3, the inverter elements INV contained in each of the inverting delay cells CE1 to CE3 are connected in a loop, with their output terminals connected to the input terminals of other inverter elements INV. In this case, the oscillation signal output from the inverter element INV of inverting delay cell CE3, with a frequency of 1 / (6 × output delay time of the inverter element INV), becomes the output clock signal CLK described above. In other words, the VCO141 forms an oscillation circuit by connecting the three inverter elements INV in a loop.
[0039] The operating current adjustment circuit CAC contained in each of the inverting delay cells CE1 to CE3 receives the control voltage Vctrl described above.
[0040] Furthermore, each operating current adjustment circuit CAC receives a binary detection signal VtH (logic levels 0 and 1) supplied from the threshold detection and determination circuit 140 as a switch signal s1, and a binary detection signal VtL (logic levels 0 and 1) as a switch signal s2. In addition, each operating current adjustment circuit CAC receives a switch signal xs1 obtained by inverting the logic level of the switch signal s1 by the inverter element IV1, and a switch signal xs2 obtained by inverting the logic level of the switch signal s2 by the inverter element IV2.
[0041] Figure 4 is a circuit diagram showing the internal configuration of each of the inversion delay cells CE1 to CE3.
[0042] As shown in Figure 4, each inverter element INV of the inverting delay cells CE1 to CE3 includes a P-channel transistor Q1 and an N-channel transistor Q2. Both transistors Q1 and Q2 have their gates connected to the input terminal IN, and their drains connected to the output terminal OUT. Transistor Q1 receives the power supply voltage Vdd for the logic circuit at its source. Transistor Q2 has its source connected to the operating current regulation circuit CAC.
[0043] The operating current regulation circuit CAC includes N-channel transistors N_0, N_1, N_2, Q3, and Q4, and transmission gates T1 and T2.
[0044] Furthermore, the N-channel transistors N_0, N_1, and N_2 are formed on the semiconductor substrate on which transistor N1, included in the threshold detection and determination circuit 140, is formed, and are MOS transistors having the same structure and characteristics as transistor N1.
[0045] Transistors N_0, N_1, and N_2 are current sources that generate the operating current that flows to the inverter element INV. The drains of transistors N_0, N_1, and N_2 are commonly connected to the source of transistor Q2 of the inverter element INV, and each of their sources receives the ground voltage VSS.
[0046] Transistor N_0 receives a control voltage Vctrl at its gate and supplies a current of a magnitude corresponding to the voltage value of the control voltage Vctrl to transistors Q1 and Q2 of the inverter element INV as the operating current.
[0047] The transmission gate T1 receives a switch signal s1 (=VtH) at its positive terminal and a switch signal xs1 at its negative terminal. Furthermore, the transmission gate T1 receives a control voltage Vctrl and turns on when the switch signal s1 indicates logic level 1, supplying the control voltage Vctrl to the gate of transistor N_1. On the other hand, when the switch signal s1 indicates logic level 0, the transmission gate T1 turns off.
[0048] Transistor Q3 has its drain connected to the gate of transistor N_1 and receives the ground voltage VSS at its source. Transistor Q3 receives a switch signal xs1 at its gate and turns on when the switch signal xs1 indicates logic level 1, applying the ground voltage VSS to the gate of transistor N_1. On the other hand, when the switch signal xs1 indicates logic level 0, transistor Q3 is in the off state.
[0049] Specifically, the transmission gate T1 and transistor Q3 supply a control voltage Vctrl to the gate of transistor N_1 when the switch signal s1, i.e., the detection signal VtH, indicates logic level 1. On the other hand, when the switch signal s1(VtH) indicates logic level 0, they supply a ground voltage VSS to the gate of transistor N_1.
[0050] Transistor N_1 turns on when its gate receives a control voltage Vctrl, and adds a current of a magnitude corresponding to the voltage value of the control voltage Vctrl to the operating current that transistor N_0 supplies to transistors Q1 and Q2 of the inverter element INV. On the other hand, when its gate receives a ground voltage VSS, transistor N_1 turns off.
[0051] Transmission gate T2 receives a switch signal xs2 at its positive terminal and a switch signal s2 (=VtL) at its negative terminal. Furthermore, transmission gate T1 receives a control voltage Vctrl and turns on when the switch signal s2 indicates logic level 0, supplying the control voltage Vctrl to the gate of transistor N_2. On the other hand, when the switch signal s2 indicates logic level 1, transmission gate T2 is in the off state.
[0052] Transistor Q4 has its drain connected to the gate of transistor N_2 and receives the ground voltage VSS at its source. Transistor Q4 receives a switch signal s2 at its gate and turns on when the switch signal s2 indicates logic level 1, applying the ground voltage VSS to the gate of transistor N_2. On the other hand, when the switch signal s2 indicates logic level 0, transistor Q4 is in the off state.
[0053] Specifically, the transmission gate T2 and transistor Q4 supply a control voltage Vctrl to the gate of transistor N_2 when the switch signal s2, i.e., the detection signal VtL, indicates logic level 0. On the other hand, when the switch signal s2(VtL) indicates logic level 1, they supply a ground voltage VSS to the gate of transistor N_2.
[0054] Transistor N_2 turns on when its gate receives a control voltage Vctrl, and adds a current of a magnitude corresponding to the voltage value of the control voltage Vctrl to the operating current that transistor N_0 supplies to transistors Q1 and Q2 of the inverter element INV. On the other hand, when its gate receives a ground voltage VSS, transistor N_2 turns off.
[0055] The operation of the threshold detection and determination circuit 140 and VCO 141 described above will be explained in detail below.
[0056] Figure 5 shows the control voltage versus frequency characteristic of the VCO141, representing the relationship between the control voltage Vctrl and the frequency of the output clock signal CLK.
[0057] Figure 5 shows the standard control voltage-to-frequency characteristics cX (thick solid line), and the control voltage-to-frequency characteristics c1 or c2 (dotted-dotted lines) when manufacturing variations, temperature fluctuations, etc., occur.
[0058] As shown in Figure 5, the frequency of the output clock signal CLK output by VCO141 in response to the control voltage Vctrl is affected by manufacturing variations and ambient temperature, and may be higher (c1) or lower (c2) than the frequency shown in the standard control voltage-frequency characteristic cX.
[0059] Here, the factors causing the frequency of the output clock signal CLK to fluctuate are variations in the output delay time of the inverter element INV due to manufacturing variations and fluctuations in ambient temperature. In other words, the longer the output delay time of each inverter element INV, the lower the frequency of the output clock signal CLK becomes.
[0060] Incidentally, the output delay time of the inverter element INV is determined by the operating current of the inverter element INV. The operating current of the inverter element INV is determined by the threshold voltages of transistors N_0, N_1, and N_2, respectively. For example, if the threshold voltages of transistors N_0, N_1, and N_2 become higher than the standard value due to manufacturing variations or fluctuations in ambient temperature, the operating current of the inverter element INV will decrease, and the output delay time will increase. On the other hand, if the threshold voltages become lower than the standard value, the operating current of the inverter element INV will increase, and the output delay time will decrease.
[0061] Therefore, the voltage-controlled oscillator circuit 14 of this disclosure is provided with a threshold detection and determination circuit 140 that detects the threshold voltage Vtn of transistor N1, which has the same structure and characteristics as transistors N_0, N_1, and N_2. Furthermore, the voltage-controlled oscillator circuit 14 employs a configuration in which an operating current adjustment circuit CAC is mounted on the VCO 141 to individually adjust the operating current of each inverter element INV based on the detected threshold voltage Vtn.
[0062] Figure 6 shows the operation of the threshold detection and determination circuit 140 and the operating current adjustment circuit CAC.
[0063] First, when the threshold voltage Vtn of transistor N1 detected by the threshold detection determination circuit 140 is higher than the upper limit voltage refH, as shown in FIG. 6, comparators 401 and 402 output detection signals VtH and VtL with logic levels [1, 0]. By the way, when the threshold voltage Vtn is higher than the upper limit voltage refH, the frequency of the output clock signal CLK output by VCO 141 according to the control voltage Vctrl becomes lower than the allowable lower limit frequency. Therefore, at this time, the control voltage-frequency characteristic of VCO 141 becomes, for example, as shown in FIG. 5, a control voltage-frequency characteristic c2 in which the frequency of the output clock signal CLK with respect to the control voltage Vctrl is lower than the standard control voltage-frequency characteristic cX. Therefore, in such a case (refH < Vtn), in the operation current adjustment circuit CAC, according to the switch signals s1, xs1, s2, and xs2 with logic levels [1, 0, 0, 1], all the transistors N_0 to N_2 of the current source are turned on. As a result, the operation current adjustment circuit CAC flows the current obtained by synthesizing the currents flowing through each of the transistors N_0 to N_2 to the inverter element INV as the maximum operation current. As a result, the frequency of the output clock signal CLK output by VCO 141 according to the control voltage Vctrl becomes higher. Therefore, at this time, the control voltage-frequency characteristic of VCO 141 transitions from the control voltage-frequency characteristic c2 to the control voltage-frequency characteristic c2X, as indicated by the blank arrow in FIG. 5, for example. Therefore, since the control voltage-frequency characteristic of VCO 141 approaches the standard control voltage-frequency characteristic cX, the error in the frequency of the output clock signal CLK generated based on the control voltage Vctrl is reduced.
[0064] Also, when the threshold voltage Vtn detected by the threshold detection determination circuit 140 is within the allowable voltage range (refL~refH), as shown in FIG. 6, the comparators 401 and 402 output detection signals VtH and VtL indicating logic levels [0, 0]. By the way, when the threshold voltage Vtn is within the allowable voltage range, the frequency of the output clock signal CLK output by the VCO 141 also falls within the desired frequency range according to the control voltage Vctrl. Therefore, in such a case (refL<Vtn<refH), in the operation current adjustment circuit CAC, according to the switch signals s1, xs1, s2, and xs2 of logic levels [0, 1, 0, 1], the transistors N_0 and N_2 are turned on, and N_1 is turned off. As a result, the operation current adjustment circuit CAC flows a current that is one step lower than the maximum operation current, which is the sum of the currents flowing through the transistors N_0 and N_2, as the intermediate operation current to the inverter element INV. As a result, the frequency of the output clock signal CLK output by the VCO 141 according to the control voltage Vctrl follows the standard control voltage-frequency characteristic cX or a characteristic in its vicinity.
[0065] Also, when the threshold voltage Vtn detected by the threshold detection determination circuit 140 is lower than the lower limit voltage refL, as shown in FIG. 6, the comparators 401 and 402 output detection signals VtH and VtL with logic levels [0, 1]. By the way, when the threshold voltage Vtn is lower than the lower limit voltage refL, the frequency of the output clock signal CLK output by the VCO 141 according to the control voltage Vctrl becomes higher than the allowable upper limit frequency. Therefore, at this time, the control voltage - to - frequency characteristic of the VCO 141 becomes, for example, as shown in FIG. 5, a control voltage - to - frequency characteristic c1 in which the frequency of the output clock signal CLK with respect to the control voltage Vctrl is higher than the standard control voltage - to - frequency characteristic cX. So, in such a case (Vtn < refL), in the operation current adjustment circuit CAC, the transistors N_1 and N_2 are in the off state and the transistor N_0 is in the on state according to the switch signals s1, xs1, s2, and xs2 with logic levels [0, 1, 1, 0]. As a result, the operation current adjustment circuit CAC causes the current flowing through the transistor N_0, that is, a current one step lower than the above - mentioned intermediate operation current, to flow through the inverter element INV as the operation current. As a result, the frequency of the output clock signal CLK output by the VCO 141 according to the control voltage Vctrl becomes lower. Therefore, at this time, the control voltage - to - frequency characteristic of the VCO 141 transitions from the control voltage - to - frequency characteristic c1 to the control voltage - to - frequency characteristic c1X, as shown by the blank arrow in FIG. 5. Therefore, since the control voltage - to - frequency characteristic of the VCO 141 approaches the standard control voltage - to - frequency characteristic cX, the error in the frequency of the output clock signal CLK generated based on the control voltage Vctrl is reduced.
[0066] In this way, in the operation current adjustment circuit CAC, based on the detection signals VtH and VtL, only one (N_), or two (N_0, N_2), or all three of the three transistors N_0 to N_2 are set to the on state. As a result, the operation current flowing through the inverter element INV is adjusted in three steps, and the frequency of the output clock signal CLK changes due to this adjustment.
[0067] Therefore, by adjusting the operating current as described above, it is possible to reduce frequency errors in the output clock signal CLK caused by manufacturing variations, temperature fluctuations, etc.
[0068] In the voltage-controlled oscillator circuit 14 of this disclosure, the following circuit configuration is adopted to adjust the frequency error of the output clock signal CLK that occurs due to manufacturing variations, temperature fluctuations, etc. In other words, the voltage-controlled oscillator circuit 14 first detects the threshold voltage Vtn of transistor N1, which fluctuates due to manufacturing variations, temperature fluctuations, etc. Then, if this threshold voltage Vtn exceeds a predetermined allowable voltage range (refL~refH), the voltage-controlled oscillator circuit 14 adjusts the frequency of the output clock signal CLK by increasing or decreasing the operating current flowing through each of the inverter elements INV that constitute the oscillator circuit.
[0069] Therefore, the voltage-controlled oscillator circuit 14 makes it possible to reduce the circuit size compared to the circuit described in Reference 1, which uses a frequency detector to compare the frequencies of the divided clock signal and the reference clock signal and controls the capacitance of the variable capacitor according to the comparison result.
[0070] Furthermore, the voltage-controlled oscillator circuit 14 of this disclosure can shorten the test time at the time of product shipment compared to the calibration method described in Reference Document 1, which involves repeatedly changing the capacitance of a variable capacitor until the frequencies of the divided clock signal and the reference clock signal match.
[0071] In the VCO141 shown in the above embodiment, as shown in Figure 3, an oscillation circuit is formed by connecting three inverter elements INV in a loop. However, the number of inverter elements INV connected in a loop is not limited to three. In other words, the VCO141 can include an oscillation circuit in which an odd number of inverter elements INV are connected in a loop, and an operating current adjustment circuit CAC that adjusts the operating current flowing through each inverter element INV.
[0072] Furthermore, in the voltage-controlled oscillator circuit 14 shown in Figure 1, the threshold determination circuit 42 shown in Figure 2 is provided within the threshold detection circuit 140 outside the VCO 141, but this threshold determination circuit 42 may also be provided inside the VCO 141.
[0073] In short, the voltage-controlled oscillator circuit of this disclosure, which generates an oscillation signal (CLK) with a frequency corresponding to the magnitude of the control voltage (Vctrl), only needs to include the following VCO and threshold detection circuit.
[0074] In other words, the VCO (141) includes an odd number of inverter elements (INV) connected in a loop, each operating with an operating current corresponding to the magnitude of the control voltage (Vctrl), and outputs the output of one of these odd number of inverter elements as an oscillation signal (CLK). The threshold detection circuit (41) includes a diode-connected first transistor (N1) and a first resistor (RX) whose one end is connected to the drain of the first transistor and to which a predetermined voltage is applied at its other end, and detects the voltage at the drain of the first transistor as the threshold voltage of the first transistor. The VCO (141) also includes an operating current adjustment circuit (CAC) that adjusts the operating current by increasing or decreasing it if the detected threshold voltage exceeds a predetermined allowable voltage range (refL~refH).
[0075] Furthermore, this disclosure is not limited to the embodiments described above, and various improvements and design modifications are possible without departing from the spirit of this disclosure.
[0076] [Note] This specification discloses the following configuration:
[0077] (Composition 1) A voltage-controlled oscillator circuit that receives a control voltage and generates an oscillation signal with a frequency corresponding to the magnitude of the control voltage, comprising: an odd number of inverter elements connected in a loop, each operating with an operating current corresponding to the magnitude of the control voltage, and outputting the output of one of the odd number of inverter elements as the oscillation signal; a first transistor connected by diodes, and a first resistor having one end connected to the drain of the first transistor and having a predetermined voltage applied to its other end, and detecting the voltage at the drain of the first transistor as the threshold voltage of the first transistor, wherein the voltage-controlled oscillator includes an operating current adjustment circuit that adjusts the operating current to increase or decrease it when the threshold voltage exceeds a predetermined voltage range.
[0078] (Configuration 2) The voltage-controlled oscillator circuit according to configuration 1, wherein the first transistor is a transistor having the same structure and characteristics as the transistors constituting each of the odd number of inverter elements.
[0079] (Composition 3) The voltage-controlled oscillator circuit according to configuration 1 or 2, wherein the operating current adjustment circuit adjusts to increase the operating current when the threshold voltage is higher than the upper limit of the voltage range, and adjusts to decrease the operating current when the threshold voltage is lower than the lower limit of the voltage range.
[0080] (Composition 4) The voltage-controlled oscillator circuit according to configuration 3, comprising: a first comparator that determines whether the threshold voltage is higher than the upper limit of the voltage range and generates a first detection signal indicating the determination result; and a second comparator that determines whether the threshold voltage is lower than the lower limit of the voltage range and generates a second detection signal indicating the determination result, wherein the operating current adjustment circuit receives the first detection signal and the second detection signal, adjusts to increase the operating current based on the first detection signal, and adjusts to decrease the operating current based on the second detection signal.
[0081] (Composition 5) Each of the inverter elements includes a first conductivity type transistor that receives the power supply voltage at its source, and a second conductivity type transistor whose drain is connected to the drain of the first conductivity type transistor and whose gate is connected to the gate of the first conductivity type transistor, and the operating current adjustment circuit includes first to third second conductivity type transistors whose respective drains are connected to the sources of the second conductivity type transistors, and a switch circuit that turns on all of the first to third second conductivity type transistors when the first detection signal indicates that the threshold voltage is higher than the upper limit of the voltage range, and turns on only one of the first to third second conductivity type transistors when the second detection signal indicates that the threshold voltage is lower than the lower limit of the voltage range, as described in configuration 4 above. [Explanation of Symbols]
[0082] 11 Phase comparator 12 Charge pump circuit 13 Loop Filters 14. Voltage-controlled oscillator circuit 15 divider 41 Threshold detection circuit 42 Threshold Judgment Circuit 100 PLL circuits 140 Threshold detection and judgment circuit 141 VCO 400 bandgap reference circuit 401, 402 Comparators CE1~CE3 Delayed Inverted Cells CAC operating current adjustment circuit INV, IV1, IV2 Inverters N1, N_0~N_2, Q1~Q4 Transistors RX, R1~R3 resistance T1, T2 Transmission Gate
Claims
1. A voltage-controlled oscillator circuit that receives a control voltage and generates an oscillation signal with a frequency corresponding to the magnitude of the control voltage, A voltage-controlled oscillator comprising an odd number of inverter elements connected in a loop, each operating with an operating current corresponding to the magnitude of the control voltage, and outputting the output of one of the odd number of inverter elements as the oscillation signal, The circuit includes a first transistor connected by diodes, and a first resistor whose one end is connected to the drain of the first transistor and to which a predetermined voltage is applied, and a threshold detection circuit that detects the voltage at the drain of the first transistor as the threshold voltage of the first transistor, The voltage-controlled oscillator is a voltage-controlled oscillator circuit that includes an operating current adjustment circuit that adjusts the operating current to increase or decrease when the threshold voltage exceeds a predetermined voltage range.
2. The voltage-controlled oscillator circuit according to claim 1, wherein the first transistor is formed on a semiconductor substrate on which transistors for supplying the operating current are formed in each of the odd number of inverter elements, and has the same structure and characteristics as the transistors for supplying the operating current to each of the odd number of inverter elements.
3. The voltage-controlled oscillator circuit according to claim 1 or 2, wherein the operating current adjustment circuit adjusts to increase the operating current when the threshold voltage is higher than the upper limit of the voltage range, and adjusts to decrease the operating current when the threshold voltage is lower than the lower limit of the voltage range.
4. A first comparator that determines whether the threshold voltage is higher than the upper limit of the voltage range and generates a first detection signal indicating the determination result, It includes a second comparator that determines whether the threshold voltage is lower than the lower limit of the voltage range and generates a second detection signal indicating the determination result, The voltage-controlled oscillator circuit according to claim 3, wherein the operating current adjustment circuit receives the first detection signal and the second detection signal, adjusts to increase the operating current based on the first detection signal, and adjusts to decrease the operating current based on the second detection signal.
5. Each of the inverter elements is A first-conductivity transistor that receives the power supply voltage at its own source, A second conductivity transistor, the second conductivity transistor having its drain connected to the drain of the first conductivity transistor and its gate connected to the gate of the first conductivity transistor, The aforementioned operating current adjustment circuit is The first to third second-conductivity transistors, each having its drain connected to the source of the aforementioned second-conductivity transistor, The voltage-controlled oscillator circuit according to claim 4, comprising a switch circuit that sets all of the first to third second conductivity type transistors to the ON state when the first detection signal indicates that the threshold voltage is higher than the upper limit of the voltage range, and sets only one of the first to third second conductivity type transistors to the ON state when the second detection signal indicates that the threshold voltage is lower than the lower limit of the voltage range.