Semiconductor equipment

Abstract

To improve the performance of semiconductor devices while ensuring their reliability. [Solution] The semiconductor device comprises an n-type semiconductor substrate, a p-type well region PW, an n-type diffusion region NM, and a p-type impurity region PZ. The impurity concentration in the impurity region PZ is higher than the impurity concentration in the well region PW. In a plan view, the impurity region PZ surrounds at least a portion of the diffusion region NM. In a plan view, the well region PW has a rectangular shape. Each corner of the well region PW is exposed from the impurity region PZ in a plan view. The cathode of the Zener diode ZD includes the diffusion region NM. The anode of the Zener diode ZD includes the well region PW and the impurity region PZ.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a Zener diode.

Background Art

[0002] A semiconductor device in which a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a control circuit for controlling each operation of the power MOSFET are mounted together has been developed. Such a semiconductor device may be referred to as an IPD (Intelligent Power Device).

[0003] For example, Patent Document 1 discloses an IPD including two output power MOSFETs and a control circuit. The output power MOSFET is a trench gate type MOSFET. The control circuit includes a plurality of circuits having various functions and includes a plurality of MOSFETs for constituting the plurality of circuits. For example, the control circuit includes a gate driver circuit, a charge pump circuit, a temperature detection circuit, a current detection circuit, and a protection circuit, etc., and includes a plurality of planar type MOSFETs as a part of these circuits.

[0004] The protection circuit has a function of protecting a plurality of planar type MOSFETs from a surge voltage or the like. A Zener diode may be used as a part of the protection circuit.

[0005] Patent Document 2 discloses a Zener diode including an n-type cathode region and a p-type anode region. The n-type cathode region is formed so as to surround the p-type anode region.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

[0007] The semiconductor substrate of an IPD consists of an n-type support substrate and an n-type semiconductor layer formed on the support substrate. The relatively high-density support substrate constitutes the drain region, and the relatively low-density semiconductor layer constitutes the drift region. To electrically isolate the n-type cathode region from the n-type semiconductor substrate, the p-type anode region is formed to surround the n-type cathode region. Since the drain electrode is formed on the underside of the semiconductor substrate, a high voltage is applied from the underside of the semiconductor substrate. The substrate breakdown voltage of the control circuit must be higher than the avalanche breakdown voltage of the power MOSFET.

[0008] On the other hand, recent IPDs employ techniques to reduce the on-resistance of power MOSFETs by thinning the drift region and increasing the impurity concentration in the n-type drift region. Furthermore, in Zener diodes, there is a demand to reduce the area of ​​the Zener diode by lowering the anode resistance and increasing the current flow per unit area. To achieve this, one possible approach is to increase the impurity concentration in the anode region.

[0009] For these reasons, it is difficult to ensure the breakdown voltage of a control circuit including a Zener diode. In other words, it is difficult to ensure a breakdown voltage between the p-type anode region and the n-type drift region. Therefore, it is necessary to reduce the on-resistance of the power MOSFET, increase the current flow of the Zener diode, and ensure a breakdown voltage between the p-type anode region and the n-type drift region. In other words, it is necessary to improve the performance of the semiconductor device while ensuring its reliability.

[0010] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0011] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0012] A semiconductor device in one embodiment includes a Zener diode. The semiconductor device comprises an n-type semiconductor substrate, a p-type first impurity region formed in the semiconductor substrate and having a rectangular shape in plan view, an n-type second impurity region formed in the first impurity region, and a p-type third impurity region formed in the first impurity region and surrounding at least a part of the second impurity region in plan view. The impurity concentration of the third impurity region is higher than that of the first impurity region. Each corner of the first impurity region is exposed from the third impurity region in plan view. The cathode of the Zener diode includes the second impurity region. The anode of the Zener diode includes the first impurity region and the third impurity region. [Effects of the Invention]

[0013] According to one embodiment, the performance of the semiconductor device can be improved while ensuring its reliability. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a plan view showing the semiconductor device in Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 3] Figure 3 is a plan view showing the Zener diode in Embodiment 1. [Figure 4] Figure 4 is a cross-sectional view showing a Zener diode in Embodiment 1. [Figure 5] Figure 5 is a plan view showing the Zener diode in Embodiment 2. [Figure 6] Figure 6 is a plan view showing the Zener diode in the modified example 1. [Figure 7] FIG. 7 is a plan view showing a Zener diode in Embodiment 3. [Figure 8] FIG. 8 is a cross-sectional view showing a Zener diode in Embodiment 3. [Figure 9] FIG. 9 is a plan view showing a Zener diode in Modification 2. [Figure 10] FIG. 10 is a plan view showing a Zener diode in Modification 3. [Figure 11] FIG. 11 is a plan view showing a Zener diode in Modification 4. [Figure 12] FIG. 12 is a plan view showing a Zener diode in a study example.

BEST MODE FOR CARRYING OUT THE INVENTION

[0015] Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary.

[0016] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, depth direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in the present application mean that the plane composed of the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.

[0017] (Embodiment 1) <Structure of semiconductor device> The structure of the semiconductor device (semiconductor chip) 100 in Embodiment 1 will be described below with reference to Figures 1 and 2. Figure 1 shows the planar layout of the semiconductor device 100. Figure 2 shows the cross-sectional structure of the Zener diode ZD formed in region 1A and the cross-sectional structure of the power MOSFET 1Q formed in region 2A.

[0018] As shown in Figure 1, the semiconductor device 100 is an IPD and comprises regions 1A, 2A, and 3A. Multiple n-type power MOSFETs 1Q are formed in regions 2A and 3A as power MOSFETs for the output of the IPD. The power MOSFETs 1Q are trench-gate type MOSFETs.

[0019] Furthermore, the semiconductor device 100 includes a control circuit for controlling the operation of each of the multiple power MOSFETs 1Q. The control circuit is formed in region 1A and includes a gate driver circuit, a charge pump circuit, a temperature sensing circuit, a current sensing circuit, and a protection circuit. As part of these circuits, multiple low-voltage MOSFETs having a lower breakdown voltage than the breakdown voltage of the multiple power MOSFETs 1Q are formed in region 1A. The low-voltage MOSFETs are planar type MOSFETs. The protection circuit has the function of protecting the multiple low-voltage MOSFETs in region 1A from surge voltages and the like. A Zener diode ZD is formed in region 1A as part of the protection circuit.

[0020] The main feature of this invention lies in the structure of the Zener diode ZD. Therefore, in the following, the Zener diode ZD will be used as a representative example of the semiconductor element formed in region 1A.

[0021] As shown in Figure 2, the semiconductor device 100 comprises an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND.

[0022] The semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by an epitaxial growth method while introducing n-type impurities. In this case, the silicon layer constitutes the drift region NV, and the silicon substrate constitutes the drain region ND.

[0023] The impurity concentration in the drain region ND (the silicon substrate) is higher than the impurity concentration in the drift region NV (the silicon layer). That is, the resistivity of the silicon substrate is lower than the resistivity of the silicon layer. The resistivity of the silicon layer is 0.10 Ω·cm or more and 0.20 Ω·cm or less. The thickness of the silicon layer is 4.0 μm or more and 5.5 μm or less.

[0024] A drain electrode DE is formed on the underside BS of the semiconductor substrate SUB. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain electrode DE is formed over the entire underside BS of the semiconductor substrate SUB. Drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0025] <Structure of Power MOSFET 1Q> The cross-sectional structure of power MOSFET 1Q in region 2A is described below using Figure 2. Note that the cross-sectional structure of power MOSFET 1Q in region 3A is the same as that of power MOSFET 1Q in region 2A.

[0026] As shown in Figure 2, a trench TR is formed in the semiconductor substrate SUB in region 2A, extending to a predetermined depth from the upper surface TS of the semiconductor substrate SUB. Inside the trench TR, a gate electrode GE is formed via a gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film. The gate electrode GE is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0027] In region 2A, a p-type body region PB is formed in the semiconductor substrate SUB such that its depth from the top surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR. An n-type source region NS is formed within the body region PB. The impurity concentration in the source region NS is higher than that of the drift region NV. The portion of the body region PB that is adjacent to the gate electrode GE via the gate insulating film GI and located between the source region NS and the drift region NV constitutes the channel region of the power MOSFET 1Q.

[0028] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. Holes are formed in the interlayer insulating film IL that penetrate the source region NS and reach the body region PB. At the bottom of the holes, a diffusion region PR is formed in the body region PB. The diffusion region PR has a higher impurity concentration than the body region PB. The diffusion region PR is mainly provided to lower the contact resistance with the plug PG and to prevent latch-up.

[0029] A plug PG is formed inside the above-mentioned hole. The plug PG is electrically connected to the source region NS, the body region PB, and the diffusion region PR. The plug PG includes, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film.

[0030] Multiple wirings M1 are formed on the interlayer insulating film IL. The wirings M1 are electrically connected to the plug PG. The wirings M1 include, for example, a second barrier metal film, a second conductive film formed on the second barrier metal film, and a third barrier metal film formed on the second conductive film. The second and third barrier metal films are, for example, laminated films of titanium film and titanium nitride film, respectively. The second conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0031] In region 2A, the source electrode SE is formed as wiring M1. The source region NS, body region PB, and diffusion region PR of power MOSFET 1Q are supplied with source potential from the source electrode SE via plug PG.

[0032] Although not shown in the diagram, multiple upper layer wirings are formed on top of the multiple wirings M1. The connection between the control circuit and the gate electrodes GE of each of the multiple power MOSFETs 1Q can be made, for example, by routing the multiple wirings M1 and the multiple upper layer wirings from region 1A to region 2A.

[0033] <Structure of a Zener diode (ZD)> The Zener diode ZD in region 1A will be described below with reference to Figures 3 and 4. Figure 3 shows the planar layout of the Zener diode ZD. Figure 4 is a cross-sectional view along line AA shown in Figure 3.

[0034] As shown in Figure 4, in region 1A, p-type well regions HPW and p-type well regions PW are formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The well region PW is formed within the well region HPW. The well region HPW is mainly provided to increase the breakdown voltage between the p-type anode of the Zener diode ZD and the n-type drift region NV. Therefore, the impurity concentration of the well region HPW is lower than that of the well region PW. In this embodiment, the impurity concentration of the well region PW is, for example, 5 × 10⁻⁶ 17 cm -3 Furthermore, the impurity concentration in the well region HPW is, for example, 5 × 10⁻⁶. 16 cm -3 Furthermore, the well region PW is formed during the process of forming the body region PB. In other words, the well region PW is formed at the same time as the body region PB.

[0035] Within the well region PW, an n-type diffusion region NM is formed. The impurity concentration in the diffusion region NM is higher than that in the drift region NV. Furthermore, within the well region PW, an n-type diffusion region NM, a p-type impurity region PZ, and a p-type diffusion region PM are formed.

[0036] The cathode of the Zener diode ZD includes a diffusion region NM. That is, the diffusion region NM constitutes the cathode of the Zener diode ZD. On the other hand, the anode of the Zener diode ZD includes a diffusion region PM, an impurity region PZ, a well region PW, and a well region HPW. That is, each of the diffusion region PM, impurity region PZ, well region PW, and well region HPW constitutes the anode of the Zener diode ZD. As shown in Figure 2, the cathode electrode CE and the anode electrode AE ​​are formed above the Zener diode ZD as wiring M1. The diffusion region NM is electrically connected to the cathode electrode CE via plug PG. The diffusion region PM is electrically connected to the anode electrode AE ​​via plug PG.

[0037] The impurity region PZ is primarily provided to lower the anode resistance of the Zener diode ZD. Therefore, the impurity concentration in the impurity region PZ is higher than that in the well region PW. In this embodiment, the impurity concentration in the impurity region PZ is, for example, 5 × 10⁻¹⁰ 18 cm -3Therefore, in order to lower the anode resistance of the Zener diode ZD, the impurity concentration in the well region PW may be increased to the same level as that of the impurity region PZ without forming the impurity region PZ. However, if the impurity concentration in the well region PW is increased to the same level as that of the impurity region PZ, the well region PW must be formed in a different process than the process for forming the body region PB. Furthermore, if the impurity concentration in the well region PW is increased to the same level as that of the impurity region PZ without forming the impurity region PZ, a high-concentration impurity region will be formed over a wider area than the low-resistance region PZZ (see Figure 4) described later (for example, the region including the area directly below the boundary between the diffusion region NM and the field insulating film IF0). As a result, it becomes difficult to control the breakdown voltage.

[0038] The impurity concentration in the diffusion region PM is higher than the impurity concentration in the impurity region PZ. The depth of the impurity region PZ from the top surface TS of the semiconductor substrate SUB is greater than the depth of the diffusion region PM from the top surface TS of the semiconductor substrate SUB.

[0039] The impurity region PZ lowers the anode resistance of the Zener diode ZD, increasing the current flowing through it. This allows for a reduction in the planar size of the Zener diode ZD. In other words, without the impurity region PZ, the anode resistance of the Zener diode ZD increases, reducing the current flowing through it. To compensate for this reduced current, measures such as increasing the planar size of the Zener diode ZD become necessary.

[0040] Furthermore, in order to adjust (lower) the Zener voltage of the Zener diode ZD, a p-type low-resistance region PZZ may be formed in the well region PW located directly below the diffusion region NM. The impurity concentration in the low-resistance region PZZ is the same as the impurity concentration in the impurity region PZ, and is higher than the impurity concentration in the well region PW.

[0041] A field insulating film IF0 is formed in the semiconductor substrate SUB. The field insulating film IF0 is, for example, a silicon oxide film. The field insulating film IF0 is formed between the diffusion region NM and the diffusion region PM. In addition, the field insulating film IF0 is also formed on the outer periphery of the diffusion region PM, separating the Zener diode ZD from the low-voltage MOSFET formed in region 1A.

[0042] As shown in Figure 3, the diffusion region NM is contained within the well region PW and the well region HPW in a plan view. The well region PW is contained within the well region HPW in a plan view. The well regions PW and HPW form a rectangular shape in a plan view. The diffusion region PM is formed in a ring shape surrounding the diffusion region NM in a plan view. More specifically, the diffusion region PM is formed in a rectangular ring shape.

[0043] The impurity region PZ encloses at least a portion of the diffusion region NM in a plan view. In Embodiment 1, the impurity region PZ partially encloses the diffusion region NM in a plan view. The impurity region PZ includes a first location PZ1 and a second location PZ2 extending in the Y direction, and a third location PZ3 and a fourth location PZ4 extending in the X direction. The diffusion region NM is located between the first location PZ1 and the second location PZ2 in the X direction, and between the third location PZ3 and the fourth location PZ4 in the Y direction. The diffusion region PM overlaps with the first location PZ1, the second location PZ2, the third location PZ3, and the fourth location PZ4 in a plan view.

[0044] The first location PZ1, the second location PZ2, the third location PZ3, and the fourth location PZ4 are physically separated from each other. That is, the first location PZ1, the second location PZ2, the third location PZ3, and the fourth location PZ4 are not formed at the corners 10 of the Zener diode ZD. Therefore, each corner of the square-shaped well region PW is exposed from the impurity region PZ in a plan view.

[0045] Furthermore, the corner 10 contains the corner of a square ring-shaped diffusion region PM. At each corner of the square ring-shaped diffusion region PM, the portion of the diffusion region PM extending in the Y direction and the portion of the diffusion region PM extending in the X direction intersect and connect with each other.

[0046] Furthermore, as in other embodiments described later, the corner portion 10 may also contain the corner portion of a square ring-shaped impurity region PZ. At each corner portion of the square ring-shaped impurity region PZ, the portion of the impurity region PZ extending in the Y direction and the portion of the impurity region PZ extending in the X direction intersect and connect with each other.

[0047] <Main features of Embodiment 1> The main features of Embodiment 1 will be described below, but before that, a study example will be described. Figure 12 shows the planar layout of the Zener diode ZD in a study example conducted by the inventors of the present invention.

[0048] As shown in Figure 12, in the example under consideration, the impurity region PZ is formed in a ring shape surrounding the diffusion region NM in a plan view. More specifically, the impurity region PZ is formed in a square ring shape. Therefore, unlike Embodiment 1, in this example, the impurity region PZ is also formed at the corner 10. Each corner of the square-shaped well region PW is not exposed from the impurity region PZ in a plan view.

[0049] As mentioned above, in recent years, in order to reduce the on-resistance of power MOSFET 1Q, the thickness of the drift region NV has become thinner than before, and the impurity concentration of the drift region NV has become higher. By forming a relatively high-concentration impurity region PZ, the amount of current flowing through the Zener diode ZD can be increased, but the electric field generated around the impurity region PZ becomes stronger than, for example, the electric field generated directly below the diffusion region NM. In other words, it becomes difficult to ensure sufficient breakdown voltage between the p-type anode and the n-type drift region NV of the Zener diode ZD around the impurity region PZ.

[0050] In particular, at the corner 10, the electric field generated from the portion of the impurity region PZ extending in the Y direction overlaps with the electric field generated from the portion of the impurity region PZ extending in the X direction. In other words, a relatively strong electric field is concentrated at the corner 10. Therefore, in the example considered, there is a problem in that it is difficult to ensure sufficient breakdown voltage at the corner 10.

[0051] In Embodiment 1, the impurity region PZ, which has a higher impurity concentration than the well region PW (i.e., the region with a higher impurity concentration than the well region HPW), is separated into a first location PZ1, a second location PZ2, a third location PZ3, and a fourth location PZ4, so that no impurity region PZ is formed in the corner 10. Therefore, the amount of current flowing through the Zener diode ZD is greater in the study example than in Embodiment 1. However, in Embodiment 1, it is easier to ensure the breakdown voltage at the corner 10 than in the study example. In other words, in Embodiment 1, it is possible to achieve both securing the amount of current flowing through the Zener diode ZD and securing the breakdown voltage at the corner 10, so that the performance of the semiconductor device 100 can be improved and the reliability of the semiconductor device 100 can be ensured.

[0052] (Embodiment 2) The semiconductor device 100 in Embodiment 2 will be described below with reference to Figure 5. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0053] As shown in Figure 5, in Embodiment 2, the impurity region PZ is formed in a ring shape so as to surround the diffusion region NM in a plan view. More specifically, the impurity region PZ is formed in a square ring shape. Therefore, the impurity region PZ has an inner circumference and an outer circumference. In Figure 5, the outer circumference of the impurity region PZ is shown as the outer circumference PZa. The diffusion region PM overlaps with the impurity region PZ in a plan view.

[0054] In the first embodiment, each corner of the rectangular well region PW is exposed from the impurity region PZ in a plan view. In the second embodiment, the outer periphery PZa of each corner of the rectangular ring-shaped impurity region PZ is chamfered. In other words, the outer periphery PZa of each corner of the impurity region PZ extends in directions different from the Y and X directions in a plan view.

[0055] Therefore, in Embodiment 2, compared to the study example, the concentration of the electric field at the corner 10 can be mitigated, and it becomes easier to ensure withstand voltage at the corner 10. Also, in Embodiment 2, because an impurity region PZ is formed at the corner 10, the electric field is more likely to concentrate at the corner 10 compared to Embodiment 1, but the amount of current flowing through the Zener diode ZD can be increased.

[0056] (Variation 1) Figure 6 shows the Zener diode ZD in Modification 1 of Embodiment 2. As shown in Figure 6, in Modification 1, similar to Embodiment 2, the impurity region PZ is formed in a ring shape surrounding the diffusion region NM in a plan view, and is formed in a square ring shape. The diffusion region PM overlaps with the impurity region PZ in a plan view.

[0057] In Modification 1, each corner of the rectangular well region PW is exposed from the impurity region PZ in a plan view. In Modification 1, the outer circumference PZa of each corner of the rectangular ring-shaped impurity region PZ is curved. Even with the Zener diode ZD of this Modification 1, almost the same effect as in Embodiment 2 can be obtained.

[0058] (Embodiment 3) The semiconductor device 100 in Embodiment 3 will be described below with reference to Figures 7 and 8. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0059] As shown in Figure 7, in Embodiment 3, the impurity region PZ is formed in a ring shape so as to surround the diffusion region NM in a plan view. More specifically, the impurity region PZ is formed in a square ring shape. In Figure 7, the outer periphery of the impurity region PZ is shown as outer periphery PZa, the outer periphery of the diffusion region PM is shown as outer periphery PMa, the outer periphery of the well region PW is shown as outer periphery PWa, and the outer periphery of the well region HPW is shown as outer periphery HPWa.

[0060] The diffusion region PM overlaps with the impurity region PZ in a plan view. However, as shown in Figures 7 and 8, the distance from the outer perimeter PZa of the impurity region PZ to the diffusion region NM is shorter than the distance from the outer perimeter PMa of the diffusion region PM to the diffusion region NM. In other words, the distance between the outer perimeter PZa of the impurity region PZ and the outer perimeter PWa of the well region PW is longer than the distance between the outer perimeter PMa of the diffusion region PM and the outer perimeter PWa of the well region PW. Furthermore, the distance between the outer perimeter PZa of the impurity region PZ and the outer perimeter HPWa of the well region HPW is longer than the distance between the outer perimeter PMa of the diffusion region PM and the outer perimeter HPWa of the well region HPW.

[0061] To put it another way, in Embodiment 3, not only are each corner of the rectangular well region PW exposed from the impurity region PZ in a plan view, but the well region PW is also exposed from the impurity region PZ in a plan view along the entire outer periphery PZa of the impurity region PZ.

[0062] By moving the outer periphery PZa of the relatively high-concentration impurity region PZ away from the outer periphery PWa of the well region PW and the outer periphery HPWa of the well region HPW, the relatively strong electric field generated around the impurity region PZ is moved further away from the drift region NV. Therefore, in Embodiment 3, compared with the study example, it becomes easier to ensure breakdown voltage between the p-type anode of the Zener diode ZD and the n-type drift region NV. Furthermore, in Embodiment 3, compared with the study example, electric field concentration can be mitigated even at the corner 10, making it easier to ensure breakdown voltage. In other words, in Embodiment 3, it is possible to achieve both securing the amount of current flowing through the Zener diode ZD and ensuring breakdown voltage between the p-type anode and the n-type drift region NV.

[0063] (Modification 2) Figure 9 shows the Zener diode ZD in Modification 2 of Embodiment 3. In Modification 2, the technology of Embodiment 3 is applied in combination with the technology of Embodiment 1.

[0064] As shown in Figure 9, the first location PZ1, second location PZ2, third location PZ3, and fourth location PZ4 of Embodiment 1 are moved away from the outer perimeter PWa of the well region PW and the outer perimeter HPWa of the well region HPW compared to the state in Figure 3. That is, the distance from the outer perimeter PZ1a of the first location PZ1, the outer perimeter PZ2a of the second location PZ2, the outer perimeter PZ3a of the third location PZ3, and the outer perimeter PZ4a of the fourth location PZ4 to the diffusion region NM is shorter than the distance from the outer perimeter PMa of the diffusion region PM to the diffusion region NM.

[0065] The amount of current flowing through the Zener diode ZD is greater in Embodiment 1 than in Modification 2. However, in Modification 2, compared to Embodiment 1, it is easier to ensure a breakdown voltage between the p-type anode and the n-type drift region NV.

[0066] (Variation 3) Figure 10 shows the Zener diode ZD in Modification 3 of Embodiment 2. In Modification 3, the technology of Embodiment 3 is applied in combination with the technology of Embodiment 2.

[0067] As shown in Figure 10, the impurity region PZ of Embodiment 2 is moved away from the outer periphery PWa of the well region PW and the outer periphery HPWa of the well region HPW compared to the state in Figure 5. That is, the distance from the outer periphery PZa of the impurity region PZ to the diffusion region NM is shorter than the distance from the outer periphery PMa of the diffusion region PM to the diffusion region NM.

[0068] The amount of current flowing through the Zener diode ZD is greater in Embodiment 2 than in Modification 3. However, in Modification 3, compared to Embodiment 2, it is easier to ensure withstand voltage between the p-type anode and the n-type drift region NV.

[0069] (Modification 4) Figure 11 shows the Zener diode ZD in Modification 4 of Modification 1. In Modification 4, the technology of Embodiment 3 is combined and applied to the technology of Modification 1.

[0070] As shown in Figure 11, the impurity region PZ of Modified Example 1 is moved further away from the outer periphery PWa of the well region PW and the outer periphery HPWa of the well region HPW compared to the state in Figure 6. That is, the distance from the outer periphery PZa of the impurity region PZ to the diffusion region NM is shorter than the distance from the outer periphery PMa of the diffusion region PM to the diffusion region NM.

[0071] The amount of current flowing through the Zener diode ZD is greater in Modification 1 than in Modification 4. However, in Modification 4, it is easier to ensure withstand voltage between the p-type anode and the n-type drift region NV compared to Modification 1.

[0072] Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention. [Explanation of Symbols]

[0073] 100 Semiconductor Equipment 10 corners 1A, 2A, 3A area Q1 Power MOSFETs AE anode electrode BS semiconductor substrate bottom surface CE cathode electrode DE drain electrode GE Terminal GI gate insulating film HPW well area HPWa outer perimeter IF0 Field Insulation Film IL interlayer film M1 Wiring ND Drain region (impurity region) NM diffusion region (impurity region) NS source area (impurity area) NV drift region (impurity region) PB body region (impurity region) PG Plug PM diffusion region (impurity region) PMa outer circumference PR diffusion region (impurity region) PW well region (impurity region) PWa outer circumference PZ impurity region PZa, PZ1a, PZ2a, PZ3a, PZ4a outer circumference PZZ low resistance region (impurity region) SE Source Electrode SUB Semiconductor Substrate TR Trench Top surface of TS semiconductor substrate ZD Zener diode

Claims

1. A semiconductor device having a Zener diode, An n-type semiconductor substrate having an upper surface and a lower surface, A first p-type impurity region is formed in the semiconductor substrate so as to extend to a predetermined depth from the upper surface of the semiconductor substrate and has a rectangular shape in plan view, The n-type second impurity region formed in the first impurity region, A p-type third impurity region is formed within the first impurity region and, in a plan view, surrounds at least a part of the second impurity region, Equipped with, The impurity concentration in the third impurity region is higher than the impurity concentration in the first impurity region. Each corner of the first impurity region is exposed from the third impurity region in a plan view. The cathode of the Zener diode includes the second impurity region, The anode of the Zener diode includes the first impurity region and the third impurity region, wherein the semiconductor device is a semiconductor device.

2. In the semiconductor device described in claim 1, The third impurity region comprises a first and second location extending in a first direction in a plan view, and a third and fourth location extending in a second direction perpendicular to the first direction in a plan view. Includes, The second impurity region is located between the first and second locations in the second direction, and between the third and fourth locations in the first direction. A semiconductor device in which the first, second, third, and fourth locations are physically separated from each other.

3. In the semiconductor device described in claim 2, The present invention further comprises a p-type fourth impurity region formed within the first impurity region and formed in a square ring shape so as to surround the second impurity region in a plan view, The impurity concentration in the fourth impurity region is higher than the impurity concentration in the third impurity region. The depth of the third impurity region from the upper surface of the semiconductor substrate is deeper than the depth of the fourth impurity region from the upper surface of the semiconductor substrate. The fourth impurity region overlaps with the first, second, third, and fourth locations in a plan view. The anode of the Zener diode further includes the fourth impurity region, wherein the semiconductor device.

4. In the semiconductor device described in claim 3, A semiconductor device wherein the distance from the outer periphery of each of the first, second, third, and fourth locations to the second impurity region is shorter than the distance from the outer periphery of the fourth impurity region to the second impurity region.

5. In the semiconductor device described in claim 1, The third impurity region is formed in a square ring shape so as to surround the second impurity region in a plan view. The impurity concentration in the third impurity region is higher than the impurity concentration in the first impurity region. The outer periphery of each corner of the third impurity region is either chamfered or curved, in a semiconductor device.

6. In the semiconductor device described in claim 5, The present invention further comprises a p-type fourth impurity region formed within the first impurity region and formed in a square ring shape so as to surround the second impurity region in a plan view, The impurity concentration in the fourth impurity region is higher than the impurity concentration in the third impurity region. The depth of the third impurity region from the upper surface of the semiconductor substrate is deeper than the depth of the fourth impurity region from the upper surface of the semiconductor substrate. The aforementioned fourth impurity region overlaps with the aforementioned third impurity region in a plan view. The anode of the Zener diode further includes the fourth impurity region, wherein the semiconductor device.

7. In the semiconductor device described in claim 6, A semiconductor device in which the distance from the outer periphery of the third impurity region to the second impurity region is shorter than the distance from the outer periphery of the fourth impurity region to the second impurity region.

8. In the semiconductor device described in claim 1, The present invention further comprises a p-type fourth impurity region formed within the first impurity region and formed in a square ring shape so as to surround the second impurity region in a plan view, The third impurity region is formed in a square ring shape so as to surround the second impurity region in a plan view. The impurity concentration in the third impurity region is higher than the impurity concentration in the first impurity region, and lower than the impurity concentration in the fourth impurity region. The depth of the third impurity region from the upper surface of the semiconductor substrate is deeper than the depth of the fourth impurity region from the upper surface of the semiconductor substrate. The distance from the outer periphery of the third impurity region to the second impurity region is shorter than the distance from the outer periphery of the fourth impurity region to the second impurity region. The anode of the Zener diode further includes the fourth impurity region, wherein the semiconductor device.

9. In the semiconductor device described in claim 8, The semiconductor device wherein the fourth impurity region overlaps with the third impurity region in a plan view.

10. In the semiconductor device described in claim 1, The semiconductor substrate further comprises a p-type fifth impurity region formed in the semiconductor substrate such that the depth from the upper surface of the semiconductor substrate is shallower than the depth of the first impurity region. The first impurity region is formed within the fifth impurity region and is contained within the fifth impurity region in a plan view. The anode of the Zener diode further includes the fifth impurity region, wherein the semiconductor device.

11. In the semiconductor device described in claim 1, The semiconductor substrate includes an n-type silicon substrate and an n-type silicon layer formed on the silicon substrate. The resistivity of the silicon substrate is lower than the resistivity of the silicon layer. The resistivity of the silicon layer is 0.10 Ω·cm or more and 0.20 Ω·cm or less. A semiconductor device wherein the thickness of the silicon layer is 4.0 μm or more and 5.5 μm or less.

12. In the semiconductor device described in claim 1, The first region where the Zener diode is formed, The second region where the power MOSFET is formed, A drain electrode formed on the lower surface of the semiconductor substrate, Furthermore, The aforementioned power MOSFET is A trench formed in the semiconductor substrate in the second region so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A gate electrode formed inside the trench via a gate insulating film, In the second region, a p-shaped body region formed in the semiconductor substrate is provided such that the depth from the upper surface of the semiconductor substrate is shallower than the depth of the trench. An n-type source region formed in the body region, A semiconductor device having

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