Semiconductor device and its design method

Abstract

This improves the performance of differential circuits. Furthermore, it suppresses increases in development costs and development time without causing characteristic variations in paired elements. [Solution] Each of the multiple MOS units 0Q is composed of at least one MOSFET, has the same structure, and is arranged adjacent to each other on the main surface of the semiconductor substrate in a plan view. The multiple MOS units 0Q include MOS units 1Q and 2Q which constitute part of a differential circuit as a pair of elements, and MOS unit 3Q which functions as a capacitive element.

Description

Technical Field

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[0001] The present invention relates to a semiconductor device and a design method thereof, and particularly to a semiconductor device including pair elements constituting a part of a differential circuit and a design method thereof.

Background Art

[0002] In the uppermost wiring layer of a semiconductor chip, a plurality of wirings are formed, and a part of these wirings is used as a pad electrode for connecting a bump electrode or a wire or the like. For example, Patent Document 1 discloses a technique for forming an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-type MOSFET below a pad electrode. Some of these MOSFETs are used as capacitive elements constituting a decoupling capacitor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Normally, the wiring thickness of the wiring in the uppermost wiring layer such as a pad electrode is the thickest among the wiring thicknesses of the wirings formed on the semiconductor chip. When a MOSFET is formed below such a thick wiring, it is known that the characteristics of the MOSFET vary due to the stress from these wirings. For example, due to the stress from the wiring in the uppermost wiring layer, the drain saturation current (IDsat) of the MOSFET may vary by about ±5%.

[0005] Semiconductor chips incorporate analog IP (Intellectual Property) as circuit functional blocks with specific roles. The paired elements used in the differential circuit of the analog IP are composed of, for example, a pair of MOSFETs with the same structure to achieve identical characteristics. Therefore, if a characteristic variation occurs in one of the MOSFETs, the sensitivity of the differential circuit changes significantly. To avoid such characteristic variations, it is effective to arrange the wiring of the top layer so as not to cover the paired elements.

[0006] Upper-level wiring, such as the top-level wiring layer, is often placed in the later stages of the design process. Furthermore, the layout of the top-level wiring layer is also changed depending on the package specifications for each product. If, after a layout change, a pair of elements is covered by the top-level wiring layer, the pair of elements must be moved, requiring a complete redesign of the floor plan around the analog IP. This results in increased development costs and development time. Additionally, as process miniaturization progresses, analog IP standards become stricter, making it increasingly difficult to meet analog IP standards.

[0007] Therefore, there is a need for a technology that can suppress increases in development costs and development time without causing characteristic variations in paired elements. Furthermore, there is a need for a technology that can easily meet analog IP standards even as process miniaturization progresses.

[0008] On the other hand, in analog IPs where high-speed operation is required, decoupling capacitors are placed within the analog IP to stabilize the power supply waveform. For example, a decoupling capacitor is electrically connected between the power supply wiring and the ground wiring used in a differential circuit. In this case, if the decoupling capacitor is placed far from the paired elements, the wiring resistance will increase, which will increase the amplitude of the power supply waveform and degrade the responsiveness of the decoupling capacitor. Therefore, if the decoupling capacitor can be placed close to the paired elements, the wiring resistance between the paired elements and the decoupling capacitor will decrease, improving the performance of the differential circuit.

[0009] To minimize wiring resistance, some measures involve creating a mesh structure for power supply wiring in the upper wiring layers. However, other circuits are also formed around the paired elements, making it difficult to always maintain a mesh structure for power supply wiring. Furthermore, the area of ​​the decoupling capacitor is relatively large, making it difficult to always place the decoupling capacitor close to the paired elements.

[0010] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0011] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0012] A semiconductor device in one embodiment comprises a semiconductor substrate having a first surface, and a plurality of MOS units, each composed of at least one MOSFET and having the same structure, and arranged adjacent to each other on the first surface of the semiconductor substrate in a plan view when the first surface of the semiconductor substrate is viewed from above. The plurality of MOS units include a first MOS unit and a second MOS unit that constitute part of a differential circuit as a pair of elements, and a third MOS unit that functions as a capacitive element.

[0013] A semiconductor device design method in one embodiment comprises: (a) preparing a plurality of MOS units, each composed of at least one MOSFET, each having the same structure, and arranged adjacent to each other on the first surface of the semiconductor substrate in a plan view when the first surface of the semiconductor substrate is viewed from above; (b) selecting a first MOS unit and a second MOS unit from the plurality of MOS units to constitute a part of a differential circuit as a pair element; and (c) after step (b), selecting a third MOS unit to function as a capacitive element from the remaining plurality of MOS units. [Effects of the Invention]

[0014] According to one embodiment, the performance of the differential circuit can be improved. Furthermore, it is possible to suppress increases in development costs and development time without causing characteristic variations in the paired elements. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1 is a plan view showing the semiconductor device in Embodiment 1. [Figure 2] Figure 2 is an equivalent circuit diagram showing an analog IP including a differential circuit in Embodiment 1. [Figure 3] Figure 3 is a plan view showing the layout of the pad electrodes and paired elements in Embodiment 1. [Figure 4] Figure 4 is a plan view showing the state of the pad electrode before and after the design change in Embodiment 1. [Figure 5] Figure 5 is a plan view showing the layout of the pad electrodes and paired elements in Study Example 1. [Figure 6] Figure 6 is a schematic diagram showing the wiring resistance between the paired elements and the decoupling capacitor in Study Example 2. [Figure 7] Figure 7 is a flowchart showing the design method for a semiconductor device in Embodiment 1. [Figure 8] Figure 8 is a plan view showing the layout of the pad electrodes and multiple MOS units in Embodiment 1. [Figure 9] Figure 9 is a plan view showing the layout of the pad electrodes and multiple MOS units in Embodiment 1. [Figure 10] Figure 10 is a plan view illustrating the number of MOS units that can be arranged in Embodiment 1. [Figure 11] Figure 11 is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 12] Figure 12 is a cross-sectional view showing the MOSFET and capacitive element in Embodiment 1. [Figure 13]FIG. 13 is a cross-sectional view showing a MOSFET and a capacitive element in Embodiment 1. [Figure 14] FIG. 14 is a perspective view showing an example of the structure of a MOSFET in Modification 1. [Figure 15] FIG. 15 is a plan view showing the state before and after design change of a pad electrode in Modification 2. [Figure 16] FIG. 16 is an equivalent circuit diagram showing an analog IP including a differential circuit in Embodiment 2. [Figure 17] FIG. 17 is a plan view showing the layout of a pad electrode and a pair element in Embodiment 2. [Figure 18] FIG. 18 is a plan view showing the layout of a pad electrode and a plurality of MOS units in Embodiment 2. [Figure 19] FIG. 19 is a plan view showing the layout of a pad electrode and a plurality of MOS units in Embodiment 2. [Figure 20] FIG. 20 is a plan view showing the layout of a plurality of MOS units in Embodiment 2. <00001​​​​​​​​​​​​​​​​​​​ [Figure 28] Figure 28 is a plan view showing the layout of the MOS unit which will be a capacitive element in Embodiment 3. [Figure 29] Figure 29 is a cross-sectional view showing a semiconductor device in Embodiment 3. [Figure 30] Figure 30 is a plan view showing the layout of the pad electrodes and multiple MOS units in Embodiment 4. [Figure 31] Figure 31 is a plan view showing the layout of multiple MOS units in Embodiment 5. [Figure 32] Figure 32 is a plan view showing the layout of the MOS units that are not used in Embodiment 5. [Figure 33] Figure 33 is the equivalent circuit diagram when components are evenly distributed. [Figure 34] Figure 34 is an equivalent circuit diagram when the components are arranged unevenly. [Modes for carrying out the invention]

[0016] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0017] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, depth direction, or thickness direction of a certain structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction. Also, expressions such as "plan view" or "planar view" mean that the main surface of the semiconductor substrate SUB is viewed from above.

[0018] (Embodiment 1) <Planar layout of semiconductor device> The semiconductor device 100 (semiconductor chip) in Embodiment 1 will be described below with reference to Figures 1 to 13.

[0019] Figure 1 is a plan view of the semiconductor device 100 as seen from above. As shown in Figure 1, the semiconductor device 100 includes a plurality of pad electrodes PAD formed on the uppermost wiring layer. The plurality of pad electrodes PAD are arranged in a staggered pattern. The number of pad electrodes PAD and the arrangement of the plurality of pad electrodes PAD shown in Figure 1 are examples and can be changed as appropriate. By connecting external connection members, such as bump electrodes, to the pad electrodes PAD, the semiconductor device 100 can be electrically connected to other semiconductor chips or wiring boards.

[0020] As shown in Figure 11, the semiconductor device 100 has a multilayer wiring layer consisting of wiring layers WL1 to WL8, with wiring layer WL8 constituting the uppermost wiring layer. Multiple wirings M8 are formed on wiring layer WL8. Pad electrodes PAD are part of the multiple wirings M8.

[0021] Furthermore, as shown in Figure 1, the semiconductor device 100 includes an analog IP10 as a circuit function block with a specific role.

[0022] Figure 2 shows a Bandgap Reference (BGR) circuit as a differential circuit included in the analog IP10 in Embodiment 1. MOS unit 1Q and MOS unit 2Q constitute part of the differential circuit as a pair of elements. In Embodiment 1, MOS unit 1Q and MOS unit 2Q are each composed of one n-type MOSFET.

[0023] Furthermore, the differential circuit uses power supply wiring Vdd and ground wiring Vss. Figure 2 shows the decoupling capacitance C electrically connected between the power supply wiring Vdd and the ground wiring Vss, and the wiring resistance R between the decoupling capacitance C and the paired elements.

[0024] Figure 3 is a plan view of the analog IP10, an enlarged portion of Figure 1, showing the positional relationship between multiple pad electrodes PAD and MOS units 1Q and 2Q. To avoid characteristic variations as a pair of elements, MOS units 1Q and 2Q are positioned such that, in a plan view, the coverage rate of MOS unit 1Q covered by the pad electrodes PAD is the same as the coverage rate of MOS unit 2Q covered by the pad electrodes PAD.

[0025] Here, MOS unit 1Q and MOS unit 2Q are not covered by the pad electrode PAD (wiring M8). However, if the coverage rate of MOS unit 1Q is the same as that of MOS unit 2Q, then all of MOS unit 1Q and all of MOS unit 2Q may be covered by wiring M8, or parts of MOS unit 1Q and parts of MOS unit 2Q may be covered by wiring M8.

[0026] As shown in Figure 4, the pitch between each pad electrode PAD (the pitch between each wiring M8) may change due to changes in the package specifications for each product, for example. In that case, the placement positions of MOS units 1Q and 2Q do not change, so a discrepancy occurs in the positional relationship between the pad electrode PAD and MOS units 1Q and 2Q. In Figure 4, the pitch becomes uniformly narrower with respect to the reference pad electrode PADa, and the amount of pad electrode PAD movement increases the further it is from the reference pad electrode PADa. In other words, the further it is from the reference pad electrode PADa, the greater the discrepancy in the positional relationship between the pad electrode PAD and MOS units 1Q and 2Q.

[0027] For example, when a pad electrode PAD located one pitch away from a reference pad electrode PADa in the X or Y direction moves 5 μm toward the reference pad electrode PADa, a pad electrode PAD located two pitches away from the reference pad electrode PADa in the X or Y direction will move 10 μm toward the reference pad electrode PADa.

[0028] This could result in changes to the coverage ratios of MOS unit 1Q and MOS unit 2Q, potentially leading to different coverage ratios for MOS unit 1Q and MOS unit 2Q. To address this, we will explain the design method described in Study Example 1 and the design method described in Embodiment 1. Furthermore, we will also discuss Study Example 2 as a consideration regarding the arrangement method of the decoupling capacitance C.

[0029] <Design method for example 1> In Example 1, first, as shown in Figure 5 under "Initial Design," the pitch between each wiring M8 is designed so that MOS unit 1Q and MOS unit 2Q are not covered by the pad electrodes PAD (wiring M8), and the layout of multiple wiring M8 is then performed.

[0030] Next, as shown in "Design Change" in Figure 5, the pitch between each wiring M8 may be changed. Then, a portion of MOS unit 1Q and a portion of MOS unit 2Q may be unevenly covered by the pad electrodes PAD. In other words, the coverage rate of MOS unit 1Q may be different from that of MOS unit 2Q.

[0031] In such cases, as shown in "Moving the Paired Elements" in Figure 5, the placement of MOS unit 1Q and MOS unit 2Q is changed to avoid variations in the characteristics of the paired elements. However, this requires redoing the floor plan design around the analog IP10, increasing development costs and development time. For example, although only the paired elements (MOS units 1Q and 2Q) are shown here, other elements used in the analog IP10 are densely packed around the paired elements. Since the placement of these other elements would also need to be changed, enormous development costs and development time would be required.

[0032] <Example 2> The capacitive element that functions as a decoupling capacitance C is formed within the analog IP10. In Example 2, as shown in "Example A" in Figure 6, the capacitive element C1 that functions as a decoupling capacitance C is located relatively far from MOS units 1Q and 2Q. In this case, the resistive component R1 is relatively large, so the overall wiring resistance R becomes large. As a result, the amplitude of the power supply waveform increases, and the responsiveness of the decoupling capacitance C deteriorates.

[0033] As shown in "Case B" in Figure 6, if part or all of the capacitive element C1 can be placed as capacitive element C2 in a location relatively close to MOS units 1Q and 2Q, the resistance component R2 will be smaller than the resistance component R1, thus reducing the overall wiring resistance R.

[0034] For example, if all capacitive elements C1, with a total capacitance of 10pF, are replaced with capacitive elements C2, and the difference between resistive components R1 and R2 is approximately 500mΩ, then a difference of approximately 10mV will occur in the amplitude of the power supply waveform.

[0035] <Design method of Embodiment 1> The design method for the semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 7, 8, and 9. The design method for the semiconductor device 100 comprises steps S1 to S7 shown in Figure 7.

[0036] First, as shown in "Initial Design" in Figure 8, in step S1, a plurality of MOS units 0Q are prepared, arranged adjacent to each other on the main surface of the semiconductor substrate in a plan view. Each of the plurality of MOS units 0Q consists of at least one MOSFET and has the same structure. In Embodiment 1, each of the plurality of MOS units 0Q consists of one n-type MOSFET.

[0037] In step S2, multiple wirings M8 are prepared on the uppermost wiring layer (wiring layer WL8) of the multilayer wiring layers formed above the multiple MOS units 0Q. Here, the wirings M8 to be used as pad electrodes (PADs) are prepared from among the multiple wirings M8. Next, the pitch between each wiring M8 is designed, and the layout of the multiple wirings M8 is performed.

[0038] Next, as shown in "Selection of Paired Elements and Capacitive Elements" in Figure 8, in step S3, MOS units 1Q and 2Q are selected from multiple MOS units 0Q to form a paired element that constitutes part of the differential circuit. Here, MOS units 1Q and 2Q are selected such that the coverage rate of MOS unit 1Q, as covered by wiring M8 in a plan view, is the same as the coverage rate of MOS unit 2Q, as covered by wiring M8 in a plan view.

[0039] Thus, in Embodiment 1, by preparing multiple candidate MOS units 0Q for the pair elements (MOS units 1Q and 2Q) in advance, it is possible to select MOS units 1Q and 2Q with the same coverage ratio regardless of the layout of multiple wirings M8. Therefore, no variation in the characteristics of the pair elements occurs. Furthermore, as in Example 1, for example, it is not necessary to avoid MOS units 1Q and 2Q when laying out the wirings M8, thus improving the flexibility of the wiring M8 layout.

[0040] In step S4, a MOS unit 3Q that functions as a capacitive element is selected from the remaining multiple MOS units 0Q. MOS unit 3Q is used as a decoupling capacitor C. In embodiment 1, all MOS units 0Q except for MOS units 1Q and 2Q are selected as MOS unit 3Q.

[0041] Subsequently, as shown in "Design Change" in Figure 9, the pitch between each wiring M8 may be changed. If the pitch between each wiring M8 is changed in step S5 (YES), then MOS unit 1Q and MOS unit 2Q are re-selected in step S6. If the pitch between each wiring M8 is not changed (NO), then steps S6 and S7 do not need to be performed.

[0042] As shown in "Reselection of Paired Elements and Capacitive Elements" in Figure 9, in step S6, MOS unit 1Q and MOS unit 2Q are reselected from multiple MOS units 0Q so that the coverage of MOS unit 1Q and MOS unit 2Q are the same.

[0043] In step S7, MOS unit 3Q is re-selected from the remaining MOS unit 0Q. In step S7, as in step S4, all MOS units 0Q, excluding MOS units 1Q and 2Q, are re-selected as MOS unit 3Q.

[0044] Thus, in Embodiment 1, even if the pitch between each wiring M8 is changed, MOS unit 1Q and MOS unit 2Q can be re-selected, so no variation in the characteristics of the paired elements occurs. Furthermore, since there is no need to change the placement of other elements used in the analog IP10, an increase in development costs and development time can be suppressed.

[0045] Furthermore, even if the pitch between each wiring M8 is changed in step S5, if the coverage rate of MOS unit 1Q is the same as that of MOS unit 2Q, steps S6 and S7 do not need to be performed. In other words, if the coverage rate of MOS unit 1Q is different from that of MOS unit 2Q, then MOS unit 1Q and MOS unit 2Q are re-selected in step S6, and MOS unit 3Q is re-selected in step S7.

[0046] Furthermore, in Embodiment 1, the remaining MOS unit 0Q is selected as MOS unit 3Q, and MOS unit 3Q is used as a capacitive element for the decoupling capacitance C. Since the capacitive element for the decoupling capacitance C can be placed near the paired elements MOS units 1Q and 2Q, the wiring resistance R between the paired elements and the decoupling capacitance C is reduced, the amplitude of the power supply waveform becomes smaller, and the responsiveness of the decoupling capacitance C is improved. In other words, the performance of the differential circuit can be improved.

[0047] Furthermore, if such a MOS unit 3Q is not provided, the capacitive element C1 must be provided in a location relatively far from MOS units 1Q and 2Q, as shown in "Case A" in Figure 6. In Embodiment 1, part or all of the capacitive element C1 can be replaced by the MOS unit 3Q, so the area that was planned to be provided by the capacitive element C1 can be reduced, and the area of ​​the analog IP10 can be reduced. Therefore, the semiconductor device 100 can be miniaturized.

[0048] Furthermore, if the number of capacitive elements required for the decoupling capacitance C is insufficient with only MOS unit 3Q, a capacitive element C1 is provided at a location relatively far from MOS units 1Q and 2Q to compensate for the deficiency.

[0049] Furthermore, in Embodiment 1, in order to select MOS unit 1Q and MOS unit 2Q from a plurality of MOS units 0Q, a control circuit 20 and a register 21 electrically connected to the plurality of MOS units 0Q are prepared at step S1. Also, at step S1, a power supply wiring Vdd and a ground wiring Vss used in the differential circuit are prepared.

[0050] When the layout of the wiring M8 is determined, the coverage rate of each of the plurality of MOS units 0Q is determined. The register 21 stores information regarding the coverage rate covered by the wiring M8 in a plan view for each of the plurality of MOS units 0Q. In steps S3 and S6, the control circuit 20 automatically selects the MOS unit 1Q and the MOS unit 2Q having the same coverage rate covered by the wiring M8 in a plan view from the plurality of MOS units 0Q based on the information in the register 21. Further, the control circuit 20 automatically selects all the MOS units 0Q except the MOS unit 1Q and the MOS unit 2Q as the MOS unit 3Q.

[0051] Hereinafter, with reference to FIG. 10, the number of MOS units that can be arranged between each pad electrode PAD will be described. The number of MOS units that can be arranged varies depending on the distance from the reference pad electrode PADa.

[0052] Let the size of one MOS unit be A1. When the number of MOS units 3Q other than the MOS units 1Q and 2Q is N, the area B1 where the plurality of MOS units 3Q are arranged can be expressed as "B1 = A1 × N". Also, let the shift amount between each pad electrode PAD when the pitch is changed be D1, and the number of pad electrodes PAD from the reference pad electrode PADa to the farthest pad electrode PADb be P. Note that the alternately arranged pad electrodes PAD are counted as 0.5. The margin with the pair element at the boundary of the pad electrode PAD is A1 / 2.

[0053] The maximum shift amount M of the pad electrode PAD viewed from the reference pad electrode PADa is "M = D1 × P+(A1 / 2). When the pad electrode PAD moves, by arranging the area B1 where M < B1 in the direction in which the pair element may be covered by the pad electrode PAD, the coverage between the pad electrode PAD and the pair element can be adjusted. Note that such a relationship is the same in other embodiments described later.

[0054] <Cross-sectional structure of semiconductor device> The cross-sectional structure of the semiconductor device 100 will be described below with reference to Figures 11 to 13. Figure 11 is a cross-sectional view along line AA shown in Figure 8.

[0055] As shown in Figure 11, the semiconductor device 100 comprises a semiconductor substrate SUB, a plurality of MOS units 1Q, 2Q, and 3Q formed on the main surface of the semiconductor substrate SUB, and a multilayer wiring layer formed above the plurality of MOS units 1Q, 2Q, and 3Q.

[0056] The multilayer wiring has wiring layers WL1 to WL8. Wires M1 to M8 are formed in wiring layers WL1 to WL8, respectively. The thickness of wiring M8 is greater than the thickness of wiring M1 to M7 formed in the multilayer wiring. Here, we illustrate with an example of eight multilayer wiring layers, but the number of multilayer wiring layers can be changed as appropriate.

[0057] Multiple MOS units 1Q, 2Q, and 3Q are electrically connected to wiring M1 by plug PG. Wirings M1 through M7 are electrically connected by vias V1 through V6, respectively. Wirings M7 and M8 are electrically connected by via V7.

[0058] Plug PG is formed primarily of a tungsten film, for example. Wirings M1 to M7 and vias V1 to V6 are damascene or dual damascene wirings, respectively, and are formed primarily of a copper film, for example. Via V7 is formed primarily of a tungsten film, for example. Wiring M8 is formed primarily of a patterned aluminum alloy film.

[0059] For example, as shown in FIG. 6, the connection from the MOS unit 1Q and the MOS unit 2Q to the capacitor element C1 is made not only through lower-layer wirings such as the wirings M1 and M2 but also through an upper-layer wiring such as the wiring M7, so the resistance component R1 tends to be large. On the other hand, the connection from the MOS unit 1Q and the MOS unit 2Q to the MOS unit 3Q can be made through lower-layer wirings such as the wirings M1 and M2. By using the MOS unit 3Q as the capacitor element C2, the resistance component R2 is small, so the overall wiring resistance R can be reduced.

[0060] <Cross-sectional structure of MOSFET> FIGS. 12 and 13 show the cross-sectional structures of the MOSFETs constituting the MOS units 1Q, 2Q, and 3Q. FIG. 12 shows a cross-section in the gate length direction of the MOSFET, and FIG. 13 shows a cross-section in the gate width direction of the MOSFET.

[0061] As shown in FIGS. 12 and 13, an element isolation portion STI is formed in the semiconductor substrate SUB. The semiconductor substrate SUB is made of, for example, p-type silicon. The element isolation portion STI includes a groove formed in the semiconductor substrate SUB so as to reach a predetermined depth from the main surface of the semiconductor substrate SUB, and an insulating film embedded in the groove. The insulating film is, for example, a silicon oxide film.

[0062] Each MOSFET is formed in an active region AR surrounded by the element isolation portion STI in a plan view of the semiconductor substrate SUB. A well region WR is formed in the semiconductor substrate SUB. The depth of the well region WR is deeper than the depth of the element isolation portion STI.

[0063] In each active region AR, a gate electrode GE is formed on the well region WR via a gate insulating film GI. The gate electrode GE is, for example, a polycrystalline silicon film. An impurity region SD is formed within the well region WR. The impurity region SD constitutes either the source region or the drain region of the MOSFET. The portion of the well region WR located between two impurity regions SD and below the gate electrode GE becomes the channel region of the MOSFET. The gate electrode GE, impurity region SD, and well region WR are electrically connected to the wiring M1 by a plug PG.

[0064] In Embodiment 1, each MOSFET is an n-type MOSFET. In this case, the well region WR has p-type conductivity, and the gate electrode GE and impurity region SD have n-type conductivity. In other embodiments described later, the MOSFETs constituting MOS units 1Q, 2Q, and 3Q may also be p-type MOSFETs. In p-type MOSFETs, the well region WR has n-type conductivity, and the gate electrode GE and impurity region SD have p-type conductivity.

[0065] In the MOSFETs constituting MOS unit 3Q, when the gate electrode GE is electrically connected to the power supply wiring Vdd, the well region WR and impurity region SD are electrically connected to the ground wiring Vss. When the gate electrode GE is electrically connected to the ground wiring Vss, the well region WR and impurity region SD are electrically connected to the power supply wiring Vdd.

[0066] As shown in Figure 11, the semiconductor device 100 also includes a control circuit 20 and a register 21, but the control circuit 20 and the register 21 are configured using multiple MOSFETs as shown in Figures 12 and 13.

[0067] Here, using Figures 12 and 13, we will explain the definition of the state in which MOS units 1Q, 2Q, and 3Q are covered by wiring M8. In Embodiment 1, it is considered that MOS units 1Q, 2Q, and 3Q located near the boundary with wiring M8 may be affected to some extent by the stress caused by wiring M8, and therefore, MOS units 1Q, 2Q, and 3Q that are not actually covered by wiring M8 may be defined as being covered by wiring M8.

[0068] Let L1 be the distance of the active region AR in the gate length direction of the MOSFET, and W1 be the distance of the active region AR in the gate width direction of the MOSFET. In Embodiment 1, if the MOSFETs included in MOS units 1Q, 2Q, and 3Q that are not covered by wiring M8 are formed in an active region AR that is less than or equal to L1 / 2 or W1 / 2 from wiring M8 in a plan view, then those MOS units 1Q, 2Q, and 3Q are considered to be covered by wiring M8 in a plan view.

[0069] (Variation 1) A modification 1 of Embodiment 1 is described below. Figures 12 and 13 illustrate a MOSFET with a planar structure, but the MOSFET may also have a FIN-FET structure. A MOSFET with a FIN-FET structure will be described using Figure 14.

[0070] As shown in Figure 14, the semiconductor substrate SUB is provided with a plurality of protrusions 30, which are part of the semiconductor substrate SUB. The plurality of protrusions 30 extend in the X direction and are separated from each other in the Y direction. Element isolation sections STI are formed on the semiconductor substrate SUB located between the plurality of protrusions 30. In other words, the space between the plurality of protrusions 30 corresponds to a groove formed in the semiconductor substrate SUB, and the element isolation sections STI are formed inside the groove. The upper surface of the element isolation section STI is lower than the upper surface of the protrusions 30.

[0071] The gate electrode GE extends in the Y direction and is formed to cover the top surface and both sides of at least one of the multiple protrusions 30. The gate insulating film GI is formed between the gate electrode GE and the protrusion 30. The well region WR is formed in the semiconductor substrate SUB containing the protrusion 30. The impurity region SD is formed in the protrusion 30 exposed from the gate electrode GE (in the well region WR).

[0072] In the case of a FIN-FET structure, the channel region of the MOSFET is the area within the well region WR that is located between the two impurity regions SD, which become the source region or drain region, and is covered by the gate electrode GE.

[0073] In FIN-FET structured MOSFETs, compared to planar structured MOSFETs, more MOSFETs can be arranged in the same planar area, and the gate width per MOSFET can be increased for the same planar area. Therefore, FIN-FET structured MOSFETs can secure a larger drive current compared to planar structured MOSFETs, thereby promoting miniaturization of the semiconductor device 100.

[0074] (Modification 2) A modified example of Embodiment 1, Part 2, is described below. In Embodiment 1, as shown in Figure 5, when the pitch between each pad electrode PAD (the pitch between each wiring M8) is changed, an example is shown in which the pitch becomes uniformly narrower with respect to the reference pad electrode PADa.

[0075] However, as shown in Figure 15, while the pitch between each pad electrode may not be changed due to product specifications, there are cases where fine adjustments to the position of each pad electrode are required. In other words, the entire pad electrode may need to be uniformly shifted in the Y or X direction. In such cases, by preparing multiple MOS units (0Q) in advance as candidates for the paired elements (MOS units 1Q and 2Q), it is possible to prevent variations in the characteristics of the paired elements.

[0076] (Embodiment 2) The semiconductor device 100 in Embodiment 2 will be described below with reference to Figures 16 to 21. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0077] Figure 16 shows the first-stage switch of the differential input circuit, which is included in the analog IP10 in Embodiment 2. MOS unit group 1QA and MOS unit group 2QA form part of the differential circuit as a pair of elements and are electrically connected to the ESD protection circuit 22.

[0078] As shown in Figure 17, MOS unit group 1QA consists of multiple MOS units 1Q, and MOS unit group 2QA consists of multiple MOS units 2Q. The number of multiple MOS units 1Q is equal to the number of multiple MOS units 2Q. In Embodiment 2, MOS unit 1Q and MOS unit 2Q are each composed of one p-type MOSFET.

[0079] In the equivalent circuit diagram of Figure 16, MOS unit group 1QA represents a state in which multiple MOS units 1Q are connected in parallel with each other, and MOS unit group 2QA represents a state in which multiple MOS units 2Q are connected in parallel with each other.

[0080] Furthermore, as shown in Figure 17, a separate wiring M8 is provided above the MOS unit group 1QA and MOS unit group 2QA in order to make an electrical connection with the ESD protection circuit 22, in addition to the pad electrode PAD.

[0081] The design method for the semiconductor device 100 in Embodiment 2 will be described below with reference to Figures 18 to 21. Figure 21 is a cross-sectional view along the line BB shown in Figure 18. In Embodiment 2, as in Embodiment 1, steps S1 to S7 shown in Figure 7 are performed.

[0082] First, as shown in "Initial Design" in Figure 18, in step S1, multiple MOS units 0Q are prepared, arranged adjacent to each other on the main surface of the semiconductor substrate in a plan view. Each of the multiple MOS units 0Q consists of one p-type MOSFET.

[0083] In step S2, multiple wirings M8 are prepared on the uppermost wiring layer (wiring layer WL8) of the multilayer wiring layers formed above multiple MOS units 0Q. Next, the pitch between each wiring M8 is designed, and the layout of the multiple wirings M8 is performed.

[0084] Next, as shown in Figure 18, "Selection of Paired Elements and Capacitive Elements," and in Figure 21, in step S3, multiple MOS units 1Q and multiple MOS units 2Q are selected from multiple MOS units 0Q to form a part of the differential circuit as paired elements. Here, the coverage rate of the MOS unit group 1QA covered by the wiring M8 in a plan view is the same as the coverage rate of the MOS unit group 2QA covered by the wiring M8 in a plan view. Therefore, in Embodiment 2, as in Embodiment 1, no variation in the characteristics of the paired elements occurs.

[0085] In step S4, a MOS unit 3Q that functions as a capacitive element is selected from the remaining multiple MOS units 0Q. MOS unit 3Q is used as a decoupling capacitor C. In embodiment 2, all MOS units 0Q except MOS units 1Q and MOS units 2Q are selected as MOS unit 3Q.

[0086] In Embodiment 2, the control circuit 20 and register 21 are not used to select the multiple MOS units 1Q, 2Q, and 3Q. Instead, multiple wirings formed in wiring layers below wiring layer WL8 and used for connecting differential circuits are used.

[0087] For example, as shown in Figure 20, the gate electrode GE, well region WR, and impurity region SD of the MOSFET are electrically connected to multiple wirings M1 by plugs PG, respectively. Each of the multiple wirings M1 is electrically connected to multiple wirings M2 by vias V1. By changing the arrangement of vias V1 connecting wirings M1 and M2, multiple MOS units 1Q, 2Q, and 3Q can be electrically connected to wiring corresponding to the equivalent circuit in Figure 16.

[0088] In the case of paired elements through which large currents flow, such as switches in differential input circuits, using the control circuit 20 may introduce resistance that affects the characteristics of the paired elements. Therefore, by switching the wiring by changing the placement of via V1, the influence of resistance on the current path of the differential input circuit can be avoided. Furthermore, this configuration minimizes the wiring load connected to the paired elements.

[0089] Subsequently, as shown in "Design Change" in Figure 19, the pitch between each wiring M8 may be changed. If the pitch between each wiring M8 is changed in step S5 (YES), then in step S6, multiple MOS units 1Q and multiple MOS units 2Q are reselected.

[0090] As shown in "Reselection of Paired Elements and Capacitive Elements" in Figure 19, in step S6, multiple MOS units 1Q and multiple MOS units 2Q are reselected from multiple MOS units 0Q so that the coverage rate of MOS unit group 1QA and MOS unit group 2QA are the same.

[0091] In step S7, MOS unit 3Q is re-selected from the remaining MOS unit 0Q. In step S7, as in step S4, all MOS units 0Q, excluding MOS units 1Q and 2Q, are re-selected as MOS unit 3Q.

[0092] Thus, in Embodiment 2, as in Embodiment 1, even if the pitch between each wiring M8 is changed, multiple MOS units 1Q and multiple MOS units 2Q can be reselected, so no variation in the characteristics of the paired elements occurs.

[0093] Furthermore, in Embodiment 2, as in Embodiment 1, the capacitive elements for the decoupling capacitance C can be placed near the paired elements, MOS unit group 1QA and MOS unit group 2QA. This reduces the wiring resistance R between the paired elements and the decoupling capacitance C, decreasing the amplitude of the power supply waveform and improving the responsiveness of the decoupling capacitance C. In other words, the performance of the differential circuit can be improved.

[0094] (Embodiment 3) The semiconductor device 100 in Embodiment 3 will be described below with reference to Figures 22 to 29. In the following description, the differences from Embodiments 1 and 2 will be mainly explained, and points that overlap with Embodiments 1 and 2 will not be explained.

[0095] Figure 22 shows a differential output circuit as a differential circuit included in the analog IP10 in Embodiment 3. MOS unit group 1QA and MOS unit group 2QA constitute a part of the differential circuit as a pair of elements.

[0096] As shown in Figure 23, MOS unit group 1QA consists of multiple MOS units 1Q, and MOS unit group 2QA consists of multiple MOS units 2Q. The number of multiple MOS units 1Q is equal to the number of multiple MOS units 2Q.

[0097] In the equivalent circuit diagram of Figure 22, MOS unit group 1QA represents a state in which multiple MOS units 1Q are connected in parallel with each other, and MOS unit group 2QA represents a state in which multiple MOS units 2Q are connected in parallel with each other.

[0098] In the case of a differential output circuit as shown in Figure 23, the size of each MOS unit group 1QA and MOS unit group 2QA is relatively large, so a portion of each MOS unit group 1QA and MOS unit group 2QA is easily covered by the pad electrodes. To prevent variation in the characteristics of the paired elements, the coverage rate of MOS unit group 1QA and MOS unit group 2QA are made the same.

[0099] The design method for the semiconductor device 100 in Embodiment 3 will be described below with reference to Figures 24 to 29. Figure 29 is a cross-sectional view along the CC line shown in Figure 23. In Embodiment 3, as in Embodiment 1, steps S1 to S7 shown in Figure 7 are performed.

[0100] First, as shown in "Initial Design" in Figure 24, in step S1, multiple MOS units 0Q are prepared, arranged adjacent to each other on the main surface of the semiconductor substrate in a plan view.

[0101] Next, in step S2, multiple wirings M8 are prepared on the uppermost wiring layer (wiring layer WL8) of the multilayer wiring layers formed above the multiple MOS units 0Q. Then, the pitch between each wiring M8 is designed, and the layout of the multiple wirings M8 is performed.

[0102] Next, as shown in Figure 24, "Selection of Paired Elements and Capacitive Elements," and in Figure 29, in step S3, multiple MOS units 1Q and multiple MOS units 2Q are selected from multiple MOS units 0Q to form a part of the differential circuit as paired elements. Here, the coverage rate of the MOS unit group 1QA covered by the wiring M8 in a plan view is the same as the coverage rate of the MOS unit group 2QA covered by the wiring M8 in a plan view. Therefore, in Embodiment 3, as in Embodiment 1, no variation in the characteristics of the paired elements occurs.

[0103] In step S4, a MOS unit 3Q that functions as a capacitive element is selected from the remaining multiple MOS units 0Q. MOS unit 3Q is used as a decoupling capacitor C. In embodiment 3, all MOS units 0Q except MOS units 1Q and MOS units 2Q are selected as MOS unit 3Q.

[0104] As shown in Figures 26, 27, and 28, the multiple MOS units 1Q, 2Q, and 3Q in Embodiment 3 are each composed of one or more n-type MOSFETs and one or more p-type MOSFETs. The number of one or more n-type MOSFETs is the same as the number of one or more p-type MOSFETs.

[0105] An n-type MOSFET has a p-type well region WRp, an n-type gate electrode GEn, and two impurity regions SDn that can be the source or drain region. A p-type MOSFET has an n-type well region WRn, a p-type gate electrode GEp, and two impurity regions SDp that can be the source or drain region. As shown in Figures 26 and 27, MOS unit 1Q and MOS unit 2Q have one or more n-type MOSFETs and one or more p-type MOSFETs connected in an inverter.

[0106] In Embodiment 3, similar to Embodiment 2, in order to select multiple MOS units 1Q, 2Q, and 3Q, multiple wirings formed in wiring layers below wiring layer WL8 and used for connecting differential circuits are used.

[0107] For example, as shown in Figures 26, 27, and 28, the gate electrode GEn, well region WRP, and impurity region SDn of an n-type MOSFET, and the gate electrode GEp, well region WRP, and impurity region SDp of a p-type MOSFET are each electrically connected to multiple wirings M1 by plugs PG. Each of the multiple wirings M1 is electrically connected to multiple wirings M2 by vias V1. By changing the arrangement of vias V1 connecting wirings M1 and M2, multiple MOS units 1Q, 2Q, and 3Q can be electrically connected to wiring corresponding to the equivalent circuit in Figure 22.

[0108] The differential output circuit of Embodiment 3, like the differential input circuit of Embodiment 2, also carries a large current. Therefore, by switching the wiring by changing the arrangement of via V1, the influence of resistance components on the current path of the differential output circuit can be avoided. Furthermore, this configuration minimizes the wiring load connected to the paired elements.

[0109] Subsequently, as shown in "Design Change" in Figure 25, the pitch between each wiring M8 may be changed. If the pitch between each wiring M8 is changed in step S5 (YES), then in step S6, multiple MOS units 1Q and multiple MOS units 2Q are reselected.

[0110] As shown in "Reselection of Paired Elements and Capacitive Elements" in Figure 25, in step S6, multiple MOS units 1Q and multiple MOS units 2Q are reselected from multiple MOS units 0Q so that the coverage rate of MOS unit group 1QA and MOS unit group 2QA are the same.

[0111] In step S7, MOS unit 3Q is re-selected from the remaining MOS unit 0Q. In step S7, as in step S4, all MOS units 0Q, excluding MOS units 1Q and 2Q, are re-selected as MOS unit 3Q.

[0112] Thus, in Embodiment 3, as in Embodiments 1 and 2, even if the pitch between each wiring M8 is changed, multiple MOS units 1Q and multiple MOS units 2Q can be re-selected, so no variation in the characteristics of the paired elements occurs.

[0113] Furthermore, in Embodiment 3, as in Embodiments 1 and 2, the capacitive element for the decoupling capacitance C can be placed near the paired elements, MOS unit group 1QA and MOS unit group 2QA. This reduces the wiring resistance R between the paired elements and the decoupling capacitance C, decreasing the amplitude of the power supply waveform and improving the responsiveness of the decoupling capacitance C. In other words, the performance of the differential circuit can be improved.

[0114] (Embodiment 4) The design method for the semiconductor device 100 in Embodiment 4 will be described below with reference to Figure 30. In the following description, the differences from Embodiments 1 to 3 will be mainly explained, and points that overlap with Embodiments 1 to 3 will not be explained.

[0115] In Embodiment 4, a portion of the remaining MOS unit 0Q in step S6 is also used as a capability adjustment element to adjust the capability of the differential circuit. For example, even with the same analog IP10, fine-tuning of the differential circuit capability may be required depending on the individual requirements of each customer. This technology provides a flexible and rapid response in such cases.

[0116] In other words, as illustrated in Embodiment 3, as shown in Figure 30, after step S6 in Figure 7, at least one MOS unit 1Q is added to the MOS unit group 1QA from the plurality of MOS units 0Q, and the same number of MOS units 2Q as the added MOS units 1Q are added to the MOS unit group 2QA from the plurality of MOS units 0Q. In this way, by adding some of the remaining MOS units 0Q to the differential circuit as MOS units 1Q and MOS units 2Q, the capability of the differential circuit can be fine-tuned. In step S7, all of the plurality of MOS units 0Q remaining after fine-tuning are re-selected as MOS units 3Q.

[0117] (Embodiment 5) The semiconductor device 100 in Embodiment 5 will be described below with reference to Figures 31 and 32. In the following description, the differences from Embodiments 1 to 4 will be mainly explained, and points that overlap with Embodiments 1 to 4 will not be explained.

[0118] In Embodiments 1 to 4, in steps S4 and S7, all MOS units 0Q, excluding MOS unit 1Q (MOS unit group 1QA) and MOS unit 2Q (MOS unit group 2QA), were selected as MOS unit 3Q. In other words, the number and arrangement of multiple MOS units 3Q arranged around MOS unit 1Q were sometimes unequal to the number and arrangement of multiple MOS units 3Q arranged around MOS unit 2Q. Hereafter, such an arrangement of multiple MOS units 3Q will be referred to as "unequal arrangement".

[0119] As shown in Figure 31, in Embodiment 5, in steps S4 and S7, multiple MOS units 3Q are selected from the remaining multiple MOS units 0Q. At this time, the number and arrangement of the multiple MOS units 3Q arranged around MOS unit 1Q (MOS unit group 1QA) are equal to the number and arrangement of the multiple MOS units 3Q arranged around MOS unit 2Q (MOS unit group 2QA). Hereinafter, equal means that the total capacitance value around MOS unit 1Q (MOS unit group 1QA) is equal to the total capacitance value around MOS unit 2Q (MOS unit group 2QA). Hereafter, such an arrangement of multiple MOS units 3Q will be referred to as "equal arrangement".

[0120] Therefore, after step S4 and after step S7, all of the remaining MOS units 0Q may become MOS unit 3Q, but one or more MOS units 0Q may remain. In Embodiment 5, if one or more MOS units 0Q remain, all of them become unused MOS units 4Q. Unused MOS units 4Q are not used in capacitive elements, differential circuits, or other circuits.

[0121] Figure 32 shows an example where the MOS unit 4Q is not used. As shown in Figure 32, in the n-type MOSFET constituting the MOS unit 4Q, the gate electrode GEn, well region WRP, and impurity region SDn are electrically connected to the ground wire Vss. In the p-type MOSFET constituting the MOS unit 4Q, the gate electrode GEp, well region WRP, and impurity region SDp are electrically connected to the power supply wire Vdd.

[0122] In circuits that perform high-speed operation, such as differential output circuits, there are standards regarding jitter, and it is desirable to minimize jitter. Jitter is a phenomenon in which the arrival time of a signal waveform deviates from its original time. Factors that increase jitter include noise, power supply fluctuations, temperature changes, and manufacturing variations.

[0123] The responsiveness of the capacitance is determined by the CR time constant. The inventors of this application have found that jitter can be reduced by evenly distributing multiple MOS units 3Q relative to MOS unit 1Q (MOS unit group 1QA) and MOS unit 2Q (MOS unit group 2QA).

[0124] Figures 33 and 34 show equivalent circuit diagrams when a decoupling capacitance C consisting of multiple MOS units 3Q is placed for a pair of differential output elements (P-out, N-out) as shown in Figure 22. Figure 33 shows the case where the multiple MOS units 3Q are evenly distributed. Figure 34 shows the case where the multiple MOS units 3Q are unevenly distributed. In Figures 33 and 34, it is assumed that each parasitic capacitance Cp, each resistance component Rp, and each decoupling capacitance component Cd are equal, and the capacitance value between P-out and N-out is divided in half.

[0125] In Figure 33, the total capacity Cpout for P-out is (4 × Cd + 4 × Cp), and the total capacity Cnout for N-out is (4 × Cd + 4 × Cp). Therefore, the total capacity Cpout is equal to the total capacity Cnout.

[0126] In Figure 34, the total capacity Cpout for P-out is (4.5 × Cd + 5 × Cp), and the total capacity Cnout for N-out is (3.5 × Cd + 4 × Cp). Therefore, the total capacity Cpout is unequal to the total capacity Cnout.

[0127] For example, if the jitter in Figure 33 is 0.1 ps, then the jitter in Figure 34 is 0.5 ps. In this way, by evenly arranging multiple MOS units 3Q around a pair of elements, the jitter can be reduced, and the performance of the differential circuit can be improved.

[0128] Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention. [Explanation of Symbols]

[0129] 100 Semiconductor Devices 10 Analog IP 20 Control circuits 21 registers 22 ESD protection circuit 30 Protrusion 0Q, 1Q, 2Q, 3Q, 4Q MOS Units 1QA, 2QA MOS unit group AR active area C Decoupling Capacity C1, C2 Capacitive elements GI gate insulating film GE Terminal GEn n-type MOSFET gate electrode GEp p-type MOSFET gate electrode M1 to M8 wiring PAD (Pad Electrode) PADa Reference Pad Electrode PG Plug R wiring resistance R1, R2 Resistance Components SD source area or drain area (impurity area) SDn n-type source region or n-type drain region (impurity region) SDp p-type source region or p-type drain region (impurity region) STI element isolation section SUB Semiconductor Substrate V1 to V7 Via Vdd Power Wiring Vss ground wiring Wiring layers WL1 to WL8 WR well region (impurity region) WRn n-type well region (impurity region) WRp p-type well region (impurity region)

Claims

1. A semiconductor substrate having a first surface, Each of the MOS units is composed of at least one MOSFET, each having the same structure, and in a plan view when the first surface of the semiconductor substrate is viewed from above, the MOS units are arranged adjacent to each other on the first surface of the semiconductor substrate. Equipped with, The plurality of MOS units include a first MOS unit and a second MOS unit that constitute part of a differential circuit as a pair of elements, and a third MOS unit that functions as a capacitive element, in a semiconductor device.

2. In the semiconductor device described in claim 1, The differential circuit further comprises power supply wiring and grounding wiring, The third MOS unit is a semiconductor device used as a decoupling capacitor electrically connected between the power supply wiring and the ground wiring.

3. In the semiconductor device described in claim 2, The MOSFET is A well region of the first conductivity type formed in the semiconductor substrate, A source region of a second conductivity type opposite to the first conductivity type is formed in the well region, The drain region of the second conductivity type formed in the well region, A gate electrode formed on the well region via a gate insulating film, It has, If the first conductivity type is n type, then the second conductivity type is p type. If the first conductivity type is p-type, then the second conductivity type is n-type. A semiconductor device comprising the MOSFET constituting the third MOS unit, wherein when the gate electrode is electrically connected to the power supply wiring, the well region, the source region and the drain region are electrically connected to the ground wiring, and when the gate electrode is electrically connected to the ground wiring, the well region, the source region and the drain region are electrically connected to the power supply wiring.

4. In the semiconductor device described in claim 1, A semiconductor device in which all of the aforementioned plurality of MOS units, excluding the first MOS unit and the second MOS unit, are third MOS units.

5. In the semiconductor device described in claim 1, The plurality of MOS units includes a plurality of the third MOS units, A semiconductor device in which the number and arrangement configuration of the plurality of third MOS units arranged around the first MOS unit are equal to the number and arrangement configuration of the plurality of third MOS units arranged around the second MOS unit.

6. In the semiconductor device described in claim 5, A semiconductor device wherein the plurality of MOS units further include a fourth MOS unit not used in the capacitive element, the differential circuit, and other circuits.

7. In the semiconductor device described in claim 1, A multilayer wiring layer formed above the plurality of MOS units, The first wiring formed in the uppermost wiring layer of the multilayer wiring layer, Furthermore, A semiconductor device in which, in the plan view, the coverage rate of the first MOS unit covered by the first wiring is the same as the coverage rate of the second MOS unit covered by the first wiring.

8. In the semiconductor device according to claim 7, A semiconductor device in which each of the plurality of MOS units is composed of one n-type MOSFET or one p-type MOSFET.

9. In the semiconductor device according to claim 7, Each of the plurality of MOS units is composed of one or more n-type MOSFETs and one or more p-type MOSFETs. The number of the one or more n-type MOSFETs is the same as the number of the one or more p-type MOSFETs. A semiconductor device in which the first MOS unit and the second MOS unit are inverter-connected, respectively, one or more n-type MOSFETs and one or more p-type MOSFETs.

10. In the semiconductor device according to claim 7, The first MOS units and second MOS units included in the plurality of MOS units are each a plurality, The number of the plurality of first MOS units is equal to the number of the plurality of second MOS units. A semiconductor device in which, when the plurality of first MOS units are designated as a first MOS unit group and the plurality of second MOS units are designated as a second MOS unit group, the coverage rate of the first MOS unit group covered by the first wiring in a plan view is the same as the coverage rate of the second MOS unit group covered by the first wiring in a plan view.

11. (a) A step of preparing a plurality of MOS units, each consisting of at least one MOSFET, each having the same structure, and arranged adjacent to each other on the first surface of the semiconductor substrate in a plan view when the first surface of the semiconductor substrate is viewed from above. (b) A step of selecting a first MOS unit and a second MOS unit from the plurality of MOS units to constitute a part of a differential circuit as a pair element, and (c) A step of selecting a third MOS unit that functions as a capacitive element from the plurality of MOS units remaining after step (b), A method for designing a semiconductor device, comprising the features described above.

12. In the semiconductor device design method described in claim 11, (d) A step of preparing power supply wiring and grounding wiring used in the differential circuit, Furthermore, A method for designing a semiconductor device, wherein the third MOS unit is used as a decoupling capacitor electrically connected between the power supply wiring and the ground wiring.

13. In the semiconductor device design method described in claim 12, The MOSFET is A well region of the first conductivity type formed in the semiconductor substrate, A source region of a second conductivity type opposite to the first conductivity type is formed in the well region, The drain region of the second conductivity type formed in the well region, A gate electrode formed on the well region via a gate insulating film, It has, If the first conductivity type is n type, then the second conductivity type is p type. If the first conductivity type is p-type, then the second conductivity type is n-type. A method for designing a semiconductor device, wherein in the MOSFET constituting the third MOS unit, when the gate electrode is electrically connected to the ground wiring, the well region, the source region and the drain region are electrically connected to the power supply wiring, and when the gate electrode is electrically connected to the power supply wiring, the well region, the source region and the drain region are electrically connected to the ground wiring.

14. In the semiconductor device design method described in claim 11, A semiconductor device design method, wherein in step (c), all of the plurality of MOS units except the first MOS unit and the second MOS unit are selected as the third MOS unit.

15. In the semiconductor device design method described in claim 11, In step (c), a plurality of the third MOS units are selected from the plurality of MOS units remaining after step (b), A method for designing a semiconductor device, wherein the number and arrangement of the plurality of third MOS units arranged around the first MOS unit are equal to the number and arrangement of the plurality of third MOS units arranged around the second MOS unit.

16. In the semiconductor device design method described in claim 15, A method for designing a semiconductor device, wherein if one or more MOS units remain after step (c), all of the one or more MOS units are made into a fourth MOS unit not used in the capacitive element, the differential circuit, and other circuits.

17. In the semiconductor device design method described in claim 11, (e) A step of preparing a first wiring that is formed in the uppermost wiring layer among the multilayer wiring layers formed above the plurality of MOS units, before step (b), Furthermore, A semiconductor device design method, wherein in step (b), the first MOS unit and the second MOS unit are selected from the plurality of MOS units such that the coverage rate of the first MOS unit covered by the first wiring in the plan view is the same as the coverage rate of the second MOS unit covered by the first wiring in the plan view.

18. In the semiconductor device design method described in claim 17, (f) If the pitch between each wiring formed in the uppermost wiring layer is changed after steps (b) and (c), the step of re-selecting the first MOS unit and the second MOS unit from the plurality of MOS units so that the coverage rate of the first MOS unit and the coverage rate of the second MOS unit are the same, and (g) A step of re-selecting the third MOS unit from the plurality of MOS units remaining after step (f), A design method for semiconductor devices that further incorporates the following features.

19. In the semiconductor device design method described in claim 17, A method for designing a semiconductor device, wherein each of the plurality of MOS units is composed of one n-type MOSFET or one p-type MOSFET.

20. In the semiconductor device design method described in claim 17, Each of the plurality of MOS units is composed of one or more n-type MOSFETs and one or more p-type MOSFETs. The number of the one or more n-type MOSFETs is the same as the number of the one or more p-type MOSFETs. A method for designing a semiconductor device, wherein the first MOS unit and the second MOS unit are inverter-connected, each containing one or more n-type MOSFETs and one or more p-type MOSFETs.

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