Wiring board and method for manufacturing a wiring board

Abstract

Providing a wiring board equipped with fine wiring. [Solution] The wiring board 1 of the embodiment includes an insulating layer 20 and a conductor layer 30 laminated on the upper surface of the insulating layer 20 and including a wiring pattern 31. The upper surface of the insulating layer 20 directly beneath the wiring pattern 31 has a curved convex shape, the lower surface of the wiring pattern 31 has a shape that curves along the convex shape, and the upper surface of the insulating layer 20 exposed from the wiring pattern 31 has a curved concave shape.

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring board using an exposure apparatus that modulates a light beam emitted from a light source according to an exposed pattern and directly draws and exposes without using a photomask. The exposure apparatus includes two light sources that emit light of different wavelengths.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, it is considered that the adhesion between the interlayer material and the wiring is insufficient, and peeling of the wiring from the interlayer material may occur.

Means for Solving the Problems

[0005] The wiring board of the present invention includes an insulating layer and a conductor layer laminated on the upper surface of the insulating layer and including a wiring pattern. The upper surface of the insulating layer directly under the wiring pattern has a curved convex shape, the lower surface of the wiring pattern has a shape that curves along the convex shape, and the upper surface of the insulating layer exposed from the wiring pattern has a curved concave shape.

[0006] The present invention provides a method for manufacturing a wiring board, comprising forming a photosensitive resin layer, forming an insulating layer by exposing the photosensitive resin layer to light, and forming a conductor layer on the upper surface of the insulating layer. Forming the insulating layer involves forming a region having a curved convex shape and a region having a curved concave shape on the upper surface, and forming the conductor layer involves forming a wiring pattern on the upper surface of the insulating layer in the convex region such that the concave region is exposed.

[0007] According to the wiring board of the embodiment of the present invention, a wiring board having a fine wiring pattern with good adhesion to the interlayer material is provided. Furthermore, according to the manufacturing method of the wiring board of the embodiment of the present invention, a wiring board having a fine wiring pattern with good adhesion to the interlayer material can be easily manufactured. [Brief explanation of the drawing]

[0008] [Figure 1] A partial cross-sectional view showing an example of a wiring board, which is one embodiment of the present invention. [Figure 2] A magnified view of a portion of the wiring board shown in Figure 1. [Figure 3A] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3B] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3C] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3D] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3E] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3F] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3G] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3H] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3I] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Modes for carrying out the invention]

[0009] The wiring board and method for manufacturing the wiring board of the present invention will be described below with reference to the drawings. Note that the drawings referenced below are not intended to show the precise proportions of each component, but are drawn in a way that facilitates understanding of the features of the present invention. Figure 1 shows a partial cross-sectional view of a wiring board 1, which is an example of a wiring board of this embodiment, and Figure 2 shows a partially enlarged view of the wiring board 1 of Figure 1. The wiring board 1, an example of a wiring board of one embodiment, is a wiring board that includes a laminated structure composed of a plurality of alternately stacked conductor layers and insulating layers. Conductor layers facing each other with a single insulating layer in between are electrically connected by via conductors that penetrate the insulating layer in the thickness direction. The number of conductor layers and insulating layers included in the manufactured wiring board is not limited to the examples in Figures 1 and 2, but can be appropriately selected. The laminated structure of the wiring board is also not limited.

[0010] The wiring board 1 shown in Figure 1 comprises an insulating layer 20 as an interlayer material formed on a conductor layer 10, and a conductor layer 30 formed on the insulating layer 20 and the conductor layer 10, facing the conductor layer 10 with the insulating layer 20 in between. A wiring pattern 31 is formed on the conductor layer 30. 34 is a via conductor connecting the conductor layer 10 and the conductor layer 30. The conductor layer 30, including the wiring pattern 31, and the via conductor 34 are composed of a metal film layer 32 and a plating film layer 33 on the metal film layer 32.

[0011] In the description of the wiring board 1 of this embodiment, in relation to the conductor layer 10 and the insulating layer 20, the conductor layer 10 side, i.e., the lower side on the page, is referred to as the "lower side" or simply "bottom," and the insulating layer 20 side is referred to as the "upper side" or simply "top." Also, in the insulating layer 20 and the conductor layer 10, the surface facing upwards is also referred to as the "upper surface," and the surface facing downwards is also referred to as the "lower surface." The lamination direction of the insulating layer 20 and the conductor layer 10, i.e., the thickness direction of the wiring board 1, is also referred to as the "Z direction." "Plan view" means viewing the object from above with a line of sight along the Z direction.

[0012] The wiring board 1 is merely an example of a wiring board in this embodiment. Although four wiring patterns 31 are shown in Figure 1, the number of wiring patterns 31 is not limited. Similarly, the number of via conductors 34 is not limited. The via conductors 34 of the wiring board 1 in this embodiment can be formed in any desired number at any desired location, depending on the wiring patterns contained in the upper and lower conductor layers to which the via conductors 34 are connected.

[0013] In this embodiment, the materials of the conductor layer 10 and the conductor layer 30 may be any conductive metal, such as copper or nickel. Preferably, the conductor layer 10 and the conductor layer 30 are made of copper. The conductor layer 10 and the conductor layer 30 may have a multilayer structure of two or more layers. As described above, in the example of Figure 1, the conductor layer 30 including the wiring pattern 31 has a two-layer structure including a metal film layer 32 (first metal film) and a plating film layer 33 (second metal film). The plating film layer 33 constitutes the portion of the wiring pattern 31 above the metal film layer 32. Preferably, the metal film layer 32 is a sputtered film. The plating film layer 33 is, for example, an electroplated film layer formed by electroplating using the metal film layer 32 as a seed layer. The plating film layer 33 can be formed, for example, by pattern plating using a plating resist having an appropriate opening pattern. The via conductor 34 is formed integrally with the conductor layer 30. Therefore, the via conductor 34 is formed from the same metal film layer 32 and plating film layer 33 as the conductor layer 30.

[0014] In this embodiment, the conductor layer 30 includes a wiring pattern 31. The wiring pattern 31 can be a conductor pattern designed and used to apply a voltage, pass an electric current, supply electric power, or transmit an electrical signal from an arbitrary position within the conductor layer of the wiring substrate 1 in a plan view to another arbitrary position different from the arbitrary position. In FIGS. 1 and 2, a plurality of wiring patterns 31 are arranged in parallel in a direction (X direction) substantially orthogonal to the direction (Y direction) in which each wiring pattern 31 extends. The wiring patterns 31 are each formed in an arbitrary pattern and can be different from each other.

[0015] The width (width in the X direction) of each wiring pattern 31 of the wiring substrate 1 is preferably 1.0 μm or more and 20.0 μm or less. Also, the interval (interval in the X direction) between each pair of wiring patterns 31 is preferably 1.0 μm or more and 20.0 μm or less. Further, the thickness of the wiring pattern 31 may be the same as the thickness of the conductor layer 30, and for example, may be 3.5 μm or more and 20.0 μm or less.

[0016] The insulating layer 20 is formed, for example, by exposing a photosensitive resin layer formed of an arbitrary photosensitive resin to light. Examples of the photosensitive resin used for forming the insulating layer 20 include, but are not limited to, photosensitive acrylic resins, photosensitive polyimide resins, photosensitive polybenzoxazole resins, photosensitive phenolic resins, photosensitive epoxy resins, photosensitive cycloolefin resins, or photosensitive benzocyclobutene resins. Regarding the examples shown in each drawing, the insulating layer 20 is described as not containing an inorganic filler such as silica, but an insulating layer 20 containing an inorganic filler to change its properties may also be used. Examples of the inorganic filler include fillers composed of fine particles such as silica (SiO2), alumina, or mullite. The insulating layer 20 can be formed of any material that provides photosensitivity and insulation with respect to the conductor layer 10 and the conductor layer 30 and can support or cover the conductor layer 10 and the conductor layer 30.

[0017] As shown in FIG. 1, the insulating layer 20 includes a first region 21 disposed under the wiring pattern 31 and a second region 22 exposed from the wiring pattern 31 in plan view. The upper surface 21a of the first region 21 has a convex shape curved toward the wiring pattern 31 side. The upper surface 22a of the second region 22 has a concave shape curved toward the conductor layer 10 side (opposite to the conductor layer 30 side). The upper surface 21a of the first region 21 is about 0.5 μm higher than the upper surface 22a of the second region 22.

[0018] The first region 21 and the second region 22 may also be regions having different Young's moduli. The Young's modulus of the second region 22 is 5% or more and 95% or less of the Young's modulus of the first region 21. Thus, the first region 21 of the insulating layer 20 where the wiring pattern 31 is disposed is in a state of having a higher Young's modulus and being harder than the second region 22.

[0019] FIG. 2 shows a partially enlarged view of the region II shown in the wiring board 1 shown in FIG. 1. As shown in FIG. 2, the upper surface 31a of the wiring pattern 31 is substantially flat. The lower surface 31b of the wiring pattern 31 has a concave shape curved upward along a convex shape formed by a part of the curved convex shape of the upper surface 21a of the first region 21 of the insulating layer 20 and the curved concave shape of the upper surface 22a of the second region 22. The curved convex shape of the upper surface 21a of the first region 21 of the insulating layer 20 and the curved concave shape of the lower surface 31b of the wiring pattern 31 are fitted together.

[0020] In the example shown in Figure 1, a metal film layer 32 (first metal film) constituting the wiring pattern 31 is formed on the upper surface 21a of the first region 21 and the upper surface 22a of the second region 22. The metal film layer 32 includes the lower surface 31b of the wiring pattern 31. The metal film layer 32 has a shape that extends down to the second region 22 of the exposed insulating layer 20. That is, the width of the metal film layer 32 on the lower surface 31b of the wiring pattern 31 is wider than the width of the plating film layer 33 (second metal film) along the convex shape of the upper surface 21a of the first region 21 of the insulating layer 20. As a result, the width (length in the X direction) of the wiring pattern 31 widens near the interface with the insulating layer 20, increasing the contact area. In addition, the metal film layer 32 has a similar shape in the land portion 35 (see Figure 1) that connects to the via conductor 34, and since the width of the metal film layer 32 is widened, the contact area between the land portion 35 and the insulating layer 20 is increased.

[0021] As described above, when the wiring pattern 31 (metal film layer 32) of the conductor layer 30 is formed on the upper surface 21a of the convexly curved first region 21, the contact area between the wiring pattern 31 and the insulating layer 20 is increased, improving adhesion. Furthermore, when the metal film layer 32 is formed on a part of the upper surface 22a of the second region 22, the contact area between the wiring pattern 31 and the insulating layer 20 is further increased, improving adhesion. Moreover, if the metal film layer 32 of the wiring pattern 31 is a sputtered film, the adhesion between the wiring pattern 31 and the insulating layer 20 is further enhanced. Thus, according to the wiring substrate 1 of this embodiment, the adhesion between the wiring pattern 31 and the insulating layer 20 is improved, making peeling less likely, and therefore, it is possible to have a fine wiring pattern that is less prone to peeling.

[0022] Next, using the wiring board 1 in Figure 1 as an example, the manufacturing method of the wiring board of the embodiment will be specifically explained with reference to Figures 3A to 3I.

[0023] As shown in Figure 3A, an insulating resin layer 200, which will become the insulating layer 20, is formed on the upper surface 10F of the conductor layer 10. A photosensitive resin is preferred as the material for the insulating resin layer 20. That is, the insulating resin layer 200 can be a photosensitive resin layer. The insulating layer 20 is formed by exposing the photosensitive resin layer to light. Examples of photosensitive resins that can be used include photosensitive acrylic resins, photosensitive polyimide resins, photosensitive polybenzoxazole resins, photosensitive phenolic resins, photosensitive epoxy resins, photosensitive cycloolefin resins, or photosensitive benzocyclobutene resins. For example, a liquid photosensitive resin is applied to the upper surface 10F of the conductor layer 10. Alternatively, a photosensitive resin molded into a film is laminated on the upper surface 10F of the conductor layer 10.

[0024] In the manufacturing method of this embodiment, the Young's modulus of the insulating resin layer 200 is adjusted by exposing the insulating resin layer 200 to light. For example, by changing the number of exposures at a specific location, the insulating resin layer 200 can be photosensitive so that multiple regions with different degrees of hardening are formed. Therefore, it is preferable that the photosensitive resin used as the material for the insulating resin layer 200 has negative photosensitivity. Since a higher degree of hardening can be obtained in regions of the insulating resin layer 200 that have been exposed more times, the hardness of the insulating resin layer 200 can be controlled by the number of exposures.

[0025] For example, the exposure process of this embodiment may include a first exposure step and a second exposure step. Specifically, in the first exposure step, the entire surface of the insulating resin layer 200 is exposed to light, excluding the area corresponding to the portion penetrated by the via conductor 34 (see Figure 1). Then, in the second exposure step, only the portion 201 of the insulating resin layer 200 exposed in the first exposure step that corresponds to the wiring pattern 31 and the land portion 35 of the via conductor 34 (see Figure 1) is additionally exposed. Through the two exposure processes, the insulating resin layer 200 is divided into the softest, unexposed region, the hardened region obtained as a result of the first exposure process, and the hardest region obtained as a result of the second exposure process.

[0026] Specifically, in the first exposure step, the entire surface of the insulating resin layer 200 is exposed to light, excluding the area corresponding to the portion penetrated by the via conductor 34 (see Figure 1). This first exposure step forms an uncured area A and a first cured area B in the insulating resin layer 200, as shown in Figure 3B. The first exposure step can be performed by any exposure method, but a direct imaging exposure method is sometimes preferred. In direct imaging exposure, laser light is directly irradiated onto the insulating resin layer 200 along the exposure pattern without using an exposure mask, and a first cured area B (insulating resin layer 201) is formed in the insulating resin layer 200. Since the entire area of ​​the wiring board can be scanned by the irradiated light in a single exposure, the increase in man-hours in the exposure process is suppressed, and therefore, the yield of wiring board manufacturing may be improved.

[0027] For direct imaging exposure, a semiconductor laser with a wavelength of 350 nm to 410 nm or a high-pressure mercury lamp can be used as the light source for illumination. The exposure amount can be determined by the illuminance of the exposure light source and the scanning speed of the illumination light.

[0028] Next, within the first cured region B, the region covered by the wiring pattern 31 and the land portion 35 of the via conductor 34 (see Figure 1) is exposed. As shown in Figure 3C, a second region 22 is formed from the insulating resin layer 201 cured in the first exposure step, and a first region 21 is formed when the insulating resin layer 201 is further cured in the second exposure step. That is, in this embodiment, the insulating layer 20 is formed such that the region (first region 21) on which the wiring pattern 31 and the land portion 35 of the via conductor 34 (see Figure 1) are formed is a harder resin layer than the other regions (second region 22).

[0029] The second exposure step can be performed using any exposure method. For example, it can be performed using a direct imaging exposure method. Compared to the case in which an exposure mask is used, direct imaging exposure not only suppresses the increase in the number of steps in the exposure step, but also, due to its high resolution, allows for exposure with a fine pattern that matches the fine pitch of the wiring pattern 31 when it is formed with a fine pitch.

[0030] The exposure conditions in the first exposure step and the second exposure step may be the same or different. For example, the illuminance of the exposure light source may differ between the first exposure step and the second exposure step. Also, the exposure times may differ. Each exposure condition can be appropriately selected and adjusted so that the degree of curing in each region of the insulating layer 20 is as desired.

[0031] Next, the insulating resin layer 200 in the uncured region A is removed by development. A through hole 34a is formed in which a via conductor 34 (see Figure 1) is formed inside. Next, the insulating resin layer 201 is baked (post-bake). This bake process forms an insulating layer 20 with irregularities on its upper surface, as shown in Figure 3D. Specifically, the upper surface 21a of the first region 21, which was exposed by the first and second exposure processes, forms a convex shape that curves upward. The upper surface 22a of the second region 22, which was exposed only by the first exposure process, forms a concave shape that curves downward. It is thought that the concave or convex shape on the upper surface of each region is caused by the difference in the amount of thermal shrinkage during baking, which is based on the difference in photosensitivity (or degree of curing) between the two regions.

[0032] In the wiring board 1 of the embodiment, the first region 21 and the second region 22 of the insulating layer 20 may be regions with different Young's moduli. The Young's moduli of the second region 22 of the insulating layer 20 cured by the first exposure treatment is, for example, 0.5 GPa or more and 1.9 GPa or less. The Young's moduli of the first region 21 of the insulating layer 20 cured by the second exposure treatment is, for example, 2.0 GPa or more and 4.0 GPa or less. The Young's moduli of the second region is 5% or more and 95% or less of the Young's moduli of the first region.

[0033] Next, as shown in Figure 3E, a metal film layer 32 (seed layer) is formed on the upper surface 20a of the insulating layer 20, the side wall of the through hole 34a, and on the conductor layer 10 exposed from the insulating layer 20 (on the inner wall of the through hole 34a). The metal film layer 32 is preferably formed by sputtering. Examples of sputtering targets include copper, copper alloys, nickel, nickel alloys, titanium, or titanium alloys. Preferably, the sputtering is copper sputtering, and the metal film layer 32 is a copper sputtered film layer.

[0034] By forming the metal film layer 32 by sputtering, a metal film layer 32 with good coverage and a thin, uniform thickness can be obtained. Furthermore, as shown in this embodiment, when the insulating layer 20 that serves as the base for sputtering has an uneven shape, the contact area increases compared to when it has a flat shape, and the adhesion between the metal film layer 32 and the insulating layer 20 is improved.

[0035] Next, as shown in Figure 3F, a resist layer 40 is laminated on the insulating layer 20 via a metal film layer 32. As the resist layer 40, any photosensitive resin, such as a dry film resist of a photosensitive epoxy resin, polyhydroxy ether resin, phenol resin, or polyimide resin, can be used. The resist layer 40 is exposed and developed using a mask having an aperture pattern corresponding to the wiring pattern 31 (see Figure 1) of the conductor layer 30. As shown in Figure 3F, a resist layer 40 is formed having apertures 40a at positions corresponding to the wiring pattern 31 and via conductors 34 of the conductor layer 30.

[0036] Next, as shown in Figure 3G, a plating film layer 33 is formed within the opening 40a of the resist layer 40. At the same time, the through hole 34a is filled with the plating film layer 33. The plating film layer 33 is preferably formed by electroplating with a metal film layer 32 as the power supply layer. That is, in this embodiment, the metal film layer 32 may be a seed layer, and the plating film layer 33 may be an electroplated film layer.

[0037] Next, the resist layer 40 is removed using, for example, an alkaline stripping solution. Removal of the resist layer 40 exposes the metal film layer 32, as shown in Figure 3H.

[0038] Next, the exposed portion of the metal film layer 32 is removed, for example, by quick etching. By removing the metal film layer 32 on the second region 22, a wiring pattern 31 is formed on the first region 21 of the insulating layer 20, as shown in Figure 3I. At the same time, a via conductor 34 is formed that penetrates the insulating layer 20 and connects the conductor layer 10 and the conductor layer 30. In the example in Figure 3I, both the conductor layer 30 and the via conductor 34 are formed as a two-layer structure consisting of a metal film layer 32 and a plating film layer 33. Thus, in the manufacturing method of the wiring substrate of this embodiment, forming the conductor layer 30 includes forming the wiring pattern 31 on the upper surface 21a of the insulating layer 20 of the first region 21, which has a convex shape, such that the second region 22 of the insulating layer 20, which has a concave shape, is exposed.

[0039] Quick etching to remove the metal film layer 32 on the second region 22 is performed, for example, by wet etching using a suitable etching solution. By appropriately setting the wet etching conditions, such as temperature, etching time, and stirring conditions of the solution, the portion of the metal film layer 32 near the outer periphery of the plating film layer 33 can be left intact, as shown in Figure 3I. As shown in Figure 3I, the retention of the metal film layer 32 near the outer periphery of the plating film layer 33 results in a width of the metal film layer 32 remaining beneath the plating film layer 33 that is greater than the width of the plating film layer 33.

[0040] Thus, in the manufacturing method of the wiring board of this embodiment, forming the conductor layer 30 may include forming a seed layer (metal film layer 32) on the insulating layer 20 and forming an electroplated film layer (plating film layer 33) constituting the wiring pattern 31 on the seed layer. Furthermore, forming the wiring pattern 31 may include removing the exposed portion of the seed layer such that the lower surface 31b of the wiring pattern 31 extends beyond the electroplated film layer along the curved convex shape of the upper surface 21a of the insulating layer 20.

[0041] As described above, the upper surface of the first region 21 of the insulating layer 20 has a curved convex shape, so the metal film layer 32 adheres to the upper surface 21a of the first region 21 of the insulating layer 20 with a high degree of adhesion. Therefore, the wiring pattern 31 is less likely to peel off from the insulating layer 20. Furthermore, by forming the wiring pattern 31 so that the width of the lower surface 31b is increased, the wiring pattern 31 adheres to the insulating layer 20 with an even higher degree of adhesion, and therefore, the wiring pattern 31 is even less likely to peel off from the insulating layer 20.

[0042] The method for manufacturing the wiring board in the embodiment is not limited to the method described with reference to the drawings. For example, the first exposure step and the second exposure step may be performed in reverse order, with the first exposure step being performed after the second exposure step. That is, only the region of the insulating resin layer 200 corresponding to the region of the insulating layer 20 covered by the wiring pattern 31 and the land portion 35 of the via conductor 34 may be exposed first, and then the entire surface of the insulating resin layer 200, excluding the region where the via conductor 34 is formed, may be additionally exposed. In this case as well, preferably, the exposure step may be performed by direct imaging exposure. Alternatively, the first exposure step may be a step in which the entire insulating resin layer 200 is exposed using a mask that covers only the region where the via conductor 34 is formed, and then, as the second exposure step, only the region of the insulating resin layer 200 corresponding to the region of the insulating layer 20 covered by the wiring pattern 31 and the land portion 35 of the via conductor 34 may be additionally exposed by direct imaging exposure.

[0043] The methods for forming each conductor layer and insulating layer are also not limited to those described with reference to Figures 3A to 3I. The manufacturing method of the wiring board in the embodiment may include additional steps other than those described above, and some of the aforementioned steps may be omitted. [Explanation of symbols]

[0044] 1 Wiring board 10 Conductor Layers 20 Insulating layer 200, 201 Insulating resin layer 21 First area 21a Upper surface of the first region 22 Second area 22a Upper surface of the second region 30 Conductor Layers 31 Wiring Patterns 32. Metal film layer (seed layer) 33 Plating film layer 34 via conductors 34a through hole 35 Land Section 40 resistance layers

Claims

1. Insulating layer and, A conductive layer including a wiring pattern is laminated on the upper surface of the insulating layer. A wiring board including, The upper surface of the insulating layer directly beneath the wiring pattern has a curved convex shape. The lower surface of the wiring pattern has a curved shape that follows the convex shape, The upper surface of the insulating layer exposed from the wiring pattern has a curved concave shape.

2. A wiring board according to claim 1, The wiring pattern comprises a first metal film including the lower surface and a second metal film that constitutes the portion above the first metal film. The width of the first metal film on the lower surface is wider than the width of the second metal film along the convex shape.

3. A wiring board according to claim 1, The insulating layer contains a negative-type photosensitive resin.

4. A wiring board according to claim 1, The upper surface of the aforementioned wiring pattern is substantially flat.

5. A wiring board according to claim 1, The Young's modulus of the insulating layer exposed from the wiring pattern is 5% or more and 95% or less of the Young's modulus of the insulating layer directly beneath the wiring pattern.

6. A wiring board according to claim 2, The first metal film is a sputtered film.

7. Forming a photosensitive resin layer, An insulating layer is formed by exposing the aforementioned photosensitive resin layer to light, A conductive layer is formed on the upper surface of the insulating layer. A method for manufacturing a wiring board, including, Forming the insulating layer includes forming a region having a curved convex shape and a region having a curved concave shape on the upper surface. Forming the conductor layer includes forming a wiring pattern on the upper surface of the insulating layer in the convex region such that the concave region is exposed.

8. A method for manufacturing a wiring board according to claim 7, Forming the conductor layer includes forming a seed layer on the insulating layer and forming an electroplated film layer constituting the wiring pattern on the seed layer. Forming the wiring pattern involves removing the exposed portion of the seed layer such that the lower surface of the wiring pattern extends beyond the electroplated film layer along the curved convex shape.

9. A method for manufacturing a wiring board according to claim 7, Forming the insulating layer involves exposing the first region having the convex shape and the second region having the concave shape of the photosensitive resin to light such that they have different degrees of curing.

10. A method for manufacturing a wiring board according to claim 9, wherein the photosensitive resin has negative-type photosensitivity.

11. A method for manufacturing a wiring board according to claim 10, Forming the insulating layer includes exposing the first and second regions of the photosensitive resin to light, selectively exposing the first region of the first and second regions to light, and baking the developed photosensitive resin.

12. A method for manufacturing a wiring board according to claim 7, The aforementioned photosensitivity is photosensitivity by direct imaging exposure.

13. A method for manufacturing a wiring board according to claim 7, Forming the insulating layer involves exposing the photosensitive resin to light such that the Young's modulus of the insulating layer in the concave region is 5% or more and 95% or less of the Young's modulus of the insulating layer in the convex region.

14. A method for manufacturing a wiring board according to claim 8, The aforementioned seed layer is formed by sputtering.

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