Semiconductor integrated circuit, microcontroller device, method for communication between a microcontroller and an external device, method for communicating with an external device using an interface circuit

Abstract

This mitigates the limitation imposed by the number of I / O banks on the number of external devices that can be controlled by an I / O bank. [Solution] The semiconductor integrated circuit 19 includes an internal circuit 27 that includes a first interface circuit 29b and a second interface circuit 29c capable of communicating with a first external device 15b operating at a first power supply voltage and a second external device 15c operating at a second power supply voltage, respectively, and a first input / output circuit 23b and a second input / output circuit 23c connected to the first interface circuit 29b and the second interface circuit 29c, respectively. The first input / output circuit 23b and the second input / output circuit 23c are connected to a bank power line 24 connected to a first power supply electrode that receives an external voltage, and the internal circuit 27 does not simultaneously activate the first communication circuit 26b, which includes the first interface circuit 29b and the first input / output circuit 23b, and the second communication circuit 26c, which includes the second interface circuit 29c and the second input / output circuit 23c.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit, a microcontroller device, a method of communicating between a microcontroller and an external device, or a method of communicating with an external device using an interface circuit.

Background Art

[0002] Patent Document 1 discloses a programmable logic integrated circuit. This integrated circuit includes a plurality of I / O ports, and the regions including the I / O ports each include a respective power-on reset circuit, and each of the power-on reset circuits monitors the power-on state at the I / O port.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] A semiconductor integrated circuit includes one or more I / O banks, and these I / O banks communicate with respective external devices. The external devices operate receiving respective power supply voltages. When the power supply voltage of this external device is supplied to the I / O bank, the external device is driven by a voltage different from the power supply voltage of the semiconductor integrated circuit. Therefore, the I / O bank has a device breakdown voltage that can withstand the applied power supply voltage of the external device.

[0005] In a semiconductor integrated circuit, the number of I / O banks is limited. The number of I / O banks limits the number of external devices that can be controlled by the I / O banks. Relaxing this limitation is required.

[0006] A semiconductor integrated circuit according to a first aspect of the present disclosure is an internal circuit capable of communicating with a processing circuit, the internal circuit including an interface circuit configured to communicate with an external device, the interface circuit including a first interface circuit and a second interface circuit, and an input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, the first input / output circuit and the second input / output circuit being connected to the bank power line of the input / output bank circuit, the first interface circuit and the first input / output circuit constituting a first communication circuit, the second interface circuit and the second input / output circuit constituting a second communication circuit, the input / output bank circuit comprising a first power electrode configured to receive an external voltage different from the voltage of the internal power line of the internal circuit and connected to the bank power line of the input / output bank circuit, a first external electrode connected to the first communication circuit, and a second external electrode connected to the second communication circuit, wherein the internal circuit is configured not to activate the first communication circuit and the second communication circuit simultaneously. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic diagram showing the microcontroller device, microcontroller, and semiconductor integrated circuit according to this embodiment. [Figure 2] Figure 2 is a schematic diagram showing the microcontroller and semiconductor integrated circuit according to this embodiment. [Figure 3] Figures 3(a) and 3(b) are diagrams showing exemplary connection circuits between the input / output bank circuit and digital input / output circuit of the semiconductor integrated circuit according to this embodiment and an external device. [Figure 4] Figure 4 is a block diagram specifically showing the configuration of an exemplary computer of the semiconductor integrated circuit according to this embodiment. [Figure 5] Figure 5 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. [Figure 6]Figure 6 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. [Figure 7] Figure 7 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. [Figure 8] Figure 8 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. [Figure 9] Figure 9 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. [Figure 10] Figure 10 is a diagram illustrating the main operations in one exemplary method according to this embodiment. [Figure 11] Figure 11 is a diagram illustrating the main operation in another exemplary method according to this embodiment. [Figure 12] Figure 12 is a diagram illustrating the main operations in an exemplary method according to this embodiment. [Figure 13] Figure 13 is a diagram illustrating the main operations in an exemplary method according to this embodiment. [Figure 14] Figure 14 is a diagram illustrating the main operations in an exemplary method according to this embodiment. [Figure 15] Figure 15 is a diagram illustrating the main operations in an exemplary method according to this embodiment. [Figure 16] Figure 16 is a diagram illustrating the specific system startup process for the input / output bank circuit. [Figure 17] Figure 17 is a diagram illustrating the specific system startup process for the input / output bank circuit. [Figure 18] Figure 18 is a diagram illustrating the process for initiating communication with the first external device using the first interface circuit. [Figure 19] Figure 19 is a diagram illustrating the process for initiating communication with the first external device using the first interface circuit. [Figure 20]FIG. 20 is a drawing showing communication stop processing with a first external device using a first interface circuit. [Figure 21] FIG. 21 is a drawing showing communication stop processing with a first external device using a first interface circuit. [Figure 22] FIG. 22 is a drawing showing communication start processing with a second external device using a second interface circuit. [Figure 23] FIG. 23 is a drawing showing communication start processing with a second external device using a second interface circuit. [Figure 24] FIG. 24 is a drawing showing communication stop processing with a second external device using a second interface circuit. [Figure 25] FIG. 25 is a drawing showing communication stop processing with a second external device using a second interface circuit.

[0008] [Detailed Description] Hereinafter, each embodiment for implementing the present disclosure will be described with reference to the drawings. The same parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] FIG. 1 is a drawing schematically showing a microcontroller device, a microcontroller, and a semiconductor integrated circuit according to the present embodiment. FIG. 2 is a drawing schematically showing a microcontroller and a semiconductor integrated circuit according to the present embodiment.

[0010] The microcontroller device 11 includes a microcontroller 13, an external device 15, and a multi-voltage output power supply circuit 17. An exemplary microcontroller 13 can be provided in the form of, for example, a semiconductor integrated circuit 19. The microcontroller 13 and the semiconductor integrated circuit 19 can include an internal circuit 21, an input / output bank circuit 23, and a plurality of electrodes 25.

[0011] The internal circuit 27 can communicate with a processing circuit 28 such as a central processing unit (e.g., CPU: central processing unit) via, for example, a bus line BUS. The internal circuit 27 includes an interface circuit 29, and the interface circuit 29 is configured to be able to communicate with an external device of the microcontroller 13, such as an external device 15. The exemplary interface circuit 29 includes at least a first interface circuit 29b and a second interface circuit 29c, and the exemplary external device 15 can include a plurality of devices, such as a first external device 15b and a second external device 15c.

[0012] The first external device 15b is configured to operate at a first power supply voltage VOUT1, and the second external device 15c is configured to operate at a second power supply voltage VOUT2. At least one of the first power supply voltage VOUT1 and the second power supply voltage VOUT2 is different from the power supply voltage VOUT0 of the internal circuit 27, and both the first power supply voltage VOUT1 and the second power supply voltage VOUT2 can be different from the power supply voltage VOUT0 of the internal circuit 27. In the exemplary external device 15, the first power supply voltage VOUT1 and the second power supply voltage VOUT2 can be different from each other.

[0013] The input / output bank circuit 23 includes a plurality of input / output circuits, and the exemplary input / output bank circuit 23 can include at least a first input / output circuit 23b and a second input / output circuit 23c. The first input / output circuit 23b and the second input / output circuit 23c are respectively connected to the first interface circuit 29b and the second interface circuit 29c. The input / output circuits 23b, specifically the first input / output circuit 23b and the second input / output circuit 23c, are connected to the bank power supply lines 24 (high-potential power supply line 24b and low-potential power supply line 24c) of the input / output bank circuit 23.

[0014] At least a portion of the circuitry within the interface circuit 29 can be connected to the corresponding circuitry in the input / output bank circuit 23 to form a communication circuit. For example, the first input / output circuit 23b and the first interface circuit 29b constitute a first communication circuit 26b configured to communicate with the first external device 15b. The second input / output circuit 23c and the second interface circuit 29c constitute a second communication circuit 26c configured to communicate with the second external device 15c.

[0015] The first input / output circuit 23b and the second input / output circuit 23c each convert the signal level, specifically the signal levels of the external device 15 and the internal circuit 27, from one of the internal voltage levels of the power supply to the internal circuit 27 and the external voltage level of the bank power line 24 of the input / output bank circuit 23 to the other.

[0016] The exemplary electrode 25 may include a first external electrode 25b, a second external electrode 25c, and a first power supply electrode 25d.

[0017] The first external electrode 25b and the second external electrode 25c are connected to the first communication circuit 26b and the second communication circuit 26c, respectively.

[0018] The first power supply electrode 25d is configured to receive an external voltage and can be connected to the bank power supply line 24 of the input / output bank circuit 23.

[0019] Specifically, the first power supply electrode 25d is configured to receive the output voltage (voltage from output Vdcdc) of a multi-voltage output power supply circuit 17 located outside the semiconductor integrated circuit 19, and the multi-voltage output power supply circuit 17 can be configured to generate a first power supply voltage VOUT1 and a second power supply voltage VOUT2 to be supplied to a first external device 15b and a second external device 15c, respectively. In the exemplary multi-voltage output power supply circuit 17, the second power supply voltage VOUT2 may be different from the first power supply voltage VOUT1.

[0020] Furthermore, the multi-voltage output power supply circuit 17 is configured to selectively generate a first power supply voltage VOUT1 and a second power supply voltage VOUT2. Alternatively, the multi-voltage output power supply circuit 17 is configured to exclusively provide the first power supply voltage VOUT1 and the second power supply voltage VOUT2.

[0021] An exemplary multi-voltage output power supply circuit 17 may include a DC-DC converter circuit 17c and further include an AC-DC converter circuit 17b. The AC-DC converter circuit 17b is configured to convert alternating current power (Vac) to direct current power (Vcc). The DC-DC converter circuit 17c is configured to receive the direct current power (Vcc) from the AC-DC converter circuit 17b. The DC-DC converter circuit 17c is configured to generate a first power supply voltage VOUT1 and a second power supply voltage VOUT2 from the received direct current power (Vcc).

[0022] The DC-DC converter circuit 17c generates the first power supply voltage VOUT1 and the second power supply voltage VOUT2, respectively, in conjunction with the activation of the first communication circuit 26b and the first communication circuit 26c.

[0023] In the microcontroller 13 and semiconductor integrated circuit 19, the internal circuit 27 further includes a digital input / output circuit 31, the exemplary digital input / output circuit 31 of which may include a general-purpose digital input / output (GPIO) circuit. The digital input / output circuit 31 is configured to generate one or more control signals for controlling the external device 15 in response to signals from the processing circuit 28. The digital input / output circuit 31 is also configured to provide one or more state control signals to the processing circuit 28 in response to signals from the external device 15. Specifically, the digital input / output circuit 31 may include a first digital input / output circuit 31f and a second digital input / output circuit 31g configured to control the external device 15. The first digital input / output circuit 31f and the second digital input / output circuit 31g are configured to communicate with a first external device 15b and a second external device 15c, respectively.

[0024] An exemplary first external device 15b may include a first switch circuit 14b and a first device 14c. The first device 14c is configured to receive the output voltage of the multi-voltage output power supply circuit 17 via the first switch circuit 14b. The exemplary first device 14c may include various electrical devices such as sensors, semiconductor devices, and semiconductor memory devices (e.g., 3.3V operating EEPROM, Electrically Erasable Programmable Read-Only Memory). Specifically, the first switch circuit 14b connects the power lines of the first device 14c to the output of the multi-voltage output power supply circuit 17. The exemplary first switch circuit 14b may include active elements such as transistors.

[0025] An exemplary second external device 15c may include a second switch circuit 16b and a second device 16c. The second device 16c is configured to receive the output voltage of the multi-voltage output power supply circuit 17 via the second switch circuit 16b. The exemplary second device 16c may include various electrical devices such as sensors, semiconductor devices, and semiconductor memory devices (e.g., 1.8V operating NOR (side-stacked)-Flash memory). Specifically, the second switch circuit 16b connects the power lines of the second device 16c to the output of the multi-voltage output power supply circuit 17. The exemplary second switch circuit 16b may include active elements such as transistors.

[0026] The digital input / output circuit 31 is configured to control the first switch circuit 14b and the second switch circuit 16b, respectively. Each of the first switch circuit 14b and the second switch circuit 16b can communicate bidirectionally with the digital input / output circuit 31. In the exemplary digital input / output circuit 31, the first digital input / output circuit 31f and the second digital input / output circuit 31g may be configured to communicate with the first switch circuit 14b and the second switch circuit 16b, respectively.

[0027] Furthermore, the interface circuits 29, specifically the first interface circuit 29b and the second interface circuit 29c, can also communicate bidirectionally with the first device 14c and the second device 16c, respectively. The exemplary digital input / output circuit 31 deconducts the first switch circuit 14b and the second switch circuit 16b until the microcontroller 13 determines that the multi-voltage output power supply circuit 17 has generated an appropriate voltage. Accordingly, the first switch circuit 14b and the second switch circuit 16b are configured to prevent the voltage of the multi-voltage output power supply circuit 17 from being applied to the first device 14c and the second device 16c, respectively.

[0028] The exemplary electrode 25 may further include a third external electrode 25f and a fourth external electrode 25g configured to communicate with the digital input / output circuit 31. The third external electrode 25f and the fourth external electrode 25g are also configured to communicate with the first external device 15b and the second external device 15c, respectively.

[0029] Figures 3(a) and 3(b) are diagrams showing exemplary communication paths between the digital input / output circuit 31 of the semiconductor integrated circuit according to this embodiment and the external device 15.

[0030] Referring to Figure 3(a), the switch circuits (14b, 16b) of the external device 15 receive signals from the digital input / output circuit 31 via the input / output bank circuits 23 (23f, 23g). Each of the switch circuits (14b, 16b) includes a switch SW. The switch SW opens and closes in response to signals from the digital input / output circuit 31.

[0031] Referring to Figure 3(b), the switch circuits (14b, 16b) of the external device 15 receive signals directly from the digital input / output circuit 31 without using the input / output bank circuit 23. The switch circuits (14b, 16b) include a switch SW and a level shifter LV. The level shifter LV operates in response to the signal from the digital input / output circuit 31 to open and close the switch SW.

[0032] In specific control operations, the digital input / output circuit 31 can generate a first control signal SCNT1 and a second control signal SCNT2 that control the first switch circuit 14b and the second switch circuit 16b, respectively, in response to a signal from the processing circuit 28, as shown in Figure 1.

[0033] The digital input / output circuit 31 is connected to the third external electrode 25f and the fourth external electrode 25g via the input / output bank circuit 23, and can provide the third external electrode 25f and the fourth external electrode 25g with a first control signal SCNT1 and a second control signal SCNT2, respectively. The input / output bank circuit 23 can shift the signal levels of the first control signal SCNT1 and the second control signal SCNT2 to generate level-shifted first control signal SCNT1 and second control signal SCNT2 (hereinafter, for simplicity, the level-shifted first control signal SCNT1 and second control signal SCNT2 will also be referred to as the first control signal SCNT1 and second control signal SCNT2, respectively).

[0034] An exemplary input / output bank circuit 23 may include a third input / output circuit 23f and a fourth input / output circuit 23g. The third input / output circuit 23f and the fourth input / output circuit 23g are connected to the digital input / output circuit 31, enabling the third input / output circuit 23f and the fourth input / output circuit 23g to communicate with the first switch circuit 14b and the second switch circuit 16b, respectively. Accordingly, the first control signal SCNT1 and the second control signal SCNT2 of the digital input / output circuit 31 are provided to the first switch circuit 14b and the second switch circuit 16b, respectively. The use of the input / output bank circuit 23 does not require a level shift circuit in the external device 15.

[0035] Alternatively, the digital input / output circuit 31 can be directly connected to the third external electrode 25f and the fourth external electrode 25g to provide the third external electrode 25f and the fourth external electrode 25g with a first control signal SCNT1 and a second control signal SCNT2, respectively. The first control signal SCNT1 and the second control signal SCNT2 are provided to the first external device 15b and the second external device 15c via the third external electrode 25f and the fourth external electrode 25g, respectively.

[0036] Referring again to Figures 1 and 2, the exemplary electrode 25 may further include a second power supply electrode 25h and a third power supply electrode 25j. The second power supply electrode 25h and the third power supply electrode 25j are configured to supply power to the internal circuit 27 and the processing circuit 28.

[0037] The internal circuit 27 may further include a control circuit 33. The control circuit 33 is configured to communicate with the processing circuit 28. The control circuit 33 is connected to the multi-voltage output power supply circuit 17 via an output electrode 25i. This connection is made directly, without going through the input / output bank circuit 23.

[0038] The control circuit 33 is configured to determine the operating state and / or output voltage of the multi-voltage output power supply circuit 17 in response to a signal from the processing circuit 28. Exemplary operating states are referred to as "Toff", "Tdeflt", "T1", "T2", and "Ton".

[0039] "Toff": Output voltage is, for example, 0 volts (grounded). "Tdeflt": The output voltage is the voltage at which the input / output bank circuit can operate (the specified value). For example, around 1 volt. "T1": Generation of the first power supply voltage of the first external device 15b (first set state). "T2": Generation of the second power supply voltage of the second external device 15c (second setting state). "Ton": Generation of power supply voltage for external devices 15, such as the first external device 15b, the second external device 15c, or other external devices (operating state).

[0040] The exemplary control circuit 33 may include, but is not limited to, a pulse width modulation (PWM) circuit. The exemplary multi-voltage output power supply circuit 17 can operate in any one of the exemplary operating states depending on the control of the pulse width modulation circuit.

[0041] The microcontroller 13 can be connected to various external devices 15 depending on the application. Accordingly, the exemplary internal circuitry 27 can optionally have a variable mode and a fixed mode. The microcontroller 13 is not limited to the implementation of these two modes. The external devices 15 connected to the microcontroller 13 when using the fixed mode may differ from at least one part of the external devices 15 connected to the microcontroller 13 when using the variable mode.

[0042] In variable mode, the multi-voltage output power supply circuit 17 can be configured to generate multiple voltages in response to control by the control circuit 33. Accordingly, the input / output bank circuit 23 can receive one of these multiple voltages. In fixed mode, the input / output bank circuit 23 can receive a single voltage.

[0043] In variable mode, the internal circuit 27 can be configured not to activate the first communication circuit 26b and the first communication circuit 26c simultaneously. Alternatively, the internal circuit 27 can be configured to activate them exclusively.

[0044] In fixed mode, the internal circuit 27 can be configured to activate the first communication circuit 26b and the first communication circuit 26c simultaneously. Alternatively, the internal circuit 27 can be configured not to activate the first communication circuit 26b and the first communication circuit 26c simultaneously. The internal circuit 27 can also be configured to activate the first communication circuit 26b and the first communication circuit 26c exclusively.

[0045] The internal circuit 27 may further include a detection circuit 35. The detection circuit 35 is configured to communicate with the processing circuit 28.

[0046] The detection circuit 35 has an input 35b and an output 35c, and is configured to receive a voltage at input 35b from at least one output of the multi-voltage output power supply circuit 17, specifically the AC / DC converter circuit 17b and the DC / DC converter circuit 17c. An exemplary detection circuit 35 is configured to receive a voltage at input 35b from the outputs of the AC / DC converter circuit 17b and the DC / DC converter circuit 17c.

[0047] The detection circuit 35 can be configured to generate a detection signal indicating the current value of the output voltage of the multi-voltage output power supply circuit 17 in response to the received voltage, and to provide this detection signal to output 35c.

[0048] The exemplary detection circuit 35 may include an input switching circuit 35f and an AD conversion circuit 35g (AD: Analog-Digita1).

[0049] The exemplary electrode 25 may further include a first input electrode 25k, a second input electrode 25m, and a third input electrode 25n. Specifically, the first input electrode 25k is configured to receive a signal from the AC / DC converter circuit 17b. The second input electrode 25m is configured to receive a signal from the DC / DC converter circuit 17c. The exemplary electrode 25 may further include a third input electrode 25n.

[0050] The input switching circuit 35f has inputs (e.g., three inputs) connected to the first input electrode 25k, the second input electrode 25m, and the third input electrode 25n. In response to a selection signal from the processing circuit 28, the input switching circuit 35f can provide the signal from any of the input electrodes (25k, 25m, 25n) as an analog signal to the AD conversion circuit 35g. The AD conversion circuit 35g is configured to receive the signal from the input switching circuit 35f as an analog value and to convert this analog value into a digital value to generate a detection signal. The detection signal can be provided to the processing circuit 28 or other circuits in the internal circuit 27 via the bus line BUS.

[0051] An example of a detection signal is as follows. The AD conversion circuit 35g can generate a first detection signal SDET1, a second detection signal SDET2, and a third detection signal SDET3 based on signals from the first input electrode 25k, the second input electrode 25m, and the third input electrode 25n, respectively.

[0052] These detection signals are provided to the processing circuit 28. Based on these detection signals, the processing circuit 28 obtains information on the operating status and / or output voltage of the external device 15 and the multi-voltage output power supply circuit 17. Based on the obtained information, the processing circuit 28 can generate signals to control the digital input / output circuit 31 and the interface circuit 29.

[0053] Specifically, the control circuit 33 is configured to adjust the output voltage of the multi-voltage output power supply circuit 17 in response to signals from the processing circuit 28 and / or the detection circuit 35.

[0054] The semiconductor integrated circuit 19 may further include a semiconductor memory 18. The semiconductor memory 18 is connected to the processing circuit 28 and the internal circuit 27 and can transmit and receive signals. It is configured to store program code 22 that the processor will run.

[0055] Figure 4 is a block diagram specifically showing the configuration of an exemplary computer associated with the semiconductor integrated circuit according to this embodiment.

[0056] An exemplary computer 20 for the microcontroller device 11 may include a central processing unit (CPU) 41, memory 42, input / output ports 43, and a network port 44, and may include an input device 45 and a display 46 if necessary. The memory 42 is communicatively coupled to the central processing unit 41. The input / output ports 43 are communicatively coupled to the central processing unit 41 and also receive and transmit data from external sensors. The network port 44 is communicatively coupled to the central processing unit 41 and connected to an (external) network. The input device 45 is communicatively coupled to the central processing unit 41. In the microcontroller device 11, the display 46 is communicatively coupled to the central processing unit 41 and the memory 42. Program code that causes a desired operation in the semiconductor integrated circuit 19 is stored in the memory 42 or provided from the network via the network port 44. The program code is executed by the central processing unit 41 to cause the semiconductor integrated circuit 19 to perform the specified operation.

[0057] The exemplary program code is configured to trigger the following actions in a semiconductor integrated circuit when executed by the processor: Operation 1: Control the multi-voltage output power supply circuit 17 using the control circuit 33 so that the first power supply voltage VOUT1 is applied to the input / output bank circuit 23 when communication is performed using the first communication circuit 26b. Operation 2: Control the multi-voltage output power supply circuit 17 using the control circuit 33 so that the second power supply voltage VOUT2 is applied to the input / output bank circuit 23 when using the second communication circuit 26c.

[0058] The microcontroller device 11 can perform various communications between the external device 15 and the semiconductor integrated circuit 19 by switching the input / output bank circuit 23 and the interface circuit 29, without being limited to the exemplary operations described above.

[0059] An exemplary semiconductor integrated circuit 19 can provide the following exemplary module. In the following description, the multi-voltage output power supply circuit 17 is referred to as “power supply circuit” in the drawings.

[0060] Figure 5 is a diagram showing the configuration of an exemplary module 47 (47b) of a semiconductor integrated circuit and microcontroller device according to this embodiment. Referring to Figure 5, a module for communication initialization processing is provided. The computer 20 can provide the following exemplary communication initialization processing 60. The program code for communication initialization processing 60 is stored in the semiconductor memory 18 and is configured to cause the computer 20 to execute the following processing.

[0061] Module 47b (47) Communication initialization process 61: Use the detection circuit 35 to detect the output voltage of the multi-voltage output power supply circuit 17 and generate a detection signal. Communication initialization process 62: When the detection signal of the detection circuit 35 indicates that the multi-voltage output power supply circuit 17 is in its initial state, select the first interface circuit 29b. Communication initialization process 63: When the detection signal from the detection circuit 35 does not indicate that the multi-voltage output power supply circuit 17 is in its initial state, control the control circuit 33 so that the multi-voltage output power supply circuit 17 is in its initial state. Here, the initial state can be either "Toff" or "Tdeflt".

[0062] Figure 6 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. Referring to Figure 6, a module 47 (47c) for communication processing is provided. The computer 20 can provide the following exemplary communication processing 70. The program code for the communication processing 70 is stored in the semiconductor memory 18 and is configured to cause the computer 20 to execute the following processing.

[0063] Module 47c (47) Communication processing 71: When the detection signal of the detection circuit 35 indicates that the multi-voltage output power supply circuit 17 is in its initial state, provide the digital input / output circuit 31 with a first setting to use the first external device 15b. Communication processing 72: Control the control circuit 33 so that the multi-voltage output power supply circuit 17 generates the first power supply voltage VOUT1. Communication processing 73: Using the detection circuit 35, detect the output voltage of the multi-voltage output power supply circuit 17 and generate a detection signal. Communication process 74: When the detection signal of the detection circuit 35 indicates that the multi-voltage output power supply circuit 17 is generating the first power supply voltage VOUT1, communicate with the first external device 15b using the first interface circuit 29b.

[0064] Figure 7 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. Referring to Figure 7, a module 47 (47d) for communication switching processing is provided. The computer 20 can provide the following exemplary communication switching processing 80 (stop). The program code for this communication switching processing 80 (stop) is stored in the semiconductor memory 18 and is configured to cause the computer 20 to execute the following processing.

[0065] Module 47d (47) Communication switching process 81: Stop communicating with the first external device using the first interface circuit 29b. Communication switching process 82: Stop supplying the first power supply voltage VOUT1 to the first external device 15b, or disconnect the first external device 15b from the multi-voltage output power supply circuit 17. Communication switching process 83: Control the control circuit 33 so that the multi-voltage output power supply circuit 17 returns to its initial state.

[0066] Figure 8 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. Referring to Figure 8, a module 47 (47f) for communication switching processing is provided. The computer 20 can provide the following exemplary communication switching processing 80 (start). The program code for this communication switching processing 80 (start) is stored in the semiconductor memory 18 and is configured to cause the computer 20 to execute the following processing.

[0067] Module 47f (47) Communication switching process 84: Using the detection circuit 35, detect the output voltage of the multi-voltage output power supply circuit 17 and generate a detection signal. Communication switching process 85: When the detection signal of the detection circuit 35 indicates that the multi-voltage output power supply circuit 17 is in its initial state, control the control circuit 33 to generate the second power supply voltage VOUT2 in the multi-voltage output power supply circuit 17. Communication switching process 86: When the detection signal of the detection circuit 35 indicates that the multi-voltage output power supply circuit 17 is generating the second power supply voltage VOUT2, the second power supply voltage VOUT2 is supplied to the second external device 15c. Communication switching process 87: When the detection signal of the detection circuit 35 indicates that the multi-voltage output power supply circuit 17 is generating the second power supply voltage VOUT2, communicate with the second external device 15c using the second interface circuit 29c.

[0068] Figure 9 is a diagram showing the configuration of an exemplary module of a semiconductor integrated circuit and microcontroller device according to this embodiment. Referring to Figure 9, a module 47 (47g) for communication switching processing is provided. The computer 20 can provide the following exemplary communication switching processing 80 (termination). The program code for this communication switching processing 80 (termination) is stored in the semiconductor memory 18 and is configured to cause the computer 20 to execute the following processing.

[0069] Module 47g (47) Communication switching process 89: Stop communicating with the second external device 15b using the second interface circuit 29c. Communication switching process 90: Stop providing the second power supply voltage VOUT2 to the second external device 15b, or disconnect the second external device 15c from the multi-voltage output power supply circuit 17. Communication switching process 91: Control the control circuit 33 so that the multi-voltage output power supply circuit 17 returns to its initial state.

[0070] The semiconductor integrated circuit 19 can be provided as a dedicated semiconductor device manufactured using a semiconductor process, or it can be provided as a reconfigurable semiconductor device (e.g., FPGA, Field Programmable Gate Array). Specifically, the reconfigurable semiconductor device can be configured according to circuit connection information, circuit connection data, or circuit connection information code representing the configuration of a specific circuit described in a hardware description language, e.g., hardware description language code. Exemplary hardware description languages ​​include, for example, HDL (Hardware Description Language) such as Verilog and VHDL. The circuit connection information, circuit connection data, or circuit connection information code according to this embodiment includes a piece of configuration information that causes the circuit to function as a processing circuit that performs a desired operation. Accordingly, the piece of configuration information is stored in the reconfigurable semiconductor device to manufacture a reconfigurable semiconductor device that has been reconfigured to operate as a specific circuit.

[0071] Specifically, the configuration of a particular circuit can be written to a reconfigurable semiconductor device to fabricate a reconfigured semiconductor device, i.e., a semiconductor integrated circuit 19. The semiconductor integrated circuit 19 of the reconfigured semiconductor device can operate as an external interface circuit.

[0072] The exemplary circuit information is described in a hardware description language and represents the configuration of a specific circuit, and is configured to allow an unconfigured circuit of a reconfigurable semiconductor device to function as an external interface circuit. Furthermore, the exemplary circuit information may include at least one component relating to the following circuit information:

[0073] Components of the internal circuitry (27 components). The internal circuit 27 is configured to communicate with the processing circuit. The internal circuit 27 is configured to include an interface circuit 29 that is configured to communicate with the external device 15, which includes a first external device 15b and a second external device 15c. The interface circuit 29 is configured to include a first interface circuit 29b and a second interface circuit 29c. The first external device 15b is configured to operate at a first power supply voltage VOUT1 that is different from the power supply voltage of the internal circuit 27, and the second external device 15c is configured to operate at a second power supply voltage VOUT2 that is different from the power supply voltage of the internal circuit 27.

[0074] Components of the input / output bank circuit 23. The input / output bank circuit 23 is configured to include a first input / output circuit 23b connected to the first interface circuit 29b, and a second input / output circuit 23c connected to the second interface circuit 29c. The first input / output circuit 23b and the second input / output circuit 23c are configured to be connected to the bank power line 24 of the input / output bank circuit 23. The first interface circuit 29b and the first input / output circuit 23b are configured to constitute a first communication circuit 26b that is capable of communicating with the first external device 15b. The second interface circuit 29c and the second input / output circuit 23c are configured to constitute a second communication circuit 26c that is capable of communicating with the second external device 15c.

[0075] Components of the first input / output circuit 23b and the second input / output circuit 23c. Each of the first input / output circuit 23b and the second input / output circuit 23c is configured to convert signal levels from one of the internal voltage levels of the internal power lines of the internal circuit 27 and the external voltage levels of the bank power lines 24 of the input / output bank circuit 23 to the other.

[0076] Components of the internal circuitry (27 components). The internal circuit 27 is configured so as not to activate the first communication circuit 26b and the second communication circuit 26c simultaneously.

[0077] Hardware resources for creating circuit information and configuring or reconfiguring a reconfigurable semiconductor device may have the same configuration as the exemplary computer configuration in Figure 4. The reconfigurable semiconductor device is connected to the I / O ports in Figure 4, and circuit information can be written to the reconfigurable semiconductor device via the I / O ports to create (configure) a reconfigured semiconductor integrated circuit 19. The circuit information is stored, for example, in the computer's memory.

[0078] An exemplary reconfigured semiconductor device may include some or all of the circuitry shown in Figure 2. The circuits and operations described with reference to Figures 1 through 9, and subsequently described, are to be reinterpreted to constitute components of the circuitry information.

[0079] Figures 10 to 15 are diagrams illustrating the main operations in an exemplary method according to this embodiment. In the following description, reference numerals already used will be used where possible for ease of understanding. In the following description, the multi-voltage output power supply circuit 17 will be referred to as the “power supply circuit” in the drawings and description.

[0080] Figure 10 is a diagram illustrating the main operations in one of the exemplary methods according to this embodiment. Referring to Figure 10, exemplary method 100 can encompass a method for communicating between a microcontroller and an external device. In the microcontroller device 11, the method for communicating between the microcontroller 13 and the external device 15 may include the following operations. Exemplary method 100 may perform some or all of the individual operations in any order.

[0081] In operation S100-1, the first power supply voltage VOUT1 is applied to the input / output bank circuit 23 of the microcontroller 13 from a power supply circuit such as the multi-voltage output power supply circuit 17.

[0082] In operation S100-2, the first power supply voltage VOUT1 is applied from the power supply circuit to the first external device 15b of the external device 15.

[0083] In operation S100-3, the first interface circuit 29b is selected from the interface circuit 29 of the microcontroller 13, and a series of communications with the first external device 15b are completed via the input / output bank circuit 23 using the first interface circuit 29b.

[0084] In operation S100-4, following the completion of communication, the first interface circuit 29b is deselected, and while maintaining the power supply voltage of the microcontroller 13, the second power supply voltage VOUT2 is applied from the power supply circuit to the input / output bank circuit 23.

[0085] In operation S100-5, the second power supply voltage VOUT2 is applied from the power supply circuit to the second external device 15c of the external device 15.

[0086] In operation S100-6, the second interface circuit 29c is selected, and a series of communications with the second external device 15c are completed via the input / output bank circuit 23 using the second interface circuit 29c.

[0087] In operation S100-7, following the completion of communication, the second interface circuit 29c is deselected, and the power supply circuit is set to a voltage state different from the second power supply voltage VOUT2 while maintaining the power supply voltage of the microcontroller 13.

[0088] Figures 11 to 15 are diagrams illustrating the main operations in another exemplary method according to this embodiment. Exemplary method 100 may include methods for communicating with an external device using an interface circuit, and methods for controlling the external device and a power supply circuit using the interface circuit. Exemplary method 100 may perform some or all of the individual operations in any order.

[0089] Referring to Figure 11, the details of the operation in the exemplary method 100 are shown.

[0090] Method 100 may include operation S101, which includes controlling a power supply circuit, such as a multi-voltage output power supply circuit 17, to receive a first power supply voltage VOUT1 from the power supply circuit into an input / output bank circuit 23.

[0091] Method 100 may include operation S102, which includes sending a first control signal from the digital input / output circuit 31 to control the first external device 15b so that a first power supply voltage VOUT1 is applied to the first external device 15b of the external device 15 from the power supply circuit.

[0092] In an exemplary transmission, the first control signal can be provided to the first external device 15b via the input / output bank circuit 23, or the first control signal can be provided to the first external device 15b without using the input / output bank circuit 23.

[0093] Method 100 may include operation S103. Operation S103 includes selecting a first interface circuit 29b from interface circuit 29 and completing a series of communications with a first external device 15b via input / output bank circuit 23 using the selected first interface circuit 29b.

[0094] Method 100 may include operation S104, which includes deselecting the first interface circuit 29b following the completion of communication.

[0095] Method 100 may include operation S105. Operation S105 includes controlling the power supply circuit to switch to the second power supply voltage VOUT2 following the completion of communication. During this switch, the power supply to the microcontroller 13 is maintained.

[0096] Method 100 may include operation S106, which includes receiving a second power supply voltage VOUT2 from the power supply circuit to the input / output bank circuit 23.

[0097] Referring to Figure 12, the details of the operations in the exemplary method 100 are shown. Operation S101 may include at least one of the following operations:

[0098] Operation S101-1 may include detecting the output voltage of the power supply circuit. This detection may be performed prior to providing the first power supply voltage VOUT1 to the input / output bank circuit 23 and to the first external device 15b.

[0099] Operation S101-2 may include controlling the power supply circuit using the control circuit 33 so that the output voltage of the power supply circuit indicates the initial state, if the detection result does not indicate that the output voltage of the power supply circuit is in the initial state.

[0100] Operation S101-3 may include controlling the power supply circuit using the control circuit 33 so that the output voltage of the power supply circuit indicates the first power supply voltage VOUT1 when the detection result indicates that the output voltage of the power supply circuit is in its initial state.

[0101] Operation S101-4 may include supplying the output voltage of the power supply circuit to the input / output bank circuit 23.

[0102] Referring to Figure 13, the details of operation S103 in exemplary method 100 are shown. Operation S103 may include at least one of the following operations:

[0103] Operation S103-1 may include selecting a first interface circuit 29b from the interface circuit 29 that is configured to communicate with the first external device 15b.

[0104] Operation S103-2 may include communicating with the first external device 15b via the input / output bank circuit 23 using the first interface circuit 29b.

[0105] Operation S103-3 may include stopping communication between the first interface circuit 29b and the first external device 15b.

[0106] Referring to Figure 14, the details of the operations in the exemplary method 100 are shown. Operation S105 may include at least one of the following operations:

[0107] Operation S105-1 may include controlling the first external device 15b to disconnect it from the first power supply voltage VOUT1 from the power supply circuit.

[0108] Operation S105-2 may include controlling the power supply circuit using the control circuit 33 to set the power supply circuit to an initial state.

[0109] Operation S105-3 may include controlling the power supply circuit using the control circuit 33 to generate the second power supply voltage VOUT2 from the initial state.

[0110] Referring to Figure 15, the exemplary method 100 allows some or all of the individual operations to be performed in any order, and the following operations can be performed following the operations in Figure 10.

[0111] Method 100 may include operation S107. Operation S107 includes controlling the second external device 15c to apply the second power supply voltage VOUT2 to the second external device 15c of the external device 15.

[0112] Method 100 may include operation S108, which includes providing a second power supply voltage VOUT2 to a second external device 15c, and then selecting a second interface circuit 29c from interface circuit 29.

[0113] Method 100 may include operation S109. Operation S109 includes communicating with a second external device 15c via the input / output bank circuit 23 using a second interface circuit 29c selected from the interface circuit 29.

[0114] Method 100 may include operation S110, which includes terminating communication using the second interface circuit 29c.

[0115] Method 100 may include operation S111, which includes stopping the application of the second power supply voltage VOUT2 to the second external device 15c.

[0116] Method 100 may include operation S112. Operation S112 includes controlling the power supply circuit using the control circuit 33 to set the power supply circuit to a state different from the second power supply voltage VOUT2, for example, an initial state.

[0117] Figures 16 and 17 show the specific system startup process of the input / output bank circuit 23. After power-on or system reset is released, the central processing unit reads the program code stored in the semiconductor memory 18 and executes the system startup process. The system startup process will be explained with reference to Figures 16 and 17.

[0118] As shown in Figure 16, in operation S161, the value of output Vdcdc is acquired using the detection circuit 35. In operation S162, if the acquired value of output Vdcdc indicates the initial state ("OFF", e.g., 0 volts), in operation S164, the state of the second interface circuit 29c is checked. On the other hand, if the acquired value of output Vdcdc is not "OFF", e.g., 0 volts, in operation S163, the setting of the control circuit 33 is set to "OFF", specifically, the output Vdcdc value from the DC-DC converter circuit 17c is controlled to become "OFF", e.g., 0 volts. After this control, in operation S161, the value of output Vdcdc is acquired again. If the result is that the value of output Vdcdc is "OFF", in operation S164, the state of the second interface circuit 29c is checked.

[0119] In operation S165, if the confirmed state of the second interface circuit 29c is not deselected, in operation S166, the second interface circuit 29c is set to deselected, and in operation S164, the state of the second interface circuit 29c is checked again. On the other hand, in operation S165, if the confirmed state of the second interface circuit 29c is deselected, in operation S171 in Figure 17, the state of the first interface circuit 29b is checked.

[0120] In operation S172, if the confirmed state of the first interface circuit 29b is deselected, in operation S173, the state of the second switch circuit 16b is acquired via the digital input / output circuit 31. On the other hand, in operation S172, if the confirmed state of the first interface circuit 29b is not deselected, in operation S174, the first interface circuit 29b is set to deselected, and then in operation S171, the state of the first interface circuit 29b is checked again. In operation S172, if the state of the first interface circuit 29b is deselected, in operation S173, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31.

[0121] In operation S175, if the acquired state of the second switch circuit 16b is "OFF", in operation S176, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31. On the other hand, in operation S175, if the confirmed state of the second switch circuit 16b is not "OFF", in operation S177, the second switch circuit 16b is set to "OFF" using the digital input / output circuit 31. Again, in operation S173, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31. In operation S175, if the state of the second switch circuit 16b is "OFF", in operation S176, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31.

[0122] In operation S178, if the acquired state of the first switch circuit 14b is "OFF", the system startup process for the input / output bank circuit 23 is terminated. On the other hand, in operation S178, if the acquired state of the first switch circuit 14b is not "OFF", in operation S179, the first switch circuit 14b is set to "OFF" using the digital input / output circuit 31. Again, in operation S176, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31. In operation S178, if the state of the first switch circuit 14b is "OFF", the system startup process for the input / output bank circuit 23 is terminated.

[0123] Figures 18 and 19 show the specific communication initiation process for the input / output bank circuit 23. The communication initiation process between the first interface circuit 29b and the first external device 15b will be explained with reference to Figures 18 and 19.

[0124] As shown in Figure 18, first, in operation S180, the control circuit 33 is set to state Toff to control the value of the output Vdcdc from the DC-DC converter circuit 17c to "OFF", for example, 0 volts. In operation S181, the value of the output Vdcdc is obtained using the detection circuit 35. In operation S182, if the obtained result indicates "OFF", the state of the second interface circuit 29c is checked in operation S184. On the other hand, if the obtained result of the output Vdcdc in operation S182 is not "OFF", then in operation S183, a certain amount of time is waited for, and in operation S181, the value of the output Vdcdc is obtained using the control circuit 33. This is repeated until the state of the output Vdcdc becomes "OFF".

[0125] Next, the second interface circuit 29c, which will not be used, is deselected.

[0126] As shown in Figure 18, in operation S184, the state of the second interface circuit 29c is checked. In operation S185, if the checked state of the second interface circuit 29c is not selected, in operation S186, the state of the first interface circuit 29b is checked. On the other hand, in operation S185, if the state of the second interface circuit 29c is not not selected, in operation S187, the second interface circuit 29c is set to not selected. Again, in operation S184, the state of the second interface circuit 29c is checked. In operation S185, if the state of the second interface circuit 29c is not selected, in operation S186, the state of the first interface circuit 29b is checked.

[0127] Next, the activation process for the first interface circuit 29b to be used is performed.

[0128] In operation S188, if the confirmed state of the first interface circuit 29b is "selected", then in operation S190, as shown in Figure 19, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31. On the other hand, as shown in Figure 18, if the state of the first interface circuit 29b is not "selected" in operation S188, then in operation S189, the first interface circuit 29b is set to "selected". Again, in operation S186, the state of the first interface circuit 29b is confirmed. In operation S188, if the state of the first interface circuit 29b is "selected", then in operation S190, as shown in Figure 19, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31.

[0129] Next, the process of not supplying power to the second external device 15c, which is not being used, is performed.

[0130] After operation S190, as shown in Figure 19, if the acquired state of the second switch circuit 16b is "OFF" in operation S191, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31 in operation S192. On the other hand, if the state of the second switch circuit 16b is not "OFF" in operation S191, the second switch circuit 16b is set to "OFF" using the digital input / output circuit 31 in operation S193. Again, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31 in operation S190. If the state of the second switch circuit 16b is "OFF" in operation S191, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31 in operation S192.

[0131] Next, the process of supplying power to the first external device 15b to be used is performed.

[0132] In operation S194, if the acquired state of the first switch circuit 14b is "ON", in operation S195, the control circuit 33 is set to state T1. On the other hand, in operation S194, if the state of the first switch circuit 14b is not "ON", in operation S196, the first switch circuit 14b is set to "ON" using the digital input / output circuit 31. Again, in operation S192, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31. As a result, in operation S194, if the state of the first switch circuit 14b is "OFF", in operation S195, the control circuit 33 is set to state T1.

[0133] Next, the process of supplying power to the input / output bank circuit 23 and the first external device 15b is performed.

[0134] In operation S195, the control circuit 33 is set to state T1, and then in operation S197, the value of the output Vdcdc is obtained using the detection circuit 35. In operation S198, when the value of the output Vdcdc is the voltage V1 at which the first device 14c can operate, the startup process of the first interface circuit is terminated.

[0135] In operation S198, if the value of output Vdcdc is not voltage V1, in operation S199, a certain amount of time is waited for, and in operation S195, the control circuit 33 is set to state T1. Then, in operation S197, the value of output Vdcdc is obtained using the detection circuit 35. These steps are repeated until the value of output Vdcdc becomes voltage V1, at which point the startup process of the first interface circuit is terminated.

[0136] Figures 20 and 21 show the specific communication termination process for the input / output bank circuit 23. Referring to Figures 20 and 21, the communication termination process for the first external device 15b using the first interface circuit 29b will be explained.

[0137] As shown in Figure 20, first, in operation S200, the communication status of the first interface circuit 29b is checked. If the communication status of the first interface circuit 29b has ended in operation S201, the status of the first interface circuit 29b is checked in operation S202. On the other hand, if the communication status of the first interface circuit 29b has not ended in operation S201, in operation S203, a certain amount of time is waited for, and then the communication status of the first interface circuit 29b is checked again in operation S200. If the communication status has ended in operation S201, the status of the first interface circuit 29b is checked in operation S202.

[0138] Next, the first interface circuit 29b is deselected.

[0139] In operation S204, if the confirmed state of the first interface circuit 29b is deselected, the state of the first switch circuit 14b is acquired in operation S210 using the digital input / output circuit 31, as shown in Figure 21. On the other hand, if the state of the first interface circuit 29b is not deselected in operation S204, the first interface circuit 29b is set to deselected in operation S205. Again, the state of the first interface circuit 29b is confirmed in operation S202. In operation S204, if the state of the first interface circuit 29b is deselected, the state of the first switch circuit 14b is acquired in operation S210 using the digital input / output circuit 31, as shown in Figure 21.

[0140] Next, referring to Figure 21, the process of not supplying power to the first external device 15b is performed.

[0141] In operation S211, if the acquired state of the first switch circuit 14b is "OFF", in operation S212, the control circuit 33 is set to state Toff. On the other hand, in operation S211, if the acquired state of the first switch circuit 14b is not "OFF", in operation S213, the first switch circuit 14b is set to "OFF" using the digital input / output circuit 31. Again, in operation S210, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31. In operation S211, if the state of the first switch circuit 14b is "OFF", in operation S212, the control circuit 33 is set to state Toff.

[0142] Next, the control circuit 33 is controlled so that the output Vdcdc from the DC-DC converter circuit 17c is in state Toff, for example, 0 volts.

[0143] After setting the control circuit 33 to state Toff, in operation S214, the value of output Vdcdc is obtained using the detection circuit 35. In operation S215, if the obtained value of output Vdcdc is "OFF", for example 0 volts, the stop process of the first interface circuit 29b is terminated.

[0144] In operation S215, if the output Vdcdc value is not OFF, for example, 0 volts, then in operation S216, after waiting for a certain period of time, in operation S214, the control circuit 33 is used to obtain the value of output Vdcdc. These steps are repeated to set the output Vdcdc value to OFF (0 volts).

[0145] Figures 22 and 23 show the specific communication initiation process for the input / output bank circuit 23. The communication initiation process for the second external device 15c using the second interface circuit 29c will be explained with reference to Figures 22 and 23.

[0146] First, the control circuit 33 is set to state Toff to control the output Vdcdc from the DC-DC converter circuit 17c to 0 volts.

[0147] As shown in Figure 22, in operation S220, the value of output Vdcdc is obtained using the control circuit 33. In operation S221, if the value of output Vdcdc is "OFF", for example 0 volts, in operation S222, the state of the first interface circuit 29b is checked. On the other hand, in operation S221, if the obtained value of output Vdcdc is not "OFF", for example 0 volts, in operation S223, the state Toff is set to output Vdcdc using the control circuit 33. After waiting for a certain period of time to elapse, in operation S220, the value of output Vdcdc is obtained using the control circuit 33. These steps are repeated to set the value of output Vdcdc to "OFF", for example 0 volts.

[0148] Next, the first interface circuit 29b, which will not be used, is deselected.

[0149] In operation S224, if the confirmed state of the first interface circuit 29b is deselected, then in operation S226, the state of the second interface circuit 29c is checked. On the other hand, in operation S224, if the state of the first interface circuit 29b is not deselected, then in operation S225, the first interface circuit 29b is set to deselected. Again, in operation S222, the state of the first interface circuit 29b is checked. In operation S224, if the state of the first interface circuit 29b is deselected, then in operation S226, the state of the second interface circuit 29c is checked.

[0150] Next, the activation process for the second interface circuit 29c to be used is performed.

[0151] In operation S227, if the confirmed state of the second interface circuit 29c is selected, the state of the first switch circuit 14b is acquired in operation S230 using the digital input / output circuit 31, as shown in Figure 23. On the other hand, if the state of the second interface circuit 29c is not selected in operation S227, the second interface circuit 29c is set to selected in operation S228. Again, the state of the second interface circuit 29c is confirmed in operation S226. In operation S227, if the state of the second interface circuit 29c is selected, the state of the first switch circuit 14b is acquired in operation S230 using the digital input / output circuit 31, as shown in Figure 23.

[0152] Next, referring to Figure 23, the process of not supplying power to the unused first external device 15b is performed.

[0153] In operation S231, if the acquired state of the first switch circuit 14b is "OFF", in operation S233, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31. On the other hand, in operation S231, if the state of the first switch circuit 14b is not "OFF", in operation S232, the first switch circuit 14b is set to "OFF" using the digital input / output circuit 31. Again, in operation S230, the state of the first switch circuit 14b is acquired using the digital input / output circuit 31. In operation S231, if the state of the first switch circuit 14b is "OFF", in operation S233, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31.

[0154] Next, the process of supplying power to the second external device 15c to be used is performed.

[0155] In operation S234, if the acquired state of the second switch circuit 16b is "ON", in operation S235, the control circuit 33 is set to state T2.

[0156] On the other hand, in operation S234, if the state of the second switch circuit 16b is not "ON", in operation S236, the digital input / output circuit 31 is used to set the second switch circuit 16b to "ON". Again, in operation S233, the digital input / output circuit 31 is used to obtain the state of the second switch circuit 16b. In operation S234, if the state of the second switch circuit 16b is "ON", in operation S235, the control circuit 33 is set to state T2.

[0157] Next, the process of supplying power to the input / output bank circuit 23 and the second external device 15c is performed.

[0158] In operation S235, the control circuit 33 is set to state T2. Then, in operation S237, the value of output Vdcdc is obtained using the detection circuit 35. In operation S238, if the value of output Vdcdc is the voltage V2 at which the second device 16c can operate, the start process of the second interface circuit 29c is terminated. On the other hand, if the value of output Vdcdc is not the voltage V2, in operation S239, the control circuit 33 is set to state T2. After waiting for a certain period of time to elapse, in operation S237, the value of output Vdcdc is obtained using the detection circuit 35. These steps are repeated until the value of output Vdcdc is set to the voltage V2.

[0159] Figures 24 and 25 show the specific communication termination process for the input / output bank circuit 23. Referring to Figures 24 and 25, the communication termination process with the second external device 15c using the second interface circuit 29c will be explained.

[0160] As shown in Figure 24, first, in operation S240, the communication status of the second interface circuit 29c is checked. If the communication status of the second interface circuit 29c has ended in operation S241, the status of the second interface circuit 29c is checked in operation S242. On the other hand, if the communication status of the second interface circuit 29c has not ended in operation S241, a certain amount of time is waited for in operation S243. After that, the communication status of the second interface circuit 29c is checked in operation S240. If the communication status has ended in operation S241, the status of the second interface circuit 29c is checked in operation S242.

[0161] Next, the second interface circuit 29c is disabled.

[0162] In operation S245, if the confirmed state of the second interface circuit 29c is deselected, the state of the second switch circuit 16b is acquired in operation S250 using the digital input / output circuit 31, as shown in Figure 25. On the other hand, if the state of the second interface circuit 29c is not deselected in operation S245, the second interface circuit 29c is set to deselected in operation S244. Again, the state of the second interface circuit 29c is confirmed in operation S242. In operation S245, if the state of the second interface circuit 29c is deselected, the state of the second switch circuit 16b is acquired in operation S250 using the digital input / output circuit 31, as shown in Figure 25.

[0163] Next, referring to Figure 25, we perform a process to disable power supply to the second external device 15c.

[0164] In operation S251, if the acquired state of the second switch circuit 16b is "OFF", in operation S253, the value of output Vdcdc is acquired using the detection circuit 35. On the other hand, in operation S251, if the acquired state of the second switch circuit 16b is not "OFF", in operation S252, the second switch circuit 16b is set to "OFF" using the digital input / output circuit 31. Again, in operation S250, the state of the second switch circuit 16b is acquired using the digital input / output circuit 31. In operation S251, if the state of the second switch circuit 16b is "OFF", in operation S253, the value of output Vdcdc is acquired using the detection circuit 35.

[0165] Next, the output Vdcdc from the DC-DC converter circuit 17c is controlled to become 0 volts.

[0166] In operation S253, after obtaining the value of output Vdcdc using the detection circuit 35, in operation S254, if the obtained value of Vdcdc is "OFF", for example 0 volts, the stop process of the second interface circuit 29c is terminated. On the other hand, in operation S254, if the value of output Vdcdc is not "OFF", in operation S255, the control circuit 33 is used to set the value of output Vdcdc to "OFF". After waiting for a certain period of time, these steps are repeated in operation S254 until the value of output Vdcdc becomes "OFF".

[0167] As explained above, in semiconductor integrated circuits with a limited number of I / O banks, the limitation on the number of external devices that can be controlled by an I / O bank can be mitigated. Such technical benefits can be applied to microcontroller devices including semiconductor integrated circuits, methods for communication between a microcontroller including a semiconductor integrated circuit and an external device, and methods for communicating with an external device using an interface circuit.

[0168] As can be understood from the description of this embodiment, this embodiment may have various aspects as shown below.

[0169] The semiconductor integrated circuit on the first side according to this embodiment is an internal circuit that can communicate with a processing circuit, the internal circuit includes an interface circuit configured to communicate with an external device, the interface circuit includes a first interface circuit and a second interface circuit, and an input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, the first input / output circuit and the second input / output circuit are connected to the bank power line of the input / output bank circuit, the first interface circuit and the first input / output circuit constitute a first communication circuit, and the second interface circuit and the second input / output circuit constitute a second communication circuit, the input / output bank circuit includes a first power electrode configured to receive an external voltage different from the voltage of the internal power line of the internal circuit and connected to the bank power line of the input / output bank circuit, a first external electrode connected to the first communication circuit, and a second external electrode connected to the second communication circuit, and the internal circuit is configured not to activate the first communication circuit and the second communication circuit simultaneously.

[0170] In the semiconductor integrated circuit relating to this aspect, the internal circuit is operated in such a way that the activation of the first communication circuit and the activation of the second communication circuit are not performed simultaneously, thereby enabling the switching of the voltage applied from the first power supply electrode to the input / output bank circuit.

[0171] In the semiconductor integrated circuit of the first side according to the first side of this embodiment, each of the first input / output circuit and the second input / output circuit may be configured to convert a signal level from one of the internal voltage level of the internal power line and the external voltage level of the bank power line of the input / output bank circuit to the other.

[0172] In the semiconductor integrated circuit relating to this aspect, the input / output bank circuit receives a voltage applied to the input / output bank circuit from the first power supply electrode, causing the first input / output circuit and the second input / output circuit to operate as level shift circuits.

[0173] In the semiconductor integrated circuit of the third aspect according to the second aspect of this embodiment, the external device includes a first external device that can communicate with the first communication circuit and a second external device that can communicate with the second communication circuit, the internal circuit further includes a digital input / output circuit, the digital input / output circuit includes a first digital input / output circuit and a second digital input / output circuit, and the first digital input / output circuit and the second digital input / output circuit can be configured to control the first external device and the second external device, respectively.

[0174] According to the semiconductor integrated circuit relating to this aspect, external devices can be controlled using digital input / output circuits, while the interface circuit can communicate with the external devices.

[0175] In a semiconductor integrated circuit of a fourth aspect according to the third aspect of this embodiment, the first power electrode is configured to receive the output voltage of a multi-voltage output power supply circuit located outside the semiconductor integrated circuit, the first external device includes a first switch circuit and a first device, the first device receiving the output voltage of the multi-voltage output power supply circuit via the first switch circuit, the second external device includes a second switch circuit and a second device, the second device receiving the output voltage of the multi-voltage output power supply circuit via the second switch circuit, the first external device may be configured to operate at a first power supply voltage different from the power supply voltage of the internal circuit, and the second external device may be configured to operate at a second power supply voltage different from the power supply voltage of the internal circuit.

[0176] According to the semiconductor integrated circuit relating to this aspect, the exemplary external device may include a switch for switching the power supply and the main device.

[0177] In the semiconductor integrated circuit of the fifth side according to the fourth side of this embodiment, the first interface circuit and the second interface circuit communicate with the first device and the second device, respectively, via the input / output bank circuit, and the digital input / output circuit can communicate with the first switch circuit and the second switch circuit.

[0178] In the semiconductor integrated circuit relating to this aspect, the interface circuit communicates with the main device, and the digital input / output circuit operates to control the switch circuit.

[0179] The semiconductor integrated circuit of the sixth side according to the fourth or fifth side according to this embodiment further comprises a third external electrode connected to the first external device and a fourth external electrode connected to the second external device, and the digital input / output circuit can be connected to the third external electrode and the fourth external electrode via the input / output bank circuit.

[0180] In semiconductor integrated circuits relating to this aspect, dedicated external electrodes are prepared for controlling external devices using digital input / output circuits.

[0181] In the semiconductor integrated circuit of the fourth, fifth, or sixth side of this embodiment, the internal circuit further comprises a control circuit that can communicate with the processing circuit, the control circuit is configured to determine the output voltage of the multi-voltage output power supply circuit, and the control circuit can control the multi-voltage output power supply circuit to selectively generate at least the first power supply voltage and the second power supply voltage.

[0182] In semiconductor integrated circuits relating to this aspect, a multi-voltage output power supply circuit is used to supply power to external devices. The multi-voltage output power supply circuit is controlled by a control circuit.

[0183] In the semiconductor integrated circuit of the eighth aspect according to the seventh aspect of this embodiment, the internal circuit further comprises a detection circuit that can communicate with the processing circuit, the detection circuit is configured to generate a detection signal indicating the value of the output voltage of the multi-voltage output power supply circuit, and the internal circuit or the processing circuit can identify the operating state of the multi-voltage output power supply circuit based on the detection signal.

[0184] In semiconductor integrated circuits relating to this aspect, the detection circuit is used to detect the output voltage of a multi-voltage output power supply circuit.

[0185] In the semiconductor integrated circuit of the ninth side according to the eighth side of this embodiment, the control circuit may be configured to adjust the output voltage of the multi-voltage output power supply circuit in response to the detection signal.

[0186] According to the semiconductor integrated circuit relating to this aspect, the control circuit can control the multi-voltage output power supply circuit in response to a detection signal from the detection circuit.

[0187] In the semiconductor integrated circuit of the tenth side according to the fourth, fifth, sixth, or seventh side of this embodiment, the internal circuit further comprises a detection circuit that can communicate with the processing circuit, the detection circuit is configured to detect the value of the output voltage of the multi-voltage output power supply circuit, and the internal circuit or the processing circuit can determine the operating state of the multi-voltage output power supply circuit based on the detection result of the detection circuit.

[0188] According to the semiconductor integrated circuit relating to this aspect, the detection circuit enables the internal circuit and processing circuit to identify the operating state of the multi-voltage output power supply circuit.

[0189] In the semiconductor integrated circuit of the 11th side according to the 4th, 5th, 6th, 7th, 8th, 9th, or 10th side according to this embodiment, the multi-voltage output power supply circuit includes an AC-DC converter circuit configured to convert AC power to DC power, and a DC-DC converter circuit configured to receive the DC power from the AC-DC converter circuit, wherein the DC-DC converter circuit may be configured to generate the first power supply voltage and the second power supply voltage.

[0190] According to the semiconductor integrated circuit relating to this aspect, the multi-voltage output power supply circuit can convert AC power to DC power and generate multiple power supply voltages from the DC power.

[0191] A semiconductor integrated circuit of a twelfth side according to the fourth, fifth, sixth, seventh, eighth, ninth, tenth, or eleventh side according to this embodiment further comprises a semiconductor memory, the processing circuit comprises a central processing unit including a processor, the semiconductor memory is connected to at least one of the internal circuit and the processing circuit, the semiconductor memory is configured to store program code that controls the external device and the multi-voltage output power supply circuit, and the program code can be configured, when executed by the processor, to cause the multi-voltage output power supply circuit to be controlled so that a first power supply voltage is applied to the input / output bank circuit when communicating using the first communication circuit, and to control the multi-voltage output power supply circuit so that a second power supply voltage is applied to the input / output bank circuit when communicating using the second communication circuit.

[0192] According to the semiconductor integrated circuit relating to this aspect, the processing circuit comprises a processor and a semiconductor memory. The processor executes program code stored in the semiconductor memory to control external devices and a multi-voltage output power supply circuit.

[0193] The microcontroller device of the 13th side according to this embodiment comprises a microcontroller, an external device including a first external device and a second external device, and a DC-DC converter circuit configured to generate a first power supply voltage and a second power supply voltage supplied to the first external device and the second external device, respectively, wherein the microcontroller is an internal circuit that can communicate with a processing circuit, the internal circuit includes an interface circuit having a first interface circuit and a second interface circuit, and an input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, the first input / output circuit and the second input / output circuit are The internal circuit comprises an input / output bank circuit connected to the bank power line of the input / output bank circuit, the first interface circuit and the first input / output circuit constitute a first communication circuit configured to communicate with the first external device, and the second interface circuit and the second input / output circuit constitute a second communication circuit configured to communicate with the second external device, a first external electrode connected to the first communication circuit, a second external electrode connected to the second communication circuit, and a first power electrode configured to receive voltage from the DC-DC converter circuit and connected to the bank power line of the input / output bank circuit, wherein the internal circuit is configured not to activate the first communication circuit and the second communication circuit simultaneously.

[0194] In this aspect of the microcontroller device, the internal circuitry is operated in such a way that the activation of the first communication circuit and the activation of the second communication circuit are not performed simultaneously, thereby enabling switching of the voltage applied from the first power supply electrode to the input / output bank circuit. This switching allows for the exclusive application of multiple power supply voltages to the input / output bank circuit, enabling both switching and control of communication between a single input / output bank circuit and external devices with multiple operating voltages.

[0195] In the microcontroller device of the 14th aspect according to the 13th aspect of this embodiment, the internal circuit further comprises a control circuit that can communicate with the processing circuit, the control circuit is configured to determine the output voltage of the DC-DC converter, and the DC-DC converter can be configured to exclusively provide the first power supply voltage and the second power supply voltage.

[0196] According to the microcontroller device relating to this aspect, the control circuit enables the DC-DC converter circuit to exclusively provide the first power supply voltage and the second power supply voltage.

[0197] In the microcontroller device of the 15th aspect according to the 14th aspect of this embodiment, the internal circuit further comprises a detection circuit that can communicate with the processing circuit, the detection circuit is configured to detect the current value of the output voltage of the DC-DC converter and to generate a detection signal indicating the detection result, the detection circuit has an input configured to receive the output voltage and an output configured to provide the detection signal, and the control circuit may be configured to adjust the output voltage of the DC-DC converter in response to the detection signal.

[0198] According to the microcontroller device relating to this aspect, the detection circuit generates a detection signal indicating the output voltage value of the DC-DC converter circuit, and the control circuit is enabled to adjust the DC-DC converter circuit in response to the detection signal.

[0199] In the microcontroller device of the 16th side according to any one of the 13th to 15th sides of this embodiment, the input / output bank circuit is configured to convert the signal levels of the external device and the internal circuit from one of the internal voltage levels supplied to the internal circuit and the external voltage levels of the bank power lines of the input / output bank circuit to the other, the internal circuit further includes a digital input / output circuit connected to the input / output bank circuit, the digital input / output circuit may be configured to generate one or more control signals for controlling the external device in response to signals from the processing circuit.

[0200] According to the microcontroller device relating to this aspect, the digital input / output circuit enables the control of external devices via the input / output bank circuit.

[0201] A method for communicating between a microcontroller and an external device according to the 17th side of this embodiment includes: applying a first power supply voltage from a power supply circuit for the external device to the input / output bank circuit of the microcontroller; applying the first power supply voltage from the power supply circuit to a first external device of the external device; completing a series of communications with the first external device via the input / output bank circuit using a first interface circuit selected from the interface circuit of the microcontroller; applying a second power supply voltage different from the first power supply voltage from the power supply circuit to the input / output bank circuit when the first interface circuit is not selected; and applying the second power supply voltage from the power supply circuit to a second external device of the external device when the first interface circuit is not selected.

[0202] According to the method for communication between a microcontroller and an external device relating to this aspect, the method for communication between the microcontroller and the external device is provided by a power supply circuit, an external device, and a microcontroller.

[0203] A method for communicating with an external device using an interface circuit on the 18th side according to this embodiment includes: controlling a power supply circuit to generate a first power supply voltage; receiving the first power supply voltage from the power supply circuit into an input / output bank circuit; sending a first control signal to control the first external device to apply the first power supply voltage from the power supply circuit to the first external device; communicating with the first external device via the input / output bank circuit using a first interface circuit selected from the interface circuits; deselecting the first interface circuit; controlling the power supply circuit to generate a second power supply voltage different from the first power supply voltage; and receiving the second power supply voltage from the power supply circuit into the input / output bank circuit.

[0204] This method of communicating with an external device using an interface circuit related to this aspect provides a method for a microcontroller to control a power supply circuit and an external device to communicate with the microcontroller.

[0205] In a method of communicating with an external device using an interface circuit of the 19th side according to the 18th side of this embodiment, the first control signal can be provided to the first external device via the input / output bank circuit.

[0206] According to the method of communicating with an external device using the interface circuit related to this aspect, the external device can be controlled using the input / output bank circuit.

[0207] In a method of communicating with an external device using an interface circuit of the 20th side according to the 18th side of this embodiment, the first control signal can be provided to the first external device without using the input / output bank circuit.

[0208] By using an interface circuit related to this aspect to communicate with an external device, it is possible to control the external device without using an input / output bank circuit.

[0209] [Note 1] Circuit connection information, circuit connection data, or program code representing the configuration of a circuit using a hardware description language, wherein the circuit connection information, circuit connection data, or program code is configured in a reconfigurable semiconductor device, causing the reconfigurable semiconductor device or the circuit to function as an external interface circuit. The external interface circuit includes an internal circuit capable of communicating with a processing circuit, the internal circuit includes an interface circuit including a first interface circuit and a second interface circuit, and an input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, the first input / output circuit and the second input / output circuit are connected to the bank power line of the input / output bank circuit, the first interface circuit and the first input / output circuit constitute a first communication circuit configured to communicate with a first external device, and the second interface circuit and the second input / output circuit constitute a second communication circuit configured to communicate with a second external device different from the first external device, the bank power line is connected to a first power electrode configured to receive an external voltage different from the voltage of the internal power line of the internal circuit, each of the first input / output circuit and the second input / output circuit is configured to convert a signal level from one of the internal voltage level of the internal power line and the external voltage level of the bank power line to the other, and the internal circuit is configured not to activate the first communication circuit and the second communication circuit simultaneously.

[0210] [Note 2] A recording medium for storing circuit connection information, circuit connection data, circuit connection information code, circuit connection data code, or program code as described in Appendix 1.

[0211] Devices and recording media suitable for storing circuit information include all forms of non-volatile memory, media, and memory devices, and may include, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks or removable disks; magneto-optical disks; and read-only disks such as CD-ROM and DVD-ROM disks; and rewritable disks such as CD-R / W, DVD-R / W, and DVD-RAM.

[0212] [Note 3] A method for manufacturing an external interface circuit using a system comprising at least one processor comprises causing at least one of the processors to execute hardware description language code to manufacture the external interface circuit from a reconfigurable semiconductor device connected to the system in accordance with the hardware description language code. The hardware description language code identifies the external interface circuit as follows: The external interface circuit as thus identified is an internal circuit capable of communicating with a processing circuit, the internal circuit comprising an interface circuit including a first interface circuit and a second interface circuit, and an input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, the first input / output circuit and the second input / output circuit being connected to the bank power lines of the input / output bank circuit, the first interface circuit and the first input / output circuit constituting a first communication circuit, and the second interface circuit and the second input / output circuit constituting a second communication circuit, each of the first input / output circuit and the second input / output circuit being configured to convert a signal level from one of the internal voltage levels of the internal power lines of the internal circuit and the external voltage levels of the bank power lines of the input / output bank circuit to the other, and the internal circuit being configured not to activate the first communication circuit and the second communication circuit simultaneously.

[0213] In this method, the system comprises at least one memory, and the method may further comprise storing the hardware description language code in the memory.

[0214] [Note 4] An exemplary reconfigurable semiconductor device, such as an FPGA, comprises multiple reconfigurable memory elements, which can store circuit connection information codes that identify an external interface circuit, causing the FPGA to operate as such an external interface circuit. When the reconfigurable memory elements store the circuit connection information codes, they identify the interconnections between one or more circuit elements of the FPGA, enabling at least a portion of the FPGA to operate as an external interface circuit. The circuit connection information codes that identify the external interface circuit are stored in the multiple reconfigurable memory elements, causing at least a portion of the FPGA to operate as an external interface circuit.

[0215] This disclosure is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit of this disclosure. All such modifications are included in the technical concept of this disclosure. [Explanation of Symbols]

[0216] 11. Microcontroller device, 13. Microcontroller, 14b...First switch circuit, 14c...First device, 15...external device, 15b...first external device, 15c...Second external device, 16b...Second switch circuit, 16c...Second device, 17. Multi-voltage output power supply circuit, 17b...AC / CDC conversion circuit, 17c···DC-DC converter circuit, 18. Semiconductor memory, 19. Semiconductor integrated circuits, 20. Computers, 23. Input / Output Bank Circuit 23b...1st input / output circuit, 23c...Second input / output circuit, 23f...Third input / output circuit, 23g...4th input / output circuit, 24...bank power lines, 24b...High potential power line, 24c...Low potential power line, 25...electrode, 25b...first external electrode, 25c...Second external electrode, 25d...1st power supply electrode, 25f...Third external electrode, 25g...4th external electrode, 25h...Second power supply electrode, 25i... Output electrode, 25j...Third power supply electrode, 25k, 25m, 25n...input electrodes, 26b...First communication circuit, 26c...Second communication circuit, 27...internal circuit, 28... Processing circuit, 29. Interface circuit, 29b...First interface circuit, 29c...Second interface circuit, 31. Digital input / output circuit, 33. Control circuits, 35...Detection circuit, 35f...Input switching circuit, 35g...AD conversion circuit, 41...Central processing unit, 47, 47b, 47c, 47d, 47f, 47g... modules, 60 to 63...Communication initialization process, 70 to 74... Communication processing, 80 to 91... Communication switching process, BUS...bus line, LV... Level Shifter.

Claims

1. An internal circuit capable of communicating with a processing circuit, the internal circuit including an interface circuit configured to communicate with an external device, the interface circuit including a first interface circuit and a second interface circuit, An input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, wherein the first input / output circuit and the second input / output circuit are connected to the bank power lines of the input / output bank circuit, the first interface circuit and the first input / output circuit constitute a first communication circuit, and the second interface circuit and the second input / output circuit constitute a second communication circuit, A first power electrode is configured to receive an external voltage different from the voltage of the internal power line of the internal circuit and is connected to the bank power line of the input / output bank circuit, A first external electrode connected to the first communication circuit, A second external electrode connected to the second communication circuit, Equipped with, The internal circuit is configured such that the activation of the first communication circuit and the activation of the second communication circuit are not performed simultaneously. Semiconductor integrated circuit.

2. Each of the first input / output circuit and the second input / output circuit is configured to convert signal levels from one of the internal voltage levels of the internal power supply line and the external voltage levels of the bank power supply line of the input / output bank circuit to the other. A semiconductor integrated circuit as described in claim 1.

3. The external device includes a first external device capable of communicating with the first communication circuit, and a second external device capable of communicating with the second communication circuit. The aforementioned internal circuit further includes a digital input / output circuit, The digital input / output circuit includes a first digital input / output circuit and a second digital input / output circuit, and the first digital input / output circuit and the second digital input / output circuit are configured to control the first external device and the second external device, respectively. A semiconductor integrated circuit as described in claim 2.

4. The first power supply electrode is configured to receive the output voltage of a multi-voltage output power supply circuit located outside the semiconductor integrated circuit. The first external device is configured to operate at a first power supply voltage different from the power supply voltage of the internal circuit, and the second external device is configured to operate at a second power supply voltage different from the power supply voltage of the internal circuit. A semiconductor integrated circuit as described in claim 3.

5. The first external device includes a first switch circuit and a first device, The first device receives the output voltage of the multi-voltage output power supply circuit via the first switch circuit. The second external device includes a second switch circuit and a second device, The second device receives the output voltage of the multi-voltage output power supply circuit via the second switch circuit. The first interface circuit and the second interface circuit communicate with the first device and the second device, respectively, via the input / output bank circuit. The digital input / output circuit communicates with the first switch circuit and the second switch circuit. A semiconductor integrated circuit as described in claim 4.

6. A third external electrode connected to the first external device, A fourth external electrode connected to the second external device, Furthermore, The digital input / output circuit is connected to the third external electrode and the fourth external electrode via the input / output bank circuit. A semiconductor integrated circuit as described in claim 4.

7. The internal circuit further comprises a control circuit capable of communicating with the processing circuit. The control circuit is configured to determine the output voltage of the multi-voltage output power supply circuit. The control circuit controls the multi-voltage output power supply circuit to selectively generate at least the first power supply voltage and the second power supply voltage. A semiconductor integrated circuit as described in claim 4.

8. The internal circuit further comprises a detection circuit capable of communicating with the processing circuit, The detection circuit is configured to generate a detection signal indicating the value of the output voltage of the multi-voltage output power supply circuit. The internal circuit or the processing circuit identifies the operating state of the multi-voltage output power supply circuit based on the detection signal. A semiconductor integrated circuit as described in claim 7.

9. The control circuit is configured to adjust the output voltage of the multi-voltage output power supply circuit in response to the detection signal. A semiconductor integrated circuit as described in claim 8.

10. The internal circuit further comprises a detection circuit capable of communicating with the processing circuit, The detection circuit is configured to detect the value of the output voltage of the multi-voltage output power supply circuit. The internal circuit or the processing circuit identifies the operating state of the multi-voltage output power supply circuit based on the detection result of the detection circuit. A semiconductor integrated circuit as described in any one of claims 4 to 7.

11. The multi-voltage output power supply circuit includes an AC / DC converter circuit configured to convert AC power to DC power, and a DC / DC converter circuit configured to receive the DC power from the AC / DC converter circuit. The DC-DC conversion circuit is configured to generate the first power supply voltage and the second power supply voltage. A semiconductor integrated circuit as described in any one of claims 4 to 9.

12. Equipped with semiconductor memory, The processing circuit includes a central processing unit including a processor, The semiconductor memory is connected to at least one of the internal circuit and the processing circuit. The semiconductor memory is configured to store program code, When the aforementioned program code is executed by the aforementioned processor, The multi-voltage output power supply circuit is controlled so that the first power supply voltage is applied to the input / output bank circuit when using the first communication circuit, and The multi-voltage output power supply circuit is controlled so that the second power supply voltage is applied to the input / output bank circuit when using the second communication circuit. Configured to cause, A semiconductor integrated circuit as described in any one of claims 4 to 9.

13. Microcontroller and External devices including a first external device and a second external device, A DC-DC converter circuit configured to generate a first power supply voltage and a second power supply voltage supplied to the first external device and the second external device, respectively, Equipped with, The aforementioned microcontroller is An internal circuit capable of communicating with a processing circuit, wherein the internal circuit includes an interface circuit having a first interface circuit and a second interface circuit, An input / output bank circuit including a first input / output circuit connected to the first interface circuit and a second input / output circuit connected to the second interface circuit, wherein the first input / output circuit and the second input / output circuit are connected to the bank power lines of the input / output bank circuit, the first interface circuit and the first input / output circuit constitute a first communication circuit configured to communicate with the first external device, and the second interface circuit and the second input / output circuit constitute a second communication circuit configured to communicate with the second external device, A first external electrode connected to the first communication circuit, A second external electrode connected to the second communication circuit, A first power electrode configured to receive voltage from the DC-DC conversion circuit and connected to the bank power line of the input / output bank circuit, Equipped with, The internal circuit is configured such that the activation of the first communication circuit and the activation of the second communication circuit are not performed simultaneously. Microcontroller device.

14. The internal circuit further comprises a control circuit capable of communicating with the processing circuit. The control circuit is configured to determine the output voltage of the DC-DC conversion circuit. The DC-DC conversion circuit is configured to exclusively provide the first power supply voltage and the second power supply voltage. A microcontroller device as described in claim 13.

15. The internal circuit further comprises a detection circuit capable of communicating with the processing circuit, The detection circuit is configured to detect the output voltage of the DC-DC conversion circuit and generate a detection signal indicating the detection result. The detection circuit has an input configured to receive the output voltage and an output configured to provide the detection signal. The control circuit is configured to adjust the output voltage of the DC-DC converter circuit in response to the detection signal. A microcontroller device as described in claim 14.

16. The input / output bank circuit is configured to convert the signal levels of the external device and the internal circuit from one of the internal voltage levels supplied to the internal circuit and the external voltage levels of the bank power lines of the input / output bank circuit to the other. The internal circuit further includes a digital input / output circuit connected to the input / output bank circuit, The digital input / output circuit is configured to generate one or more control signals for controlling the external device in response to a signal from the processing circuit. A microcontroller device according to any one of claims 13 to 15.

17. A method for communicating between a microcontroller and an external device, The first power supply voltage is applied from the power supply circuit for the external device to the input / output bank circuit of the microcontroller, The first power supply voltage is applied to the first external device of the external device from the power supply circuit, The first interface circuit selected from the interface circuits of the microcontroller is used to complete a series of communications with the first external device via the input / output bank circuit, When the first interface circuit is not selected, a second power supply voltage different from the first power supply voltage is applied from the power supply circuit to the input / output bank circuit, When the first interface circuit is not selected, the second power supply voltage is applied from the power supply circuit to the second external device of the external device, A method that includes [a certain feature].

18. A method of communicating with an external device using an interface circuit, Controlling the power supply circuit to generate the first power supply voltage, The first power supply voltage is received from the power supply circuit to the input / output bank circuit, Sending a first control signal to control the first external device so that the first power supply voltage is applied to the first external device from the power supply circuit, To communicate with the first external device via the input / output bank circuit using the first interface circuit selected from the interface circuits, By deselecting the first interface circuit, Controlling the power supply circuit to generate a second power supply voltage different from the first power supply voltage, The power supply circuit receives the second power supply voltage from the power supply circuit to the input / output bank circuit, A method that includes [a certain feature].

19. The first control signal is provided to the first external device via the input / output bank circuit. The method described in claim 18.

20. The first control signal is provided to the first external device without using the input / output bank circuit. The method described in claim 19.

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