Multi-channel memory

Abstract

It provides memory that adjusts the number of memory channels and ranks as needed. [Solution] The memory 100 includes a first command address decoder that decodes a first chip selection signal and a first command address signal to generate a first address signal and a first control signal; a second command address decoder that, in multi-channel mode, decodes a second chip selection signal and a second command address signal to generate a second address signal and a second control signal, and in multi-rank mode, decodes a second chip selection signal and the first command address signal to generate a second address signal and a second control signal; a first memory core that includes a large number of memory cells and is controlled by the first address signal and the first control signal; and a second memory core that includes a large number of memory cells and is controlled by the second address signal and the second control signal.

Description

Technical Field

[0001] This patent document relates to memory.

Background Art

[0002] As the demand for large-capacity memory increases, memory systems are often configured with a multi-rank structure. In a multi-rank structure, a number of ranks are independently distinguished within one channel, which is a suitable method for increasing the capacity of a memory system without increasing the number of channels. Such a rank-based structure has the advantage of providing a large-capacity memory while maintaining manufacturing cost efficiency.

[0003] On the other hand, in order to improve the performance of a memory system, a method of increasing the number of channels is also widely used. By increasing the number of channels, the number of data paths that can operate in parallel increases, and the bandwidth can be widened. Therefore, in order to optimize the performance and capacity of a memory system, a balanced configuration of ranks and the number of channels is important. With an appropriate configuration, an optimal memory system design can be achieved according to a specific application field.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a technique for adjusting the number of channels and ranks of a memory according to requirements.

Means for Solving the Problems

[0005] A memory according to one embodiment of the present invention may include: a first command address decoder that decodes a first chip selection signal and a first command address signal to generate a first address signal and a first control signal; a second command address decoder that decodes a second chip selection signal and a second command address signal in multi-channel mode to generate a second address signal and a second control signal, and decodes the second chip selection signal and the first command address signal to generate a second address signal and a second control signal in multi-rank mode; a first memory core that includes a number of memory cells and is controlled by the first address signal and the first control signal; and a second memory core that includes a number of memory cells and is controlled by the second address signal and the second control signal.

[0006] A memory according to one embodiment of the present invention may include: a first command address decoder that decodes a first chip selection signal and a first command address signal to generate a first address signal and a first control signal; a second command address decoder that decodes a second chip selection signal and a second command address signal in multi-channel mode to generate a second address signal and a second control signal; a first memory core that includes a number of memory cells and is controlled by the first address signal and the first control signal; and a second memory core that includes a number of memory cells and is controlled by the second address signal and the second control signal in multi-channel mode and by the first address signal and the first control signal in single-rank mode.

[0007] A memory according to one embodiment of the present invention may include a first command address decoder for decoding a command address signal and a chip selection signal; a second command address decoder for decoding signals that are at least partially different from those of the first command address decoder; a first data transmission / reception circuit for transmitting and receiving data via a first data terminal; a second data transmission / reception circuit for transmitting and receiving data via a second data terminal; and a configuration mode setting circuit for controlling the activation / deactivation of the second command address decoder and the second data transmission / reception circuit according to a set mode. [Effects of the Invention]

[0008] According to embodiments of the present invention, the number of memory channels and ranks is adjustable. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram showing the configuration of memory 100 according to one embodiment of the present invention. [Figure 2] Figure 1 is a diagram illustrating one embodiment of the configuration mode setting circuit 140. [Figure 3] This figure shows the levels of the selection signals S1 to S4 and activation signals E1 to E5 generated by the signal generation unit 220 according to the set mode. [Figure 4] This figure shows the connection state when memory 100 in Figure 1 is set to multi-channel mode. [Figure 5] This figure shows the linkage state when memory 100 in Figure 1 is set to multi-rank mode. [Figure 6] This figure shows the linked state when memory 100 in Figure 1 is set to single rank mode. [Modes for carrying out the invention]

[0010] The following describes embodiments of the technical concept of the present invention with reference to the attached drawings.

[0011] Figure 1 is a diagram showing the configuration of a memory 100 according to one embodiment of the present invention. Figure 1 shows one memory die or chip.

[0012] Referring to Figure 1, the memory 100 includes a first clock receiving circuit 101_A, a second clock receiving circuit 101_B, a first chip selection receiving circuit 102_A, a second chip selection receiving circuit 102_B, a first command address signal receiving circuit 103_A, a second command address signal receiving circuit 103_B, a first command address decoder 110_A, a second command address decoder 110_B, a first memory core 120_A, a second memory core 120_B, a first data transmission / reception circuit 130_A, a second data transmission / reception circuit 130_B, configuration signal receivers 141 and 142, a configuration mode setting circuit 140, and selection circuits 151, 152, 153, and 154.

[0013] The first clock receiving circuit 101_A receives the first clock signal from the first clock terminal CLK_A, and the first chip selection signal receiving circuit 102_A receives the first chip selection signal from the first chip selection signal terminal CS_A. The first command address signal receiving circuit 103_A receives the first command address signal from the first command address terminal CAs_A. The first command address signal is multi-bit, and the first command address terminal CAs_A may be multiple.

[0014] The second clock receiving circuit 101_B receives the second clock signal from the second clock terminal CLK_B, and the second chip selection signal receiving circuit 102_B receives the second chip selection signal from the second chip selection signal terminal CS_B. The second command address signal receiving circuit 103_B receives the second command address signal from the second command address terminal CAs_B. The second command address signal is multi-bit, and the second command address terminal CAs_B may be multiple.

[0015] The first command address decoder 110_A operates in synchronization with the first clock received by the first clock receiving circuit 101_A, and decodes the first chip selection signal received by the first chip selection signal receiving circuit 102_A and the first command address signal received by the first command address receiving circuit 103_A to generate the first control signal CON_A. The first control signal CON_A may include the row address, column address, a signal to instruct active operation, a signal to instruct precharge operation, a signal to instruct refresh operation, a signal to instruct read operation, and a signal to instruct write operation, etc.

[0016] In response to the first selection signal S1, the selection circuit 151 selects and outputs either the first clock received by the first clock receiving circuit 101_A or the second clock received by the second clock receiving circuit 101_B. Then, in response to the second selection signal S2, the selection circuit 152 selects and outputs either the first command address signal received by the first command address receiving circuit 103_A or the second command address signal received by the second command address receiving circuit 103_B.

[0017] The second command address decoder 110_B operates in synchronization with the clock transmitted from the selection circuit 151 and decodes the second chip selection signal received by the second chip selection signal receiving circuit 102_B and the command address signal transmitted from the selection circuit 152 to generate the second control signal CON_B. The second control signal CON_B may include the row address, column address, a signal to instruct active operation, a signal to instruct precharge operation, a signal to instruct refresh operation, a signal to instruct read operation, and a signal to instruct ride operation, etc.

[0018] The selection circuit 153 selects and outputs either the first control signal CON_A or the second control signal CON_B in response to the third selection signal S3.

[0019] The memory cores 120_A and 120_B are locations in the memory 100 where data is stored. Each of the memory cores 120_A and 120_B can include a number of memory cells and a configuration for writing and reading data to / from the memory cells. The first memory core 120_A can be controlled by the first control signal CON_A, and the second memory core 120_B can be controlled by the control signal selected by the selection circuit 153.

[0020] The selection circuit 154 can connect either the first memory core 120_A or the second memory core 120_B to the first data transceiver circuit 130_A.

[0021] The first data transceiver circuit 130_A transmits and receives data of the memory core selected by the selection circuit 154 to / from the first data terminal DQs_A. And it can transmit and receive a data strobe signal for strobbing the data to / from the first data strobe terminal DQS_A. The first data transceiver circuit 130_A can perform a serial-to-parallel conversion operation during a write operation and a parallel-to-serial conversion operation during a read operation. For example, if the number of the first data terminals is 8, during the write operation, 128 (= 8 × 16) -bit data can be received via 8 first data terminals DQs_A with a burst length (BL) of 16, and the received data can be converted from serial to parallel at a ratio of 8:128 and transmitted to the memory core selected by the selection circuit 154. Also, during the read operation, 128 -bit data read from the memory core selected by the selection circuit 154 can be converted from parallel to serial at a ratio of 128:8 and output via 8 first data terminals DQs_A with a BL of 16.

[0022] The second data transceiver circuit 130_B transmits and receives data of the second memory core 120_B to and from the second data terminal DQs_B. And it can transmit and receive a data strobe signal for strobbing data to and from the second data strobe terminal DQS_B. The second data transceiver circuit 130_A can convert the data received from the second data terminal DQs_B into serial-parallel form during a write operation and transmit it to the second memory core 120_B, and can convert the data read from the second memory core 120_B into parallel-serial form and transmit it to the second data terminal DQs_B during a read operation.

[0023] The configuration signal receivers 141 and 142 receive configuration signals of the configuration terminals ORG1 and ORG2. The configuration signal can be a signal for setting the number of channels and the number of ranks of the memory 100. The configuration mode setting circuit 140 can set the number of channels and the number of ranks of the memory 100 by using the configuration signals received by the configuration signal receivers 141 and 142. The configuration mode setting circuit 140 generates selection signals S1 to S4 and activation signals E1 to E5. Depending on the levels of the selection signals S1 to S4 and the activation signals E1 to E5, the number of channels and the number of ranks of the memory 100 may be changed. The activation signals E1 to E5 are signals for deactivating unused configurations according to the mode to reduce power consumption. The first activation signal E1 controls the activation / deactivation of the second clock receiving circuit 101_B, the second activation signal E2 controls the activation / deactivation of the second chip selection signal receiving circuit 102_B, the third activation signal E3 controls the activation / deactivation of the second command address signal receiving circuit 103_B, the fourth activation signal E4 controls the activation / deactivation of the second command address decoder 110_B, and the fifth activation signal E5 can control the activation / deactivation of the second data transceiver circuit 130_B. Since it is necessary to confirm not only the mode setting but also the selected rank for the generation of the selection signal S4, the configuration mode setting circuit 140 can use the chip selection signals CS_A_SIG and CS_B_SIG received by the chip selection signal receiving circuits 102_A and 102_B.

[0024] FIG. 2 is a configuration diagram of an embodiment of the configuration mode setting circuit 140 in FIG. 1.

[0025] Referring to Figure 2, the configuration mode setting circuit 140 includes a mode setting unit 210 and a signal generation unit 220.

[0026] The mode setting unit 210 decodes the configuration signals ORG1_T, ORG1_B, ORG2_T, and ORG2_B received by the configuration signal receivers 141 and 142, and generates mode signals 2CH_MODE, 2RK_MODE, and 1RK_MODE. The first configuration signal ORG1_T is the signal received by the configuration signal receiver 141, and the inverted first configuration signal ORG1_B is the signal obtained by inverting the first configuration signal ORG1_T. The second configuration signal ORG2_T is the signal received by the configuration signal receiver 142, and the inverted second configuration signal ORG2_B is the signal obtained by inverting the second configuration signal ORG2_T. The mode setting unit 210 includes NAND gates 211 to 213 and inverters 214 to 216. When the first configuration signal ORG1_T and the second configuration signal ORG2_T are (1, 1), the multi-channel mode signal 2CH_MODE is activated as "1". When they are (0, 1), the multi-rank mode signal 2RK_CODE is activated as "1". When they are (1, 0), the single-rank mode signal 1RK_MOD is activated as "1". Here, we have illustrated that the mode is set according to the levels of the signals ORG1_T and ORG2_T received from the configuration signal terminals ORG1 and ORG2, but it is also natural that the mode may be set based on settings such as the mode register in memory 100.

[0027] The signal generation unit 220 generates selection signals S1 to S4 and activation signals E1 to E5 according to the set mode. Figure 3 shows the levels of the selection signals S1 to S4 and activation signals E1 to E5 generated by the signal generation unit 220 according to the set mode. When the multi-channel mode signal 2CH_MODE is activated, signals S1, S2, S3, S4, E1, E2, E3, E4, and E5 may be generated as (0, 0, 0, 0, 1, 1, 1, 1, 1). When the multi-rank mode signal 2RK_MODE is activated, S1, S2, S3, E1, E2, E3, E4, and E5 are generated as (1, 1, 0, 0, 1, 0, 1, 0), and the selection signal S4 is generated as "1" or "0" depending on the rank selection, but may be generated as "0" if the lung corresponding to the first chip selection signal CS_A_SIG is selected, or as "1" if the rank corresponding to the second chip selection signal CS_B_SIG is selected.

[0028] The configuration of the memory 100 changes according to the levels of signals S1, S2, S3, S4, E1, E2, E3, E4, and E5 generated by the signal generation unit 220, as will be explained in detail in Figures 4 to 6.

[0029] Figure 4 shows the linked state when the memory 100 in Figure 1 is set to multi-channel mode.Here, the configuration signal receivers 141 and 142, the configuration mode setting circuit 140, and the selection circuits 151, 152, 153, and 154 are not shown, and the state in which the internal configuration of the memory 100 is linked by the selection circuits 151, 152, 153, and 154 is shown.

[0030] Referring to Figure 4, in multi-channel mode, the first command address decoder 110_A generates a first control signal CON_A using signals received by the receiving circuits 101_A, 102_A, and 103_A, and the first memory core 120_A is controlled by the first control signal CON_A. The data of the first memory core 120_A is transmitted and received by the first data transmission / reception circuit 130_A.

[0031] Furthermore, the second command address decoder 110_B generates a second control signal CON_B using signals received by the receiving circuits 101_B, 102_B, and 103_B, and the second memory core 120_B is controlled by the second control signal CON_B. The data of the second memory core 120_B is transmitted and received by the second data transmission / reception circuit 130_B.

[0032] In other words, in multi-channel mode, the configuration labeled A operates as one channel, and the configuration labeled B operates as another channel. That is, one memory 100 can operate as two channels.

[0033] Figure 5 shows the linked state when the memory 100 in Figure 1 is set to multi-rank mode.Here, the configuration signal receivers 141 and 142, the configuration mode setting circuit 140, and the selection circuits 151, 152, and 153 are not shown, and the state in which the internal configuration of the memory 100 is linked by the selection circuits 151, 152, and 153 is shown.

[0034] Referring to Figure 5, it can be seen that the second clock receiving circuit 101_B, the second command address signal receiving circuit 103_B, and the second data transmission / reception circuit 130_B, which are deactivated in multi-rank mode, are shown in dim light.

[0035] In multi-rank mode, the first command address decoder 110_A generates a first control signal CON_A using signals received by the first clock receiving circuit 101_A, the first chip selection signal receiving circuit 102_A, and the first command address signal receiving circuit 103_A. The second command address decoder 110_B generates a second control signal CON_B using signals received by the first clock receiving circuit 101_A, the second chip selection signal receiving circuit 102_B, and the first command address receiving circuit 103_A. That is, the first command address decoder 110_A and the second command address decoder 110_B receive the same command address signal as input, and only the chip selection signal for distinguishing ranks differs from each other as input.

[0036] The first memory core 120_A is controlled by the first control signal CON_A, and the second memory core 120_B is controlled by the second control signal CON_B. Data from both the first memory core 120_A and the second memory core 120_B are transmitted and received by the first data transmission / reception circuit 130_A, but the first data transmission / reception circuit 130_A transmits and receives data of the selected rank. That is, when the first memory core 120_A, which is the rank corresponding to the first chip selection signal CS_A_SIG, is selected, the first data transmission / reception circuit 130_A transmits and receives data from the first memory core 120_A, and when the second memory core, which is the rank corresponding to the second chip selection signal CS_B_SIG, is selected, the first data transmission / reception circuit 130_A transmits and receives data from the second memory core 120_B.

[0037] In multi-rank mode, the first memory core 120_A and the second memory core 120_B belong to the same channel, but operate as different ranks within the same channel. In other words, one memory 100 can operate as two ranks.

[0038] Figure 6 shows the linked state when the memory 100 in Figure 1 is set to single rank mode.Here, the configuration signal receivers 141 and 142, the configuration mode setting circuit 140, and the selection circuits 151, 152, 153, and 154 are not shown, and the state in which the internal configuration of the memory 100 is linked by the selection circuits 151, 152, 153, and 154 is shown.

[0039] Referring to Figure 6, it can be seen that the second clock receiver circuit 101_B, the second chip selection signal receiver circuit 102_B, the second command address receiver circuit 103_B, and the second command address decoder 110_B, which are deactivated in single-rank mode, are shown in dim light.

[0040] In single-rank mode, the first command address decoder 110_A generates a first control signal CON_A using signals received by the receiving circuits 101_A, 102_A, and 103_A. The first memory core 120_A and the second memory core 120_B are then controlled by the first control signal CON_A. In other words, the first memory core 120_A and the second memory core 120_B perform the same operation.

[0041] Data from the first memory core 120_A is transmitted and received by the first data transmission / reception circuit 130_A, and data from the second memory core 120_B is transmitted and received by the second data transmission / reception circuit 130_B. Since the first memory core 120_A and the second memory core 120_B perform write operations or read operations simultaneously, the first data transmission / reception circuit 130_A and the second data transmission / reception circuit 130_B receive data or transmit data simultaneously. In other words, the number of bits of data input / output for each write and read operation in single-rank mode may be twice the number of bits of data input / output for each write and read operation in multi-channel mode and multi-rank mode.

[0042] In single-rank mode, the first memory core 120_A and the second memory core 120_B operate as the same rank. That is, one memory 100 can operate as one rank.

[0043] The technical concept of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it should be noted that these embodiments are for illustrative purposes only and are not intended to limit it. Furthermore, experts in the technical field of the present invention will understand that various embodiments are possible within the scope of the technical concept of the present invention. [Explanation of Symbols]

[0044] 100: Memory 101_A, 101_B: Clock receiving circuit 102_A, 102_B: Chip Select Receiver Circuit 103_A, 103_B: Command address signal receiving circuit 110_A, 110_B: Command address decoder 120_A, 120_B: Memory cores 130_A, 130_B: Data transmission and reception circuits 141, 142: Component signal receiver 140: Configuration mode setting circuit 151, 152, 153, 154: Selection circuits

Claims

1. A first command address decoder that decodes a first chip selection signal and a first command address signal to generate a first address signal and a first control signal, A second command address decoder that decodes a second chip selection signal and a second command address signal in multi-channel mode to generate a second address signal and a second control signal, and decodes the second chip selection signal and the first command address signal to generate a second address signal and a second control signal in multi-rank mode, A first memory core including a large number of memory cells and controlled by the first address signal and the first control signal, A second memory core, which includes a large number of memory cells and is controlled by the second address signal and the second control signal, Memory containing this.

2. A first data transmission and reception circuit that transmits data read from the first memory core to the first data terminal in the multi-channel mode and receives data written to the first memory core from the first data terminal, and transmits data read from a selected memory core among the first and second memory cores to the first data terminal in the multi-rank mode and receives data written to a selected memory core among the first and second memory cores from the first data terminal, In the multi-channel mode, a second data transmission / reception circuit transmits data read from the second memory core to the second data terminal and receives data written to the second memory core from the second data terminal. The memory according to claim 1, further comprising:

3. In the multi-rank mode, the second data transmission / reception circuit is deactivated. The memory according to claim 2.

4. The second memory core is controlled by the first address signal and the first control signal instead of the second address signal and the second control signal in single rank mode. The memory according to claim 2.

5. The first data transmission and reception circuit transmits data read from the first memory core in the single-rank mode to the first data terminal and receives data written to the first memory core from the first data terminal. The second data transmission / reception circuit transmits data read from the second memory core to the second data terminal in the single-rank mode and receives data written to the second memory core from the second data terminal. The memory according to claim 4.

6. The second command address decoder is deactivated in the single rank mode. The memory according to claim 5.

7. The first data transmission / reception circuit transmits and receives a first data strobe signal to the first data strobe terminal when transmitting or receiving data at the first data terminal. The second data transmission / reception circuit transmits and receives a second data strobe signal to the second data strobe terminal when transmitting or receiving data at the second data terminal. The memory according to claim 2.

8. First component terminal and, The second configuration terminal and A configuration mode setting circuit for setting the multi-channel mode, the multi-rank mode, and the single-rank mode according to the voltage levels of the first and second configuration terminals, The memory according to claim 4, further comprising:

9. A first command address decoder that decodes a first chip selection signal and a first command address signal to generate a first address signal and a first control signal, A second command address decoder that decodes the second chip selection signal and the second command address signal in multi-channel mode to generate a second address signal and a second control signal, A first memory core including a large number of memory cells and controlled by the first address signal and the first control signal, A second memory core, which includes a large number of memory cells, is controlled by the second address signal and the second control signal in the multi-channel mode, and is controlled by the first address signal and the first control signal in the single-rank mode. Memory containing this.

10. A first data transmission and reception circuit that transmits data read from the first memory core to the first data terminal and receives data written to the first memory core from the first data terminal, A second data transmission and reception circuit transmits data read from the second memory core to the second data terminal and receives data written to the second memory core from the second data terminal. The memory according to claim 9, further comprising:

11. The second command address decoder is deactivated in the single rank mode. The memory according to claim 10.

12. The first data transmission / reception circuit transmits and receives a first data strobe signal to the first data strobe terminal when transmitting or receiving data at the first data terminal. The second data transmission / reception circuit transmits and receives a second data strobe signal to the second data strobe terminal when transmitting or receiving data at the second data terminal. The memory according to claim 10.

13. One or more terminals, A configuration mode setting circuit for setting the multi-channel mode and the single-rank mode according to the voltage level of one or more of the configuration terminals. The memory according to claim 10, further comprising:

14. A first command address decoder that decodes the command address signal and the chip selection signal, A second command address decoder that decodes signals that are at least partially different from the first command address decoder, A first data transmission / reception circuit that transmits and receives data via a first data terminal, A second data transmission / reception circuit that transmits and receives data via a second data terminal, A configuration mode setting circuit that controls the activation / deactivation of the second command address decoder and the second data transmission / reception circuit according to the set mode, Memory containing this.

15. The first memory core and the second memory core each contain a large number of memory cells. The memory according to claim 14, further comprising:

16. When setting up multi-channel mode, The configuration mode setting circuit activates the second command address decoder and the second data transmission / reception circuit. The first memory core is controlled by the first command address decoder and transmits and receives data via the first data transmission / reception circuit. The second memory core is controlled by the second command address decoder and transmits and receives data via the second data transmission / reception circuit. The memory according to claim 15.

17. When setting up multi-rank mode, The configuration mode setting circuit activates the second command address decoder and deactivates the second data transmission / reception circuit. The first memory core is controlled by the first command address decoder and transmits and receives data via the first data transmission / reception circuit. The second memory core is controlled by the second command address decoder and transmits and receives data via the first data transmission / reception circuit. The memory according to claim 15.

18. When setting to single rank mode, The configuration mode setting circuit deactivates the second command address decoder and the second data transmission / reception circuit. The first memory core is controlled by the first command address decoder and transmits and receives data via the first data transmission / reception circuit. The second memory core is controlled by the first command address decoder and transmits and receives data via the first data transmission / reception circuit. The memory according to claim 15.

19. It further includes one or more component terminals, The configuration mode setting circuit sets the mode according to the voltage level of one or more configuration terminals. The memory according to claim 14.

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