Electronic module and method for manufacturing the same
The glass substrate-based laser trimming method for electronic modules addresses the issues of damage and high costs in adjusting IPDs by enabling precise adjustments without decapping, ensuring efficient and cost-effective production.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ULTRABAND TECH INC
- Filing Date
- 2026-01-14
- Publication Date
- 2026-07-29
AI Technical Summary
Existing methods for adjusting integrated passive devices (IPDs) in electronic modules, such as RF modules, require redesigning and decapping, which can damage internal elements and result in low yield and high costs.
A novel electronic module design using a glass substrate with laser trimming to adjust IPDs, eliminating the need for decapping and redesign, by incorporating laser-trimmed inductance, capacitance, and resistance units.
This approach avoids damage to internal elements, prevents yield loss, and reduces costs by directly modifying IPD values without decapping, ensuring precise adjustments and efficient production.
Smart Images
Figure 2026122919000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to modules and methods, and particularly to electronic modules and methods for manufacturing the same.
Background Art
[0002] For example, when existing electronic modules applied to radio frequency (RF) modules, amplifier modules, or sensor modules, etc. need to improve the performance of the entire module by adjusting the characteristics (e.g., resistance value, capacitance value, or inductance value) of integrated passive devices (IPDs) in the electronic module after encapsulation integration to ensure that the performance in the circuit meets the design requirements, it is necessary to redesign, manufacture, and encapsulate a completely new electronic module based on the circuit characteristics required for the product manufactured by applying the electronic module, or first remove the top layer of the existing electronic module package (e.g., by methods such as decap or decoupage) to expose the internal integrated passive devices, and then perform adjustments on the integrated passive devices (e.g., resistors, capacitors, or inductors), and after the adjustment, reseal the top layer of the electronic module.
Summary of the Invention
[0003] Although the integrated passive devices in the electronic module can be adjusted by the above methods, in the decap or decoupage process, it is easy to damage the internal elements, chips, or wirings, and the yield of the resealing process is low. Furthermore, all of the above adjustment methods result in high costs.
[0004] Therefore, when adjusting the integrated passive devices in the electronic module, it is extremely important to realize a design that can avoid damage to the internal elements, chips, or wirings caused by decap or decoupage, prevent the reduction of the yield due to resealing, and reduce the required costs.
[0005] In view of this, the present invention provides a novel electronic module and a method for manufacturing an electronic module that can effectively solve the above-mentioned problems.
[0006] The present invention provides an electronic module comprising a glass substrate having an upper surface and a lower surface, and an integrated passive element layer disposed on at least a portion of the lower surface of the glass substrate and including at least one integrated passive element, wherein the total inductance value, total capacitance value, or total resistance value of the integrated passive element is changed by laser trimming that penetrates from the upper surface of the glass substrate to the integrated passive element.
[0007] In some embodiments, the integrated passive elements of the electronic module include an inductance unit having a preset inductance laser cutting section that changes the total inductance value of the integrated passive elements by being laser-trimmed.
[0008] In some embodiments, the integrated passive elements of the electronic module include a capacitor unit having a preset capacitance cutting section that changes the total capacitance value of the integrated passive elements by being laser-trimmed.
[0009] In some embodiments, the integrated passive elements of the electronic module include a resistor unit having a preset resistance cutting section that changes the total resistance value of the integrated passive elements by being laser-trimmed.
[0010] In some embodiments, the electronic module further includes a bypass capacitor layer disposed on the upper surface of the glass substrate, and an opening corresponding to the position of the integrated passive element is formed in a portion of the upper surface of the glass substrate.
[0011] In some embodiments, the electronic module further includes a sealing mold layer disposed on the upper surface of the glass substrate, wherein an opening is defined by the sealing mold layer and the upper surface of the glass substrate, and the position of the opening corresponds to the position of the integrated passive element.
[0012] In some embodiments, the electronic module further includes: an active-passive element redistribution layer disposed below the glass substrate and the integrated passive element layer and coupled to the integrated passive element layer; a ceramic substrate disposed below the active-passive element redistribution layer and having a metal heat dissipation layer, which together with the metal heat dissipation layer defines a cavity; and a semiconductor chip disposed within the cavity and located above the metal heat dissipation layer, which is electrically connected to the integrated passive element via an electrically conductive interconnect configuration.
[0013] In some embodiments, the electronic module further includes blind via holes formed within the glass substrate, the integrated passive element layer, and the active / passive element redistribution layer, penetrating from the upper surface of the glass substrate to the semiconductor chip, and used for heat dissipation.
[0014] In some embodiments, the active and passive element redistribution layers of the electronic module are formed based on a thin-film transistor process and a panel-level packaging process.
[0015] In some embodiments, the semiconductor chip of the electronic module is a radio frequency circuit.
[0016] The present invention provides a method for manufacturing an electronic module, comprising the steps of: (A) forming an integrated passive element layer on at least a portion of the lower surface of a glass substrate, wherein the integrated passive element layer includes at least one integrated passive element, and the total inductance, total capacitance, or total resistance of the integrated passive element is changed by laser trimming that penetrates from the upper surface of the glass substrate to the integrated passive element; (B) forming an active / passive element redistribution layer below the integrated passive element layer and the glass substrate, and coupling the active / passive element redistribution layer with the integrated passive element layer; (C) forming a metal heat dissipation layer on a ceramic substrate, and defining a cavity with the metal heat dissipation layer and the ceramic substrate; (D) placing a semiconductor chip in the cavity and positioning it above the metal heat dissipation layer; and (E) bonding the active / passive element redistribution layer to the ceramic substrate and electrically connecting the semiconductor chip to the integrated passive element via an electrically conductive interconnect configuration.
[0017] In some embodiments, the integrated passive element of the manufacturing method includes an inductance unit having a preset inductance laser cutting section that is laser-trimmed to change the total inductance value of the integrated passive element.
[0018] In some embodiments, the integrated passive element of the manufacturing method includes a capacitor unit having a preset capacitance cut-off section that is laser-trimmed to change the total capacitance value of the integrated passive element.
[0019] In some embodiments, the integrated passive element of the manufacturing method includes a resistor unit having a preset resistance cut section that is laser-trimmed to change the total resistance of the integrated passive element.
[0020] In some embodiments, the manufacturing method further includes, after step (E), a step (F) of installing a bypass capacitor layer on the upper surface of the glass substrate, wherein an opening corresponding to the integrated passive element is formed in a portion of the upper surface of the glass substrate.
[0021] In some embodiments, after step (E) of the manufacturing method, the further step (F) includes placing a sealing mold layer on the upper surface of the glass substrate, wherein the sealing mold layer and a portion of the upper surface of the glass substrate define an opening corresponding to the integrated passive element.
[0022] In some embodiments, the manufacturing method further includes, between step (B) and step (C), (F) forming blind via holes in the glass substrate, the integrated passive element layer, and the active / passive element redistribution layer, penetrating from the upper surface of the glass substrate to the semiconductor chip.
[0023] In some embodiments, the active and passive element redistribution layers of the manufacturing method include a thin-film transistor configuration and an interconnection / encapsulation configuration, respectively, formed based on a thin-film transistor process and a panel-level packaging process.
[0024] As a result, the effect of the present invention lies in the fact that by combining the design of the glass substrate with the laser trimming method, it is possible to change the total inductance value, total capacitance value, or total resistance value of the integrated passive elements. Therefore, with the present invention, there is no need to redesign, manufacture, or encapsulate an entirely new electronic module, nor is there a need to remove the top layer of an existing electronic module package first, adjust the internal integrated passive elements, and then reencapsulate it. Thus, according to the present invention, damage to internal elements, chips, or wiring due to decapping or decaplage can be avoided, yield reduction due to reencapsulation can be prevented, and necessary costs can be reduced. [Brief explanation of the drawing]
[0025] [Figure 1] This is a schematic diagram illustrating an embodiment of the electronic module according to the present invention. [Figure 2] This is a schematic diagram illustrating the configuration of an integrated passive element of an electronic module according to the said embodiment, including an inductance unit. [Figure 3] It is a schematic diagram for explaining an equivalent circuit of the inductance unit according to the embodiment. [Figure 4] It is a schematic configuration diagram for explaining the inductance unit according to the embodiment after laser trimming. [Figure 5] It is a schematic diagram for explaining an equivalent circuit of the inductance unit according to the embodiment after laser trimming. [Figure 6] It is a schematic configuration diagram for explaining that the integrated passive element of the electronic module according to the embodiment includes a resistance unit. <0OO0094> [Figure 7] It is a schematic diagram for explaining an equivalent circuit of the resistance unit according to the embodiment. [Figure 8A] It is a schematic configuration diagram for explaining that the integrated passive element of the electronic module according to the embodiment includes a capacitor unit. [Figure 8B] It is a schematic diagram for explaining an equivalent circuit of the capacitor unit according to the embodiment. [Figure 9] It is a schematic configuration diagram for explaining another embodiment of the present invention. [Figure 10] It is a schematic configuration diagram for explaining still another embodiment of the present invention. [Figure 11] It is a schematic configuration diagram for explaining an embodiment based on the electronic module of FIG. 1. [Figure 12] It is a flowchart for explaining a manufacturing method of an electronic module according to the present invention.
Embodiments for Carrying Out the Invention
[0026] To fully understand the object, features, and effects of the present invention, the present invention will be described in detail as follows through the following specific embodiments in conjunction with the accompanying drawings. It should be noted that components and operating principles that are similar or identical in the drawings are denoted by the same reference numerals.
[0027] Please refer to Figure 1. Figure 1 is a schematic diagram illustrating an embodiment of the electronic module 1 according to the present invention. The electronic module 1 is formed by encapsulation and integration. The electronic module 1 includes a glass substrate 11, an integrated passive element layer 12, an active / passive element redistribution layer (RDL) 13, a ceramic substrate 14, three semiconductor chips 15, 16, 17, and two input / output ports 19, 20 for input / output signals. Both the left and right sides between the glass substrate 11 and the active / passive element redistribution layer 13 are sealed with an encapsulant 18 (e.g., plastic, ceramic, metal, or glass). In this embodiment, the number of semiconductor chips is, for example, three, but the present invention is not limited thereto. In other embodiments, the number of semiconductor chips may be one.
[0028] The glass substrate 11 includes an upper surface 111 and a lower surface 112. The glass substrate 11 has optical transparency to the laser wavelength, and the laser wavelength can pass through the glass substrate 11 to perform laser trimming on the integrated passive element layer 12, such as laser cutting of resistors, inductors and / or capacitors.
[0029] The integrated passive device layer 12 is installed on at least a portion of the lower surface 112 of the glass substrate 11. The integrated passive device layer 12 includes at least one integrated passive device (IPD). In this embodiment, the integrated passive device layer 12 includes 10 integrated passive devices 120 to 129, but the present invention is not limited thereto. Integrated passive devices are circuits formed by resistors, capacitors, inductors, or combinations thereof, and are commonly used for filtering, matching, tuning, or decoupling. The total inductance, total capacitance, or total resistance of each of the integrated passive devices 120 to 129 is changed by laser trimming (not shown) that penetrates from the upper surface 111 of the glass substrate 11 to the corresponding integrated passive device. The laser is a laser light source having a laser wavelength that can penetrate the glass substrate 11, and its types include, for example, ultraviolet (355 nm), green light (532 nm), infrared (1064 nm), optical fiber (1064 nm), or ultrashort pulse (200-1000 nm). The laser is used to adjust the parameters of integrated passive elements such as resistors, capacitors, or inductors by precisely removing material through laser trimming. Details are described below.
[0030] The active / passive element redistribution layer 13 is located beneath the glass substrate 11 and the integrated passive element layer 12, and is bonded to the integrated passive element layer 12. The active / passive element redistribution layer 13 includes a thin-film transistor configuration (not shown) and an interconnection / sealing configuration (not shown), which are formed based on a thin-film transistor (TFT) process and a panel-level packaging (PLP) process, respectively. In other words, the active / passive element redistribution layer 13 is formed based on a TFT process and a PLP process. The TFT process and PLP process are well-known to those with ordinary skill in this art, so for the sake of simplicity, a detailed explanation is omitted here.
[0031] The ceramic substrate 14 is positioned below the active / passive element redistribution layer 13 and has a metal heat dissipation layer 141. The material of the metal heat dissipation layer 141 is, for example, copper (Cu) or copper-tungsten alloy (CuW). Two cavities 142 are defined by the metal heat dissipation layer 141 and the ceramic substrate 14, but are not limited to this. In other embodiments, only one cavity may be defined by the metal heat dissipation layer 141 and the ceramic substrate 14.
[0032] The semiconductor chips 15, 16, and 17 are each placed in their corresponding cavities 142 and positioned above the metal heat dissipation layer 141, and are electrically connected to their corresponding integrated passive elements (e.g., as shown in reference numerals 121, 122, 126, and 127) via electrically conductive interconnect configurations. These electrically conductive interconnect configurations include, for example, electrically conductive vias (or metal wiring) and solder 10. The semiconductor chips 15, 16, and 17 are bonded to the metal heat dissipation layer 141 by silver paste 140, ensuring good thermal and electrical conductivity, and allowing thermal energy generated by the semiconductor chips 15, 16, and 17 to be rapidly conducted to the metal heat dissipation layer 141. Each of the semiconductor chips 15, 16, and 17 is a radio frequency circuit, such as, but not limited to, a power amplifier.
[0033] In this embodiment, the detailed circuit configurations and laser trimming methods of the integrated passive elements 120-123 and 125-129 are similar to those of integrated passive element 124. To simplify the explanation, redundant or similar explanations will be avoided, and below, only the internal circuit configuration and laser trimming of integrated passive element 124 will be described as an example, but the embodiment is not limited to this.
[0034] Please also refer to Figures 2 and 3. Figure 2 is a schematic diagram illustrating the configuration in which the integrated passive element 124 of the electronic module 1 according to this embodiment includes an inductance unit LU. Figure 3 is a schematic diagram illustrating the equivalent circuit of the inductance unit LU according to this embodiment. The inductance unit LU includes a main coil LP and a sub-coil LS. The main coil LP includes coils LP1, LP2, LP3, and LP4, with coils LP2 and LP4 connected in parallel. The sub-coil LS includes coils LS1, LS2, LS3, and LS4, with coils LS2 and LS4 connected in parallel. The total inductance value of the main coil LP is the sum of the inductance value of coil LP1, the parallel inductance value of coils LP2 and LP4, and the inductance value of coil LP3 (for example, Lp1 + (Lp2 / / Lp4) + Lp3 = 0.20 nH, where Lp1 to Lp4 are the inductance values of coils LP1 to LP4, respectively). The total inductance value of the sub-coil LS is the sum of the inductance value of coil LS1, the parallel inductance value of coils LS2 and LS4, and the inductance value of coil LS3 (for example, Ls1 + (Ls2 / / Ls4) + Ls3 = 0.28 nH, where Ls1 to Ls4 are the inductance values of coils LS1 to LS4, respectively). Existing inductance units have the characteristic that, once formed, it is impossible or difficult to adjust the inductance value. Therefore, in actual circuit design, in order to avoid the problem of frequency shift occurring due to the difference between the inductance value and the desired inductance value during the manufacturing process, existing technology employs a method of improving the frequency shift by switching the inductance value using a transistor as a switch. However, this method leads to an increase in the layout area of the electronic module. Therefore, in the present invention, instead of the existing method of switching the inductance value using a transistor as a switch, the inductance value of the integrated passive element (as shown by reference numeral 124 in Figures 1 and 2) is changed by combining the design of the glass substrate 11 and a laser trimming method, thereby significantly reducing the layout area of the electronic module.In detail, in this embodiment, the main coil LP has a preset inductance laser cutting section C1, and the sub-coil LS has a preset inductance laser cutting section C2, but is not limited to this. When the preset inductance laser cutting sections C1 and C2 are laser trimmed (for example, as shown in the laser cutting LC1 and LC2 in Figures 2 and 3), the total inductance values of the input and output of the integrated passive element 124 change.
[0035] For example, please refer to Figures 4 and 5. Figure 4 is a schematic diagram illustrating the configuration after the preset inductance laser cutting sections C1 and C2 of the inductance unit LU according to the embodiment have been laser-trimmed (in Figure 4, the laser-trimmed inductance unit is denoted by the symbol LU'). Figure 5 is a schematic diagram illustrating the equivalent circuit after the preset inductance laser cutting sections C1 and C2 of the inductance unit LU according to the embodiment have been laser-trimmed (in Figure 5, the laser-trimmed inductance unit is denoted by the symbol LU'). After laser trimming, the main coil LP includes coils LP1, LP2, and LP3 in series, and the sub-coil LS includes coils LS1, LS2, and LS3 in series. The total inductance value of the main coil LP is the sum of the inductance values of coils LP1, LP2, and LP3 (for example, Lp1 + Lp2 + Lp3 = 0.50 nH), and the total inductance value of the sub-coil LS is the sum of the inductance values of coils LS1, LS2, and LS3 (for example, Ls1 + Ls2 + Ls3 = 0.67 nH). As a result, the total inductance values of both the input and output of the integrated passive element 124 increase, and in this invention, it is no longer necessary to switch inductance values by using a transistor as a switch, which significantly reduces the layout area of the electronic module.
[0036] Please refer to Figures 6 and 7. Figure 6 is a schematic diagram illustrating the configuration in which the integrated passive element 124 of the electronic module 1 according to this embodiment includes a resistor unit RU. Figure 7 is a schematic diagram illustrating the equivalent circuit of the resistor unit RU according to this embodiment. The resistor unit RU has a vertical configuration, but is not limited thereto. In other embodiments, the resistor unit RU may have a horizontal configuration. The resistor unit RU realizes a parallel configuration of resistors (for example, as shown by the labels R1, R2, and R3 in Figure 7) using three metal layers M1, M2, and M3 and vias Via1 and Via2, but is not limited thereto. The resistance values of resistors R1, R2, and R3 are determined by the metal layers M1, M2, and M3 in Figure 6, respectively. In existing circuit implementations, the resistance value is mostly varied by adding a transistor as a changeover switch. However, this method has the disadvantage of requiring a relatively large layout area for the electronic module and an additional bias control circuit. Therefore, the present invention, instead of the existing method of adjusting the resistance value by using a transistor as a changeover switch, changes the resistance value of the integrated passive element by combining the design of the glass substrate 11 and a laser trimming method. As a result, the present invention does not require a radio frequency changeover switch and an additional bias control circuit, reduces the layout area of the electronic module, and optimizes the circuit design. In detail, in this embodiment, the resistor unit RU has a preset resistance cut section (for example, a part of the resistive thin film of the metal layer M3 (and / or metal layers M2, M1)), and this preset resistance cut section is laser trimmed (as shown by laser-cut LC3 or laser-cut LC4 in Figures 6 and 7), changing the total resistance value of the integrated passive element 124.For example, based on the resistance value R = ρ × L / A (where ρ is the resistivity of the material (constant), L is the effective length through which current flows, and A is the cross-sectional area of the conductor), laser-cut LC3 reduces the effective conductive path width of the metal layer (i.e., the effective conductor cross-sectional area A becomes smaller) or increases the effective length (L) through which current flows, thereby increasing the resistance value of resistor R3 (or resistors R3, R2), and increasing the total resistance value of the integrated passive element 124. Therefore, according to the present invention, there is no need to adjust the resistance value by using a radio frequency switching switch and a bias control circuit, which reduces the layout area of the electronic module.
[0037] Please refer to Figures 8A and 8B. Figure 8A is a schematic diagram illustrating the configuration in which the integrated passive element 124 of the electronic module 1 according to this embodiment includes a capacitor unit CU. Figure 8B is a schematic diagram illustrating the equivalent circuit of the capacitor unit CU according to this embodiment. The capacitor unit CU includes, but is not limited to, a parallel plate capacitor CU1 and a finger capacitor CU2 connected in parallel to the parallel plate capacitor CU1. In this embodiment, the capacitor unit CU has a preset capacitance cutting section (for example, a portion of the electrode area of the parallel plate capacitor CU1 (and / or a portion of the finger tip or finger of the finger capacitor CU2)), and the preset capacitance cutting section is laser trimmed (for example, as shown in laser-cut LC5 or laser-cut LC6 in Figure 8B), and the total capacitance value of the integrated passive element 124 changes. For example, the capacitance value is C = ε × A / d, where ε is the dielectric constant determined by the material, A is the electrode overlap area (or conductor plate area) of the capacitor, and d is the distance between electrodes (or conductor plate spacing) of the capacitor. Therefore, when roughly adjusting the capacitance value of the finger capacitor CU2, for example, a portion of the tip of each finger of the finger capacitor CU2 is removed by laser cutting to shorten the effective overlap length, and Coarse adjustment can be performed by removing all or part of the fingers to reduce the overlapping area of the electrodes (i.e., reduce the capacitance value). Fine adjustment of the capacitance value of the finger capacitor CU2 can be performed, for example, by forming tiny notches or grooves at the tips of the fingers of the finger capacitor CU2 to reduce the overlapping area of the electrodes. Coarse adjustment of the capacitance value of the parallel plate capacitor CU1 can be performed, for example, by removing an entire area of the upper electrode of the parallel plate capacitor CU1 by laser cutting to reduce the overlapping area of the electrodes, and the reduction in area directly corresponds to a reduction in capacitance value. Fine adjustment of the capacitance value of the parallel plate capacitor CU1 can be performed, for example, by forming thin grooves or small holes on the electrodes of the parallel plate capacitor CU1 and removing electrodes with a very small area.Furthermore, by locally destroying the dielectric layer in a portion of the parallel plate capacitor CU1 or finger capacitor CU2 using laser cutting, the inter-electrode distance can be increased, and similarly, this makes it possible to reduce the capacitance value of the parallel plate capacitor CU1 or finger capacitor CU2. As the capacitance values of the parallel plate capacitor CU1 and / or finger capacitor CU2 are reduced, the total capacitance value of the integrated passive element 124 is also reduced accordingly.
[0038] Please refer to Figure 9. Figure 9 is a schematic diagram illustrating another embodiment of the electronic module of the present invention. The electronic module 2 in Figure 9 is similar to the electronic module 1 in Figure 1, the difference being that the electronic module 2 further includes two blind via holes 21 and 22, but the present invention is not limited thereto. In other embodiments, the electronic module 2 may include only one blind via hole. The blind via holes 21 and 22 are formed in the glass substrate 11, the integrated passive element layer 12, and the active / passive element redistribution layer 13, and penetrate from the upper surface 111 of the glass substrate 11 to above the semiconductor chips 16 and 17, respectively, to dissipate the thermal energy generated by the semiconductor chips 16 and 17. In this way, the electronic module 2 has bidirectional thermal conduction paths, and the thermal energy from the surface of the semiconductor chips 16 and 17 is conducted upward by the blind via holes 21 and 22 for upward heat dissipation, and is guided, for example, to an upper external heat sink (not shown). The lower metal heat dissipation layer 141 releases the thermal energy from the back surface of the semiconductor chips 16 and 17 downward, and is conducted, for example, to a substrate or module shell (not shown). Furthermore, the junction temperature (Tj) of the semiconductor chips 16 and 17 can be significantly reduced, the heat distribution can be made uniform, and the lifespan can be further extended, thereby improving the reliability of the entire electronic module 2.
[0039] Please refer to Figure 10. Figure 10 is a schematic diagram illustrating yet another embodiment of the electronic module of the present invention. The electronic module 3 in Figure 10 is similar to the electronic module 1 in Figure 1, the difference being that the electronic module 2 further includes a molded layer 31. The molded layer 31 is provided on the upper surface 111 of the glass substrate 11, and the molded layer 31 and the upper surface 111 of the glass substrate 11 define an opening 310. The position of the opening 310 corresponds to, but is not limited to, the position of the integrated passive elements (e.g., integrated passive elements 123, 124, 125 on which laser trimming is performed). In this way, the laser can penetrate from the upper surface 111 of the glass substrate 11 through the opening 310 to the integrated passive elements 123, 124, 125 to perform laser trimming. In this embodiment, the sealing mold layer 31 is a protective layer formed, for example, by molding the upper surface 111 of the glass substrate 11 and the upper surface of the sealing material 18 with epoxy resin. For example, it contributes to preventing damage to the internal circuit due to external environmental factors and maintaining the reliability of the electronic module 3.
[0040] Please refer to Figure 11. Figure 11 is a schematic diagram illustrating an embodiment based on the electronic module 1 of the present invention. The electronic module 4 in Figure 11 is similar to the electronic module 1 in Figure 1, the difference being that vias 18' are used instead of the sealing material 18 in Figure 1, and the electronic module 4 includes a bypass capacitor layer 41, blind via holes 42 and conductors 43. The bypass capacitor layer 41, blind via holes 42 and conductors 43 are all installed on the upper surface 111 of the glass substrate 11, but are not limited to this. An opening 40 is formed in a part of the upper surface 111 of the glass substrate 11 (for example, defined by a part of the upper surface 111 of the glass substrate 11, the blind via holes 42 and conductors 43). The position of the opening 40 corresponds to the position of integrated passive elements (for example, integrated passive elements 122, 123 that are laser trimmed), but is not limited to this. In this way, the laser can penetrate from the upper surface 111 of the glass substrate 11 through the opening 40 to the integrated passive elements 122 and 123 to perform laser trimming. In this embodiment, the bypass capacitor layer 41 can be used, for example, to suppress power supply noise or reduce external electromagnetic interference. Furthermore, while conventional methods, when a bypass capacitor layer is directly placed on a semiconductor chip, have the disadvantage of occupying a large area and wasting horizontal space, the present invention makes it possible to achieve this by directly installing the bypass capacitor layer 41 on the upper surface 111 of the glass substrate 11, manufacturing each layer separately, and making the entire layer a bypass capacitor, thereby reducing the required horizontal space.
[0041] Please also refer to Figure 12. Figure 12 is a flowchart illustrating the manufacturing method of the above-mentioned electronic module. The manufacturing method of the electronic module 1 according to the present invention includes, but is not limited to, the following steps 51 to 55.
[0042] In step 51, an integrated passive element layer 12 is formed on at least a portion of the lower surface 112 of the glass substrate 11. The integrated passive element layer 12 includes at least one integrated passive element (for example, at least one of the reference numerals 120 to 129 in Figure 1), and the total inductance, total capacitance, or total resistance of the integrated passive element is changed by laser trimming that penetrates from the upper surface 111 of the glass substrate 11 to the integrated passive element.
[0043] In step 52, an active / passive element redistribution layer 13 is formed below the integrated passive element layer 12 and the glass substrate 11.
[0044] In step 53, a metal heat dissipation layer 141 is formed on the ceramic substrate 14 (for example, its lower surface), and the metal heat dissipation layer 141 and the ceramic substrate 14 define a cavity 142.
[0045] In step 54, the semiconductor chips 15-17 are placed inside the cavity 142 and positioned above the metal heat dissipation layer 141.
[0046] In step 55, the active / passive element redistribution layer 13 is bonded to the ceramic substrate 14, and the semiconductor chips 15-17 are electrically connected to the integrated passive elements (for example, as shown by reference numerals 121, 122, and 126 in Figure 1) via an electrically conductive interconnect configuration.
[0047] In some embodiments of the above-described method for manufacturing the electronic module, between step 52 and step 53, a step is further included in which blind via holes 21 and 22 are formed in the glass substrate 11, the integrated passive element layer 12, and the active / passive element redistribution layer 13, and the blind via holes 21 and 22 penetrate from the upper surface 111 of the glass substrate 11 to the semiconductor chips 16 and 17, thereby realizing some of the electronic modules 2 shown in Figure 9.
[0048] In some embodiments of the above-described method for manufacturing the electronic module, after step 55, a further step (not shown) is included in which a sealing mold layer 31 is placed on the upper surface 111 of the glass substrate 11, an opening 310 is defined by the sealing mold layer 31 and the upper surface 111 of the glass substrate 11, the position of the opening 310 corresponds to the positions of the integrated passive elements 123 to 125, and some electronic modules 3 shown in Figure 10 are realized.
[0049] In some embodiments of the above-described method for manufacturing the electronic module, after step 55, a via (indicated by reference numeral 18' in Figure 11) is used instead of the encapsulating material (indicated by reference numeral 18 in Figure 1), and a bypass capacitor layer 41 is placed on the upper surface 111 of the glass substrate 11, forming an opening 40 in a part of the upper surface 111 of the glass substrate 11, with the position of the opening 40 corresponding to the positions of the integrated passive elements 122 and 123, thereby realizing a part of the electronic module 4 shown in Figure 11 (not shown).
[0050] In summary, the electronic module and its manufacturing method according to the present invention, in addition to achieving the above-mentioned effects, have advantages over the prior art. By combining the design of the glass substrate 11 with the laser trimming method, the present invention can achieve changes in the total inductance, total capacitance, or total resistance of the integrated passive elements. Therefore, according to the present invention, there is no need to redesign, manufacture, and encapsulate an entirely new electronic module, or to remove the top layer of an existing electronic module package, adjust the internal integrated passive elements, and then reseal it. Consequently, damage to internal elements, chips, or wiring due to decapping or decoupage processes can be avoided, yield reductions due to resealing processes can be prevented, and necessary costs can be further reduced. Furthermore, by modifying the matching network through laser trimming and cutting of the integrated passive elements, the requirements for product production can be directly met.
[0051] The above description is merely an embodiment of the present invention and does not limit the scope of the present invention. Any simple equivalent modifications and alterations made based on the claims and specification of the present invention are included within the scope of the present invention. [Explanation of Symbols]
[0052] 1-4 Electronic Modules 10 Solder 11 Glass substrate 12 Integrated Passive Element Layer 13 Active / Passive Element Redistribution Layer 14 Ceramic substrate 15-17 Semiconductor chips 18. Sealing material 18' Beer 19, 20 input / output ports 21, 22 Blind Beer Hall 31. Sealing mold layer 40 openings 41 Bypass capacitor layer 42 Blind Beer Hall 43 Conductor Steps 51-55 111 Top surface 112 Bottom surface 120-129 Integrated Passive Elements 140 Silver Paste 141 Metal heat dissipation layer 142 Cavity 310 Opening C1, C2 Pre-set inductance laser cutting section CU Capacitor Unit CU1 Parallel Plate Capacitor CU2 Finger Capacitor LC1~LC6 Laser Cutting LP Main Coil LP1~LP4 Coil LS Sub-coil LS1~LS4 Coil LU, LU' Inductance Unit M1, M2, M3 metal layer R1, R2, R3 resistance RU Resistor Unit Via1, Via2
Claims
1. A glass substrate having an upper surface and a lower surface, The glass substrate includes an integrated passive element layer disposed on at least a portion of its lower surface and containing at least one integrated passive element, An electronic module characterized in that the total inductance, total capacitance, or total resistance of the integrated passive element is changed by laser trimming that penetrates from the upper surface of the glass substrate to the integrated passive element.
2. The aforementioned integrated passive element is The electronic module according to claim 1, characterized in that it includes an inductance unit having a preset inductance laser cutting section that changes the total inductance value of the integrated passive element by being laser trimmed.
3. The aforementioned integrated passive element is The electronic module according to claim 1, characterized in that it includes a capacitor unit having a preset capacitance cutting section that changes the total capacitance value of the integrated passive element by being laser trimmed.
4. The aforementioned integrated passive element is The electronic module according to claim 1, characterized in that it includes a resistor unit having a preset resistance cutting section that changes the total resistance value of the integrated passive elements by being laser trimmed.
5. The electronic module according to claim 1, further comprising a bypass capacitor layer disposed on the upper surface of the glass substrate, wherein an opening corresponding to the position of the integrated passive element is formed in a part of the upper surface of the glass substrate.
6. The electronic module according to claim 1, further comprising a sealing mold layer disposed on the upper surface of the glass substrate, wherein an opening is defined by the sealing mold layer and the upper surface of the glass substrate, and the position of the opening corresponds to the position of the integrated passive element.
7. The glass substrate and the integrated passive element layer are disposed below it and coupled to the integrated passive element layer, and the active / passive element redistribution layer is located below it. A ceramic substrate is disposed below the active / passive element redistribution layer, has a metal heat dissipation layer, and together with the metal heat dissipation layer defines a cavity, A semiconductor chip is disposed within the cavity and located above the metal heat dissipation layer, and is electrically connected to the integrated passive element via an electrically conductive interconnect configuration. The electronic module according to claim 1, further comprising:
8. The electronic module according to claim 7, further comprising blind via holes formed in the glass substrate, the integrated passive element layer, and the active / passive element redistribution layer, penetrating from the upper surface of the glass substrate to the semiconductor chip, and used for heat dissipation.
9. The electronic module according to claim 7, characterized in that the active / passive element redistribution layer is formed based on a thin-film transistor process and a panel-level packaging process.
10. The electronic module according to claim 7, characterized in that the semiconductor chip is a radio frequency circuit.
11. (A) A step in which an integrated passive element layer is formed on at least a portion of the lower surface of a glass substrate, the integrated passive element layer includes at least one integrated passive element, and the total inductance value, total capacitance value, or total resistance value of the integrated passive element is changed by laser trimming that penetrates from the upper surface of the glass substrate to the integrated passive element, (B) The steps of forming an active / passive element redistribution layer below the integrated passive element layer and the glass substrate, and coupling the active / passive element redistribution layer with the integrated passive element layer, (C) A step of forming a metal heat dissipation layer on a ceramic substrate and defining a cavity with the metal heat dissipation layer and the ceramic substrate, (D) A step in which a semiconductor chip is placed in the cavity and is located above the metal heat dissipation layer, (E) The steps of bonding the active / passive element redistribution layer to the ceramic substrate and electrically connecting the semiconductor chip to the integrated passive element via an electrically conductive interconnect configuration, A method for manufacturing an electronic module, characterized by including the following:
12. The manufacturing method according to claim 11, characterized in that the integrated passive element includes an inductance unit having a preset inductance laser cutting section that is laser-trimmed to change the total inductance value of the integrated passive element.
13. The manufacturing method according to claim 11, characterized in that the integrated passive element includes a capacitor unit having a preset capacitance cutting portion that is laser-trimmed to change the total capacitance value of the integrated passive element.
14. The manufacturing method according to claim 11, characterized in that the integrated passive element includes a resistor unit having a preset resistance cutting portion that is laser-trimmed to change the total resistance value of the integrated passive element.
15. The manufacturing method according to claim 11, further comprising the step of installing a bypass capacitor layer (F) on the upper surface of the glass substrate after step (E), and forming an opening corresponding to the integrated passive element in a part of the upper surface of the glass substrate.
16. The manufacturing method according to claim 11, further comprising the step of (F) installing a sealing mold layer on the upper surface of the glass substrate after step (E), wherein the sealing mold layer and a portion of the upper surface of the glass substrate define an opening corresponding to the integrated passive element.
17. The manufacturing method according to claim 11, further comprising the step between step (B) and step (C) of forming (F) blind via holes penetrating from the upper surface of the glass substrate to the semiconductor chip within the glass substrate, the integrated passive element layer, and the active / passive element redistribution layer.
18. The manufacturing method according to claim 11, characterized in that the active and passive element redistribution layers include a thin-film transistor configuration and an interconnection / sealing configuration, respectively, formed based on a thin-film transistor process and a panel-level packaging process.