Semiconductor equipment

Abstract

To provide a semiconductor device that can perform multiply-accumulate operations with low power consumption. [Solution] In a semiconductor device, the circuit MC included in the circuit MP has transistors M1 to M4 and a capacitive element C1. The holding part HC is formed by transistor M1 and the capacitive element C1. In transistors M1 to M4 having back gates, the gate and back gate may be electrically connected in order to increase the on-current of the transistor. In transistors having back gates, wiring that is electrically connected to an external circuit may be provided to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, and a potential may be applied to the back gate of the transistor by the external circuit.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic devices.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention is: Process, machine, manufacture, or composition of matter This relates to the technology of one aspect of the present invention disclosed more specifically herein. The fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, Memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, and A manufacturing method or inspection method thereof can be given as an example. [Background technology]

[0003] Currently, there is a lot of activity in developing integrated circuits that mimic the structure of the human brain. The pathway is an electronic circuit that incorporates the brain's structure, and the "neurons" and "s It has a circuit equivalent to a "naps." Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "Brainmorphic," "Brain-Inspired," or "Brain-Inspired." The integrated circuit has a non-von Neumann architecture, and its power consumption increases with increasing processing speed. Compared to the larger von Neumann architecture, it performs parallel processing with extremely low power consumption. It is expected to happen.

[0004] Information processing models that mimic neural networks with "neurons" and "synapses" are artificial It is called an artificial neural network (ANN). For example, Non-Patent Document 1 and Non-Patent Document 2 disclose an arithmetic unit that uses SRAM (Static Random Access Memory) to construct an artificial neural network.

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In an artificial neural network, a calculation is performed by multiplying the connection strength (sometimes referred to as a weight coefficient) of the synapse that connects two neurons and the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and sum the connection strength of each synapse between a plurality of first neurons in the first layer and a second neuron in the second layer, and each signal input from the plurality of first neurons in the first layer to the second neuron in the second layer. According to the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, in the artificial neural network ​​​​​​​In a neuronal network, the number of neurons increases as the number of layers and neurons increases. The number of circuits corresponding to each "synapse" can increase significantly, and the amount of computation can become enormous. .

[0007] As the number of circuits that make up the chip increases, power consumption increases, and the electricity generated when the device is running increases. The amount of heat generated also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements contained in the chip change. Because this affects the chip, the circuits that make up the chip have circuit elements that are less susceptible to temperature changes. It is preferable to do so.

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. One of the objectives is to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention is a semiconductor device with low power consumption. One of the objectives is to provide the following. Alternatively, one aspect of the present invention is to provide the following, which are affected by the temperature of the environment. One of the objectives is to provide semiconductor devices that are less prone to damage. Alternatively, one aspect of the present invention is a new One of our objectives is to provide standard semiconductor devices and the like.

[0009] The problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described in the following section. This is an issue not mentioned in the specification. Issues not mentioned in this section can be found in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention addresses at least one of the problems listed above and other problems. This invention solves the problems. One aspect of the present invention addresses the problems listed above, as well as other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having a first circuit and a second circuit, wherein the first circuit The first circuit has a first holding node, the second circuit has a second holding node, and the first circuit has a first input The wiring, second input wiring, first wiring, and second wiring are electrically connected, and the second circuit is connected to the first input The power wiring, second input wiring, first wiring, and second wiring are electrically connected, and the first circuit is the first The second circuit has the function of holding a first potential corresponding to the data in the first holding node, and the first data The first circuit has the function of holding a second potential corresponding to the first input wiring in the second holding node, and the first circuit is the first input wiring When a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, It has a function to output a current to the first wiring according to the potential, and when a low-level potential is input to the first input wiring... Furthermore, when a high-level potential is input to the second input wiring, the current corresponding to the first potential is supplied to the second wiring. It has a function to output to a line, and when a low level potential is input to the first input wiring and a low level is input to the second input wiring When a bell potential is input, a current corresponding to the first potential is output to the first and second wirings. The second circuit has a function that does not exist, and a high-level potential is input to the first input wiring, and the second input When a low-level potential is input to the power wiring, a current corresponding to the second potential is output to the second wiring. The function is that a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring. When power is applied, it has the function of outputting a current corresponding to the second potential to the first wiring, and low to the first input wiring. When a level potential is input and a low level potential is input to the second input wiring, the second potential This semiconductor device has a function of not outputting a corresponding current to the first and second wirings. .

[0011] (2) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the first circuit is the first to fourth transistors The circuit has a transistor and a first capacitance element, and the second circuit has a fifth to eighth transistor and a second The device has a capacitive element, and the first holding node has the first terminal of the first transistor and the second transistor The gate of the transistor and the first terminal of the first capacitance element are electrically connected, and the first terminal of the second transistor The terminal is electrically connected to the second terminal of the first capacitance element, and the second terminal of the second transistor is The first terminal of the third transistor and the first terminal of the fourth transistor are electrically connected. The gate of the third transistor is electrically connected to the first input wiring, and the gate of the fourth transistor The terminal is electrically connected to the second input wiring, and the second terminal of the third transistor is connected to the first wiring. Electrically connected, the second terminal of the fourth transistor is electrically connected to the second wiring, and the second The holding node consists of the first terminal of the fifth transistor, the gate of the sixth transistor, and the second capacitor. The first terminal of the element is electrically connected to the first terminal of the sixth transistor, and the first terminal of the second capacitor element is connected to the first terminal of the second capacitor element. Electrically connected to two terminals, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor. The child, and electrically connected to the first terminal of the 8th transistor, and the gate of the 7th transistor. It is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The 7th transistor's 2nd terminal is electrically connected to the 2nd wire, and the 8th transistor The second terminal of the transistor is a semiconductor device that is electrically connected to the first wiring.

[0012] (3) Alternatively, in one aspect of the present invention, in (1) above, the first circuit is a first to fourth transistor The circuit has a 9th transistor and a 1st capacitance element, and the 2nd circuit has 5th to 8th transistors It has a zista, a 10th transistor, and a 2nd capacitance element, and the first holding node is the 1st The first terminal of the transistor, the gate of the second transistor, the gate of the ninth transistor, and The first terminal of the first capacitance element is electrically connected, and the second terminal of the first capacitance element is connected to the second transistor. The first terminal of the transistor and the first terminal of the ninth transistor are electrically connected, and the second transistor The second terminal of the transistor is electrically connected to the first terminal of the third transistor, and the ninth transistor The second terminal is electrically connected to the first terminal of the fourth transistor, and the gate of the third transistor. The gate of the fourth transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is connected to the second input wiring. Electrically connected, the second terminal of the third transistor is electrically connected to the first wiring, and the fourth The second terminal of the transistor is electrically connected to the second wiring, and the second holding node is connected to the fifth transistor. The first terminal of the transistor, the gate of the sixth transistor, the gate of the tenth transistor, and The first terminal of the 2-capacitance element is electrically connected to the 6th transistor, and the second terminal of the 2-capacitance element is connected to the 6th transistor. The first terminal of the transistor and the first terminal of the 10th transistor are electrically connected, and the 6th transistor The second terminal of the sta is electrically connected to the first terminal of the seventh transistor, and the tenth transistor The second terminal of the transistor is electrically connected to the first terminal of the 8th transistor, and the 7th transistor The gate is electrically connected to the first input wiring, and the gate of the eighth transistor is connected to the second input wiring. The wire is electrically connected, and the second terminal of the seventh transistor is electrically connected to the second wire. The second terminal of the eighth transistor is a semiconductor device that is electrically connected to the first wiring.

[0013] (4) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the first circuit is the first to fourth transistors It has an inverter, a first logic circuit, and a second logic circuit, and the second circuit has 5 to 8 transistors. It has an inverter, a third logic circuit, and a fourth logic circuit, and each of the first to fourth logic circuits This has the function of outputting an inverted signal of the signal input to the input terminal from the output terminal, and the first retain The holding node is the input terminal of the first logic circuit, the output terminal of the second logic circuit, and the terminal of the first transistor. The first terminal is electrically connected to the gate of the second transistor, and the output terminal of the first logic circuit is The input terminal of the second logic circuit is electrically connected to the second terminal of the second transistor, and the second terminal of the second transistor is connected to the third terminal. The first terminal of the transistor and the first terminal of the fourth transistor are electrically connected, and the third transistor The gate of the transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is The second input wiring is electrically connected, and the second terminal of the third transistor is electrically connected to the first wiring. The second terminal of the fourth transistor is connected to the second wiring, and the second holding nozzle is connected to the second wiring. D is the input terminal of the third logic circuit, the output terminal of the fourth logic circuit, and the first terminal of the fifth transistor. , and electrically connected to the gate of the 6th transistor, the output terminal of the 3rd logic circuit is connected to the 4th The input terminal of the logic circuit is electrically connected, and the second terminal of the sixth transistor is connected to the seventh transistor. The first terminal of the sta and the first terminal of the 8th transistor are electrically connected, and the 7th transistor The gate of transistor 8 is electrically connected to the first input wiring, and the gate of transistor 8 is connected to the second input wiring. The power wiring is electrically connected, and the second terminal of the seventh transistor is electrically connected to the second wiring. Therefore, the second terminal of the eighth transistor is a semiconductor device that is electrically connected to the first wiring. ru.

[0014] (5) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the first circuit is the first to fourth transistors It has an inverter, a first logic circuit, and a second logic circuit, and the second circuit has 6th to 8th transistors. It has a transistor, and each of the first logic circuit and the second logic circuit receives the signal input to the input terminal. The first holding node has the function of outputting an inverted signal from the output terminal, and the input of the first logic circuit Terminal, output terminal of second logic circuit, first terminal of first transistor, and second transistor The gate is electrically connected, and the output terminal of the first logic circuit is electrically connected to the input terminal of the second logic circuit. They are connected in a specific manner, with the second terminal of the second transistor being connected to the first terminal of the third transistor, and the fourth The first terminal of the transistor is electrically connected, and the gate of the third transistor is connected to the first input terminal. The gate of the fourth transistor is electrically connected to the second input wiring. The second terminal of the third transistor is electrically connected to the first wiring, and the fourth terminal of the fourth transistor is electrically connected to the first wiring. Terminal 2 is electrically connected to the second wiring, and the second holding node is the input terminal of the second logic circuit. The output terminal of the first logic circuit and the gate of the sixth transistor are electrically connected, and the sixth transistor The second terminal of the transistor is the first terminal of the seventh transistor, and the first terminal of the eighth transistor. The gate of the seventh transistor is electrically connected to the first input wiring. The gate of the 8th transistor is electrically connected to the 2nd input wiring, and the 7th transistor The second terminal is electrically connected to the second wiring, and the second terminal of the eighth transistor is connected to the first wiring. It is a semiconductor device that is electrically connected.

[0015] (6) Alternatively, one aspect of the present invention is a semiconductor device having a first circuit and a second circuit, the Circuit 1 has a first load circuit, Circuit 2 has a second load circuit, and Circuit 1 has a first load circuit and Each of the two load circuits has a first terminal and a second terminal, and the first load circuit and the second The load circuit and each of them change the resistance value between the first terminal and the second terminal according to the first data. It has the function of transforming, and the first circuit consists of a first input wiring, a second input wiring, a first wiring, and a second wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The wire is electrically connected, and the first circuit has a high-level potential input to the first input wiring, and the second When a low-level potential is applied to the input wiring, the current corresponding to the resistance value of the first load circuit is supplied to the first load circuit. The function outputs to the wiring, and when a low level potential is input to the first input wiring and a high level potential is input to the second input wiring... When a level potential is input, a current corresponding to the resistance value of the first load circuit is output to the second wiring. The function is that when a low level potential is input to the first input wiring and a low level potential is input to the second input wiring When input is received, a current corresponding to the resistance value of the first load circuit is output to the first and second wiring. The second circuit has a function that does not exert force, and a high-level potential is input to the first input wiring, and the When a low-level potential is applied to the 2-input wiring, the current corresponding to the resistance value of the 2nd load circuit is generated. It has a function to output to two wires, and when a low level potential is input to the first input wire, and the second input wire... When a high-level potential is input, a current corresponding to the resistance value of the second load circuit is output to the first wiring. The function is such that a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. When this input is received, a current corresponding to the resistance value of the second load circuit is supplied to the first and second wirings. This is a semiconductor device that has a function that does not output.

[0016] (7) Alternatively, in one aspect of the present invention, in the configuration of (6) above, the first circuit is a third transistor The second circuit has a fourth transistor and a seventh transistor and an eighth transistor. The first load circuit has the first terminal of the third transistor and the fourth transistor. The first terminal of the zista is electrically connected, and the gate of the third transistor is electrically connected to the first input wiring. The gate of the fourth transistor is electrically connected to the second input wiring, and the third The second terminal of the transistor is electrically connected to the first wiring, and the second terminal of the fourth transistor... It is electrically connected to the second wiring, and the first terminal of the second load circuit is the first of the seventh transistor. The terminal, and the first terminal of the 8th transistor are electrically connected, and the gate of the 7th transistor. It is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The 7th transistor's 2nd terminal is electrically connected to the 2nd wire, and the 8th transistor The second terminal of the transistor is a semiconductor device that is electrically connected to the first wiring.

[0017] (8) Alternatively, in one aspect of the present invention, in the configuration of (7) above, the first circuit is the first transistor The second circuit has a second transistor, and the first terminal of the first transistor is the first negative The first terminal of the second transistor is electrically connected to the first terminal of the load circuit, and the first terminal of the second transistor is connected to the second load circuit. This is a semiconductor device that is electrically connected to the first terminal.

[0018] (9) Alternatively, in one aspect of the present invention, in any one of the configurations (6) to (8) above, the first negative The load circuit has one of the following: a resistive switching element, an MTJ element, or a phase-change memory, and the second load circuit This is a semiconductor device having one of the following: a resistive switching element, an MTJ element, or a phase-change memory.

[0019] (10) Alternatively, in one aspect of the present invention, in any one of the configurations (1) to (9) above, the third The circuit has a path and a fourth circuit, and the third circuit has a first input wiring and a second input wiring, respectively The fourth circuit has a function to input a potential corresponding to the second data, and the first wiring and the second wiring By comparing the currents flowing from each of them, the first data and the second data are obtained from the output terminal of the fourth circuit. This is a semiconductor device that has the function of outputting a potential corresponding to the product of two factors.

[0020] (11) Alternatively, one aspect of the present invention comprises any one of the semiconductor devices described in (1) to (10) above, This is an electronic device that performs neural network calculations using semiconductor devices.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor properties. Circuits containing structural elements (transistors, diodes, photodiodes, etc.), and circuits having the same This refers to devices, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, Integrated circuits, chips containing integrated circuits, and electronic components that house chips in a package are called semiconductors. This is an example of a device. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic equipment are also examples. It is a semiconductor device in itself, and may have a semiconductor device.

[0022] Furthermore, if it is stated in this specification, etc., that X and Y are connected, then X and When Y is electrically connected, when X and Y are functionally connected, and when X and The case in which Y and are directly connected is disclosed in this specification, etc. Furthermore, the predetermined connection relationships, for example, the connection relationships shown in the diagram or text, are not limited to those shown in the diagram or text. Other connection relationships besides those shown are also disclosed in the diagram or text. X and Y are, Let's assume the object is (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). .

[0023] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not it is released.

[0024] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), changes the potential level of the signal Level shifter circuits, etc.), voltage sources, current sources, switching circuits, amplification circuits (signal amplitude or Circuits that can increase the amount of current, etc., operational amplifiers, differential amplifiers, source follower circuits, batteries One or more circuits (such as FA circuits, signal generation circuits, memory circuits, control circuits, etc.) are located between X and Y. It is possible to connect them. For example, if another circuit is placed between X and Y... However, if a signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be considered as such.

[0025] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When connected with another circuit in between) and when X and Y are directly connected (that is (including cases where X and Y are connected without another element or circuit in between) In other words, if you explicitly state that they are electrically connected, then simply say they are connected. This is equivalent to the case where it is explicitly stated that it is present.

[0026] Also, for example, "X and Y and the source (or first terminal, etc.) and drain of the transistor ( (or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor. (or the first terminal, etc.), the transistor drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor ( The first terminal (or the first terminal, etc.) is electrically connected to X, and the drain (or second terminal) of the transistor is connected to X. The terminals (or other terminals) are electrically connected to Y, and X is the source of the transistor (or the first terminal, etc.). The transistor's drain (or second terminal, etc.), Y, are electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal) (etc.), Y is provided in this connection order. By using a similar method of expression to specify the order of connections in the circuit configuration, Connect the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor. By distinguishing between them, the technical scope can be determined. Note that these expressions are just examples. However, it is not limited to these methods of expression. Here, X and Y are objects (e.g., devices, elements, (This refers to circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0027] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0028] Furthermore, in this specification, a transistor is referred to as gate, source, and drain. It has three terminals. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. The input / output terminals specify the transistor's conductivity type (n-channel type, p-channel type) and the transistor's... Depending on the potential applied to the three terminals of the sta, one becomes the source and the other the drain. Therefore, in this specification, the terms source and drain may be rephrased. It shall be possible to do so. Furthermore, in this specification, when describing the connection relationships of transistors, "either the source or the drain" (or the first electrode or the first terminal), "either the source or the drain The notation "the other side" (or second electrode, or second terminal) is used. Note that the structure of a transistor Depending on the model, in addition to the three terminals mentioned above, there may be a back gate. In this specification, either the gate or the back gate of a transistor is referred to as the first gate. The other side of the transistor's gate or back gate is sometimes referred to as the second gate. Furthermore, within the same transistor, the terms "gate" and "back gate" are interchangeable. It may be possible to replace it. Also, if the transistor has 3 or more gates In this specification, etc., each gate is referred to as the first gate, the second gate, the third gate, etc. It is sometimes referred to as such.

[0029] Furthermore, in this specification, etc., a node has terminals, distributions, etc., depending on the circuit configuration and device structure. These can be rephrased as wire, electrode, conductive layer, conductor, impurity region, etc. Also, terminal, Wiring and other components can be referred to as nodes.

[0030] Furthermore, in this specification and other documents, "voltage" and "potential" may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential. For example, if the reference potential is ground... If we consider it as ground potential, then "voltage" can be replaced with "potential". The potential does not necessarily mean 0V. Furthermore, potential is relative, and it is based on a reference point. Depending on the potential, it may change the potential supplied to wiring, etc.

[0031] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction), for example, "electricity of a positively charged body." The statement "conduction is occurring" means "electrical conduction of a negatively charged body is occurring in the opposite direction." This can be rephrased as follows. Therefore, in this specification, the term "electric current" is not used unless otherwise specified. In this context, it refers to the phenomenon of charge transfer associated with carrier movement (electrical conduction). Carriers include electrons, holes, anions, cations, complex ions, etc., which are involved in the flow of electric current. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). In lines and other structures, the "direction of current" is defined as the direction in which positive carriers move, and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative current It is expressed in terms of flow rate. Therefore, in this specification, etc., the positive and negative (or direction of the current) of the current is not specified. Unless otherwise stated, descriptions such as "current flows from element A to element B" should be interpreted as "current flows from element B to element B." This can be rephrased as "current flows through A," etc. Also, "current enters element A." Descriptions such as "forced" can be rephrased as "current is output from element A," etc. Let's assume that.

[0032] Furthermore, in this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to constituent elements. This was added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. For example, one of the embodiments described herein The components referred to as "first" in this invention may be used in other embodiments or claims. It may also be the component referred to in "Section 2". For example, in this specification, etc. In one embodiment, the component referred to as "first" may be used in other embodiments, or in other embodiments. It may be possible to omit certain details within the scope of the permitted claim.

[0033] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. In some cases, positional relationships are used for convenience in explaining them by referring to diagrams. The relative positions of the elements change appropriately depending on the direction in which each element is depicted. Therefore, The terminology is not limited to what is explained in the detailed document, etc., and can be appropriately rephrased depending on the situation. For example, However, in the expression "insulator located on the upper surface of the conductor," the orientation of the diagram shown should be rotated 180 degrees. By rephrasing it, it can be described as "an insulator located on the underside of a conductor."

[0034] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0035] Furthermore, in this specification, terms such as "membrane" and "layer" may be interchanged depending on the context. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". It may be possible to change the terminology to this. Or, depending on the circumstances, or depending on the situation. Therefore, it is possible to replace terms such as "membrane" and "layer" with other terms without using them. For example, changing the term "conductive layer" or "conductive film" to the term "conductor" It may be possible. Or, for example, the terms "insulating layer" and "insulating film" could be changed to "insulator". It may be possible to change the terminology.

[0036] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" or " This includes cases where the wiring is formed as a single integrated unit.

[0037] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. Therefore, or depending on the situation, they can be interchanged. For example, "wiring" In some cases, it is possible to change the term "signal line" to "signal line". Also, for example In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" should be changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" should be changed to terms such as "signal lines." In some cases, this is possible. Conversely, terms like "signal line" can also be used for "power line." It may be possible to change the terminology. Also, the "potential" applied to the wiring Depending on the circumstances, or in some cases, the term may be changed to a term such as "signal". In some cases, this is possible. Conversely, terms like "signal" can also be expressed as "electric potential." It may be possible to change the terminology.

[0038] In this specification, semiconductor impurities refer to, for example, components other than the main components that constitute the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. For example, when DOS (Density of States) is formed in a semiconductor... In some cases, this can lead to a decrease in carrier mobility or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main component. These include transition metals, and in particular, for example, hydrogen (also found in water), lithium, sodium, These include silicon, boron, phosphorus, carbon, and nitrogen. Specifically, semiconductors are made up of silicon layers. In this case, impurities that alter the properties of semiconductors include, for example, Group 1 elements other than oxygen and hydrogen. These include elements from Group 2, Group 13, Group 15, and so on.

[0039] In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow, or a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows. One example is... Electrical switches, mechanical switches, etc., can be used. In other words, switches are Any device capable of controlling the current will suffice; it is not limited to any specific device.

[0040] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is. Furthermore, when using a transistor as a switch, the "conductivity state" of the transistor... This refers to a state where the source and drain electrodes of a transistor can be considered to be electrically short-circuited. It refers to a state. Also, the "non-conductive state" of a transistor is when the source electrode and the drive of the transistor are not connected. This refers to a state in which the input electrode can be considered electrically isolated. Note that a transistor is not simply a transistor. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0041] One example of a mechanical switch is MEMS (Micro-Electro-Mechanical Systems). There are switches that use (STEM) technology. These switches are capable of being moved mechanically. It has electrodes, and operates by controlling the transition between conductivity and non-conductivity through the movement of these electrodes. [Effects of the Invention]

[0042] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed It can provide a place for, etc. Alternatively, according to one aspect of the present invention, a semiconductor with low power consumption. The present invention can provide devices, etc. Alternatively, according to one aspect of the present invention, the influence of ambient temperature can be reduced. It is possible to provide semiconductor devices that are less susceptible to damage. Or, according to one aspect of the present invention, We can provide standard semiconductor devices and the like.

[0043] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described by those skilled in the art in the specification or This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the effect of... Therefore, one aspect of the present invention may, in some cases, have the effects listed above. They may not always be present. [Brief explanation of the drawing]

[0044] [Figure 1] Figures 1A and 1B illustrate a hierarchical neural network. [Figure 2] Figure 2 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 3] Figures 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing example configurations of circuits in semiconductor devices. [Figure 4] Figures 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing example circuit configurations of semiconductor devices. [Figure 5] Figures 5A, 5B, 5C, 5D, 5E, and 5F are circuit diagrams showing examples of circuit configurations of semiconductor devices. [Figure 6] Figure 6 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 7] Figure 7 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 8] Figure 8 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 9] Figures 9A, 9B, and 9C are circuit diagrams showing examples of circuit configurations in semiconductor devices. [Figure 10] Figures 10A and 10B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 11] Figures 11A and 11B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 12] Figures 12A and 12B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 13] Figures 13A, 13B, and 13C are timing charts showing examples of the operation of circuits in semiconductor devices. [Figure 14] Figures 14A, 14B, and 14C are timing charts showing examples of circuit operation in a semiconductor device. [Figure 15] Figures 15A, 15B, and 15C are timing charts showing examples of the operation of circuits in semiconductor devices. [Figure 16] Figures 16A and 16B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 17] Figure 17 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 18] Figures 18A, 18B, 18C, and 18D are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 19] Figure 19 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 20] Figures 20A and 20B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 21] Figures 21A and 21B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 22] Figures 22A, 22B, and 22C are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 23] Figures 23A, 23B, and 23C are circuit diagrams showing examples of the circuit configurations of semiconductor devices. [Figure 24] Figures 24A and 24B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 25] Figures 25A and 25B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 26] Figures 26A and 26B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 27] Figures 27A and 27B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 28] Figure 28 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 29] Figure 29 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 30] Figures 30A, 30B, and 30C are cross-sectional views showing examples of transistor structures. [Figure 31]Figures 31A, 31B, and 31C are top views and cross-sectional views showing examples of transistor structures. [Figure 32] Figures 32A, 32B, and 32C are top views and cross-sectional views showing examples of transistor structures. [Figure 33] Figures 33A, 33B, and 33C are top views and cross-sectional views showing examples of transistor structures. [Figure 34] Figures 34A, 34B, and 34C are top views and cross-sectional views showing examples of transistor structures. [Figure 35] Figures 35A, 35B, and 35C are top views and cross-sectional views showing examples of transistor structures. [Figure 36] Figures 36A and 36B are top and perspective views, respectively, illustrating examples of transistor structures. [Figure 37] Figures 37A and 37B are cross-sectional views showing examples of transistor structures. [Figure 38] Figures 38A, 38B, and 38C are top views and perspective views showing examples of the structure of a capacitive element. [Figure 39] Figures 39A, 39B, and 39C are top views and perspective views showing examples of the structure of a capacitive element. [Figure 40] Figures 40A, 40B, 40C, and 40D are perspective views showing examples of semiconductor wafers and electronic components. [Figure 41] Figure 41 is a perspective view showing an example of an electronic device. [Figure 42] Figure 42A is a front view showing an example of an electronic device, while Figures 42B and 42C are perspective views showing an example of an electronic device. [Modes for carrying out the invention]

[0045] In artificial neural networks (hereinafter referred to as neural networks): The synaptic connection strength is determined by providing existing information to the neural network. It can change. In this way, by giving existing information to a neural network, The process of determining the overall strength is sometimes called "learning."

[0046] Furthermore, for a neural network that has undergone "learning" (where connection strengths have been defined), By providing that information, new information can be output based on the bond strength. Thus, in a neural network, based on the given information and connection strength... The process of outputting new information is sometimes called "inference" or "cognition."

[0047] Examples of neural network models include the Hopfield type and the hierarchical type. One example is a multi-layered neural network called a "deep neural network." It is called a "deep neural network" (DNN), and machine learning using deep neural networks is called It is sometimes referred to as "deep learning."

[0048] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called OS) They are classified into the following categories. For example, when a metal oxide is used in the active layer of a transistor, the metal acid These oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplification and rectification effects. and constitute a channel formation region of a transistor having at least one switching action. If possible, the metal oxide is used as a metal oxide semiconductor. It can also be called an OS FET or OS transistor. When this is stated, it is equivalent to a transistor having a metal oxide or oxide semiconductor. It is possible.

[0049] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0050] Furthermore, in this specification, the configurations shown in each embodiment are different from the configurations shown in other embodiments. By combining them as appropriate, one embodiment of the present invention can be formed. If multiple configuration examples are provided, it is possible to combine them as appropriate.

[0051] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one of the following: It is possible to replace or otherwise perform actions such as [doing something else].

[0052] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0053] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, it becomes possible to construct even more diagrams.

[0054] Embodiments described herein are explained with reference to the drawings. However, implementation may differ. The form can be implemented in many different ways, and it does not deviate from the purpose and scope. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention is not to be interpreted as being limited to the embodiments described herein. In the configuration of the invention in the form of application, the same reference numeral is used for identical parts or parts having similar functions. In some cases, explanations of repetitions used across different drawings may be omitted. Also, perspective drawings. In some cases, the description of certain components may be omitted in order to ensure clarity in the drawings. be.

[0055] In this specification, when the same reference numeral is used for multiple elements, it is particularly important to distinguish between them. When necessary, add identifying codes such as "_1", "[n]", or "[m,n]" to the code. It may be noted or written down.

[0056] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. In some cases, this may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are for reference only. This is a schematic representation of a hypothetical example and is not limited to the shapes or values ​​shown in the drawing. This can be due to variations in signals, voltages, or currents caused by noise, or to timing discrepancies. This can include variations in signals, voltages, or currents.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention is used to perform a neural network This section explains the arithmetic circuits that perform calculations.

[0058] <Hierarchical Neural Network> First, a hierarchical neural network will be described. The hierarchical neural network has, as an example, one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A shows an example thereof, and the neural network 100 has the first layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers . In FIG. 1A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted .

[0059] Each layer of the neural network 100 has one or more neurons. In FIG. 1A , the first layer has neurons N1 , , , (1) , q , (k) , ,<着

[0060] , , , (R) ,<着 (R) to neuron N p (1) (where p is an integer of 1 or more ). The (k - 1)th layer has neurons N1 (k-1) to neuron N m (k-1) (where m is an integer of 1 or more). The kth layer has neurons N1 ( k) to neuron N n (k) (where n is an integer of 1 or more). The Rth layer has neurons N1 (R) to neuron N<000着0012> (R) (where q is an integer of 1 or more). has.

[0060] Note that in FIG. 1A, neurons N1 (1) , neurons Np (1) , neuron N1 ( k-1) , Neuron N m (k-1) , neuron N1 (k) , Neuron N n (k) , Neuron N1 (R) , Neuron N q (R) In addition, the (k-1) layer neurons N i (k-1) (Here, i is an integer between 1 and m, inclusive.) Neuron N of layer k j ( k) (Here, j is an integer between 1 and n, inclusive.) is also illustrated, as are other neurons The diagram for "n" has been omitted.

[0061] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and each of the neurons This section describes the signals that are input and output in the ron. Note that in this explanation, the k-th layer of the neurons... N j (k) We are focusing on that.

[0062] Figure 1B shows neurons N in layer k. j (k) And, neuron N j (k) The signal input to And, neuron N j (k) This shows the signal output from and .

[0063] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1 ) z1 is the output signal of each of the following: (k-1) ~z m (k-1) However, neuron Nj ( k) It is outputting towards neuron N. j (k) is z1 (k-1) ~z m (k-1) z j (k) Generate z j (k) The (k+1)th is used as the output signal. Output is sent to each neuron in the layer (not shown in the diagram).

[0064] The signals that are input from neurons in the previous layer to neurons in the next layer are transmitted between those neurons. The strength of the synaptic connections (hereinafter referred to as the weighting coefficient) determines the transmission of signals. The degree is determined. In neural network 100, the output from the neurons of the previous layer The signal is multiplied by the corresponding weight coefficient and input to the neuron in the next layer. i is greater than or equal to m Let the following integers represent the (k-1)th neuron N i (k-1) and the k-th layer of neurons N j (k) The weight coefficient of the synapse between w i (k-1) j (k) When this is the case, the kth layer URON N j (k) The signal input to the device can be expressed by equation (1.1).

[0065]

number

[0066] In other words, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) of From each, the k-th layer neurons Nj (k) When a signal is transmitted to it, the signal z1 (k-1) to z m (k-1) is multiplied by the weight coefficients (w1 (k-1 ) j (k) to w m (k-1) j (k) ) corresponding to each signal. And for the neuron N in the k-th layer j (k) w1 (k-1) j (k) ·z1 (k-1) to w m (k-1) j (k) · z m (k-1) is input. At this time, the sum u j (k) of the signals input to the neuron N in the k-th layer is given by Equation (1.2). j (k)

[0067]

Equation

[0068] The neuron N j (k) generates an output signal z[[ID=Y]] j (k) in response to u j (k) . Here the output signal z j (k) from the neuron N j (k) is defined by the following equation.

[0069]

Equation

[0070] function f(u j (k) ) is an activation function in hierarchical neural networks. Step functions, linear ramp functions, sigmoid functions, etc. can be used. The tempering function may be the same for all neurons, or it may be different for all neurons. Therefore, the activation function of neurons may be the same or different in each layer.

[0071] By the way, the signals output by neurons in each layer may be analog values ​​or digital values. It can be treated as a value. As a digital value, for example, it can be a binary value or a ternary value. For analog values, activation functions include, for example, the linear ramp function and the sigmoid function. You can use this. In the case of a binary digital value, for example, the output can be -1 or 1, or 0. Alternatively, a step function set to 1 can be used. Also, the signals output by neurons in each layer It may have three or more values, in which case the activation function has three values, for example the outputs are -1, 0, or If you use a step function where is 1, or a step function where is 0, 1, or 2, good.

[0072] The neural network 100 is formed when an input signal is input to the first layer (input layer) So, in each layer from the first layer (input layer) to the last layer (output layer), the input is processed sequentially from the previous layer. Based on the transmitted signal, an output signal is generated using equations (1.1) to (1.3), and the output The operation involves outputting a force signal to the next layer. The signal output from the last layer (output layer) is then used to generate a new signal. This corresponds to the result calculated by RAL network 100.

[0073] <Example of arithmetic circuit configuration> Here, in the neural network 100 described above, equation (1.2) and equation (1 An example of an arithmetic circuit that can perform the calculation in 3) will be described. For example, the weight coefficients of the synaptic circuits in neural network 100 are binary. (A combination of "-1" and "+1", or a combination of "0" and "+1", etc.), or 3 The value is a combination of "-1", "0", and "1", and the neuron's activation function is binary. (A combination of "-1" and "+1", or a combination of "0" and "+1", etc.), or 3 This function will output a value (such as a combination of "-1", "0", and "1"). In books and other texts, the weight coefficient and the signal input from the previous layer neuron to the next layer neuron are used. Regarding the value (sometimes called the calculated value), one of them shall be called the first data. The other is referred to as the second data.

[0074] The calculation circuit 110 shown in Figure 2 includes, as an example, an array unit ALP, a circuit ILD, and a circuit W This is a semiconductor device having an LD, an XLD circuit, and an AFP circuit. The arithmetic circuit 110 is Neurons N1 in layer k in Figures 1A and 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1) Process, neuron N1 (k) No Destination neuron N n (k) The signal z1 is output from each of them. (k) ~z n (k) generate This is a circuit that does that.

[0075] Furthermore, the entirety or a part thereof of the arithmetic circuit 110 may be subjected to a neural network or It may be used for purposes other than AI. For example, calculations for graphics or scientific calculations. In such cases, when performing multiply-accumulate operations or matrix operations, the entire arithmetic circuit 110, It is also possible to use a part of it to perform processing. In other words, not only calculations for AI, but also general calculations. For calculations, the entirety or a part of the arithmetic circuit 110 may be used.

[0076] Circuit ILD is, for example, a wiring IL[1] through wiring IL[n] and wiring ILB[1] The circuit WLD is electrically connected to the wiring ILB[n]. For example, the wiring WL It is electrically connected to S[1] or wiring WLS[m]. Circuit XLD is, for example, wiring It is electrically connected to XLS[1] or wiring XLS[m]. Circuit AFP is an example. And, wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n], It is electrically connected to it.

[0077] <<Array Unit ALP>> The array unit ALP has, for example, m × n circuits MP. Within the ALP array section, they are arranged in an m x n matrix. In Figure 2, row i, column j (where i is an integer between 1 and m, and j is an integer between 1 and n). It is a number. The circuit MP located at ( ) is denoted as circuit MP[i,j]. However, in Figure 2 These are circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], and circuit MP[1,n Only the MP[m,n] circuit is shown; the MPC circuit is omitted from the illustration. They are doing it.

[0078] Circuit MP[i,j] is, for example, a combination of wiring IL[j], wiring ILB[j], and wiring W LS[i], wiring XLS[i], wiring OL[j], wiring OLB[j], and electrical Connected.

[0079] Circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k ) The weight coefficient between (sometimes referred to as either the first data or the second data. Here It has the function of holding (referred to as the first data). Specifically, the circuit MP[i,j] is Based on the first data (weighting coefficient) input from wiring IL[j] and wiring ILB[j] It stores information (e.g., potential, resistance, current, etc.). Also, the circuit MP[i,j] , Neuron N i (k-1) The signal z output from i (k-1) (First data or second data) The product of the other data (sometimes referred to as the second data, which we will call the second data here) and the first data. It has the function of outputting. For example, circuit MP[i,j] is wired XLS[i ] from the second data z i (k-1) When this is input, the product of the first data and the second data is Corresponding information (e.g., current, voltage, etc.), or related to the product of the first data and the second data. The collected information (e.g., current, voltage, etc.) is output to wiring OL[j] and wiring OLB[j]. The example shown is for the case where wiring IL[j] and wiring ILB[j] are present, One aspect of the present invention is not limited to this. Either wiring IL[j] or wiring ILB[j] Only one of them may be provided. Note that wiring OL[j] and wiring OLB[j] are provided. An example of a case where this is the case has been shown, but one aspect of the present invention is not limited thereto. Wiring OL[j Either ] or the wiring OLB[j] may be present.

[0080] <<Circuit ILD>> Circuit ILD is, for example, a wiring IL[1] through wiring IL[n] and wiring ILB[1] Through the wiring ILB[n], the same of circuit MP[1,1] to circuit MP[m,n] For each of these, the weight coefficient is the first data w1 (k-1) 1 (k) Or maybe lol m (k-1) n (k) It has a function to input corresponding information (e.g., electric potential, resistance value, current value, etc.). As a specific example, circuit ILD has a first weighting coefficient for circuit MP[i,j]. Data w i (k-1) j (k) Corresponding information (e.g., electric potential, resistance, or current value) These are supplied by wiring IL[j] and wiring ILB[j].

[0081] <<Circuit WLD>> Circuit WLD, for example, provides information corresponding to the first data input from circuit ILD (for example) It also has a function to select the circuit MP to which values ​​(such as potential, resistance, and current) will be written. For example, circuits MP[i,1] to MP[i,n] located in row i of the array ALP When writing information (e.g., potential, resistance, current, etc.) to the WLD circuit, for example, For example, the writing switching element included in circuit MP[i,1] to circuit MP[i,n] A signal is supplied to the wiring WLS[i] to turn the child on or off, except for row i. A potential that turns off the writing switching element included in the circuit MP is supplied to the wiring WLS. It is sufficient to supply it. Note that the example shown is for the case where wiring WLS[i] is installed, but this invention The embodiment is not limited to this. For example, the wiring WLS[i] is arranged as multiple wirings. That's fine.

[0082] <<Circuit XLD>> Circuit XLD is, for example, connected to circuit M via wiring XLS[1] to wiring XLS[m]. For each of P[1,1] or the circuit MP[m,n], neuron N1 (k-1) No Destination neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~ z m (k-1) It has the function of supplying. Specifically, circuit XLD has the function of supplying circuit MP[i,1 For a circuit MP[i,n], neuron N i (k-1) The second day output from Ta z i (k-1) The corresponding information (e.g., potential, current value, etc.) is stored in the wiring XLS[i]. Therefore, it is supplied. Note that the example shown is for the case where wiring XLS[i] is present, but this invention... One aspect of this is not limited to this. For example, the wiring XLS[i] can be arranged as multiple wirings. You may do so.

[0083] <<Circuit AFP>> Circuit AFP may include, for example, circuits ACTF[1] to ACTF[n]. Circuit ACTF[j] is, for example, a combination of wiring OL[j] and wiring OLB[j]. It is electrically connected to the following. Circuit ACTF[j] is, for example, connected to wiring OL[j]. Depending on the information input from the wiring OLB[j] (e.g., potential, current value, etc.) It generates a signal. For example, the input from wiring OL[j] and wiring OLB[j]. The information (for example, electric potential or current value) is compared, and a signal is generated according to the comparison result. This generates a signal. The signal is sent to neuron N j (k) The signal z output from j (k) This corresponds to In other words, circuits ACTF[1] to ACTF[n] are, for example, the two mentioned above. It functions as a circuit that performs calculations on the activation function of a neural network. However, this invention The embodiment is not limited to this. For example, circuits ACTF[1] to ACTF[n] are It may also have a function to convert analog signals to digital signals. Or, for example, a circuit ACTF[1] or ACTF[n] is a function that amplifies and outputs an analog signal, that is, It may also have a function to convert the output impedance. Note that the ACTF circuit is arranged While an example of a case where this is the case has been shown, the present invention is not limited to this. Circuit ACTF It is not necessary for it to be placed there.

[0084] Circuits ACTF[1] to ACTF[n] have, as an example, the circuit configuration shown in Figure 3A. This is possible. Figure 3A shows an example of input from wiring OL[j] and wiring OLB[j]. Depending on the current applied, the signal z j (k) This is a circuit that generates [something]. Specifically, Figure 3A shows: The output signal z is represented by two values. j (k) This shows an example of an activation function arithmetic circuit that outputs [the specified value]. It is.

[0085] In Figure 3A, the circuit ACTF[j] consists of resistor RE, resistor REB, and comparator CM. It has P. Resistor elements RE and REB have the function of converting current to voltage. Therefore, any element or circuit that has the function of converting electric current into voltage is not limited to resistive elements. It is not done. Wiring OL[j] is the first terminal of the resistor RE and the first input terminal of the comparator CMP. Electrically connected, the wiring OLB[j] is connected to the first terminal of the resistive element REB and the comparator CM. It is electrically connected to the second input terminal of P. Also, the second terminal of the resistor RE is wired The second terminal of the resistor REB is electrically connected to VAL, and the wiring VAL is electrically connected to VAL. It is connected to the same wiring. It may be connected to the same wire. Alternatively, it may be connected to another wire with the same potential.

[0086] It is preferable that the resistance values ​​of resistor element RE and resistor element REB are equal to each other. For example, the difference in resistance values ​​between resistor RE and resistor REB should be within 10%, which is preferable. Ideally, it should be within 5%. However, in one aspect of the present invention, this is not the case. Not limited to. Depending on the circumstances, or depending on the situation, resistor element RE, resistor element REB Each resistance value may be different from the others.

[0087] Wiring VAL functions, for example, as wiring that provides a constant voltage. For example, VDD is a high-level potential, VSS is a low-level potential, and GND is the ground potential. ) and so on. Furthermore, the constant voltage can be set appropriately according to the configuration of the circuit MP. It is preferable to do so. Furthermore, for example, a pulse signal, rather than a constant voltage, is supplied to the wiring VAL. It's okay if it's not allowed.

[0088] The voltage between the first and second terminals of the resistor RE is the voltage from the wire OL[j]. It is determined according to the current. For this reason, the resistance value of the resistive element RE is set at the first input terminal of the comparator CMP. A voltage corresponding to the current is input. Similarly, the first and second terminals of the resistor REB and The voltage between them is determined by the current flowing from the wiring OLB[j]. Therefore, comparator CM The second input terminal of P receives the resistance value of the resistor REB and a voltage corresponding to the current.

[0089] The comparator CMP, for example, is input to the first input terminal and the second input terminal respectively. A device that compares voltages and outputs a signal from the output terminal of a comparator CMP according to the comparison result. It has the ability to... For example, the comparator CMP... When the voltage input to the child is high, a high-level potential is output from the output terminal of the comparator CMP. If the voltage input to the first input terminal is higher than the voltage input to the second input terminal, low-level The bell potential can be output from the output terminal of the comparator CMP. In other words, the comparator CMP The potential output from the output terminal can be either a high-level potential or a low-level potential, therefore the circuit The output signal z of ACTF[j] j (k) It can be represented as a binary value. For example, comparison The high-level potential and low-level potential output from the output terminal of the CMP unit are, respectively, the output signals. z j (k) It can be used to correspond to "+1" and "-1". Also, in some cases, The high-level potential and low-level potential output from the output terminal of the comparator CMP are, respectively, the output signal z j (k)It can also be represented as "+1" and "0".

[0090] Furthermore, in the circuit ACTF[j] in Figure 3A, resistors RE and REB were used, Any element or circuit that has the function of converting electric current into voltage is not limited to a resistive element. Therefore, the resistors RE and REB in the circuit ACTF[j] in Figure 3A are separate circuit elements. It can be replaced with a child. For example, the circuit ACTF[j] shown in Figure 3B is the same as the circuit in Figure 3A. Resistors RE and REB included in path ACTF[j] are capacitive elements CE and capacitive elements This circuit replaces CEB and performs almost the same operation as the ACTF[j] circuit in Figure 3A. This is possible. Note that the capacitance values ​​of the capacitive elements CE and CEB are relative to each other. It is preferable that they be equal. For example, the respective capacitance values ​​of capacitive element CE and capacitive element CEB. The difference should preferably be within 10%, and more preferably within 5%. However, the present invention is not limited to this aspect. A circuit for initializing the charged charge may be provided. For example, in parallel with the capacitive element CE, A switch may be provided. That is, the second terminal of the switch is connected to the wiring VAL. The first terminal of the switch is connected to the first terminal of the capacitive element CE, the wiring OL[j], and the comparator. It may be connected to the first input terminal of the CMP. Alternatively, the second terminal of the switch may be connected to wiring V AL is connected to a different wiring, and the first terminal of the switch is connected to the first terminal of the capacitive element CE, and the wiring OL[j] and the first input terminal of the comparator CMP may also be connected. Also, see Figure 3 The circuit ACTF[j] shown in C includes the resistor RE, which is included in the circuit ACTF[j] in Figure 3A. This circuit replaces the resistor REB with diodes DE and DEB. The circuit ACTF[j] in Figure 3A can perform almost the same operation. Diode element D E. The orientation of diode element DEB (the connection point between the anode and cathode) is determined by the power of the wiring VAL. It is desirable to adjust the size as appropriate depending on the magnitude of the position.

[0091] Furthermore, the comparator CMP included in the ACTF[j] circuit in Figures 3A to 3C is, as an example, It can be replaced with an operational amplifier OP. The circuit ACTF[j] shown in Figure 3D is shown in Figure 3 The circuit diagram shows the ACTF[j] circuit A with the comparator CMP replaced by an operational amplifier OP. ru.

[0092] Also, even if switches S01a and S01b are added to the ACTF[j] circuit in Figure 3B Good. As a result, the circuit ACTF[j] is determined by the capacitance elements CE and CEB respectively. It is possible to maintain a potential corresponding to the current input from wiring OL[j] and wiring OLB[j]. Yes. As an example of a specific circuit, as shown in Figure 3E, the first of switch S01a A wire OL[j] is electrically connected to the terminal, and a capacitive element CE is connected to the second terminal of switch S01a. The first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP, and the first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP. A wiring OLB[j] is electrically connected to terminal 1, and a capacitive element is connected to terminal 2 of switch S01b. The configuration should be such that the first terminal of the CEB is electrically connected to the second input terminal of the comparator CMP. i. In the ACTF[j] circuit of Figure 3E, the first and second input terminals of the comparator CMP are respectively When the potentials of wiring OL[j] and wiring OLB[j] are input, switch S01a, switch This can be done by turning on each of the S01b switches. By turning off switches S01a and S01b respectively, a comparison can be made. The potentials input to the first and second input terminals of the CMP are measured by the capacitive element CE. It can be held in the quantitative element CEB. Note that switches S01a and S01b are used. For example, applying an electrical switch such as an analog switch or a transistor. This is possible. Also, as switches S01a and S01b, for example, mechanical switches A switch may be applied. Furthermore, transistors may be applied to switches S01a and S01b. When used, the transistor is an OS transistor, or a silicon transistor in the channel formation region. It can be a transistor having a silicon (hereinafter referred to as a Si transistor). Alternatively, control the duration for which switches S01a and S01b remain in the ON state. By doing so, the voltage values ​​of the capacitive elements CE and CEB can be controlled. For example If the current flowing through capacitive elements CE and CEB is large, switch S01a By shortening the time that each of the switches S01b is kept in the ON state, This prevents the voltage values ​​of the capacitance element CE and the capacitance element CEB from becoming too high.

[0093] Furthermore, the comparator CMP included in the ACTF[j] circuit in Figures 3A to 3C and 3E is, for example, For example, it can be a chopper-type comparator. The comparator CMP shown in Figure 3F is a chopper This shows the type of comparator, and the comparator CMP is for switch S02a, switch S02b, switch It has a switch S03, a capacitive element CC, and an inverter circuit INV3. Switch S02b and Switch S03 are the same as the aforementioned Switch S01a and Switch S Similar to 01b, transistors such as mechanical switches, OS transistors, and Si transistors. It can be made into a zista.

[0094] The first terminal of switch S02a is electrically connected to terminal VinT, and switch S02b The first terminal of the switch S02a is electrically connected to terminal VrefT, and the second terminal of the switch S02a is The second terminal of switch S02b is electrically connected to the first terminal of capacitive element CC. The second terminal of the capacitive element CC is connected to the input terminal of the inverter circuit INV3 and the terminal of the switch S03. Terminal 1 is electrically connected to the output of the inverter circuit INV3. Terminal VoutT is the output of the inverter circuit INV3. The power terminal is electrically connected to the second terminal of switch S03.

[0095] Terminal VinT functions as a terminal for inputting the input potential to comparator CMP, and terminal V refT functions as a terminal for inputting a reference potential to the comparator CMP, and terminal Vout T functions as a terminal for outputting the output potential from the comparator CMP. Note that terminal Vi nT corresponds to either the first or second terminal of the comparator CMP in Figures 3A to 3C and 3E. The terminal VrefT is the first or second terminal of the comparator CMP in Figures 3A to 3C and 3E. It can respond to the other side of the child.

[0096] The circuit ACTF[j] in Figures 3A to 3E is an output signal z represented by a binary value. j (k) This is an activation function arithmetic circuit that outputs z, but the circuit ACTF[j] is the output signal z j (k) of The configuration may also output three or more values, or as analog values.

[0097] Figures 4A to 4F show the current input from wiring OL[j] and wiring OLB[j]. , signal z j (k)This is a circuit that generates an output signal z, which is represented by three values. j (k) Leave An example of an operational circuit for the activation function is shown.

[0098] The circuit ACTF[j] shown in Figure 4A consists of resistor RE, resistor REB, and comparator CMPa , and has a comparator CMPb. Wiring OL[j] is connected to the first terminal of the resistor RE and comparator CM The first input terminal of Pa is electrically connected to the wiring OLB[j], and the first resistor of REB The terminal is electrically connected to the first input terminal of comparator CMPb. The second input terminal of Pa and the second input terminal of comparator CMPb are electrically connected to the wiring VrefL. It is connected to the following. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL. The second terminal of resistor REB is electrically connected to wiring VAL.

[0099] Wiring VrefL is constant voltage V ref It functions as wiring that gives V ref For example, It is preferable that it be above GND and below VDD. Also, depending on the situation, V ref , GN The potential may be less than D, or higher than VDD. ref The comparator CMPa, ratio It is treated as the reference potential (comparison potential) in comparator CMPb.

[0100] The voltage between the first and second terminals of the resistor RE is the voltage from the wire OL[j]. It is determined according to the current. For this reason, the resistance of the resistive element RE is connected to the first input terminal of the comparator CMPa. A voltage corresponding to the value and current is input. Similarly, the first and second terminals of the resistor REB The voltage between them is determined by the current flowing from the wiring OLB[j]. Therefore, comparison The first input terminal of the CMPb device receives the resistance value of the REB resistor and a voltage corresponding to the current. It will be done.

[0101] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal, respectively. Then, depending on the comparison result, a signal is output from the output terminal of the comparator CMPa. For example, The comparator CMPa is determined by the voltage input to the second input terminal being greater than the voltage input to the first input terminal. V ref When the ) is high, the high-level potential is output from the output terminal of the comparator CMPa, and the second input Voltage (V) input to the power terminal ref When the voltage input to the first input terminal is higher than ) The low-level potential can be output from the output terminal of the comparator CMPa.

[0102] Comparator CMPb, like comparator CMPa, uses the first input terminal and the second input terminal respectively. The input voltage is compared, and according to the comparison result, a signal is sent from the output terminal of the comparator CMPb. It outputs a number. For example, comparator CMPb outputs a number that is higher than the voltage input to the first input terminal than the voltage input to the second input terminal. Voltage (V) input to the power terminal ref When the high level potential is high, the output of comparator CMPb The voltage (V) output from the power terminal and input to the second input terminal is measured. ref ) is entered into the first input terminal When the applied voltage is high, the low-level potential is output from the output terminal of the comparator CMPb. It is possible.

[0103] At this time, the potentials output from the respective output terminals of comparator CMPa and comparator CMPb Accordingly, the three-value output signal z j (k) It can represent the output of comparator CMPa. For example, the output of comparator CMPa A high-level potential is output from the power terminal, and a low-level potential is output from the output terminal of comparator CMPb. If this occurs, the output signal z j (k) Set to "+1", and the low level is output from the output terminal of the comparator CMPa. If a low potential is output and a high-level potential is output from the output terminal of comparator CMPb, the output signal z j (k) Set to "-1", and a low-level potential is output from the output terminal of the comparator CMPa. If a low-level potential is output from the output terminal of comparator CMPb, the output signal z j (k) teeth It can be set to "+0".

[0104] Furthermore, the ACTF[j] circuit is not limited to the circuit configuration shown in Figure 4A, but can be adapted depending on the situation. It can be changed. For example, in the circuit ACTF[j] in Figure 4A, the comparator CMPa If you want to combine the two output results of the comparator CMPb into a single signal, use the ACTF circuit. A conversion circuit TRF can be provided at [j]. The circuit ACTF[j] in Figure 4B is the same as the circuit in Figure 4A. This is an example configuration in which a conversion circuit TRF is provided to ACTF[j], and the comparators CMPa and CMPb Each output terminal is electrically connected to the input terminal of the conversion circuit TRF. A concrete example of RF is a digital-to-analog conversion circuit (in this case, the signal z j (k) is A This will be an analog value. ) (This can be expressed as follows.)

[0105] Furthermore, for example, in Figure 4A, the second inputs of comparators CMPa and CMPb The wiring VrefL that is electrically connected to the power terminal is connected to the wiring Vref1L and Vref2L. They can be replaced with separate wires. Circuit ACTF[j] in Figure 4C is the same as circuit ACTF in Figure 4A. The second terminal of comparator CMPa included in [j] is wired Vref1, not wired VrefL. Electrically connected to L, the second terminal of comparator CMPb is wired Vref, not wired VrefL. It is configured to be electrically connected to 2L. Wiring Vref1L and Vref2L are input. By setting the potentials to be applied to each other to different values, the comparators CMPa and CMPb The reference potentials can be set separately.

[0106] Furthermore, for example, an amplifier circuit is a configuration different from the ACTF[j] circuit shown in Figures 4A to 4C. Alternatively, an impedance conversion circuit may be used. For example, the circuit AC shown in Figure 4D. TF[j] can be applied to the circuit AFP of the calculation circuit 110 in Figure 2. Circuit in Figure 4D ACTF[j] refers to the resistor RE, the resistor REB, the operational amplifier OPa, and the operational amplifier OP. It has b and functions as an amplification circuit.

[0107] Wiring OL[j] connects the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa. Electrically connected, the wiring OLB[j] is connected to the first terminal of the resistive element REB and the op-amp O It is electrically connected to the non-inverting input terminal of Pb. Also, it is connected to the inverting input of the operational amplifier OPa. The terminal is electrically connected to the output terminal of op-amp OPa and to the inverting input of op-amp OPb. The terminal is electrically connected to the output terminal of the operational amplifier OPb. Furthermore, the resistor RE The second terminal is electrically connected to the wiring VAL, and the second terminal of the resistor REB is connected to the wiring VAL. It is electrically connected to it.

[0108] In other words, the operational amplifiers OPa and O are included in the ACTF[j] circuit in Figure 4D. Pb is configured as a voltage follower. This allows the op-amp OPa to The potential output from the output terminal is the same as the potential input to the non-inverting input terminal of the operational amplifier OPa. They become almost equal, and the potential output from the output terminal of the op-amp OPb is, This becomes approximately equal to the potential input to the non-inverting input terminal. In this case, the output signal z j (k) teeth The two analog values ​​are output from the ACTF[j] circuit. Note that the operational amplifier OPa Connect the output terminal of the op-amp OPb to the input terminal of the comparator CMP, respectively. You may continue. Then, take the output from comparator CMP as the output signal z j (k) That is also acceptable.

[0109] Furthermore, for example, as a configuration different from the ACTF[j] circuit in Figures 4A to 4D, an integrating circuit A current-voltage conversion circuit may also be used. Furthermore, an operational amplifier can be used to create an integrating circuit and a current converter. A voltage conversion circuit may be constructed. As an example, the circuit ACTF[j] shown in Figure 4E is shown in Figure 2. This can be applied to the circuit AFP of the arithmetic circuit 110. The circuit ACTF[j] in Figure 4E is It has operational amplifiers OPa and OPb, and load elements LEa and LEb.

[0110] Wiring OL[j] connects to the first input terminal of the operational amplifier OPa (e.g., the inverting input terminal) and the negative The first terminal of the charge element LEa is electrically connected to the OLB[j] wiring, and the op-amp OP The first input terminal of b (for example, the inverting input terminal) and the first terminal of the load element LEb are electrically connected. They are connected. Also, the second input terminal of the op-amp OPa (for example, the non-inverting input terminal) is , electrically connected to the wiring Vref1L, and the second input terminal of the op-amp OPb (for example, non The inverting input terminal is electrically connected to wiring Vref2L. The second of the load element LEa The terminal is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is It is electrically connected to the output terminal of the operational amplifier OPb.

[0111] Note that the wiring Vref1L and Vref2L here have the same voltage, or different voltages. It functions as wiring that supplies voltage. Therefore, wiring Vref1L, wiring Vref2 L can be combined into a single wire.

[0112] In the circuit ACTF[j] in Figure 4E, the load elements LEa and LEb are, for example, For example, they can be resistive elements or capacitive elements. In particular, load elements LEa and load elements LEb By using a capacitive element, the operational amplifier OPa and load element LEa, the operational amplifier OPb and the load element LEb each function as an integrating circuit. In other words, the wiring OL[j] Alternatively, depending on the amount of current flowing through the wiring OLB[j], each capacitive element (load element LEa Charge is stored in LEb. In other words, it flows from wiring OL[j] and wiring OLB[j]. The current is converted into a voltage by an integrating circuit, and the integrated current is then converted into a signal z j (k) year The output is then connected to the output terminals of the operational amplifier OPa and the output terminals of the operational amplifier OPB. They may be connected to the input terminals of the comparator CMP. And the output from the comparator CMP output signal z j (k) This is also acceptable. Note that the capacitive elements of load element LEa and load element LEb A circuit may be provided to initialize the charge accumulated in the load element LEa( A switch may be provided in parallel with the capacitive element. That is, the second terminal of the switch is The output terminal of the op-amp OPa is connected, and the first terminal of the switch is wired OL[j], Furthermore, it may be connected to the first input terminal of the operational amplifier OPa (for example, the inverting input terminal). stomach.

[0113] Furthermore, in the circuit ACTF[j] in Figure 4E, from wiring OL[j] and wiring OLB[j] If you want to convert the flowing current into a voltage and output it, the load elements LEa and LEb are as follows: Besides capacitive elements, resistive elements can also be used.

[0114] Furthermore, for example, as a configuration different from the ACTF[j] circuit in Figures 4A to 4E, Figure 4F shows The circuit ACTF[j] shown can be applied to the circuit AFP of the calculation circuit 110 in Figure 2. The circuit ACTF[j] in Figure 4F consists of resistor RE, resistor REB, and analog-to-digital converter. It has an ADCa circuit and an ADCb analog-to-digital conversion circuit.

[0115] Wiring OL[j] connects the input terminal of the analog-to-digital conversion circuit ADCa to the resistor RE. The first terminal is electrically connected to the wiring OLB[j], and the analog-to-digital conversion circuit AD The input terminal of Cb is electrically connected to the first terminal of the resistive element REB. The second terminal of RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is connected to the wiring It is electrically connected to VAL.

[0116] In the circuit ACTF[j] in Figure 4F, the current flows from wiring OL[j] and wiring OLB[j]. The potential of the first terminals of resistor RE and resistor REB is determined according to the current. The ACTF[j] circuit converts the analog potential to an analog-to-digital value. The ADCa and ADCb lines produce binary or triple or more (e.g., 256 values) digital signals. Convert to z value and the signal z j (k) It has the function to output as [a specific format].

[0117] Note that the resistors RE and REB shown in Figures 4A to 4F are the same as those in Figures 3B and 3C. Similarly, capacitive element CE, capacitive element CEB, or diode element DE, diode element DE It can be replaced with B. In particular, the resistive element RE shown in Figures 4A to 4F, resistive element If REB is replaced with capacitive elements CE and CEB, the switch will be similar to that shown in Figure 3E. By providing switch S01a and switch S01b, wiring OL[j] and wiring OLB[j] It can retain the input potential.

[0118] Note that the calculation circuit 110 in Figure 2 is configured according to the circuit configuration of circuit MP[i,j] The number of wires electrically connected to i,j can be changed. For example, in Figure 2 In the arithmetic circuit 110, the wiring WLS[i ] can be one or more wires. Also, for example, in circuit MP[i,j] The electrically connected wiring XLS[i] can consist of one or more wires. .

[0119] <<Circuit MP>> Next, we will describe an example of the configuration of the circuit MP[i,j] included in the arithmetic circuit 110.

[0120] Figure 5A shows an example configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 110. A path MP[i,j] includes, for example, circuit MC and circuit MCr. In circuit MCr, the weight coefficient and the input signal (calculated value) of the neuron are used in circuit MP. This is a circuit that calculates the product of [the two numbers]. Circuit MC has the same configuration as circuit MCr, or a different configuration from circuit MCr. This configuration is possible. Therefore, to distinguish the circuit MCr from the circuit MC, The letter "r" is added to the number. Also, the symbols of the circuit elements described later, which are included in circuit MCr, It also has "r" added to it.

[0121] For example, a circuit MC has a retaining part HC, and a circuit MCr has a retaining part HCr. The retaining part HC and the retaining part HCr each contain information (e.g., potential, resistance, current, etc.). It has the function of holding the first data w set in circuit MP[i,j]. i (k -1) j (k) This refers to the information held in the holding part HC and the holding part HCr, respectively (for example, electricity It is determined according to the position, resistance value, current value, etc. Therefore, the retaining part HC and retaining part HCr Each of these is the first data w i (k-1) j (k) Each piece of information corresponding to (e.g., electric potential, resistance) Electrically connected to wiring IL[j] and wiring ILB[j] that supply values ​​(current values, etc.) Yes, they are.

[0122] Wiring WL[i] shown in Figure 5A corresponds to wiring WLS[i] in Figure 2. Wiring W L[i] is electrically connected to the holding part HC and the holding part HCr, respectively. Circuit M The first data w is assigned to each of the retaining part HC and retaining part HCr contained in P[i,j]. i (k -1) j (k)When writing information corresponding to (for example, electric potential, resistance value, current value, etc.), By supplying a predetermined potential to the line WL[i], the wiring IL[j] and the retaining part HC are guided. Set to a conductive state, and make the wiring ILB[j] and the retaining part HCr conductive. Then, wiring I The first data w is assigned to L[j] and ILB[j] respectively. i (k-1) j (k) The electric potential corresponding to By supplying such a potential, the holding part HC and the holding part HCr are each supplied with the corresponding potential. It can be input. Then, a predetermined potential is supplied to the wiring WL[i], and the wiring IL[j The wire ILB[j] and the retaining part HC are made non-conductive, and the wiring ILB[j] and the retaining part HCr are made non-conductive. Set to the state. Then, the first data w is set for each of the holding part HC and the holding part HCr. i (k-1 ) j (k) Each potential and other parameters corresponding to the current are maintained.

[0123] For example, the first data w i (k-1) j (k) The three values ​​are "-1", "0", and "1". Let's consider the case where we choose either one. First data w i (k-1) j (k) If it is "1", here is an example Therefore, a high-level potential is maintained in the holding part HC, and a low-level potential is maintained in the holding part HCr. Also, the first data w i (k-1) j (k) If it is "-1", as an example, the holding part H A low-level potential is maintained in C, and a high-level potential is maintained in the holding part HCr. And, Day 1 Ta lol i (k-1)j (k) If it is "0", for example, a low-level potential is present in the holding part HC. It maintains a low potential in the holding part HCr. As another example, the first data w i (k-1) j (k) This is an analog value, specifically a "negative analog value", "0", or Let's consider the case where it takes a "positive analog value". First data w i (k-1) j (k) is “positive In the case of an "analog value," for example, a high level of analog potential is held in the holding part HC. The holding part HCr maintains a low level potential. Also, the first data w i (k-1) j (k) but" In the case of a "negative analog value," as an example, a low-level potential is held in the holding part HC, and the holding part A high level of analog potential is maintained in HCr. And the first data w i (k-1) j (k ) If it is "0", as an example, a low-level potential is maintained in the holding part HC, and the holding part HCr It maintains a low level potential. Note that the analog value is a multi-bit (multi-level) digital value. This is also acceptable. For example, the first data w i (k-1) j (k) However, “1”, If the values ​​are "2" and "3", as an example, the retaining part HC will correspond to "1", "2", and "3". It maintains a high potential with a variable potential, and maintains a low potential in the holding part HCr. , 1st data w i (k-1) j (k)For example, if the values ​​are "-1", "-2", and "-3", The holding part HC maintains a low level potential, and the holding part HCr has "-1" and "-2" It maintains high levels of potential corresponding to the absolute values ​​of "-3", which are "1", "2", and "3". And then, the first data w i (k-1) j (k) If it is "0", as an example, the holding part A low potential is maintained in the HC, and a low potential is maintained in the holding part HCr.

[0124] As another example, the circuit MC stores information (for example, potential, resistance value) in the holding part HC. Current, voltage, etc., according to the current value, etc., are transmitted to one of the wiring OL[j] or wiring OLB[j]. It has a function to output, and the circuit MCr has a function to output information (for example, potential, Current, voltage, etc., according to resistance value, current value, etc., are measured in wiring OL[j] or wiring OLB[j]. It has the function of outputting to the other side. For example, when a high level potential is held in the holding part HC. In total, the circuit MC outputs a current with a first current value, and a low-level potential is maintained in the holding part HC. If present, the circuit MC shall output a current with a second current value. Similarly, the holding part HC When a high-level potential is maintained at r, the circuit MCr outputs a current with a first current value. When a low-level potential is maintained in the holding part HCr, the circuit MCr is a current with a second current value. The output shall be as follows. Note that the magnitudes of the first current value and the second current value are as follows: The configuration of the circuit MCr, holding part HC, holding part HCr, etc., and the first data w i (k-1) j ( k) It is determined by the value of . For example, if the first current value is greater than the second current value. It may also be small. Furthermore, either the first current value or the second current value may be zero current. Sometimes the current value is 0. Or, there is a current with a first current value and a current with a second current value. And the direction of current flow can also be different. In particular, for example, the first data w i (k-1) j (k) If it takes one of the three values ​​"-1", "0", or "1", then the first current value or the second current value It is preferable to configure circuit MC and circuit MCr such that one of the current values ​​is 0. , 1st data w i (k-1) j (k) This is an analog value, for example, a "negative analog value", "0 ", or, if it takes a "positive analog value", then the first current value or the second current value as well. For example, it can take analog values.

[0125] Furthermore, in this specification, etc., the information held in the retaining part HC and the retaining part HCr (for example) Currents, voltages, etc., corresponding to potential, resistance, current, etc., are treated as positive currents, voltages, etc. It may also be a negative current or voltage, or a mixture of both positive and negative. For example, the information held in the aforementioned "holding unit HC" (for example, potential, resistance, current, etc.) The system outputs the corresponding current, voltage, etc., to either wiring OL[j] or wiring OLB[j]. The circuit MCr has a function, and the information held in the holding part HCr (e.g., potential, resistance value, electric current) is stored in the holding part HCr. Current, voltage, etc., according to the current value (such as current value), are output to the other side of wiring OL[j] or wiring OLB[j]. The phrase "has the function of exerting power" means "information held in the holding part HC (e.g., potential, resistance)" Current, voltage, etc., according to resistance value, current value, etc., of wiring OL[j] or wiring OLB[j] It has a function of discharging from one side, and the circuit MCr is charged according to the potential held in the holding part HCr. The description states that it has the function of discharging current from the other of wiring OL[j] or wiring OLB[j]. It can be rephrased as "to include" or "to carry."

[0126] The wiring X1L[i] and wiring X2L[i] shown in Figure 5A correspond to the wiring XLS in Figure 2. This corresponds to [i]. Note that the second data z is input to circuit MP[i,j]. i (k-1) teeth For example, the potential and current of wiring X1L[i] and wiring X2L[i], etc. It is determined by the following. Therefore, for example, the circuit MC and circuit MCr have wiring X1L[ i] and wiring X2L[i], the second data z i (k-1) Each potential corresponding to the input is input. It can be done.

[0127] Circuit MC is electrically connected to wiring OL[j] and wiring OLB[j], and circuit MC r is electrically connected to wiring OL[j] and wiring OLB[j]. Circuit MC and Circuit MCr is, for example, a circuit that receives power input to wiring X1L[i] and wiring X2L[i]. Depending on the position, the first data w is set to wiring OL[j] and wiring OLB[j]. i (k-1) j (k ) and the second data z i (k-1) It outputs current, potential, etc., corresponding to the product of the two. Specific examples and Therefore, the output destinations of the current from circuits MC and MCr are wires X1L[i] and X2L[i]. Determined by the potential of ]. For example, circuit MC and circuit MCr are each... The current output from C flows to either wiring OL[j] or wiring OLB[j], and the circuit MCr A circuit configuration such that the current output from one wire flows to the other wire of either wire OL[j] or wire OLB[j]. This is the result. In other words, the currents output from circuit MC and circuit MCr are, The current flows through different wiring, not the same wiring. For example, the circuit MC and the circuit In cases where no current flows from circuit MCr to either wiring OL[j] or wiring OLB[j] be.

[0128] For example, the second data z i (k-1) The value is one of the three values: "-1", "0", or "1". Let's consider the case where, for example, the second data z i (k-1) If it is "1", then circuit MP is The circuit MC and wiring OL[j] are in a conductive state, and the circuit MCr and wiring OLB[j] This is set to a conductive state. Also, for example, the second data z i (k-1) If it is "-1", then The path MP is conductive between circuit MC and wiring OLB[j], and between circuit MCr and wiring OL[ The connection between [j] and [j] is made conductive. For example, the second data z i (k-1) If it is "0", The currents output by circuits MC and MCr are measured in wiring OL[j] and wiring OLB[j]. To prevent the current from flowing to either of them, circuit MP is positioned between circuit MC and wiring OL[j], Furthermore, the circuit MC and the wiring OLB[j] are made non-conductive, and the circuit MCr and the wiring OL[j The connection between [ ] and the circuit MCr and the wiring OLB[j] is made non-conductive.

[0129] An example of combining the above actions is shown below. Data 1 w i (k-1) j (k) is "1" In this case, the circuit MC outputs current, and the first data w i (k-1) j (k) is "-1" In this case, the circuit MCr outputs current. Then, the second data z i (k-1) is “1” In this case, the circuit MC and wiring OL[j], and the circuit MCr and wiring OLB[j] A conductive state is established between them. Second data z i (k-1) If it is "-1", then the circuit MC and Conduction occurs between the wiring OLB[j] and the circuit MCr and the wiring OL[j]. Based on the above, the first data w i (k-1) j (k) and the second data z i (k-1) product If the value is positive, current is output to the wiring OL[j]. First data w i (k-1) j (k) and the second data z i (k-1) If the product of the two values ​​is negative, then current flows through the wiring OLB[j]. Output. First data w i (k-1) j (k) and the second data z i (k-1) The product is zero In the case of this value, no current is output to either wire.

[0130] To illustrate the above example with a concrete example, the first data w i (k-1) j (k) is “1” There is, the second data z i (k-1) If it is "1", for example, from circuit MC to wiring OL A current I1[i,j] with a first current value flows through [j], and the circuit MCr is connected to the OLB[j]. A current I2[i,j] with a second current value flows through it. At this time, the magnitude of the second current value is one For example, it is zero. In other words, strictly speaking, the current from circuit MCr to wiring OLB[j] It won't flow. First data lol i (k-1) j (k) The second data z is "-1", and i (k -1) If it is "1", for example, a second current value is transmitted from circuit MC to wiring OL[j]. A current I1[i,j] flows, and a current I2 with a first current value flows from the circuit MCr to the wiring OLB[j]. [i,j] flows. In this case, the magnitude of the second current value is, for example, zero. More precisely, no current flows from the circuit MC to the wiring OL[j]. (First data w) i (k- 1) j (k) The second data z is "0". i (k-1) If it is "1", then circuit M A current I1[i,j] with a second current value flows from C to wiring OL[j], and from circuit MCr A current I2[i,j] with a second current value flows through line OLB[j]. At this time, the second current value The magnitude of is, for example, zero. In other words, strictly speaking, the wiring OL[j No current flows through ], and no current flows from circuit MCr to wiring OLB[j].

[0131] Also, the first data w i (k-1) j (k) The second data z is "1", and i (k-1 )If it is "-1", then a current I1[ with the first current value is sent from the circuit MC to the wiring OLB[j] Currents i and j flow, and a second current I2[i, j] with a second current value is drawn from circuit MCr to wiring OL[j]. A current flows. At this time, the magnitude of the second current value is, for example, zero. In other words, strictly speaking In this case, no current flows from circuit MCr to wiring OL[j]. First data w i (k-1) j ( k) The second data z is "-1", and i (k-1) If it is "-1", then the circuit MC or A current I1[i,j] with a second current value flows through the wiring OLB[j], and the wiring from the circuit MCr A current I2[i,j] with a first current value flows through OL[j]. At this time, the second current value For example, the size is zero. In other words, strictly speaking, the wiring from the circuit MC to the OLB[j] No current flows through it. First data w i (k-1) j (k) The second data z is "0". i (k-1) If it is "-1", then the circuit MC has a second current value in the wiring OLB[j]. A current I1[i,j] flows, and a second current I2 with a specific value flows from the circuit MCr to the wiring OL[j]. Currents [i, j] flow. In this case, the magnitude of the second current is, for example, zero. More precisely, no current flows from circuit MC to wiring OLB[j], and no current flows from circuit MCr to wiring O No current flows through L[j].

[0132] Also, the second data z i (k-1) If it is "0", one example is the circuit MC and wiring. The connection between OL[j] and the circuit MC and the wiring OLB[j] becomes non-conductive. Furthermore, between circuit MCr and wiring OL[j], and between circuit MCr and wiring OLB[j] It becomes non-conductive. Therefore, the first data w i (k-1) j (k) Whatever the value No current is output from circuits MC and MCr to wiring OL[j] and wiring OLB[j]. stomach.

[0133] Thus, as an example, the first data w i (k-1) j (k) and the second data z i (k -1) If the product of the two takes a positive value, then either circuit MC or circuit MCr is used for wiring. Current flows through OL[j]. At this time, the first data w i (k-1) j (k) In the case where the value is positive In this case, current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) If the value is negative, current flows from circuit MCr to wiring OL[j]. On the other hand, the first data w i (k-1) j (k) and the second data z i (k-1) If the product of these two values ​​is negative, then Current flows through the wiring OLB[j] from either the path MC or the circuit MCr. At this time, First data w i (k-1) j (k) If the value is positive, the wiring OLB[j] from the circuit MC Current flows through it, and the first data w i (k-1) j (k)If the value is negative, then from the circuit MCr Current flows through wiring OLB[j]. Therefore, multiple circuits M connected to wiring OL[j] are affected. The sum of the currents output from C or circuit MCr will flow through wiring OL[j]. In other words, the current flowing through wiring OL[j] will be the sum of positive values. On the other hand, current output from multiple circuit MCs or circuit MCrs connected to the wiring OLB[j] The sum of these will flow into wiring OLB[j]. In other words, in wiring OLB[j], negative A current equal to the sum of the values ​​will flow. As a result of the above operation, the wiring OL[ The total current value flowing through [j], that is, the sum of positive values, and the total current value flowing through the wiring OLB[j], In other words, by using the sum of negative values, it is possible to perform sum-of-products operations. If the total current flowing through wiring OL[j] is greater than the total current flowing through wiring OLB[j] If the value is large, it can be determined that the result of the sum-of-products operation will be a positive value. If the total current flowing through OL[j] is less than the total current flowing through wiring OLB[j] In this case, it can be determined that the result of the sum-of-products operation will be a negative value. Wiring OL[j When the total current flowing through ] and the total current flowing through wiring OLB[j] are approximately the same value. It can be concluded that the result of the sum-of-products operation will be zero.

[0134] Note that the second data z i (k-1) is one of the binary values ​​"-1", "0", or "1". For example, in the case of binary values ​​"-1" and "1", or in the case of binary values ​​"0" and "1", the same applies. It can be made to work in this way. Similarly, the first data w i (k-1) j (k) is "-1", If the binary value is either "0" or "1", for example, "-1" and "1", Alternatively, the same operation can be performed for binary values, "0" and "1".

[0135] Note that the first data w i (k-1) j (k) This refers to analog values, or multi-bit (multi-level) values. It may also take a digital value. For example, instead of "-1", you can use "negative analog". The value can be ", and a "positive analog value" can be taken instead of "1". In this case, circuit M The magnitude of the current flowing from C or circuit MCr is also, as an example, the first data w i (k-1 ) j (k) The value will be an analog value corresponding to the absolute value of the value.

[0136] Next, we will explain an example of a modified circuit MP[i,j] in Figure 5A. Regarding the modified version of [i,j], we will mainly explain the differences from the circuit MP[i,j] in Figure 5A. In some cases, the explanation of the parts common to the circuit MP[i,j] in Figure 5A may be omitted.

[0137] The circuit MP[i,j] shown in Figure 5B is a modified version of the circuit MP[i,j] in Figure 5A. Circuit MP[i,j] in 5B is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit It has MCr and, however, circuit MP[i,j] in Figure 5B has a holding part HCr in circuit MCr. It differs from the circuit MP[i,j] in Figure 5A in that it does not include [a specific element].

[0138] Furthermore, since the circuit MCr does not have a holding part HCr, the circuit MP[i,j] in Figure 5B The applied calculation circuit uses wiring ILB[j] to supply the potential to be held in the holding part HCr. It is not necessary to have it. In addition, circuit MCr is not electrically connected to wiring WL[i]. That's good too.

[0139] In circuit MP[i,j] in Figure 5B, the retaining part HC included in circuit MC is located in circuit MCr. It is electrically connected to circuit MCr. In other words, circuit MP[i,j] in Figure 5B is electrically connected to circuit MCr. The configuration is such that MC and share a holding part HC with each other. One example is the holding part H The inverted signal of the signal held by C is supplied from the holding unit HC to the circuit MCr. This makes it possible for circuit MC and circuit MCr to operate differently. Alternatively, the internal circuit configurations of circuit MC and circuit MCr may be different, and as a result For the same signal held in the holding section HC, the output voltage is determined by the circuit MC and the circuit MCr. It is also possible to make the flow magnitudes different. Here, the first data w is entered into the holding part HC. i (k-1) j (k) Maintain the potential corresponding to the second data z i (k-1) The potential is distributed according to the By supplying power to line X1L[i] and wiring X2L[i], circuit MP[i,j] is supplied. The first data w is entered into the wiring OL[j] and wiring OLB[j]. i (k-1) j (k) and Day 2 Ta z i (k-1) It can output a current corresponding to the product of the two factors.

[0140] Furthermore, the arithmetic circuit 110 to which the circuit MP shown in Figure 5B is applied is the same as the arithmetic circuit 120 shown in Figure 6. The circuit configuration can be changed. The calculation circuit 120 is wired from the calculation circuit 110 in Figure 2 to IL. The configuration excludes B[1] or wiring ILB[m].

[0141] The circuit MP[i,j] shown in Figure 5C is a modified version of the circuit MP[i,j] in Figure 5A. In essence, this is an example of the configuration of circuit MP[i,j] that can be applied to the arithmetic circuit 120 in Figure 6. Figure 5 Circuit MP[i,j] of C is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit M It has Cr and, however, the circuit MP[i,j] in Figure 5C and the circuit MP[i,j] in Figure 5A are The configuration of the electrically connected wiring is different.

[0142] Wiring W1L[i] and W2L[i] shown in Figure 5C correspond to wiring WLS in Figure 6. This corresponds to [i]. Wiring W1L[i] is electrically connected to the retaining part HC, and wiring W2L[i ] is electrically connected to the holding part HCr.

[0143] Furthermore, the wiring IL[j] is electrically connected to the retaining part HC and the retaining part HCr. .

[0144] In the circuit MP[i,j] in Figure 5C, the holding part HC and the holding part HCr are different When maintaining potential, the potential-maintaining operations to the holding part HC and the holding part HCr are not simultaneous. It is preferable to perform the operations sequentially. For example, the first data w of circuit MP[i,j] i (k-1) j (k ) This can be expressed by maintaining a first potential in the holding part HC and a second potential in the holding part HCr. Let's consider the case where a predetermined electrical current is applied to each of the wires W1L[i] and W2L[i]. By assigning a position, electrical contact is established between the retaining part HC and the wiring IL[j], and the retaining part HCr and the wiring The connection between the wire IL[j] and the circuit is made non-conductive. Next, the first potential is supplied to the wiring IL[j]. This allows the first potential to be applied to the holding part HC. After that, the wiring W1L[i] and the wiring A predetermined potential is applied to each of the lines W2L[i], and the distance between the holding part HC and the wiring IL[j] is The connection is made non-conductive, and the connection between the retaining part HCr and the wiring IL[j] is made conductive. Then, By supplying a second potential to the wiring IL[j], a second potential can be applied to the holding part HCr. This allows the circuit MP[i,j] to use w as the first data. i (k-1) j (k) of It can be configured.

[0145] Furthermore, when approximately equal potentials are maintained in both the holding part HC and the holding part HCr (circuit M The first data point w of P[i,j] i (k-1) j (k) However, the same applies to the retaining part HC and the retaining part HCr. (When set by maintaining approximately equal potentials to each other), the holding part HC and the wiring IL The connection between [j] and the holding part HCr and the wiring IL[j] are made conductive. To that end, a predetermined potential is applied to each of the wires W1L[i] and W2L[i], After that, the relevant potential should be supplied to the wiring IL[j].

[0146] The circuit MP[i,j] in Figure 5C has a holding part HC and a holding part HCr with the first data w i (k -1) j (k) Maintain the potential corresponding to the second data z i (k-1) Wiring X to determine the appropriate potential By supplying 1L[i] and wiring X2L[i], the circuit MP[i,j] in Figure 5A Similarly, the first data w is set for wiring OL[j] and wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) It can output a current corresponding to the product of the two factors.

[0147] The circuit MP[i,j] shown in Figure 5D is a modified version of the circuit MP[i,j] in Figure 5A. Circuit MP[i,j] in 5D is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit It has MCr and, however, circuit MP[i,j] in Figure 5D and circuit MP[i,j] in Figure 5A The configuration of the electrically connected wiring is different.

[0148] The wiring IOL[j] in Figure 5D is the same as the wiring IL[j] and wiring OL[j] in Figure 5A. It functions as a wiring diagram compiled in a book, and wiring IOLB[j] in Figure 5D corresponds to wiring I in Figure 5A. It functions as a single wire combining LB[j] and wiring OLB[j]. Therefore, wiring IOL[j] is electrically connected to the retaining part HC, the circuit MC, and the circuit MCr, and wiring IOLB[j] is electrically connected to the holding part HCr, the circuit MC, and the circuit MCr. Yes, they are.

[0149] The first data point w is in the circuit MP[i,j] in Figure 5D. i (k-1) j (k) When holding, Therefore, between circuit MC and wiring IOL[j], and between circuit MC and wiring IOLB[j] The circuit becomes non-conductive, and the circuit MCr and the wiring IOL[j], and the circuit MCr and the wiring Wiring X1L[i] and wiring X2L[ A predetermined potential is input to [i]. Then, a predetermined potential is input to the wiring WL[i] and held. The connection between part HC and wiring IOL[j] is made conductive, and the connection between the holding part HCr and wiring IOL[j] By creating a conductive state between ] and each of the wiring IOL[j] and wiring IOLB[j], 1 data w i (k-1) j (k) By supplying various potentials according to the requirements, the holding part HC, Each of the holding part HCr can be input to a different potential. The connection between the wire IOL[j] and the holding part HCr and the wiring IOLB[j] is non-conductive, and the connection between the holding part HCr and the wiring IOLB[j] By inputting a predetermined potential to the wiring WL[i] so that the space between them becomes non-conductive, For each of the holding part HC and the retaining part HCr, the first data w i (k-1) j (k) Each It can maintain electrical potential.

[0150] First data w for each of the retaining part HC and retaining part HCr i (k-1) j (k) in response After maintaining the potential, the second data z i (k-1) The potential corresponding to wiring X1L[i] and By supplying power to wiring X2L[i], the wiring is configured similarly to circuit MP[i,j] in Figure 5A. OL[j] and wiring OLB[j], first data w i (k-1) j (k) and the second data z i (k-1) It can output a current corresponding to the product of the two factors.

[0151] Furthermore, the calculation circuit 110 to which the circuit MP shown in Figure 5D is applied is the same as the calculation circuit 130 shown in Figure 7. The circuit configuration can be changed. The arithmetic circuit 130 is arranged in the arithmetic circuit 110 of Figure 2. Lines IL[1] through wiring IL[n] and wiring OL[1] through wiring OL[n] are connected to wiring IO. Group them together as L[1] or wiring IOL[n], and wiring ILB[1] or wiring ILB[n] , wiring OLB[1] to wiring OLB[n] and, wiring IOLB[1] to wiring IOLB[ The configuration is grouped as n]. Also, in the arithmetic circuit 130, the wiring IOL[1 ] or wiring IOL[n], wiring IOLB[1] or wiring IOLB[n] to circuit ILD They are electrically connected. That is, wiring IOL[j] and wiring IOLB[j] are connected to circuit MP. For [i,j], the first data w i (k-1) j (k) Signal lines for transmitting, and circuit It has the function of a current line for supplying current to ACTF[j]. In this case, circuit MP [i,j] contains the first data w i (k-1) j (k) When transmitting, circuit ILD, circuit I The connection between LD and wiring IOL[j] and between circuit ILD and wiring IOLB[j] is made conductive. Furthermore, circuit ACTF[j] is connected to the wiring IOL[j] and circuit AC It is preferable to make the connection between TF[i] and the wiring IOLB[j] non-conductive. When supplying current to circuit ACTF[j], circuit ILD and wiring IOL[j The connection between ] and the circuit ILD and the wiring IOLB[j] is made non-conductive, and the circuit ACTF[ j) is between circuit ACTF[j] and wiring IOL[j], and between circuit ACTF[j] and wiring I It is preferable to maintain a conductive state between OLB[j] and the other element.

[0152] The circuit MP[i,j] shown in Figure 5E is a modified example of the circuit MP[i,j] in Figure 5A. In essence, this is an example of the configuration of circuit MP[i,j] that can be applied to the arithmetic circuit 110 in Figure 2. Figure 5 Circuit MP[i,j] of E is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit M It has Cr and, however, in the circuit MP[i,j] of Figure 5E, the circuit MC is wired OLB[j] The fact that it is not electrically connected, and that circuit MCr is electrically connected to wiring OL[j] It differs from the circuit MP[i,j] in Figure 5A in that it does not have [a certain feature].

[0153] Wiring WL[i] shown in Figure 5E corresponds to wiring WLS[i] in Figure 2. Wiring W L[i] is electrically connected to the retaining part HC and the retaining part HCr.

[0154] Furthermore, the wiring XL[i] shown in Figure 5E corresponds to the wiring XLS[i] in Figure 2. Wiring XL[i] is electrically connected to circuit MC and circuit MCr.

[0155] As mentioned earlier, circuit MP[i,j] in Figure 5E has circuit MC electrically connected to wiring OLB[j]. It is not connected, and circuit MCr is not electrically connected to wiring OL[j]. Unlike the circuits MP[i,j] in Figure 5E, the circuit MP[i,j] in Figures 5A to 5D is different in that it is The current output from the circuit MC does not flow into the wiring OLB[j], but the current output from the circuit MCr The configuration is such that the current does not flow into wiring OL[j].

[0156] Therefore, the circuit MP[i,j] in Figure 5E is the second data z i (k-1) is "0", or It is preferable to apply this to the arithmetic circuit when the value is a binary "1". For example, the second data z i (k-1) If it is "1", then circuit MP is conductive between circuit MC and wiring OL[j]. Set the circuit MCr and the wiring OLB[j] to a conductive state. Also, for example, the second taz i (k-1) If it is "0", the power output from circuit MC and circuit MCr respectively In order to prevent current from flowing through either wiring OL[j] or OLB[j], circuit MP is configured to avoid the current flowing through either wiring OL[j] or OLB[j]. The connection between MC and wiring OL[j] is made non-conductive, and the connection between circuit MCr and wiring OLB[j] To deconduct.

[0157] The circuit MP[i,j] in Figure 5E, when applied to the arithmetic circuit 110, is shown as an example. This is the first data w i (k-1) j (k) The value is one of the three values: "-1", "0", or "1". For the second data z i (k-1) When the value can take two values, "0" or "1", the operation is performed. This can be done. Note that the circuit MP[i,j] in Figure 5E is the first data w i (k-1) j ( k) is one of the two values ​​among "-1", "0", and "1", for example, "-1" and "1" It can also operate in the case of binary values, or the binary values ​​"0" and "1". First data w i (k-1) j (k) This refers to analog values, or multi-bit (multi-level) digital values. You can also take a negative value. For example, instead of "-1", you can take a "negative analog value". And instead of "1", you may take a "positive analog value". In this case, the circuit MC or The magnitude of the current flowing from the circuit MCr is, for example, shown in the first data w. i (k-1) j (k ) The value will be an analog value corresponding to the absolute value of the value.

[0158] The circuit MP[i,j] shown in Figure 5F has wiring OL[j] and wiring OLB, similar to Figure 5A. [j] contains the first data w i (k-1) j (k) and the second data z i (k-1) Depending on the product This is a circuit capable of outputting a current. Note that the circuit MP[i,j] in Figure 5F is, for example, This can then be applied to the arithmetic circuit 110 in Figure 2.

[0159] The circuit MP[i,j] in Figure 5F consists of circuit MC and circuit MCr, in addition to a transistor. It has MZ.

[0160] The first terminal of transistor MZ is connected to the first terminal of circuit MC and the first terminal of circuit MCr. They are electrically connected. The second terminal of transistor MZ is electrically connected to wiring VL. The gate of transistor MZ is electrically connected to wiring XL[i].

[0161] Wiring VL functions, for example, as wiring that provides a constant voltage. This constant voltage is used in the circuit. It is preferable to determine the constant voltage by the configuration of MP[i,j] and the calculation circuit 110. For example, VDD is a high-level potential, VSS is a low-level potential, and the ground potential is... It can be done like this.

[0162] Furthermore, the wiring WL[i] shown in Figure 5F corresponds to the wiring WLS[ in the calculation circuit 110 in Figure 2. This corresponds to [i]. Wiring WL[i] is electrically connected to the retaining part HC and the retaining part HCr. It is being done.

[0163] Furthermore, wiring OL[j] is electrically connected to the second terminal of circuit MC. OLB[j] is electrically connected to the second terminal of circuit MCr.

[0164] Furthermore, wiring IL[j] is electrically connected to the retaining part HC, and wiring ILB[j] is a retaining part. It is electrically connected to part HCr.

[0165] In the circuit MP[i,j] of Figure 5F, the first data is applied to each of the holding part HC and the holding part HCr. Regarding the operation when maintaining a potential corresponding to the data, in the circuit MP[i,j] in Figure 5A... Refer to the explanation of the operation that maintains the potential corresponding to the first data.

[0166] In circuit MP[i,j] in Figure 5F, the wiring VL is connected to the first terminal of circuit MC. When a constant voltage is supplied, the current corresponding to the potential held in the holding part HC is rotated. It has the function of flowing between the first and second terminals of the circuit MC. In addition, circuit MCr is circuit MC When a constant voltage is supplied to the first terminal by the wiring VL, the holding part HCr is held It has the function of flowing a current corresponding to the potential between the first and second terminals of the circuit MCr. Furthermore, the first data w is assigned to the holding part HC and the holding part HCr of the circuit MP[i,j]. i (k -1) j (k) By maintaining a potential corresponding to the circuit MC, the first and second terminals and Determine the amount of current flowing between them and the amount of current flowing between the first and second terminals of the circuit MCr. This is possible. Furthermore, the constant voltage supplied by the wiring VL to the first terminal of circuit MC (circuit MCr) is supplied. If not supplied, the circuit MC (circuit MCr) is, for example, the first of the circuit MC (circuit MCr). It is also acceptable to not allow current to flow between terminal 1 and terminal 2.

[0167] For example, the first data w is "1" for each of the retaining part HC and retaining part HCr. i (k-1) j (k) When the corresponding potential is maintained, the constant voltage supplied by the wiring VL is applied to the circuit MC. By doing so, the circuit MC flows a predetermined current between the first and second terminals of the circuit MC. Therefore, current flows between circuit MC and wiring OL. At this time, circuit MCr The circuit assumes that no current flows between the first and second terminals of the MCr. Therefore, the circuit No current flows between the MCr and the wiring OLB. Also, for example, the retaining part HC, retaining part HC The first data for each of r is "-1" w i (k-1) j (k) A corresponding potential is maintained. When a constant voltage is applied to the circuit MC by the wiring VL, the circuit MCr A predetermined current is passed between the first and second terminals of the circuit MCr. Therefore, the circuit MCr and Current flows between the wiring OLB. At this time, the circuit MC is connected to the first terminal of the circuit MC and the second terminal. No current is to flow between the two terminals. Therefore, no current flows between the circuit MC and the wiring OL. The flow does not flow. Also, for example, the first day of the holding part HC and the holding part HCr is "0". Ta lol i (k-1) j (k)When the corresponding potential is maintained, circuit MC and circuit MCr Regardless of whether a constant voltage is applied to the wiring VL, the circuit MC is connected to the first terminal of the circuit MC. No current flows between the first and second terminals of the circuit MCr. No current flows. In other words, no current flows between circuit MC and wiring OL, and between circuit MCr and wiring OL. No current flows between the line OLB and the circuit.

[0168] In addition, in the circuit MP[i,j] of Figure 5F, the holding part HC and the holding part HCr are held , 1st data w i (k-1) j (k) For specific examples of the potential corresponding to this, see circuit M in Figure 5A. Refer to the description of P[i,j]. Also, in the circuit MP[i,j] of Figure 5F, the holding part H C, the holding part HCr, is measured not by potential but by current and resistance, similar to the circuit MP[i,j] in Figure 5A. It has the function of holding information such as the above, and the circuit MC and circuit MCr flow current according to that information. It may have a function.

[0169] The wiring XL[i] shown in Figure 5F corresponds to the wiring XLS[i] in the calculation circuit 110 in Figure 2. It corresponds to the second data z input to circuit MP[i,j]. i (k-1) This is just one example. Therefore, it is determined by the potential and current of the wiring XL[i]. The gate of MZ receives, for example, the second data z via wiring XL[i]. i (k-1) in response A potential is input.

[0170] For example, the second data z i (k-1) Let's consider the case where it takes one of two values, "0" or "1". For example, the second data zi (k-1) If it is "1", then the wiring XL[i] has high Assume that a bell potential is applied. At this time, transistor MZ will be in the ON state, Circuit MP creates a conductive state between wiring VL and the first terminal of circuit MC, and wiring VL and circuit MC The first terminal of r is made conductive. In other words, the second data z i (k-1) is “1” When this happens, a constant voltage from the wiring VL is applied to circuit MC and circuit MCr. Also, for example Then, the second data z i (k-1) If it is "0", then the wiring XL[i] has a low-level potential. It shall be given. In this case, circuit MP has no connection between circuit MC and wiring OLB[j]. The circuit MCr and the wiring OL[j] are made to be in a conductive state, and the connection between them is made to be non-conductive. In other words, the second taz i (k-1) When is "0", the wiring VL is connected to circuit MC and circuit MCr. A constant voltage is not provided.

[0171] Here, for example, the first data w i (k-1) j (k) The second data z is "1", and i (k-1) If it is "1", current flows between circuit MC and wiring OL, and circuit MC As a result, no current flows between r and the wiring BLB. Also, for example, the first data w i ( k-1) j (k) The second data z is "-1", and i (k-1) If it is "1", No current flows between circuit MC and wiring OL, and no current flows between circuit MCr and wiring OLB. The result will be a flow. Also, for example, the first data w i (k-1) j (k) is "0" , second data z i (k-1) If it is "1", then between circuit MC and wiring OL, and the circuit As a result, no current flows between the MCr and the OLB wiring. Also, for example, the second data z i (k-1) If it is "0", then the first data w i (k-1) j (k) is "-1", "0 Whether it is "" or "1", the connection between circuit MC and wiring OL, and between circuit MCr and wiring O As a result, no current flows between LB and the circuit board.

[0172] In other words, circuit MP[i,j] in Figure 5F is similar to circuit MP[i,j] in Figure 5E, as an example. For example, the first data w i (k-1) j (k) The value is one of the three values: "-1", "0", or "1". Take the second data z i (k-1) When it takes two values, "0" and "1", the operation This can be done. Also, similar to the circuit MP[i,j] in Figure 5E, the circuit MP[ in Figure 5F i,j] is the first data w i (k-1) j (k) Of the following, Either of the two values, for example, "-1" and "1", or "0" and "1". It can also be operated in this case. Note that the first data w i (k-1) j (k) , Ana It may take a logarithmic value or a multi-bit (multi-level) digital value. A specific example is: Instead of "-1", use a "negative analog value", and instead of "1", use a "positive analog value". You may also take this. In this case, the magnitude of the current flowing from circuit MC or circuit MCr is also an example. For example, the first data w i (k-1) j (k) The value will be an analog value corresponding to the absolute value of the value.

[0173] <Example of operation of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit 110 in Figure 2 will be described. Note that in this explanation of the operation example, As an example, we use the arithmetic circuit 110 shown in Figure 8.

[0174] The arithmetic circuit 110 in Figure 8 focuses on the circuit located in the j-th column of the arithmetic circuit 110 in Figure 2. This is what has been shown. In other words, the arithmetic circuit 110 in Figure 8 is the neural network shown in Figure 1A. Neuron N in twerk 100 j (k) The input is sent to neuron N1 (k-1 ) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) And weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) The sum-of-products operation and the said sum-of-products operation This corresponds to the calculation of the activation function using the result of the calculation, and the circuit that performs the calculation. Furthermore, Figure 8 shows the calculation circuit 11. The circuit MP included in the array section ALP of 0 is the same as the circuit MP in Figure 5A. do.

[0175] First, in the arithmetic circuit 110, the first circuit MP[1,j] to the circuit MP[m,j] Data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) This is set. First data w i (k-1) j (k) The method of setting this up is by using the circuit WLD, and wiring WLS[1] A predetermined potential is applied sequentially to the wiring WLS[m], and then to circuit MP[1,j] to circuit MP[m] Select ,j] in order, and the holding part HC of the circuit MC included in the selected circuit MP, And to the holding part HCr of the circuit MCr, from the circuit ILD, wiring IL[j], wiring ILB A potential corresponding to the first data is supplied via [j]. Then, after the potential is supplied, circuit W The LD is used to deselect each of the circuits MP[1,j] through MP[m,j]. This allows each of circuits MP[1,j] through MP[m,j] to maintain the circuit MC. The first data w1 is entered in the holding part HC and the circuit MCr of the holding part HCr. (k-1) j (k) Or maybe lol m ( k-1) j (k) It can maintain a potential corresponding to the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) If each of them takes a positive value For the holding part HC, input a value corresponding to its positive value, and for the holding part HCr, input a value equivalent to zero. Enter the value to be used. Meanwhile, the first data w1 (k-1)j (k) Or maybe lol m (k-1) j (k ) If each of these values ​​is negative, the holding part HC will be assigned a value equivalent to zero. Then, input a value corresponding to the absolute value of a negative value into the holding part HCr.

[0176] Next, the circuit XLD will route the wiring X1L[1] to wiring X1L[m], wiring X2L[1 ] or each of the wiring X2L[m], second data z1 (k-1) ~z m (k-1) of To supply. As a specific example, the second data to wiring X1L[i] and wiring X2L[i] z1 (k-1) The following will be supplied. Note that wiring X1L[i] and wiring X2L[i] are shown in Figure 2. This corresponds to the wiring XLS[i] of the calculation circuit 110.

[0177] The second data z1 is input to each of the circuits MP[1,j] through MP[m,j]. ( k-1) ~z m (k-1) Depending on the circuit, the contents of circuit MP[1,j] to circuit MP[m,j] are The conductivity between the circuit MC and circuit MCr, and the wiring OL[j] and circuit OLB[j] The state is determined. As a concrete example, the circuit MP[i,j] is determined by the second data z i (k-1) to Accordingly, "the circuit MC and wiring OL[j] become conductive, and the circuit MCr and wiring OLB[j The state in which there is conductivity between ] and the circuit MC and the wiring OLB[j], and the state in which there is conductivity between the circuit MC and the wiring OLB[j], The state in which there is conductivity between circuit MCr and wiring OL[j], and the state in which circuit MC and circuit MCr are The wiring OL[j] and OLB[j] respectively are in a non-conductive state, or they take one of the following states. One example is the second data z1 (k-1) If it takes a positive value, then wiring X1L [1] is a conductive state between circuit MC and wiring OL[j], and circuit MCr and wiring Enter a value that allows conductivity between the line OLB[j] and the wiring X2L. [1] is a non-conductive state between circuit MC and wiring OLB[j], and circuit MCr Input a value that will result in a non-conductive state between and wiring OL[j]. Then, the second data ta z1 (k-1) If it takes a negative value, then the wiring X1L[1] has circuit MC The circuit MCr and the wiring OLB[j] are in a conductive state, and the circuit MCr and the wiring OL[j] are in a conductive state. Input a value that allows it to be in a conductive state. Then, the wiring X2L[1] is connected to circuit MC. The circuit MCr and the wiring OL[j] become non-conductive, and the circuit MCr and the wiring OLB[j] Enter a value that allows the connection to become non-conductive. Then, enter the second data z1 (k-1) to Therefore, if the value is zero, the wiring X1L[1] is connected to circuit MC and wiring OLB[j] The connection between and becomes non-conductive, and the connection between circuit MCr and wiring OL[j] becomes non-conductive. Enter a value that can be used. Then, in wiring X2L[1], connect circuit MC and wiring OL[j The connection between ] and the circuit MCr and the wiring OLB[j] is non-conductive, and the connection between circuit MCr and wiring OLB[j] is non-conductive. Enter a value that can result in this.

[0178] The second data z is input to circuit MP[i,j] i (k-1) Depending on the circuit MP[i, The circuit MC and circuit MCr included in j, and the wiring OL[j] and circuit OLB[j] The conduction or non-conduction state between them determines the relationship between circuit MC and circuit MCr, Current input and output occurs between wiring OL[j] and wiring OLB[j]. Furthermore, the current The amount of flow is the first data w set in circuit MP[i,j] i (k-1) j (k) and / also is the second data z i (k-1) It depends on the circumstances.

[0179] For example, in circuit MP[i,j], from wiring OL[j], circuit MC or circuit MCr Let I[i,j] be the current flowing through it, and let the current flow from wiring OLB[j] to circuit MC or circuit MCr. The current is I B Let [i,j] be the points. Then, flow from circuit ACTF[j] to wiring OL[j]. The current is I out Let [j] be the current flowing from the wiring OLB[j] to the circuit ACTF[j]. to I Bout If we set it to [j], then I out [j] and I Bout [j] can be expressed by the following formula: It is possible.

[0180]

number

[0181] In circuit MP[i,j], as an example, the first data w i (k-1) j (k) ga “+ When it is 1”, circuit MC emits I(+1) and circuit MCr emits I(-1). That year, the first data w i (k-1) j (k) When is "-1", the circuit MC is I(-1 ) is discharged, and the circuit MCr discharges I(+1), and the first data w i (k-1) j (k) When is "0", circuit MC discharges I(-1) and circuit MCr discharges I(-1) It shall be discharged.

[0182] Furthermore, the circuit MP[i,j] is given by the second data z i (k-1) When is "+1", The circuit MC and wiring OL[j] become conductive, and the circuit MCr and wiring OLB[j] Continuity is established, and the connection between circuit MC and wiring OLB[j] becomes non-conductive, and the connection between circuit MCr and wiring OL The state in which there is no conduction between [j] and the second data z i (k-1) is "-1" Sometimes, there is conduction between circuit MC and wiring OLB[j], and circuit MCr and wiring OL[j The connection between ] becomes conductive, the connection between circuit MC and wiring OL[j] becomes non-conductive, and circuit MCr and The state in which there is no conductivity between the wiring OLB[j] and the second data z i (k-1) is “0 "When this is the case, "the relationship between circuit MC and wiring OL[j], and between circuit MC and wiring OLB[j] The connection between them is non-conductive, and the connection between circuit MCr and wiring OL[j], and between circuit MCr and OL The connection between B[j] and the circuit MCr and the wiring OL[j], and the circuit MC The state between r and OLB[j] is assumed to be non-conductive.

[0183] At this time, in circuit MP[i,j], from wiring OL[j], circuit MC or circuit MC The current I[i,j] flowing through r and the current flowing from the wiring OLB[j] to circuit MC or circuit MCr Current I B[i,j] are as shown in the table below. Note that in some cases, I(- The circuit MP[i,j] may be configured such that the current in 1) becomes 0. Note that the current I[ i,j] may be the current flowing from circuit MC or circuit MCr to wiring OL[j]. Similarly, current I B [i,j] is the flow from circuit MC or circuit MCr to wiring OLB[j]. Electric current is also acceptable.

[0184] [Table 1]

[0185] Then, I flow from wiring OL[j] and wiring OLB[j] respectively. out [ j] and I Bout Each of [j] is input to the circuit ACTF[j] For example, the circuit ACTF[j] is I out [j] and I Bout [j] comparison The circuit ACTF[j] is, for example, determined by the result of the comparison, by the neuron. N j (k) The signal z that is sent to the (k+1) layer neuron j (k) Outputs.

[0186] As an example, the arithmetic circuit 110 in Figure 8 can be used to process neuron N j (k) The input is, Neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~ z m (k-1) And the weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1)j (k) And, It can perform sum-of-products operations and the calculation of activation functions using the results of those sum-of-products operations. In the array section ALP of the arithmetic circuit in Figure 8, by providing n rows of circuit MP, the calculation in Figure 2 is achieved. A circuit equivalent to the arithmetic circuit 110 can be constructed. In other words, the arithmetic circuit 110 in Figure 2 can be used to generate a new - Ron N1 (k) Neuron N n (k) In each of these, the sum-of-products operation and the sum-of-products operation The calculation of the activation function using the result of the operation can be performed simultaneously.

[0187] <<Examples of changes to circuits included in the arithmetic circuitry>> The above-mentioned array section ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit Some or all of the transistors contained in each of the MPs, for example, It is preferable to use an OS transistor. For example, it is desirable to have a low off-current. In the case of a transistor, a specific example is the function of retaining the charge accumulated in a capacitive element. The transistors present are preferably OS transistors. In particular, the transistors When an OS transistor is used as the transistor, the OS transistor is described in particular in Embodiment 3. It is more preferable that the transistor structure is such that it is mounted on the transistor. However, one aspect of the present invention is this Not limited to this.

[0188] Additionally, there are the array section ALP, circuits ILD, WLD, XLD, AFP, and MP. Transistors included in these include, besides OS transistors, channel type transistors, for example. Even as a transistor containing silicon in its region (hereinafter referred to as a Si transistor) Good. Also, as for silicon, for example, single-crystal silicon, hydrogenated amorphous silicon. Microcrystalline silicon or polycrystalline silicon can be used. Also, OS Transition Besides Si transistors, other transistors include, for example, activated semiconductors such as Ge. Layered transistors, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Transistors with compound semiconductors as the active layer, transistors with carbon nanotubes as the active layer A transistor with an organic semiconductor as the active layer can be used.

[0189] Furthermore, in the metal oxide of the semiconductor layer of the OS transistor, metal oxide containing indium In materials (e.g., In oxide), or metal oxides containing zinc (e.g., Zn oxide), While n-type semiconductors can be fabricated, p-type semiconductors are difficult to fabricate due to their mobility and reliability. There are also cases where this is the case. Therefore, the calculation circuit 110, calculation circuit 120, and calculation circuit 130 are located in the array section A LP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit MP etc. include n An OS transistor is applied as a channel-type transistor, and it is a p-channel type transistor. A configuration using Si transistors may also be used.

[0190] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0191] (Embodiment 2) This embodiment describes a specific configuration example of the circuit MP described in Embodiment 1. ru.

[0192] In Embodiment 1, the code for circuit MP indicates its position within the array section ALP [1,1 Although ], [i,j], [m,n], etc. are noted, in this embodiment, unless otherwise specified, the number of times The notation [1,1], [i,j], [m,n], etc. is omitted for the route MP symbols.

[0193] <Configuration Example 1> First, we will describe an example of a circuit configuration that can be applied to circuit MP in Figure 5A. (See Figure 9A) Circuit MP is an example of the configuration of circuit MP in Figure 5A, and the circuits included in circuit MP in Figure 9A A circuit MC, for example, consists of transistors M1 to M4 and a capacitive element C1. It has the following characteristics. For example, the holding part HC is formed by the transistor M1 and the capacitive element C1. It is composed of.

[0194] Transistors M1 to M4 shown in Figure 9A are, for example, It is an n-channel transistor with a multi-gate structure having gates above and below the Nell. Each of transistors M1 through M4 has a first gate and a second gate. However, in this specification, for convenience, as an example, the first gate may be referred to as the gate (front gate). It may be written as "To" (or "T"). Also, the second gate is sometimes described as the back gate to distinguish it. However, the first gate and the second gate can be swapped with each other. Therefore, this specification In such instances, the term "gate" is replaced with the term "backgate." It is possible to do so. Similarly, the phrase "backgate" can be replaced with the phrase "gate". It can be written as follows. For example, "The gate is electrically connected to the first wiring, and The connection configuration states that "the back gate is electrically connected to the second wiring." The connection is described as "Electrically connected to the first wiring, and the gate is electrically connected to the second wiring." It can be replaced as a component.

[0195] Furthermore, a semiconductor device according to one aspect of the present invention depends on the connection configuration of the back gate of the transistor. No. In each of the transistors M1 to M4 shown in Figure 9A, The back gate is shown in the diagram, but the connection configuration of the said back gate is not shown. The electrical connections of the back gate can be determined during the design phase. For example, In a transistor with a gate, in order to increase the on-current of the transistor, The gate and back gate may be electrically connected. That is, for example, transistor M1 In each of transistors M4, the gate and back gate are electrically connected. This is also fine. Also, for example, in a transistor having a back gate, the transistor To vary the threshold voltage, or to reduce the off-current of the transistor Therefore, wiring is provided that is electrically connected to external circuits, etc., and by said external circuits, etc. A potential may be applied to the back gate of the transistor. Note that this is only shown in Figure 9A. Rather, transistors described elsewhere in the specification, or those illustrated in other drawings. The same applies to transistors.

[0196] Furthermore, the semiconductor device according to one aspect of the present invention has a structure of transistors included in the semiconductor device. It does not depend on. For example, transistors M1 to M4 shown in Figure 9A, As shown in Figure 9C, transistors M1r to M4r have a back gate. It can also be a configuration that does not exist, that is, a single-gate transistor. The transistor has a back gate configuration, while some other transistors have a back gate. A configuration without a gate is also acceptable. For details, please refer to the circuit diagram shown in Figure 9A. In addition, transistors described elsewhere in the specification, or illustrated in other drawings The same applies to transistors.

[0197] Furthermore, in this specification, transistors of various structures are used as transistors. This is possible. Therefore, there are no restrictions on the type of transistor used. An example of a transistor is... For example, transistors made of single-crystal silicon, or amorphous silicon, polycrystalline silicon N, microcrystals (also called nanocrystals or semi-amorphous silicon) Transistors having non-single-crystal semiconductor films, such as those represented by , can be used. Alternatively, thin-film transistors (TFTs) made by thinning these semiconductors can be used. Yes, it is possible. When using TFTs, there are various advantages. For example, compared to single-crystal silicon... Because it can be manufactured at a low temperature, it is possible to reduce manufacturing costs or to increase the size of the manufacturing equipment. It is possible. Because the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Therefore, many can be manufactured simultaneously. Because individual display devices can be manufactured, they can be produced at a low cost. Alternatively, because the manufacturing temperature is low. Therefore, substrates with poor heat resistance can be used. It is possible to manufacture transistors. Alternatively, transistors on a light-transmitting substrate can be used in display elements. Light transmission can be controlled. Or, because the transistor film thickness is thin, the transistor A portion of the film that forms the aperture can transmit light. Therefore, the aperture ratio can be improved. It is possible.

[0198] For example, a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having n-Sn-Zn-O, etc., can be used. These compound semiconductors, or thin-film transistors made by thinning these oxide semiconductors, etc. These can be used. This allows for lower manufacturing temperatures, so for example, at room temperature... This makes it possible to manufacture ZISTAS. As a result, substrates with low heat resistance, such as plastics, can be used. Transistors can be formed directly on a substrate or film substrate. Compound semiconductors or oxide semiconductors are used not only in the channel portion of transistors, but also They can also be used for other purposes. For example, these compound semiconductors or oxide semiconductors It can be used as wiring, resistive elements, pixel electrodes, or light-transmitting electrodes, etc. Since these can be deposited or formed simultaneously with the transistor, costs can be reduced.

[0199] As an example of a transistor, a transistor formed using an inkjet method or printing method is... Rangistas and the like can be used. These allow for manufacturing at room temperature, manufacturing at low vacuum levels, and It can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This makes it possible to easily change the layout of the transistors. Alternatively, since it is possible to manufacture without using resist, material costs are reduced, and the number of processes is also reduced. It can be reduced. Or, since it is possible to apply the film only to the necessary parts, after forming a film over the entire surface... This method is less wasteful and lower-cost than etching.

[0200] As an example of a transistor, there are transistors that have organic semiconductors or carbon nanotubes. Transistors and the like can be used. With these, transients can be applied to a bendable substrate. It is possible to form transistors using organic semiconductors or carbon nanotubes. Devices using this technology can be made more resistant to impact.

[0201] Furthermore, transistors with various other structures can also be used. For example, transistors include MOS type transistors, junction type transistors, and bipod type transistors. A transistor such as a MOS-type transistor can be used. By using this, the size of the transistor can be reduced. Therefore, a large number of transistors It can be equipped with a transistor. Bipolar transistors are used as transistors. This allows for the flow of a large current. Therefore, it is possible to operate the circuit at high speed. Yes, it is possible. Furthermore, MOS transistors and bipolar transistors can be mixed on a single substrate. It may be formed in this way. This will enable low power consumption, miniaturization, and high-speed operation. can.

[0202] One example of a transistor is a structure in which gate electrodes are arranged above and below the active layer. This transistor can be applied. The structure has gate electrodes positioned above and below the active layer. This results in a circuit configuration where multiple transistors are connected in parallel. Therefore, the channel formation region increases, making it possible to increase the current value. Alternatively, the active layer By arranging the gate electrodes at the top and bottom, a depletion layer is more likely to form. This allows for improvement of the S value.

[0203] For example, one transistor has a structure in which the gate electrode is placed on top of the active layer. Structures in which the gate electrode is positioned below the active layer, positive staggered structure, inverse staggered structure, channel Structures in which the region is divided into multiple regions, structures in which the active layers are connected in parallel, or structures in which the active layers are connected in series. A transistor with a structure such as the following can be used. Alternatively, as a transistor, Fin type, fin type, tri-gate type, top gate Type, bottom gate type, double gate type (gates are located above and below the channel), It can take on a variety of configurations.

[0204] As an example of a transistor, the active layer (or part thereof) has source electrodes and drains. A transistor with an overlapping in electrode structure can be used. By creating a structure in which the source electrode and drain electrode overlap a part of the active layer, This prevents the device from becoming unstable due to the accumulation of electric charge.

[0205] As an example of a transistor, a structure with an LDD region can be applied. By creating a range, the off-current can be reduced, or the transistor's breakdown voltage can be improved (reliability can be improved). This can be achieved. Alternatively, by providing an LDD region, when operating in the saturation region... Even if the voltage between the drain and source changes, the drain current does not change much, and the slope is A flat voltage-current characteristic can be obtained.

[0206] For example, in this specification, transistors can be formed using various substrates. Yes. The type of circuit board is not limited to a specific one. One example of such a circuit board is a semi-circular board. Conductive substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, stainless steel Substrate having a resin-steel foil, tungsten substrate, having a tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Examples include glass or soda-lime glass. Flexible substrates, laminated films, and base material films. Examples of materials include the following: For example, polyethylene terephthalate. PET, polyethylene naphthalate (PEN), polyethersulfone (PES) ), there are plastics such as polytetrafluoroethylene (PTFE). One example is synthetic resins such as acrylic. Alternatively, another example is polypropylene. Examples include polyester, polyvinyl fluoride, or polyvinyl chloride. Examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or Paper products are among them. In particular, semiconductor substrates, single crystal substrates, or SOI substrates are used for transients. By manufacturing the staves, variations in characteristics, size, and shape are minimized, and current capacity is reduced. It is possible to manufacture transistors that are powerful and small in size. By configuring the circuit using this method, it is possible to reduce the power consumption of the circuit or increase its integration. Cut.

[0207] Furthermore, a flexible substrate is used as the substrate, and transistors are formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After partially or completely completing a semiconductor device, it is separated from the circuit board and transferred to another circuit board. It can be used in this way. In this case, the transistor can be used on substrates with poor heat resistance or flexible substrates. It can be mounted. Furthermore, the aforementioned release layer may include, for example, an inorganic tungsten film and a silicon oxide film. This method utilizes a layered film structure or a configuration in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0208] In other words, a transistor is formed using one substrate, and then the transistor is placed on another substrate. The transistor may be transposed and placed on a different substrate. As an example, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) (or recycled fibers (acetate, cupro, rayon, recycled polyester, etc.)) These include leather substrates and rubber substrates. By using these substrates, a tiger with good characteristics can be produced. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance This allows for the addition of features, weight reduction, or thinning of the material.

[0209] Furthermore, all the circuits necessary to realize the specified function are placed on the same circuit board (for example, glass It can be formed on substrates such as stainless steel substrates, plastic substrates, single crystal substrates, or SOI substrates. Yes. In this way, costs are reduced by reducing the number of parts, or the number of connection points with circuit components is reduced. This can improve reliability.

[0210] Furthermore, it is not necessary to form all the circuits required to achieve a specific function on the same circuit board. It is possible. In other words, some of the circuits necessary to achieve a certain function can be formed on a certain circuit board. Another part of the circuit necessary to achieve the predetermined function is formed on a separate substrate. It is possible that some of the circuits necessary to achieve a certain function are gas Another part of the circuitry formed on the lath substrate and necessary to realize a predetermined function is a single crystal base. It can be formed on a plate (or SOI substrate). And it can realize a predetermined function. A single-crystal substrate (also called an IC chip) on which another part of the necessary circuitry is formed is called COG (Chip On Glass) connects to a glass substrate, and its I It is possible to place a C chip. Alternatively, the IC chip can be placed in a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology, or using printed circuit boards, etc. It is possible to connect to a lath substrate. In this way, a part of the circuit is formed on the same substrate as the pixel section. This reduces costs by reducing the number of components, or by reducing the connection points with circuit components. Reliability can be improved by reducing the number of components. In particular, in circuits where the drive voltage is high, Alternatively, circuits with high drive frequencies often consume a lot of power. Therefore, by forming such a circuit on a substrate separate from the pixel section (for example, a single-crystal substrate), the IC chip is formed. This constitutes the chip. By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0211] In circuit MP of Figure 9A, the first terminal of transistor M1 is electrically connected to wiring IL. The second terminal of transistor M1 is connected to the first terminal of capacitive element C1, and transistor M2 The gate of transistor M1 is electrically connected to the wiring WL. They are connected. The first terminal of transistor M2 is connected to the second terminal of capacitive element C1 and to wiring VL. The second terminal of transistor M2 is electrically connected to the first terminal of transistor M3. The child is electrically connected to the first terminal of transistor M4. The first terminal of transistor M3 Terminal 2 is electrically connected to wiring OL. The gate of transistor M3 is connected to wiring X1L. Electrically connected. The second terminal of transistor M4 is electrically connected to the OLB wiring. The gate of transistor M4 is electrically connected to wiring X2L. Note that in Figure 9B... As shown, the second terminal of the capacitive element C1 is electrically connected to another wire VLm, not to the wire VL. They may be connected. Similarly, the second terminal of the capacitive element C1r is not connected to the wiring VLr. It may also be electrically connected to another wiring VLmr. Note that this applies not only to Figure 9A, but also to other In the circuit diagram, the second terminal of the capacitive element C1 is connected to a different wire VL, not the same wire VL. The configuration may be such that it is electrically connected to m. Also, in Figure 9B, for example, wiring VL and wiring VLr are treated as one identical wiring, and wiring VLm and wiring VLmr are treated as one identical wiring. It may also be considered a single wiring (not shown in the diagram).

[0212] In the holding part HC shown in Figure 9A, the second terminal of transistor M1 and the capacitive element C The electrical connection point between the first terminal of 1 and the gate of transistor M2 is defined as node nd1. ru.

[0213] The holding part HC, as described in Embodiment 1, for example, corresponds to the first data w It has the function of maintaining the potential. The potential is maintained at the holding part HC included in the circuit MC in Figure 9A. The holding state is maintained when transistor M1 is turned ON, and the corresponding potential is input from wiring IL. This is done by writing to the capacitive element C1 and then turning off the transistor M1. This allows the potential of node nd1 to be maintained as the potential corresponding to the first data. can.

[0214] Furthermore, transistor M1 maintains the potential of node nd1 for a long time, resulting in low off-current. It is preferable to use transistors that do not have an off-current. Examples of transistors with low off-current include For example, an OS transistor can be used. Also, as transistor M1, A transistor with a gate is applied, and a low-level potential is applied to the back gate, thereby reducing the threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-current.

[0215] Circuit MCr has almost the same circuit configuration as Circuit MC. Therefore, Circuit MCr The circuit elements possessed are designated with the letter "r" to distinguish them from the circuit elements possessed by the circuit MC. It is.

[0216] In circuit MCr, a different connection configuration from circuit MC will be explained. Transistor M3 The second terminal of r is electrically connected to wiring OLB, not wiring OL, and transistor M4r The second terminal is electrically connected to wiring OL, not wiring OLB. Transistor M The first terminal of 2 is electrically connected to the wiring VLr.

[0217] In the operation example described later, to briefly explain the current entering and leaving circuit MP, Figure The ends of wiring OL shown in 9A are designated as node ina and node outa, and the ends of wiring OLB are designated as node Let node inb and node outb.

[0218] Wiring VL functions, for example, as wiring that supplies a constant voltage. This means that transistor M2, or transistor M2r, is an n-channel type transistor. In some cases, for example, the VSS (Variable State Station), the ground potential, and other low-level potentials are considered. It can be done in this way. Also, wiring VLr is a wiring that supplies a constant voltage, similar to wiring VL. It functions as such, and the constant voltage is set to a low-level potential such as VSS or ground potential. This is possible. In this case, the circuits ACT of arithmetic circuit 110, arithmetic circuit 120, and arithmetic circuit 130 F[1] or circuit ACTF[n] is shown in Figures 3A to 3E, 4A to 4D, and 4F. If applied, electrically connected to circuits ACTF[1] through ACTF[n] The constant voltage supplied by wiring VAL is higher than the potential supplied by wiring VL and wiring VLr. For example, it is preferable to use VDD.

[0219] Furthermore, the constant voltage supplied by wiring VLr may be different from the constant voltage supplied by wiring VL. They may be considered identical. For example, when the constant voltages provided by wiring VL and wiring VLr are approximately equal. As shown in circuit MP in Figure 10A, wiring VLr can be the same wiring as wiring VL. .

[0220] Furthermore, the configuration of circuit MP in Figure 9A can be changed depending on the situation. For example, Figure As shown in 10B, transistors M2, M2r, and tra Transistor M3, Transistor M3r, Transistor M4, Transistor M4r These are p-channel transistors such as transistor M2p, transistor M2pr, and transistor Place the transistors M3p, M3pr, M4p, and M4pr in the following locations: It may be replaced. In particular, transistors M2 and M2r can be replaced with p-channel type transistors. When replacing with a standard, the constant voltage supplied by the wiring VL is set to VDD, which is the high-level potential. This is preferable. In addition to this case, arithmetic circuit 110, arithmetic circuit 120, arithmetic circuit 130 The circuits ACTF[1] to ACTF[n] are shown in Figures 3A to 3E and Figures 4A to 4. D. When Figure 4F is applied, circuits ACTF[1] to ACTF[n] are electrically connected. The constant voltage supplied by the connected wiring VAL is preferably the ground potential or VSS. Thus, when the potential of the wiring is changed, the direction in which the current flows also changes. ru.

[0221] Similarly, transistor M1 can also be replaced with a p-channel type transistor. This is also good. Also, in Figure 10B, transistor M2 of circuit MP in Figure 9A, transistor M2 r, transistor M3, transistor M3r, transistor M4, transistor M4r These are p-channel transistors, transistor M2p and transistor M2pr. , transistor M3p, transistor M3pr, transistor M4p, transistor M4 Although it was replaced with pr, in the circuit MP of Figure 9A, transistor M2, transistor M2r, and tra Selected from Transistor M3, Transistor M3r, Transistor M4, and Transistor M4r One or more transistors may be replaced with p-channel transistors.

[0222] Furthermore, as shown in Figure 11A, for example, transistors M3 and M3r of circuit MP in Figure 9A Transistor M4 and transistor M4r are each controlled by analog switch A3, analog You may also replace switch A4, analog switch A3r, and analog switch A4r. Note that Figure 11A shows analog switch A3, analog switch A4, and analog switch To operate A3r and analog switch A4r, wiring X1LB and wiring X2LB are also shown. Wiring X1LB is electrically connected to analog switch A3 and analog switch A3r. Connected and wired X2LB to analog switch A4 and analog switch A4r electrically They are connected. Wiring X1LB receives the inverted signal of the signal input to wiring X1L. The inverted signal of the signal input to wiring X2L is input to wiring X2LB. Also, Figure 1 As shown in 1B, wiring X1L and wiring X2L are designated as wiring XL, and wiring X1LB and wiring X2L B can be bundled together as a wiring XLB. For example, analog switch A3, A The Analog Switch A4, Analog Switch A3r, and Analog Switch A4r are n-channel switches. A CMOS configuration using type 1 transistors and p-channel transistors may also be used.

[0223] Also, for example, as shown in Figure 12A, transistor M4 of circuit MP in Figure 9A, Each of the transistors M4r is a p-channel transistor, namely transistor M4p, and It may be replaced with Zistar M4pr. In circuit MP of Figure 12A, transistor M3 The gate is electrically connected to the gate of transistor M4p and to wiring XL. Wiring X L corresponds to the two wires X1L and X2L in Figure 9A being combined into one. The polarities of transistors M3 and M4p are different, and The gates of transistors M3 and M4p are electrically connected to wiring XL. Therefore, by applying a predetermined potential to the wiring XL, transistor M3 and One side of transistor M4p is turned ON, and the other side of transistors M3 and M4p is turned ON. It can be turned off.

[0224] Also, for example, as shown in Figure 12B, the circuit MP in Figure 9A has transistor M2m, Add transistor M2mr, and the first of transistors M4 and M4r The electrical connection destination of the terminals may be changed. In circuit MP in Figure 12B, transistor M The first terminal of the 2m cable is connected to the second terminal of the capacitive element C1, the first terminal of the transistor M2, and the wiring V. L is electrically connected to the second terminal of transistor M2m, and the first terminal of transistor M4 is connected to the first terminal of transistor M4. It is electrically connected to the terminal. Note that in circuit MP of Figure 9A, the second of transistor M2 The terminal was electrically connected to the first terminal of transistor M4, but the circuit MP in Figure 12B Then, the second terminal of transistor M2 is electrically connected to the first terminal of transistor M4. In the circuit MP shown in Figure 12B, the currents flowing through transistors M3 and M4 are as follows: This is determined by the gate potentials of transistors M2 and M2m. Examples include the size of transistor M2 and transistor M2m, for example, the channel length or It is preferable that the channel widths are equal to each other. By using such a circuit configuration, It may be possible to lay it out efficiently. Also, the current flows to transistors M3 and M4. It may be possible to equalize the currents being applied.

[0225] <<Example of operation>> Next, we will explain an example of the operation of circuit MP shown in Figure 9A.

[0226] Figures 13A to 13C, 14A to 14C, and 15A to 15C show the circuit MP. This is a timing chart showing an example of operation, with wiring IL, wiring ILB, and wiring WL. This shows the potential fluctuations of wiring X1L, wiring X2L, node nd1, and node nd1r. Furthermore, as described in Figures 13A to 13C, 14A to 14C, and 15A to 15C... "High" indicates a high-level potential, and "low" indicates a low-level potential. From the wiring OL I is the amount of current output to node outa (or from node outa to wiring OL). OL It is stated that the wiring is done from OLB to node outb (or from node outb). The amount of current output to OLB is I OLB This is as follows: Figures 13A to 13C, Figure 14A In the timing charts shown in Figures 14C and 15A to 15C, the current quantity I OL , I O LB The amount of change is also illustrated.

[0227] In this example, the constant voltage supplied by wiring VL and wiring VLr is VSS (low-level potential). In this case, current flows from wiring VAL through wiring OL to wiring VL. Similarly, current flows from wiring VAL through wiring OLB to wiring VLr. Yes.

[0228] Furthermore, in this specification and elsewhere, the terms "low-level potential" and "high-level potential" are particularly... This does not mean a fixed potential; the specific potential may differ depending on the wiring. For example, the low-level potential and high-level potential held at node nd1 and node nd1r. These are different potentials from the low-level potential and high-level potential applied to wiring X1L and wiring X2L. That's fine.

[0229] Before explaining the operation example, the weight coefficient held by circuit MP is defined as follows: Holding part H A high-level potential is maintained at node nd1 of C, and a low-level potential is maintained at node nd1r of the holding part HCr. When this is done, the circuit MP is assumed to hold a weight coefficient of "+1". A low-level potential is maintained at node nd1 of the HC, and a high-level potential is maintained at node nd1r of the holding part HCr. When held, circuit MP is assumed to hold "-1" as a weighting coefficient. A low-level potential is present at node nd1 of part HC, and a low-level potential is present at node nd1r of holding part HCr. When held, circuit MP is assumed to hold "0" as its weight coefficient. The high-level potentials held at nodes nd1 and nd1r include, for example, VDD, or This allows the potential to be slightly lower than VDD, and is maintained at nodes nd1 and nd1r. The low-level potential to be maintained can be, for example, VSS. The weighting coefficient is It is also possible to use analog values. In that case, for example, a positive analog value can be used as the weighting coefficient. In the case of the value ", a high level analog potential is applied to node nd1 of the holding part HC, and the holding part HCr A low-level potential is maintained at node nd1r. A "negative analog value" is used as the weighting coefficient. In this case, for example, a low-level potential at node nd1 of the holding part HC, and node n of the holding part HCr. A high level of analog potential is maintained at d1r. When the weighting coefficient is "0", For example, a low-level potential at node nd1 of the retaining part HC, and a low-level potential at node nd1r of the retaining part HCr. The level potential is maintained.

[0230] Furthermore, the neuron signal (calculated value) input to circuit MP is, as an example, as follows: Defined when a high-level potential is applied to wiring X1L and a low-level potential is applied to wiring X2L. Circuit MP receives a "+1" input as a neuron signal. Low-voltage wiring X1L When a high-level potential is applied to the bell potential and wiring X2L, a neuron exists in circuit MP. A signal of "-1" is input. Low level potential is applied to wiring X1L, and low level potential is applied to wiring X2L. When a bell potential is applied, the circuit MP receives a "0" as a neuron signal. It shall be assumed that it is.

[0231] Furthermore, in this specification and elsewhere, transistor M2 and transistor M2r are referred to as such unless otherwise specified. If not present, the ON state includes cases where it ultimately operates in the saturation region. The gate voltage, source voltage, and drain voltage of each of the transistors mentioned above are This includes cases where the voltage is properly biased to operate in the saturation region. However, the present invention is not limited thereto. It involves reducing the amplitude value of the supplied voltage. Therefore, transistors M2 and M2r may operate in the linear region. Note that the weighting coefficient is A When using analog values, depending on the magnitude of the weighting coefficient, for example, transistor M2, M2 r may operate in a combination of the linear domain and the saturation domain.

[0232] Furthermore, in this specification, etc., transistor M1, transistor M3, transistor M 4. Transistors M1r, M3r, and M4r are specified without further notice. In the case of the ON state, this includes the case where it ultimately operates in the linear domain. The gate voltage, source voltage, and drain voltage of each of the transistors mentioned above are: This includes cases where the voltage is appropriately biased within the range of operation in the linear domain.

[0233] Below, we will examine the possible combinations of values ​​for each of the weight coefficients and the neuron signals. Next, we will explain an example of the operation of circuit MP.

[0234] [Condition 1] First, as an example, consider a neuron input to circuit MP with a weight coefficient w of "0". Let's consider the case where the signal (calculated value) is "+1". Figure 13A shows the circuit M in that case. This is the timing chart for P.

[0235] Between time T1 and time T2, wiring IL and wiring ILB each have a hold. To initialize the potential of node nd1 of part HC and the potential of node nd1r of holding part HCr Initialization potential V ini This is the input. Note that in Figure 13A, V ini That's a low-level potential. Although it is shown as a potential that is higher and lower than the high-level potential, V ini low-level potential It may be set to a potential lower than or higher than the high-level potential. Alternatively, V i ni This may be set to the same potential as the low-level potential, or to the same potential as the high-level potential. Furthermore, the initialization potential V applied to wiring IL and wiring ILB, respectively. ini They are different from each other It may also be defined as an electric potential. Furthermore, an initial potential V is set for each of the wirings IL and ILB. ini of You don't need to input anything. In other words, you don't need to specify a period between time T1 and time T2. .

[0236] Furthermore, between time T1 and time T2, a low-level potential is input to the wiring WL. Therefore, transistors M1 and M1r are in the off state. It is.

[0237] Furthermore, between time T1 and time T2, node nd1 and node nd1r The potentials of each node are not specifically defined. In Figure 13A, node nd1 and node nd Each potential of 1r is higher than the low-level potential, V ini It is set to a lower potential than .

[0238] Low-level potentials are input to wiring X1L and wiring X2L, respectively. , transistor M3, transistor M4, transistor M3r, and transistor M4r Each of these is currently in the off state.

[0239] Next, between time T2 and time T3, a high-level potential is input to the wiring WL. As a result, transistors M1 and M1r are turned ON. , the wiring IL and node nd1 become conductive, and the wiring ILB and node nd1r This creates a conductive state. Therefore, the potentials of node nd1 and node nd1r are V, respectively. ini This is the result. Note that the potentials of node nd1 and node nd1r are the initialization potential V ini So It's not necessary. In other words, it's not necessary to include a period between time T2 and time T3.

[0240] Between time T3 and time T4, low loads were applied to both wiring IL and wiring ILB. A bell potential is applied, and "0" is input as the weighting coefficient w. Wiring WL is connected from time T3. A high-level potential has been input from before, and the weight coefficient w has been set to "0". Therefore, transistors M1 and M1r are in the ON state. The potentials at nd1 and node nd1r are both low-level potentials.

[0241] Between time T4 and time T5, a low-level potential is input to the wiring WL. As a result, transistors M1 and M1r are turned off, and the capacitance element Child C1 and capacitive element C1r respectively affect nodes nd1 and nd1r. Each potential is maintained.

[0242] The operation from time T1 to time T5 sets the weight coefficient of circuit MP to "0". It can be done.

[0243] The operations described so far have affected the gates of transistors M2 and M2r. The potential of transistor M2 and transistor M2r becomes a low-level potential, and each The potential of the first terminal is VSS, and therefore the potential of transistors M2 and M2r is VSS. It will be turned off.

[0244] Between time T5 and time T6, for example, wiring IL and wiring ILB will be initialized. Potential V ini This is input. Note that this operation is not particularly necessary, so wiring I Initialization potential V for L and wiring ILB ini You don't have to enter it. In other words, from time T5 It is not necessary to provide a period of time until time T6. Also, each of the wiring IL and wiring ILB Different potentials may be input to these devices.

[0245] From time T6 onward, the input of the neuron signal "+1" to circuit MP is wire X A high-level potential is input to 1L, and a low-level potential is input to wiring X2L. This causes a transient Transistor M3 and transistor M3r are both turned ON, and transistor M4 and The transistors M4r are each turned off. In other words, this operation causes the circuit MC and Conductivity is established between wiring OL and circuit MCr, and conduction is established between circuit MCr and wiring OLB.

[0246] At this time, in circuit MC, transistor M2 is in the OFF state, so wiring O No current flows between L and wiring VL. In other words, there is no output from node outa of wiring OL. The current I OL This does not change before and after time T6. Similarly, in circuit MCr, Because the inverter M2r is in the off state, current is not flowing between the OLB wiring and the VLr wiring. No current flows. In other words, the current I output from node outb of the wiring OLB. OLB Also, time There is no change before and after T6.

[0247] By the way, this condition sets the weight coefficient to "0" and the signal of the neuron input to circuit MP. Since we set it to "+1", using equation (1.1), the product of the weight coefficient and the neuron's signal is The result is "0". The product of the weight coefficient and the neuron's signal being "0" indicates that the circuit MP During operation, the current I OL and current I OLB In a field where each of them remains unchanged It corresponds to the combination.

[0248] Note that once the weight coefficient w is entered, only the calculated value is changed without updating the input value. Multiple sum-of-products operations may be performed by doing so. In this case, updating the weight coefficient w is not This is essential, and therefore power consumption can be reduced. Furthermore, the number of updates to the weight coefficient w is minimized. To achieve this, the weight coefficient w needs to be maintained for a long period of time. In this case, for example, OS Transis By using this method, it is possible to maintain the weighting coefficient w for a long period of time by taking advantage of its low off-current. This is the result.

[0249] [Condition 2] Next, as an example, consider a neuron input to circuit MP with a weight coefficient w of "+1". Let's consider the case where the signal (calculated value) is "+1". Figure 13B shows the circuit M in that case. This is the timing chart for P.

[0250] For the operation between time T1 and time T3, the conditions for time T1 to time T3 of condition 1 apply. Since the operation is similar to that between time T1 and time T3 in condition 1, please refer to the explanation of the operation between time T1 and time T3. To pour a drink.

[0251] Between time T3 and time T4, wiring IL has a high-level potential, and wiring ILB has a low-level potential. A bell potential is applied, and a weighting coefficient w of "1" is input. Wiring WL is connected from time T3. A high-level potential has been input from before, and the weighting coefficient w is set to "1". Therefore, transistors M1 and M1r are in the ON state. The potential at node nd1 becomes a high-level potential, while the potential at node nd1r becomes a low-level potential.

[0252] Between time T4 and time T5, a low-level potential is input to the wiring WL. As a result, transistors M1 and M1r are turned off, Nodes nd1 and nd1 are determined by the capacitance element C1 and the capacitance element C1r respectively. Each potential of r is maintained.

[0253] Based on the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "+1". It will be done.

[0254] As a result of the operations so far, the gate potential of transistor M2 is at a high level potential. The gate potential of transistor M2r becomes a low level potential, and transistor M2 and transistor M2 are also at a low level. Since the potential of each first terminal of transistor M2r is VSS, transistor M2 is O In this state, transistor M2r is in the off state.

[0255] For the operation between time T5 and time T6, the conditions for time T5 to time T6 of condition 1 apply. Since the operation is similar to that between time T5 and time T6 in condition 1, please refer to the explanation of the operation between time T5 and time T6. To pour a drink.

[0256] From time T6 onward, the input of the neuron signal "+1" to circuit MP is wire X A high-level potential is input to 1L, and a low-level potential is input to wiring X2L. This causes a transient Transistor M3 and transistor M3r are both turned ON, and transistor M4 and The transistors M4r are each turned off. In other words, this operation causes the circuit MC and Conductivity is established between wiring OL and circuit MCr, and conduction is established between circuit MCr and wiring OLB.

[0257] At this time, in circuit MC, transistor M2 is in the ON state, so wiring O Current flows from L to wiring VL. In other words, the output from node outa of wiring OL Current I OL It increases after time T6 has elapsed (in Figure 13B, current I OL The increase It is written as ΔI.) On the other hand, in circuit MCr, transistor M2r is in the off state. Therefore, no current flows between wiring OLB and wiring VLr. In other words, wiring O Current I output from LB node outb OLB This does not change before or after time T6.

[0258] By the way, this condition sets the weight coefficient w to "+1", and the neurons input to circuit MP Since the signal (calculated value) is set to "+1", using equation (1.1), the weight coefficient and New The product of Ron's signals is "+1". The product of the weight coefficient and the neuron's signal is "1". The result is that in the operation of circuit MP, the current I OL As the current I changes OLB but Deal with situations where there is no change.

[0259] [Condition 3] Next, as an example, consider a neuron input to circuit MP with a weight coefficient w of "-1". Let's consider the case where the signal (calculated value) is "+1". Figure 13C shows the circuit M in that case. This is the timing chart for P.

[0260] For the operation between time T1 and time T3, the conditions for time T1 to time T3 of condition 1 apply. Since the operation is similar to that between time T1 and time T3 in condition 1, please refer to the explanation of the operation between time T1 and time T3. To pour a drink.

[0261] Between time T3 and time T4, wiring IL has a low potential and wiring ILB has a high potential. A bell potential is applied, and a weighting coefficient w of "-1" is input. At time T3, the wiring WL is connected. Because a high-level potential has been continuously input from before, transistor M1 and transistor Zista M1r is in the ON state. Therefore, "-1" is input as the weight coefficient w. The potential at node nd1 becomes a low-level potential, and the potential at node nd1r becomes a high-level potential. ru.

[0262] Between time T4 and time T5, a low-level potential is input to the wiring WL. As a result, transistors M1 and M1r are turned off, Nodes nd1 and nd1 are determined by the capacitance element C1 and the capacitance element C1r respectively. Each potential of r is maintained.

[0263] Based on the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "-1". It will be done.

[0264] As a result of the operations so far, the gate potential of transistor M2 is at a low level potential. The gate potential of transistor M2r becomes a high-level potential, and the potential of transistors M2 and M2r Since the potential of each first terminal is VSS, transistor M2 is in the off state. The M2r will be turned on.

[0265] For the operation between time T5 and time T6, the conditions for time T5 to time T6 of condition 1 apply. Since the operation is similar to that between time T5 and time T6 in condition 1, please refer to the explanation of the operation between time T5 and time T6. To pour a drink.

[0266] From time T6 onward, the input of the neuron signal "+1" to circuit MP is wire X A high-level potential is input to 1L, and a low-level potential is input to wiring X2L. This causes a transient Transistor M3 and transistor M3r are both turned ON, and transistor M4 and The transistors M4r are each turned off. In other words, this operation causes the circuit MC and Conductivity is established between wiring OL and circuit MCr, and conduction is established between circuit MCr and wiring OLB.

[0267] At this time, in circuit MC, transistor M2 is in the OFF state, so wiring O No current flows between L and wiring VL. In other words, there is no output from node outa of wiring OL. The current I OL This does not change before and after time T6. On the other hand, in circuit MCr, Because the ZISTA M2r is ON, current flows between the OLB wiring and the VLr wiring. It flows. In other words, the current I output from node outb of the wiring OLB. OLB This is at time T6 It increases after a certain period (in Figure 13C, current I OLB The increase is denoted as ΔI.

[0268] By the way, this condition sets the weight coefficient w to "-1", and the neurons input to circuit MP Since the signal (calculated value) is set to "+1", using equation (1.1), the weight coefficient and New The product of Ron's signals is "-1". The product of the weight coefficient and the neuron's signal is "-1". The result shows that in the operation of circuit MP, the current I is active from time T6 onward. OL If the current I does not change, OL B This handles cases where [something] changes.

[0269] [Condition 4] Under these conditions, as an example, the weight coefficient w is set to "0", and the neuron input to circuit MP... Let's consider the operation of circuit MP when the signal (calculated value) is set to "-1". Figure 14A shows the operation in that case. This is a timing chart for the MP circuit in the combined circuit.

[0270] For the operation between time T1 and time T6, the conditions for time T1 to time T6 of condition 1 apply. Since the operation is similar to that between time T1 and time T6 in condition 1, please refer to the explanation of the operation between time T1 and time T6. To pour a drink.

[0271] From time T6 onward, the input to the circuit MP is set to the neuron's signal (calculated value) "-1". As a result, a low-level potential is input to wiring X1L and a high-level potential is input to wiring X2L. Transistor M3 and transistor M3r are each turned off, Transistors M4 and M4r are both turned ON. In other words, this operation means that Circuit MC and wiring OLB are conductive, and circuit MCr and wiring OL are conductive. It will become.

[0272] At this time, in circuit MC, transistor M2 is in the OFF state, so wiring O No current flows between LB and wiring VL. In other words, from node outb of wiring OLB... Output current I OLB This does not change before and after time T6. Similarly, in circuit MCr Because transistor M2r is in the off state, between wiring OL and wiring VLr No current flows. In other words, the current I output from node outa of wiring OL is not present. OL Also, time There is no change before and after T6.

[0273] By the way, this condition sets the weight coefficient w to "0", and the signal of the neuron input to circuit MP Since the unit (calculated value) is set to "-1", using equation (1.1), the weight coefficient and neuro The product of the signals from the two neurons is "0". The result when the product of the weight coefficient and the neuron's signal is "0" is In the operation of circuit MP, the current I OL and current I OLB Each of them This addresses the case where there is no change, which is consistent with the result of the circuit operation under condition 1.

[0274] [Condition 5] Under these conditions, as an example, the weight coefficient w is set to "+1", and the neuron input to circuit MP Let's consider the operation of circuit MP when the signal (calculated value) of n is set to "-1". Figure 14B shows the operation of the circuit MP. This is a timing chart for the circuit MP in the given case.

[0275] For operations between time T1 and time T6, the conditions for time T1 to time T6 in condition 2 apply. Since the operation is similar to that between time T1 and time T6 in condition 2, refer to the explanation of the operation between time T1 and time T6. To pour a drink.

[0276] From time T6 onward, the input to the circuit MP is set to the neuron's signal (calculated value) "-1". As a result, a low-level potential is input to wiring X1L and a high-level potential is input to wiring X2L. Transistor M3 and transistor M3r are each turned off, Transistors M4 and M4r are both turned ON. In other words, this operation means that Circuit MC and wiring OLB become conductive, and circuit MCr and wiring OL become conductive. It will become.

[0277] At this time, in circuit MC, transistor M2 is in the ON state, so wiring O Current flows between LB and wiring VL. In other words, current flows from node outb of wiring OLB. Current I OLB It increases after time T6 has elapsed (in Figure 14B, current IOLB of The increase is denoted as ΔI.) On the other hand, in circuit MCr, transistor M2r is Because it is in a "f" state, no current flows between wiring OL and wiring VLr. In other words, Current I output from node outa of wiring OL OL This does not change before or after time T6.

[0278] By the way, this condition sets the weight coefficient w to "+1", and the neurons input to circuit MP Since the signal (calculated value) is set to "-1", using equation (1.1), the weight coefficient and New The product of Ron's signals is "-1". The product of the weight coefficient and the neuron's signal is "-1". The result shows that in the operation of circuit MP, the current I is active from time T6 onward. OL If the current I does not change, OL B This corresponds to the case where the value changes, which is consistent with the result of the circuit operation under condition 3.

[0279] [Condition 6] Under these conditions, as an example, the weight coefficient w is set to "-1", and the neuron input to circuit MP Let's consider the operation of circuit MP when the signal (calculated value) of n is set to "-1". Figure 14C shows the operation of the circuit MP. This is a timing chart for the circuit MP in the given case.

[0280] For the operation between time T1 and time T6, condition 3 applies to time T1 to time T6. Since the operation is similar to that between time T1 and time T6 in condition 3, please refer to the explanation of the operation between time T1 and time T6. To pour a drink.

[0281] From time T6 onward, the input to the circuit MP is set to the neuron's signal (calculated value) "-1". As a result, a low-level potential is input to wiring X1L and a high-level potential is input to wiring X2L. Transistor M3 and transistor M3r are each turned off, Transistors M4 and M4r are both turned ON. In other words, this operation means that Circuit MC and wiring OLB are conductive, and circuit MCr and wiring OL are conductive. It will become.

[0282] At this time, in circuit MC, transistor M2 is in the OFF state, so wiring O No current flows between LB and wiring VL. In other words, from node outb of wiring OLB... Output current I OLB This does not change before and after time T6. On the other hand, in circuit MCr, Because transistor M2r is in the ON state, electricity is running between wiring OL and wiring VLr. A current flows. In other words, the current I is output from node outa of wiring OL. OL This is at time T6 It increases after a certain period (in Figure 14C, current I OL The increase is denoted as ΔI.

[0283] By the way, this condition sets the weight coefficient w to "-1", and the neurons input to circuit MP Since the signal (calculated value) is set to "-1", using equation (1.1), the weight coefficient and New The product of Ron's signals is "+1". The product of the weight coefficient and the neuron's signal is "+1". The result shows that in the operation of circuit MP, the current I is active from time T6 onward. OL As the current I changes OLB This corresponds to the case where the value does not change, which is consistent with the result of the circuit operation under condition 2.

[0284] [Condition 7] Under these conditions, as an example, the weight coefficient w is "0", and the new input to circuit MP is Let's consider the operation of circuit MP under condition 7, where Ron's signal (calculated value) is "0". (See diagram) 15A is the timing chart for the circuit MP in that case.

[0285] For the operation between time T1 and time T6, the conditions for time T1 to time T6 of condition 1 apply. Since the operation is similar to that between time T1 and time T6 in condition 1, please refer to the explanation of the operation between time T1 and time T6. To pour a drink.

[0286] From time T6 onward, the input of the neuron signal (calculated value) "0" to circuit MP is A low-level potential is input to wiring X1L and wiring X2L. As a result, Transistors M3, M3r, M4, and M4r are Each of them turns off. In other words, this operation turns off the MC circuit and the MCr circuit. This results in a non-conductive state whether the connection is between wiring OL or wiring OLB.

[0287] Therefore, in the circuit MC, between wiring OL and either wiring VL or wiring VLr No current flows. In other words, the current I output from node outb of the wiring OLB is not flowing. OLB teeth, It does not change before and after time T6. Similarly, in circuit MCr, from wiring OLB to wiring VL or No current flows between the other end of wiring VLr. In other words, no current flows between the outa node of wiring OL. The output current I OL However, it does not change around time T6.

[0288] By the way, this condition assumes that the weight coefficient w is "0", and the signal of the neuron input to circuit MP Since the unit (operational value) is set to "0", using equation (1.1), the weight coefficient and the neuron The product of the signals is "0". The result when the product of the weight coefficient and the neuron's signal is "0" is: In the operation of circuit MP, the current I OL and current IOLB Each of them changes This corresponds to the case where this does not happen, which is consistent with the results of the circuit operation under conditions 1 and 4.

[0289] [Condition 8] Under these conditions, as an example, the weight coefficient w is "+1", and the input to circuit MP is Let's consider the operation of circuit MP under condition 8, where the signal (calculated value) of -ron is "0". Figure 15B shows the timing chart of the circuit MP in that case.

[0290] For operations between time T1 and time T6, the conditions for time T1 to time T6 in condition 2 apply. Since the operation is similar to that between time T1 and time T6 in condition 2, refer to the explanation of the operation between time T1 and time T6. To pour a drink.

[0291] From time T6 onward, the input of the neuron signal (calculated value) "0" to circuit MP is A low-level potential is input to wiring X1L and wiring X2L. In other words, condition 7 Since this operation is the same as the operation after time T6, this operation causes circuit MC to wire OL, O In either case between LB, the circuit becomes non-conductive, and the circuit MCr is connected to wiring OL and wiring OLB. In either case, the circuit becomes non-conductive. Therefore, from wiring OL or wiring OLB, Since no current flows between either wiring VL or wiring VLr, the no- Current I output from outa OL , and output from node outb of the wiring OLB. current I OLB Each of these values ​​remains unchanged before and after time T6.

[0292] By the way, this condition sets the weight coefficient w to "+1", and the neurons input to circuit MP Since the signal (calculated value) is set to "0", using equation (1.1), the weight coefficient and the neuron The product of the signals from the two neurons is "0". The result when the product of the weight coefficient and the neuron's signal is "0" is In the operation of circuit MP, the current I OL and current I OLB Each of them To address the case where there is no change, this matches the results of the circuit operation under conditions 1, 4, and 7. ru.

[0293] [Condition 9] Under these conditions, as an example, the weight coefficient w is "-1", and the input to circuit MP is Let's consider the operation of circuit MP under condition 9, where the signal (calculated value) of -ron is "0". Figure 15C shows the timing chart of the circuit MP in that case.

[0294] For the operation between time T1 and time T6, condition 3 applies to time T1 to time T6. Since the operation is similar to that between time T1 and time T6 in condition 3, please refer to the explanation of the operation between time T1 and time T6. To pour a drink.

[0295] From time T6 onward, the input of the neuron signal (calculated value) "0" to circuit MP is A low-level potential is input to wiring X1L and wiring X2L. In other words, condition 7 Since this operation is the same as the operation after time T6, this operation causes circuit MC to wire OL, and The circuit MCr is non-conductive between either the OL or OLB wiring, and the circuit MCr is non-conductive between the OL and OLB wirings. The circuit will be non-conductive regardless of which side of LB is connected. Therefore, either the OL circuit or the OLB circuit Therefore, no current flows between either wiring VL or wiring VLr, so wiring OL Current I output from node outa OL , and output from node outb of the wiring OLB Current I OLB Each of these values ​​remains unchanged before and after time T6.

[0296] By the way, this condition sets the weight coefficient w to "-1", and the neurons input to circuit MP Since the signal (calculated value) is set to "0", using equation (1.1), the weight coefficient and the neuron The product of the signals from the two neurons is "0". The result when the product of the weight coefficient and the neuron's signal is "0" is In the operation of circuit MP, the current I OL and current I OLB Each of them In cases where there is no change, this is the result of the circuit operation under conditions 1, 4, 7, and 8. This matches.

[0297] The results of the operation examples for conditions 1 through 9 described above are summarized in the table below. Note that in the table below, high level The high potential is indicated as "high," and the low-level potential is indicated as "low."

[0298] [Table 2]

[0299] Here, one circuit MC and one circuit MCr are connected to wiring OL and wiring OLB. This is shown as an example. This is illustrated in Figures 2, 6, 7, and 8. Multiple circuits MC and MCr are connected to wiring OL and wiring OLB. In this case, the current output from each circuit MC and circuit MCr is determined according to Kirchhoff's current law. Therefore, they will be added together. As a result, a summation operation will be performed. In circuits MC and MCr, a product operation is performed, and from multiple circuits MC and MCr... The summation operation is performed by adding up the currents. As a result, the sum-of-products operation is performed. This will happen.

[0300] By the way, in the operation of the MP circuit, the weight coefficients are limited to only two values, "+1" and "-1". By performing calculations that treat the neuron's signals as only two values, "+1" and "-1", the circuit MP becomes It can perform the same operation as the negation of the exclusive OR (the coincidence circuit).

[0301] Furthermore, in the operation of the MP circuit, the weight coefficients are limited to only two values: "+1" and "0". By performing calculations using only two values ​​for Ron's signal, "+1" and "0", the circuit MP performs logical AND It can perform operations similar to those of a circuit.

[0302] By the way, in this example of operation, the holding part HC and the holding part of the circuit MC and MCr of the circuit MP are The potential held in the HCr part was set to either a high-level potential or a low-level potential, but the holding part HCr The holding part HCr may hold a potential that shows an analog value. For example, as a weighting coefficient. In the case of a "positive analog value," a high-level analog potential is applied to node nd1 of the holding unit HC. A low-level potential is maintained at node nd1r of the holding part HCr. The weighting coefficient is "negative". In the case of the analog value of, for example, a low level potential is applied to node nd1 of the holding part HC, and the holding part A high level of analog potential is maintained at node nd1r of HCr. And current I O L and current I OLB The magnitude of the current will be proportional to the analog potential. Regarding the maintenance of analog potentials in parts HC and HCr, see the circuit MP in Figure 9A. This example of operation is not limited to the one described herein, but may also be applied to other circuits MP as shown in this specification.

[0303] <Configuration Example 2> Next, we will explain an example of a circuit configuration that can be applied to the circuit MP shown in Figures 5C and 5D. do.

[0304] The circuit MP shown in Figure 16A is an example of the configuration of the circuit MP in Figure 5C, and the circuit M in Figure 9A is a different circuit from Figure 9A. The difference from P is that wiring IL and wiring ILB are combined into one, and wiring WL is as shown in Figure 9A. The point is that it has wiring W1L and wiring W2L.

[0305] In circuit MP in Figure 16A, the first terminal of transistor M1 and transistor M1r The first terminal is electrically connected to wiring IL. In addition, the gate of transistor M1 is The gate of transistor M1r is electrically connected to wiring W1L and to wiring W2L. It is continued. Furthermore, the circuit MP in Figure 16A and the circuit MP in Figure 9A have the same connection configuration. I will omit explanations for the parts that are already explained.

[0306] When setting weighting coefficients for circuit MP in Figure 16A, first, the wiring W1L and wiring W2L are used By changing the supplied potential, transistor M1 is turned ON, and transistor M1r is turned OFF Set to the F state, then supply a potential for holding from the wiring IL to the holding part HC, and the transistor Turn off the M1 switch. Then, change the potential supplied to wiring W1L and wiring W2L. Next, turn transistor M1 to the OFF state, turn transistor M1r to the ON state, and then distribute The wire IL supplies a potential to the holding part HCr for retention, and transistor M1r is turned off. In this way, in the case of circuit MP in Figure 16A, the wiring IL is connected to the retaining part HC, and the retaining part HC By sequentially supplying potential to r, the holding part HC and the holding part HCr are supplied with a weighting coefficient equivalent to the current. It can maintain electrical potential.

[0307] The circuit MP shown in Figure 16B is an example of the configuration of the circuit MP in Figure 5D, and the circuit M in Figure 9A is a different circuit from Figure 9A. The difference from P is that wiring IL and wiring OL are combined into wiring IOL, and wiring ILB and wiring OLB are combined. The key point is that the wiring is consolidated into an IOLB (Internet Load Balance).

[0308] In circuit MP of Figure 16B, the first terminal of transistor M1 is electrically connected to wiring IOL. The first terminal of transistor M1r is connected and electrically connected to the wiring IOLB. In addition, the second terminal of transistor M3 is electrically connected to the wiring IOL, and the transistor The second terminal of M4 is electrically connected to the wiring IOLB, and the second terminal of transistor M3r is The wiring is electrically connected to IOL, and the second terminal of transistor M4r is electrically connected to the wiring IOL. They are electrically connected. Note that the circuit MP in Figure 16B and the circuit MP in Figure 9A have the same connection configuration. Explanations for sections marked "completed" will be omitted.

[0309] In the circuit MP shown in Figure 16B, the wiring IOL is electrically connected to the retaining part HC, and the retaining part HCr Wiring IOLB is electrically connected, and transistors M1 and M1r are connected to wiring WL. Since each gate is electrically connected, the holding part H is the same as in circuit MP in Figure 9A. The potential corresponding to the weighting coefficient can be simultaneously written to C and the holding part HCr.

[0310] <Configuration Example 3> Unlike the circuit MP in Figure 9A, the circuit MP shown in Figure 17 only has a retaining part HC and a retaining part HCr. Instead, it is a circuit having retaining parts HCs and retaining parts HCsr.

[0311] The circuit MC included in circuit MP in Figure 17 is added to the circuit elements of circuit MP in Figure 9A. Uh, transistor M1s, transistor M2s, transistor M5, transistor M5s It has a capacitive element C1s. Also, the circuit MCr included in the circuit MP in Figure 17 is a circuit Because it has the same circuit elements as an MC, the transistors M1s and M2 of the MC circuit s, transistor M5, transistor M5s, and capacitive element C1s correspond to each of these. Transistor M1sr, Transistor M2sr, Transistor M5r, Transistor M5s It has a capacitance element C1sr.

[0312] In this specification, etc., transistor M5, transistor M5s, transistor Unless otherwise specified, M5r and M5sr transistors, when in the ON state, ultimately connect to the wire. This includes cases where the transistor operates in the shape domain. That is, each of the transistors described above The gate voltage, source voltage, and drain voltage are appropriate for voltages within the range that allows operation in the linear region. This includes cases where there is a bias.

[0313] Next, the configuration of circuit MP in Figure 17 will be explained. Note that in circuit MP in Figure 17, Sections that have the same configuration as circuit MP in Figure 9A are omitted.

[0314] The gate of transistor M1 is electrically connected to wiring W1L. The first terminal of 5 is electrically connected to the second terminal of transistor M2, and the transistor M5 The second terminal is electrically connected to the first terminal of transistor M3 and the first terminal of transistor M4. The gate of transistor M5 is connected to wiring S1L.

[0315] The first terminal of transistor M1s is electrically connected to wiring IL, and transistor M1s The second terminal is electrically connected to the first terminal of the capacitive element C1s and the gate of the transistor M2s. It is connected to and the gate of transistor M1s is electrically connected to wiring W2L. The first terminal of the transistor M2s is electrically connected to the second terminal of the capacitive element C1s and to the wiring VLs. The second terminal of transistor M2s is electrically connected to the first terminal of transistor M5s. It is connected. The second terminal of transistor M5s is connected to the first terminal of transistor M3, and The first terminal of transistor M4 is electrically connected to the gate of transistor M5s, and the wiring It is electrically connected to S2L.

[0316] In circuit MP in Figure 17, circuit MCr has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0317] Wiring VLs functions as wiring that supplies a constant voltage, and this constant voltage is low-level voltage. This can be the VSS (Variable Level Saturation), other low-level potentials besides VSS, or the ground potential. The constant voltage may be VDD, which is a high-level potential. Also, the wiring VLs are supplied The constant voltage may be different from or the same as the constant voltage supplied by wiring VL. When the constant voltage supplied by VL and the wiring VLs are approximately equal, the wiring VLs are the same as the wiring VL. It can be represented as a line.

[0318] Wiring VLsr functions as wiring that supplies a constant voltage, and this constant voltage is low level. This can be the VSS (Variable Voltage System), other low-level potentials besides VSS, the ground potential, etc. The constant voltage may be VDD, which is a high-level potential. Also, the wiring VLsr is The constant voltage supplied may be different from or the same as the constant voltage supplied by the wiring VLr. When the constant voltages supplied by wiring VLr and wiring VLsr are approximately equal, wiring VLsr is equal to wiring V The wiring can be the same as for Lr.

[0319] Furthermore, the constant voltages provided by each of the wires VL, VLs, VLr, and VLsr are They may have different voltages or the same voltage. Also, wiring VL, wiring VLs, wiring The constant voltages supplied by two or three wires selected from line VLr and wiring VLsr are equal to each other. It's fine.

[0320] Wiring S1L controls the ON / OFF state of transistors M5 and M5r. Wiring S2L functions as a wire that supplies potential for transistor M5s, and As wiring that supplies the potential to turn transistor M5sr on or off, To be able to.

[0321] The circuit MP shown in Figures 5C and 5D should apply the configuration shown in the circuit MP of Figure 17. This allows for the storage of two weight coefficients. Specifically, the circuit MP in Figure 17 is 1 The potential corresponding to the weight coefficient of the first element is determined by the holding part HC of the circuit MC and the holding part HCr of the circuit MCr. , held in place, the potential corresponding to the second weight coefficient is applied to the holding part HCs of the circuit MC and the circuit MC The holding part HCsr can hold it. Also, the circuit MP in Figure 17 has wiring S1L. The weight coefficients used in the calculation can be switched depending on the potential supplied from wiring S2L. For example, the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 110 contain Each retaining part HC and retaining part HCr has a weighting coefficient w1 (k-1) j (k) Or maybe lol m (k-1 ) j (k) It maintains a potential equivalent to the circuit MP[1,j] of the calculation circuit 110 or circuit MP Each retaining part HCs and HCsr included in [m,j] has a weighting coefficient w1 (k-1) h ( k) Or maybe lol m (k-1) h (k) (Here, h is an integer greater than or equal to 1 and not equal to j.) Maintain the corresponding potential, and connect wiring XLS[1] to wiring XLS[m] (circuit MP in Figure 17) The signal z1 is connected to the wiring X1L, X2L. (k-1) ~z m (k-1) Input the appropriate electric potential. At this time, a high-level potential is applied to the wiring S1L, and transistor M5, transistor Turn on transistor M5r and apply a low-level potential to the wiring S2L, then transistor M5s, By turning off transistor M5sr, the circuit MP[1,j] of the arithmetic circuit 110 The circuit MP[m,j] is determined by the weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) It is possible to perform product-sum and activation function operations with [the specified value]. Also, by applying a low-level potential to the wiring S1L, transistor M5, transistor M5 With r turned off, a high-level potential is applied to the wiring S2L, and transistor M5s, By turning on the ZISTA M5sr, the circuit MP[1,j] of the arithmetic circuit 110 or the circuit MP[m,j] is the weight coefficient w1 (k-1) h (k) Or maybe lolm (k-1) h (k) and signal z1 (k-1) ~z m (k-1) It is possible to perform sum-of-product and activation function operations with respect to [the specified variable].

[0322] As described above, by applying the circuit MP in Figure 17 to the arithmetic circuit 110, the weight coefficients can be calculated. It can hold two values, and the weight coefficients can be switched to perform sum-of-products and activation function operations. This is possible. The arithmetic circuit 110 that constitutes the circuit MP in Figure 17, for example, the k-th layer - When the number of rons is greater than n, when operations are performed in an intermediate layer different from the kth layer, etc. This is effective. Also, in the circuit MP of Figure 17, the holding part of circuit MC and circuit MCr Each of the above is set to 2, but each of the circuit MC and circuit MCr can be set to 3 depending on the situation. The device may have the above-mentioned retaining parts.

[0323] <Configuration Example 4> The circuit MP shown in Figure 18A is a circuit that can be applied to the circuit MP in Figure 5A, and the holding part HC, And each of the holding part HCr is a load circuit LC instead of capacitive element C1 and capacitive element C1r. It differs from circuit MP in Figure 9A in that it has a load circuit LCr.

[0324] In the circuit MC of circuit MP in Figure 18A, the first terminal of the load circuit LC is connected to transistor M. The second terminal of transistor 1, the first terminal of transistor M3, and the first terminal of transistor M4 are connected to the They are electrically connected, and the second terminal of the load circuit LC is electrically connected to the wiring VL.

[0325] Note that circuit MCr of circuit MP in Figure 18A has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0326] Here, wiring VL and wiring VLr function as wiring that supplies a constant voltage VCNS. For example, CNS could be ground potential (GND), or the load circuit LC, or the load circuit LCr. The potential can be kept low enough to operate at all times.

[0327] Load circuit LC and load circuit LCr are, for example, the resistance values ​​between the first terminal and the second terminal. This is a circuit that can change the load circuit LC and the first and second terminals of the load circuit LCr. By changing the resistance value between the child, the first terminal and the second terminal of the load circuit LC and load circuit LCr can be changed. The amount of current flowing between the two terminals can be changed.

[0328] Here, in circuit MP of Figure 18A, the first terminal and the second terminal of load circuit LC and load circuit LCr This explains how to change the resistance value between two terminals. First, wire X1L, wire X2 A low-level potential is applied to each of L, and transistors M3, M3r, and Turn off transistors M4 and M4r. Next, apply a high-level potential to the wiring WL. This forces transistors M1 and M1r to turn on, and changes the potential of wiring IL (wiring ILB). By doing so, the resistance value between the first and second terminals of the load circuit LC (load circuit LCr) is changed. Set it up. For example, the first load circuit LC (load circuit LCr) in wiring IL (wiring ILB) A potential is input to reset the resistance between the terminal and the second terminal, and then the wiring IL (Wiring ILB) has a resistor between the first and second terminals of the load circuit LC (load circuit LCr). One method is to input a potential that will result in the desired value. (Load circuit LC) After setting the resistance value between the first and second terminals of r) to the desired value, low-voltage wiring WL is used. Simply input a bell potential to turn off transistors M1 and M1r.

[0329] For the load circuit LC and load circuit LCr, for example, as shown in Figure 18B, the resistance changes A VR element can be used. Also, as the load circuit LC and load circuit LCr, for example... As shown in Figure 18C, the circuit VC can include an MTJ element MR. Furthermore, as the load circuit LC and load circuit LCr, for example, as shown in Figure 18D, the phase change Resistors containing phase change materials used in PCMs and the like (as specified herein, etc.) For convenience, a phase-change memory (PCM) can be used.

[0330] Furthermore, the circuit MP using load circuit LC and load circuit LCr is not limited to the configuration shown in Figure 18A. The configuration of circuit MP in Figure 18A is not fixed and can be changed depending on the situation. An example of changing the circuit MP is to add wiring IL and wiring ILB to circuit MP in Figure 18A, and the transition A circuit configuration can be made without providing sta M1 and transistor M1r. Figure 19 shows This is a circuit diagram showing the said circuit configuration, and is one example of the configuration of circuit MP in Figure 5D.

[0331] In the circuit MP shown in Figure 19, the setting of the resistance value between the first and second terminals of the load circuit LC. This involves inputting a high-level potential to wiring X1L and a low-level potential to wiring X2L, and then applying it to transistor M Set transistor 3 to ON and transistor M4 to OFF, and wire from IOL through transistor M3 This can be done by applying a potential to the first terminal of the load circuit LC. From the wiring IOLB, a potential is transmitted to the first terminal of the load circuit LCr via transistor M3r. Because it can be provided, simultaneously with the load circuit LC, the first and second terminals of the load circuit LCr The resistance value between them can also be set.

[0332] Furthermore, the resistance value between the first and second terminals of the load circuit LC is set to low resistance in wiring X1L. By applying a high-level potential to the bell potential and wiring X2L, transistor M3 is turned off. Turn on transistor M4, and connect the wiring from IOLB through transistor M4 to the load circuit LC. This can also be done by applying a potential to the first terminal. A potential can be applied to the first terminal of the load circuit LCr via transistor M4r. Therefore, simultaneously with the load circuit LC, the resistance value between the first and second terminals of the load circuit LCr is set. It is also possible to set a fixed price.

[0333] Furthermore, the first load circuits LC and LCr shown in Figures 18A and 19 The resistance between the terminal and the second terminal may be binary, or ternary or more, and may also be an analog value. You may do so.

[0334] <Configuration Example 5> Circuit MP shown in Figure 20A is a circuit that can be applied to circuit MP in Figure 5A, and the holding part HC, Each of the holding HCr elements replaces the capacitive element C1 and the capacitive element C1r with an inverter loop. It differs from circuit MP in Figure 9A in that it has a different circuit configuration.

[0335] In the circuit MC of circuit MP in Figure 20A, the holding part HC is connected to the inverter circuit INV1, It has an inverter circuit INV2 and the input terminal of inverter circuit INV1. The output terminal of circuit INV2, the second terminal of transistor M1, and the gate of transistor M2 It is electrically connected to and . Also, as explained in Figure 9A, the part of transistor M1 2 terminals, the gate of transistor M2, the input terminal of inverter circuit INV1, and inverter The output terminal of the data circuit INV2 and the electrical connection point are referred to as node nd1. nd1 is not an input terminal of inverter circuit INV1, but an output terminal of inverter circuit INV1. It may be connected to a power terminal.

[0336] Note that circuit MCr of circuit MP in Figure 20A has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0337] The retaining part HC included in the circuit MC is the inverter circuit INV1 and the inverter circuit I The NV2 and the holding part H included in the circuit MCr form an inverter loop. Cr is an inverter, and is an inverter, with inverter circuit INV1r and inverter circuit INV2r. A loop is formed. In other words, the circuit MP in Figure 20A consists of a holding part HC and a holding part H Each inverter loop of Cr maintains a potential corresponding to the weighting coefficient. can.

[0338] Note that in circuit MP of Figure 20A, inverter circuit INV1 and inverter circuit INV1r The inverter circuits INV2 and INV2r are shown in the diagram, but the inverter circuit Circuit INV1, Inverter circuit INV1r, Inverter circuit INV2, Inverter circuit IN At least one of V2r is a logic that receives an input signal and outputs an inverted signal of that input signal. It may be replaced with a circuit. Examples of such logic circuits include NAND gates, NOR gates, XOR circuits, circuits combining these, etc., can be used. Specifically, inverters When replacing the circuit with a NAND gate, set one of the two input terminals of the NAND gate to a fixed potential. By inputting a high-level potential, the NAND gate can function as an inverter circuit. Yes, it is possible. Also, when replacing an inverter circuit with a NOR circuit, the two input terminals of the NOR circuit By inputting a low-level potential as a fixed potential to one side, the NOR circuit becomes an inverter circuit. It can function in this way. Also, when replacing an inverter circuit with an XOR circuit, XO By inputting a high-level potential as a fixed potential to one of the two input terminals of the R circuit, the XOR circuit is formed. It can function as an inverter circuit.

[0339] As described above, the inverter circuits described in this specification include NAND gates and NOR gates. It can be replaced with logic circuits such as paths, XOR circuits, or circuits that combine these. Therefore, in this specification and elsewhere, the term "inverter circuit" is used instead of "logic circuit". It can be referred to as such.

[0340] Furthermore, the circuit MP in Figure 20A can be modified depending on the situation. Figure 20A An example of a modified circuit MP is shown in Figure 20B. The circuit MP in Figure 20B is the same as the circuit in Figure 20A. The MP has a configuration where the retaining part HCr is removed from the circuit MCr, and the retaining part HC of the circuit MC is the circuit It is configured to be electrically connected to the gate of the MCr transistor M2r.

[0341] Figure 20B shows the output terminal of inverter circuit INV1 and the input of inverter circuit INV2. The terminal and the electrical connection point are designated as node nd2. In other words, the gate of transistor M2r. The potential of node nd2 is input to the terminal.

[0342] The circuit MP shown in Figure 20B does not include a holding part HCr in the circuit MCr, and is a transistor. The potential applied to the gate of M2r is maintained by the holding part HC of the circuit MC. The HC section consists of an inverter circuit INV1 and an inverter circuit INV2. Because it has a p configuration, either a high-level potential or a low-level potential is maintained at node nd1. At node nd2, either a high-level potential or a low-level potential is maintained.

[0343] Furthermore, due to the configuration of the inverter loop, the holding unit HC is located at node nd1 and node nd2. It is not possible to maintain the same potential for each. Therefore, in circuit MP in Figure 20B The weight is represented by maintaining the same potential at node nd1 and node nd2, respectively. It is not possible to set the coefficient. Specifically, in the above example of operation, transistor M 2. Because a low-level potential cannot be maintained at each gate of transistor M2r, Figure 20 It is not possible to set the weight coefficient "0" for circuit MP of B.

[0344] <Configuration Example 6> The circuit MP shown in Figure 21A is a circuit that can be applied to the circuit MP in Figure 5A, and the holding part HC, Each of the holding HCr components has two transistors and two capacitive elements, etc. Therefore, it differs from circuit MP in Figure 9A.

[0345] In the circuit MC of circuit MP shown in Figure 21A, the holding part HC is a transistor M1, It has transistor M1s, capacitive element C2, and capacitive element C2s. Terminal 1 is electrically connected to wiring IL, and terminal 2 of transistor M1 is connected to capacitive element C2 The first terminal of transistor M1 is electrically connected to the gate of transistor M6, and the first terminal of transistor M1 is electrically connected to the gate of transistor M6. The gate is electrically connected to the wiring WL. The first terminal of transistor M1s is connected to the wiring Electrically connected to IL, the second terminal of transistor M1s is connected to the first terminal of capacitive element C2s. The gate of transistor M7 is electrically connected to the gate of transistor M1s. It is electrically connected to the wiring WL. Furthermore, as explained in Figure 9A, transistor M1 The electrical connection between the second terminal, the gate of transistor M6, and the first terminal of capacitive element C2. The point is called nd1, and it is connected to the second terminal of transistor M1s and the gate of transistor M7. The electrical connection point between the first terminal of the capacitive element C2s and the other terminal is called nd1s.

[0346] The second terminal of the capacitive element C2 is electrically connected to the wiring X1L, and the second terminal of the capacitive element C2s The child is electrically connected to wiring X2L.

[0347] The first terminal of transistor M6 is electrically connected to the first terminal of transistor M7 and to the wiring VL. The second terminal of transistor M6 is electrically connected to wiring OL. The second terminal of the ZISTA M7 is electrically connected to the wiring OLB.

[0348] Note that circuit MCr of circuit MP in Figure 21A has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0349] The holding part HC included in the circuit MC is at a potential due to the capacitance elements C2 and C2s. It has the function of maintaining the transistor. Specifically, it inputs a high-level potential to the wiring WL and After turning on transistor M1 and transistor M1s, a predetermined potential is applied to the wiring IL. As a result, the potential is written to the first terminal of each of the capacitive element C2 and the capacitive element C2s. Then, a low-level potential is input to the wiring WL, and transistor M1, transistor By turning off M1s, the nodes nd1 and nd1s of the holding part HC are respectively The potential can be maintained in this manner. Furthermore, a predetermined potential can be written to the holding part HC and held. In this process, the potentials of wiring X1L and wiring X2L are, for example, set to a constant potential. Preferably, the potential should be higher than the low-level potential and lower than the high-level potential. For convenience, this constant potential will be referred to as the reference potential.

[0350] Furthermore, in circuit MP of Figure 21A, the wiring WL is connected to the retaining part HC and the retaining part HCr. Since they are electrically connected to each other, the holding part HC and the holding part HCr each have weight When writing and retaining the potential corresponding to the coefficient, when the potential of the wiring WL is a high-level potential... Simultaneously, a predetermined potential is written to the holding part HC and the holding part HCr, and then the wiring WL Lowering the potential to a low level, transistors M1, M1s, and M1r And transistor M1sr should be turned off simultaneously.

[0351] Furthermore, the neuron signal input to circuit MP is defined as follows: Wiring X A voltage higher than the reference potential (hereinafter referred to as the high-level potential) is applied to 1L, and the reference voltage is applied to wiring X2L. When a voltage lower than the specified level (hereinafter referred to as the low-level potential) is applied to circuit MP, When "+1" is input as a neuron signal, a low-level potential is applied to wiring X1L, and wiring X2 When a high-level potential is applied to L, the circuit MP receives a neuron signal of "-1 When " is input and a low-level potential is applied to each of the wires X1L and X2L The circuit MP is assumed to receive "0" as the neuron's signal.

[0352] For example, after holding a potential equivalent to the weighting coefficient in the holding part HC and holding part HCr, the circuit When "+1" is input to MP as a neuron signal, a high-level potential is applied to wiring X1L. Therefore, the potentials of nodes nd1 and nd1r are such that the potentials of capacitive element C2 and capacitive element C2 The capacitance increases due to the capacitive coupling by r. As a result, transistor M6, transistor M6 Because the potential of each gate of r increases, transistors M6 and M6r It turns ON. Also, a low-level potential is input to wiring X2L, so node nd1s, The potentials of each node nd1sr are capacitively coupled by the capacitive elements C2s and C2sr. This lowers the respective gates of transistor M7 and transistor M7r. Because the potential of the terminal becomes low, transistors M7 and M7r turn off. In other words, when a "+1" signal is input to circuit MP as a neuron signal, circuit M The circuit between C and wiring OL becomes conductive, and the circuit between MCr and wiring OLB becomes conductive. .

[0353] Furthermore, for example, after holding a potential corresponding to the weighting coefficient in the holding part HC and the holding part HCr... When "-1" is input to circuit MP as the neuron signal, a low-level electric current is supplied to wiring X1L. Since the position is input, the potentials of node nd1 and node nd1r are the same as those of the capacitive element C2. The capacitance is reduced by capacitive coupling with the capacitive element C2r. As a result, transistor M6, Because the potential of each gate of transistor M6r becomes lower, transistor M6, transistor The M6r will be in the off state. Also, a high-level potential will be input to the X2L wiring, so The potentials of node nd1s and node nd1sr are the same as those of capacitive elements C2s and C2sr. This increases due to capacitive coupling. As a result, transistors M7 and M7r Because the potential of each gate increases, transistors M7 and M7r turn on. This is the state that occurs. In other words, when "-1" is input to circuit MP as a neuron signal, Then, the circuit MC and the wiring OLB become conductive, and the circuit MCr and the wiring OL become conductive. It enters a normal state.

[0354] Furthermore, for example, after holding a potential corresponding to the weighting coefficient in the holding part HC and the holding part HCr... When "0" is input to circuit MP as a neuron signal, a low-level potential is present in wiring X1L. Because this is input, the potentials of node nd1 and node nd1r are the same as those of the capacitive element C2. The capacitance is reduced by the capacitive coupling by the element C2r. As a result, transistor M6 and Because the potential of each gate of transistor M6r becomes lower, transistor M6 and The M6r transistor will be in the off state. Also, a low-level potential will be input to the X2L wiring. The potentials of node nd1s and node nd1sr are those of capacitive element C2s and capacitive element C2 It is reduced by capacitive coupling by sr. As a result, transistor M7 and the transistor Because the potential of each gate of transistor M7r becomes lower, transistor M7 and the transistor The M7r is turned off. In other words, the circuit MP receives a "0" as a neuron signal. As a result, the relationship between circuit MC and circuit MCr and wiring OL and wiring OLB is , it becomes non-conductive.

[0355] Note that transistors M6, M6r, M7, and transistor For example, the ON state of M7r is preferably in the saturation region. Transistor M6, transistor M6r, transistor M7, and transistor M7r Each gate, source, and drain is properly configured to operate in the saturation region when on. It is preferable that it is biased. Transistor M6, Transistor M6r, Transistor By operating the ON states of transistors M7 and M7r in the saturation region, When the gate-source potential increases, the current flowing between the source and drain of the transistor increases. The value increases. In other words, when wiring X1L (wiring X2L) is at a high potential, the transient Source-D for transistors M6, M6r (transistor M7, M7r) The current flowing between nodes is given by node nd1, node nd1r(node ​​nd1s, node nd It is determined by the magnitude of the potential of 1 sr). However, one aspect of the present invention is not limited thereto. stomach.

[0356] Furthermore, the circuit MP in Figure 21A can be modified depending on the situation. Figure 21A An example of a modified circuit MP is shown in Figure 21B. The circuit MP in Figure 21B is the same as the one in Figure 21A. Transistor M6, Transistor M6r, Transistor M7, and Transistor M7r The configuration excludes the block gate. Therefore, the transistors included in the circuit MP M6, transistor M6r, transistor M7, and transistor M7r are transistors It can be decided at the design stage, regardless of the structure of the device.

[0357] For example, transistors M6, M6r, M7, and in Figure 21B The M7r transistor contains either single-crystal silicon or non-single-crystal silicon in its active layer. It can be an Si transistor. Also, transistor M6 in Figure 21B, Transistors M6r, M7, and M7r contain an oxide semiconductor in their active layer. It can be an OS transistor. Also, transistor M6, transistor M6r, transistor M7, and transistor M7r are organic semiconductors, compound semiconductors. It may also be a transistor that has a body or other components.

[0358] As described above, by applying the circuit MP shown in Figures 21A and 21B to the arithmetic circuit 110 Similar to the MP circuit in Figure 9A, sum-of-products and activation function operations can be performed.

[0359] <Configuration Example 7> In Configuration Examples 1 to 6, the weight coefficients held by the circuit MP are "+1", "-1", and "0 The three values ​​of ", and the neuron signal corresponding to the potential input from wiring X1L and wiring X2L are " This section describes a circuit MP that can calculate the product of three values: +1, -1, and 0. As explained, in this example configuration, the weight coefficients are three values: "+1", "-1", and "0". The neuron's signal (calculated value) can be either "+1" or "0", and its product can be calculated. Let's explain the MP circuit.

[0360] The circuit MP shown in Figure 22A is obtained by removing transistors M4 and M4r from the circuit MP in Figure 9A. This is the circuit. Also, since transistors M4 and M4r have been removed, in Figure 22A... The wiring for inputting potential to the gates of transistors M4 and M4r Wire X2L is also excluded. Furthermore, the wiring corresponding to wiring X1L is labeled as wiring XL in Figure 22A. It is included.

[0361] The weighting coefficient set in circuit MP in Figure 22A is the high-level electric current at node nd1 of the holding part HC. The value is set to "+1" when a low-level potential is maintained at node nd1r of the holding part HCr. Low-level potential at node nd1 of the retaining part HC, and high-level potential at node nd1r of the retaining part HCr. If the potential is maintained, it is set to "-1", and a low-level potential is set at node nd1 of the holding part HC. This value is set to "0" when a low-level potential is maintained at node nd1r of the holding part HCr.

[0362] Furthermore, the neuron signal input to circuit MP in Figure 22A has a high-level potential in wiring XL. When a voltage is applied, it is set to "+1", and when a low-level potential is applied to wiring XL, Set it to "0".

[0363] For the operation of circuit MP in Figure 22A, please refer to the explanation of the operation example in Configuration Example 1.

[0364] In circuit MP in Figure 22A, as described above, the weight coefficient and the input neuron signal When defined, in each weight coefficient case, the neuron's signal enters the circuit MP. As a result of the force applied, the current I is output from node outa of wiring OL. OL Changes Current I output from node outb of an OLB with no wiring OLB Whether or not there has been a change is as follows: The table below shows the results. In the table below, high-level potentials are indicated as "high," and low-level potentials are indicated as "high." It is written as "low".

[0365] [Table 3]

[0366] As shown in the table above, the circuit MP in Figure 22A has three weight coefficients: "+1", "-1", and "0". Then, the product of the neuron's signal, which is either "+1" or "0", can be calculated. The weight coefficients do not have to be 3 values; they can be 2 values ​​or 3 or more values. For example, “+ It can also be a binary value of 1" or "0", or a binary value of "+1" or "-1". Alternatively, it can be a weighting coefficient. This can be an analog value or a multi-bit (multi-level) digital value.

[0367] In this example, the holding parts HC of circuit MP and circuit MCr are each... The potential held in the holding part HCr was set to either a high-level potential or a low-level potential, but the holding The HC section and the holding section HCr may hold potentials that represent analog values. For example, weighted In the case of a "positive analog value" as a number, a high level of analog is set to node nd1 of the holding unit HC. A low-level potential is maintained at node nd1r of the holding part HCr. In the case of a "negative analog value," for example, a low-level potential is applied to node nd1 of the holding unit HC. A high level of analog potential is maintained at node nd1r of the holding part HCr. Flow I OL and current I OLB The magnitude of the current will depend on the analog potential.

[0368] Circuit MP in Figure 22A, like circuit MP in Figure 16A, uses a single wire for wiring IL and wiring ILB. It is also possible to combine them and divide the wiring WL into wiring W1L and W2L. The configuration is shown in Figure 22B. Circuit MP in Figure 22B is applied to the arithmetic circuit 120 in Figure 6 as an example. This is possible. Furthermore, the operation method of circuit MP in Figure 22B is explained in the circuit M in Figure 16A. Refer to the description of how P operates.

[0369] Furthermore, circuit MP in Figure 22A is configured by dividing wiring XL into wiring X1L and wiring X2L. This is also acceptable. Such a circuit configuration is shown in Figure 22C. Wiring X1L and wiring X2L each have If a high-level potential or a low-level potential is applied, the transistors M3 and M3r... There are four possible combinations of the on and off states for each. Also, the holding part HC, the holding part Each node nd1 and node nd1r of HCr has either a high-level potential or a low-level potential. Assuming that the potentials are maintained, the combination of potentials held at node nd1 and node nd1r is There are four possible outcomes.

[0370] Specifically, a high-level potential is maintained at node nd1, and a high-level potential is marked on wiring X1L. When connected, wiring OL and wiring VL are electrically connected, so current flows into wiring OL. Current quantity I OL This changes. Also, a high level potential is maintained at node nd1r, and wiring X2 When a high-level potential is applied to L, the wiring OLB and wiring VLr are electrically connected. Therefore, the amount of current flowing through the wiring OLB is I OLB This changes. In circuit MP in Figure 22C The combination of potentials held at nodes nd1 and nd1r, and the given wiring X1L and X2L The combination of potentials, and the output from node outa of wiring OL, are determined by these. current I OLWhether or not there is a change, and the current I output from node outb of the wiring OLB. OLB The presence or absence of changes is as shown in the table below. Note that in the table below, high-level potential is referred to as high. It is described as such, and low-level potentials are indicated as "low".

[0371] [Table 4]

[0372] Next, we will describe a circuit with a different configuration from circuit MP shown in Figures 22A to 22C.

[0373] The circuit MP shown in Figure 23A, like the circuit MP in Figure 22A, has weight coefficients of "+1" and "- We calculate the product of the three values ​​"1" and "0" and the two values ​​"+1" and "0" from the neuron's signal. In the circuit, the circuit MP in Figure 21A has transistors M1s, M1sr, and The circuit does not include transistor M7, transistor M7r, and capacitive elements C2s and C2sr. This is the circuit configuration. Also, since the capacitive elements C2s and C2sr have been removed, Figure 23A So, to input a potential to the second terminals of the respective capacitive elements C2s and C2sr... Wiring X2L is also excluded. Furthermore, the wiring corresponding to wiring X1L is shown as wiring XL in Figure 23A. It is stated.

[0374] For the operation of Figure 23A, please refer to the description in Configuration Example 6.

[0375] Similar to the circuit MP in Figure 22A, the weight coefficients and neurons are applied to the circuit MP in Figure 23A. By defining the signal and, as shown in the table above, the weight coefficients are "+1", "-1", and It is possible to calculate the product of the trinity of "0" and the binary values ​​of the neuron's signal, "+1" and "0". It can be done. Note that the weight coefficients can be binary (not necessarily 3-value), or even 3 or more values. Example For example, it could be a binary value of "+1" or "0", or a binary value of "+1" or "-1". The weight coefficients can be analog values ​​or multi-bit (multi-level) digital values. For example , circuit MP, circuit MC, circuit MCr, holding part HC, held by holding part HCr The potential was set to either a high-level potential or a low-level potential, but the holding part HC and holding part HCr were analogous The potential representing the value may be maintained. For example, in the case of a "positive analog value" as the weighting coefficient. This involves a high-level analog potential at node nd1 of the holding part HC, and node nd1 of the holding part HCr. A low-level potential is maintained at r. For example, if the weighting coefficient is a "negative analog value," For example, a low-level potential at node nd1 of the holding part HC, and a high-level potential at node nd1r of the holding part HCr. The analog potential of the bell is maintained. And the current I OL and current I OLB Large current The size will be determined by the analog potential.

[0376] Circuit MP in Figure 23A, like circuit MP in Figure 16A, uses a single wire for wiring IL and wiring ILB. Alternatively, the wiring WL may be divided into wiring W1L and wiring W2L. The circuit configuration is shown in Figure 23B. Circuit MP in Figure 23B is, as an example, connected to the arithmetic circuit 120 in Figure 6. It can be applied. Note that the operation method of circuit MP in Figure 23B is described in Figure 16A. Refer to the description of how the MP works.

[0377] Also, circuit MP in Figure 23A is similar to circuit MP in Figure 22C, where wiring XL is connected to wiring X1L. The configuration may also be divided into wiring X2L. Such a circuit configuration is shown in Figure 23C. Wiring X1 If L and wiring X2L are each supplied with either a high-level potential or a low-level potential, Combinations of the on and off states of transistors M6 and M6r There are four possibilities. Also, nodes nd1 and n of the holding part HC and holding part HCr respectively. Assuming that a high-level potential or a low-level potential is maintained at d1r, node nd1, There are four possible combinations of potentials held at node nd1r. For example, circuit MP The circuit MC, the holding part HC of the circuit MCr, and the potential held in the holding part HCr are high Level potential or low-level potential is used, but analog values ​​are shown for the holding part HC and holding part HCr. The potential may be held. For example, if the weighting coefficient is a "positive analog value", the holding part A high-level analog potential is applied to node nd1 of the HC, and a low-level analog potential is applied to node nd1r of the holding section HCr. The potential is maintained. In the case of a “negative analog value” as the weighting coefficient, for example, the potential is maintained. A low-level potential is present at node nd1 of the HC part, and a high-level potential is present at node nd1r of the holding part HCr. The log potential is maintained. And the current I OL and current I OLB The magnitude of the current is, The magnitude will depend on the analog potential.

[0378] In circuit MP in Figure 23C, the change in current flowing through wiring OL and wiring OLB is shown in Figure 22C. It can be considered similarly to the circuit MP in Figure 23C. Therefore, in the circuit MP in Figure 23C, The combination of potentials held at node nd1 and node nd1r, and the given wiring X1L and X2L The combination of potentials, and the output from node outa of wiring OL, are determined by these. current I OL Whether or not there is a change, and the current I output from node outb of the wiring OLB. OLB Whether or not there is a change is as shown in the table above, which was explained using circuit MP in Figure 22C.

[0379] <Configuration Example 8> Circuit MP shown in Figure 24A is an example of a circuit that can be applied to circuit MP in Figure 5F.

[0380] The circuit MP in Figure 24A includes circuit MC, circuit MCr, and transistor MZ.

[0381] Note that circuit MCr of circuit MP in Figure 24A has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0382] Furthermore, the circuit MC has a holding part HC and a transistor M8, and the circuit MCr is a holding part It has a part HCr and a transistor M8r.

[0383] The retaining part HC included in the circuit MC of circuit MP in Figure 24A is, for example, as shown in Figures 9A to Circuit MP, as shown in Figures 9C, 10A, 10B, 11A, 11B, 12A, and 12B. The retaining part HC included in the circuit MC can be configured similarly.

[0384] The first terminal of transistor M8 is electrically connected to the first terminal of transistor MZ, The gate of transistor M8 is connected to the second terminal of transistor M1 and the first terminal of capacitive element C1. The second terminal of transistor M8 is electrically connected to the wiring OL. The second terminal of the capacitive element C1 is electrically connected to the wiring CVL. The first terminal of M1 is electrically connected to wiring IL.

[0385] Furthermore, the first terminal of transistor M8r is electrically connected to the first terminal of transistor MZ. The gate of transistor M8r is connected to the second terminal of transistor M1r and the capacitive element C1 The first terminal of r is electrically connected to the OLB, and the second terminal of transistor M8r is connected to the OLB wiring. They are electrically connected. The second terminal of the capacitive element C1r is electrically connected to the wiring CVL. The first terminal of transistor M1 is electrically connected to the wiring ILB.

[0386] Wiring CVL functions, for example, as wiring that provides a constant voltage. For example, these can be high-level potential, low-level potential, ground potential, etc.

[0387] The retaining parts HC and HCr included in circuit MP in Figure 24A are shown in Figure 9A, etc. Similar to the retaining parts HC and HCr included in the circuit MP, the potential is proportional to the weighting coefficient. It can maintain. Specifically, for example, by applying a predetermined potential to the wiring WL, Turn on transistor M1 and transistor M1r, and from wiring IL to the first of capacitive element C1 By supplying potential to terminal 1, and then supplying potential from the wiring ILB to the first terminal of the capacitive element C1r, i. Then, a predetermined potential is applied to the wiring WL, and transistor M1, and transistor M1 You just need to turn off r.

[0388] Here, for example, the weight coefficient set in circuit MP in Figure 24A is node n of the holding part HC. In a case where a high-level potential is maintained at d1 and a low-level potential is maintained at node nd1r of the holding part HCr. Set the combined value to "+1", set the low-level potential at node nd1 of the holding part HC, and node n of the holding part HCr. If a high-level potential is maintained at d1r, it is set to "-1", and the node nd1 of the holding part HC When a low-level potential is maintained at node nd1r of the holding part HCr, Set it to "0".

[0389] A potential corresponding to the weight coefficient is maintained in each of the holding parts HC and HCr. Therefore, the gate potentials of transistors M8 and M8r are determined. Here, by applying a potential to the wiring XL, for example, according to the value of the neuron's signal... The current flowing from circuit MP to wiring IL and / or wiring ILB is determined. For example, wiring X When a high-level potential is applied to L as the second data "1", the constant voltage provided by wiring VL This is applied to the first terminal of transistor M8 and the first terminal of transistor M8r. When the gate potential of transistor M8 is at a high level potential, transistor M8 Current flows between the first and second terminals, and the gate potential of transistor M8 is at a low level. When the potential is zero, no current flows between the first and second terminals of transistor M8. Furthermore, when the gate potential of transistor M8r is at a high-level potential, transistor M8r Current flows between the first and second terminals, and the gate potential of transistor M8r is lowered to a low level. When the potential is zero, no current flows between the first and second terminals of transistor M8r. Also, for example, when a low-level potential is applied to wiring XL as a second data of "0", The first terminal of transistor M8 and the first terminal of transistor M8r are connected by a wire VL. Since no constant voltage is applied, the current between the first and second terminals of each transistor is It won't flow.

[0390] In short, to summarize the above, the product of the weight coefficient and the value of the neuron's signal is "+1". At that time, a predetermined current flows from circuit MC to wiring OL, and a predetermined current flows from circuit MCr to wiring OLB. No flow occurs. Also, when the product of the weight coefficient and the value of the neuron's signal is "-1", A predetermined current flows from the circuit MCr to the wiring OLB, and a predetermined current flows from the circuit MC to the wiring OL. No. Also, when the product of the weight coefficient and the value of the neuron's signal is "0", from the circuit MC No current flows through wiring OL, and the specified current does not flow from circuit MCr to wiring OLB.

[0391] Based on the above, the circuit MP in Figure 24A has a weighting coefficient similar to the circuit MP described in Configuration Example 7. The three values ​​are "+1", "-1", and "0", and the neuron's signal (calculated value) is "+1" or "0". The product of the two values ​​of and can be calculated. Furthermore, the circuit MP in Figure 24A is explained in Configuration Example 7. Similar to the MP circuit, the weight coefficients can be analog values, multi-bit (multi-level) digital values, etc. That's fine.

[0392] Furthermore, the circuit MP shown in Figure 24A can be applied to an arithmetic circuit, which is a semiconductor device according to one aspect of the present invention. This may be modified as appropriate depending on the situation.

[0393] For example, when applying circuit MP in Figure 24A to the arithmetic circuit 130 in Figure 7, the circuit in Figure 24A MP can be modified to the circuit MP shown in Figure 24B. In circuit MP of A, wiring OL and wiring IL are combined into a single wiring, wiring IOL. Furthermore, the wiring OLB and wiring ILB are combined into a single wiring configuration called wiring IOLB. This is the case. Note that the wiring XL shown in Figure 24B is the same as the wiring XLS[1] to wiring shown in Figure 7. It corresponds to any one of the XLS[m], and the wiring WL shown in Figure 24B is the same as the wiring WLS shown in Figure 7. [1] Equivalent to any one of the following: wiring WLS[m]

[0394] Furthermore, the circuits that can be applied to circuit MP in Figure 5A are not limited to circuit MP in Figure 24A.

[0395] For example, the circuit MP in Figure 18A, explained in Configuration Example 4, can be applied to the circuit MP in Figure 5A. It can be transformed into a path. The circuit MP shown in Figure 25A can be applied to the circuit MP in Figure 5A. The circuit includes a holding section HC containing a load circuit LC, similar to Figure 18A, and a load circuit LCr. It has a retaining part HCr and a circuit MP of Figure 24A. Refer to the explanation of the operation example of the circuit MP in Figure 18A.

[0396] For example, when applying circuit MP in Figure 25A to the arithmetic circuit 130 in Figure 7, Figure 25A The circuit MP can be modified to the circuit MP shown in Figure 25B. The circuit MP in Figure 25B is In circuit MP in Figure 25A, wiring OL and wiring IL are treated as a single wiring, IOL. To combine them, the OLB wiring and ILB wiring are combined into a single wiring, called IOLB, and Furthermore, the configuration does not include transistors M1 and M1r. The wiring XL shown in Figure 25B is any of the wiring XLS[1] to wiring XLS[m] shown in Figure 7. It corresponds to one of the following, and the wiring WL shown in Figure 25B is the same as the wiring WLS[1] to wiring WL shown in Figure 7. It corresponds to one of S[m].

[0397] Furthermore, for example, the circuit MP in Figure 20A explained in Configuration Example 5 can be applied to the circuit MP in Figure 5A. It can be transformed into a circuit. Circuit MP shown in Figure 26A is applicable to circuit MP in Figure 5A. This is a circuit that can be formed, and similar to Figure 20A, includes inverter circuit INV1 and inverter circuit IN The holding part HC including V2, and inverter circuits INV1r and INV2r are included. It has a retaining part HCr. Note that the circuit MP in Figure 26A has transistor M3, Transistors M3r, M4, and M4r are not provided. (See Figure 26A) For details on its operation, please refer to the explanations of the operation examples such as circuit MP in Figure 24A and circuit MP in Figure 20A. do.

[0398] Furthermore, for example, the circuit MP in Figure 20B, explained in Configuration Example 5, can be applied to the circuit MP in Figure 5A. It can be transformed into a circuit. Circuit MP shown in Figure 26B is applicable to circuit MP in Figure 5A. This is a circuit that can be formed, and similar to Figure 20B, includes inverter circuit INV1 and inverter circuit IN It has a retaining part HC including V2. Note that the circuit MP in Figure 26B is transistor M3, Transistors M3r, M4, and M4r are not provided. (See Figure 26) For the operation of B, please refer to the explanation of the operation examples of circuit MP in Figure 24A and circuit MP in Figure 20B. To pour a drink.

[0399] Furthermore, for example, the circuit MP in Figure 22A, explained in Configuration Example 7, can be applied to the circuit MP in Figure 5A. It can be transformed into a circuit. Circuit MP shown in Figure 27A is applicable to circuit MP in Figure 5A. This is a possible circuit, and is a modified version of circuit MP in Figure 22A. Note that circuit MP in Figure 22A is The second terminal of the capacitive element C1 is electrically connected to the wiring VL, and the second terminal of the capacitive element C1r The two terminals are electrically connected to the wiring VL, and the first terminal of transistor M2 and the transistor The first terminal of transistor M2 is the point where it is electrically connected to the first terminal of transistor MZ. The circuit MP in Figure 22A differs from that of the other components, such as the absence of transistors M3 and M3r. Yes. Note that the operation of Figure 27A is related to the circuit MP in Figure 24A, the circuit MP in Figure 22A, etc. Refer to the explanation of the example operation.

[0400] For example, when applying circuit MP in Figure 27A to the arithmetic circuit 120 in Figure 6, Figure 27A The circuit MP can be modified to the circuit MP shown in Figure 27B. The circuit MP in Figure 27B is In circuit MP in Figure 27A, wiring IL and wiring ILB are treated as a single wiring, with wiring IL being considered as one wiring. The configuration is as follows. Note that the wiring XL shown in Figure 27B is the same as the wiring XLS shown in Figure 6. [1] corresponds to any one of the wiring XLS[m], and the wiring WL shown in Figure 27B corresponds to Figure 6. This corresponds to any one of the wiring WLS[1] to wiring WLS[m] shown.

[0401] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0402] (Embodiment 3) In this embodiment, the OS transistor applicable to the semiconductor device described in the above embodiment Let's explain an example of the configuration of the TA.

[0403] <Example of semiconductor device configuration> The semiconductor device shown in Figure 28 includes transistor 300, transistor 500, and a capacitive element. It has 600 and . Figure 30A is a cross-sectional view of transistor 500 in the channel length direction. Figure 30B is a cross-sectional view of transistor 500 in the channel width direction, and Figure 30C is a cross-sectional view of transistor 500. This is a cross-sectional view of the ZISTA 300 in the channel width direction.

[0404] Transistor 500 is a transistor (OS) having a metal oxide in the channel formation region. Transistor 500 has a small off-current, so it is used in semiconductor devices. In particular, transistors M1 and M3 of circuit MP included in the arithmetic circuit 110, By using it in transistors such as M4, it is possible to retain written data for a long period of time. This is possible. In other words, the refresh operation is infrequent, or the refresh operation is Since no operation is required, the power consumption of semiconductor devices can be reduced.

[0405] Transistor 500 is located above transistor 300, and capacitive element 600 is located above transistor 300. It is located above the zista 300 and transistor 500. Note that the capacitive element 600 These can be capacitive elements C1, C1r, etc., in the MP circuit.

[0406] The transistor 300 is mounted on the substrate 311 and consists of a conductor 316, an insulator 315, and the substrate A semiconductor region 313 consisting of part of 311, a low-level region that functions as a source region or drain region. It has a resistive region 314a and a low-resistance region 314b. Note that the transistor 300 is an example For example, it can be applied to the transistor in the above embodiment.

[0407] As shown in Figure 30C, transistor 300 is located on the top surface and channel of semiconductor region 313. The sides in the width direction are covered by the conductor 316 via the insulator 315. In this way, By making the ZISTA 300 a Fin type, the effective channel width is increased. The ON characteristics of the transistor 300 can be improved. Also, the contribution of the electric field of the gate electrode. This allows for an increase in the off-peak characteristics of transistor 300. .

[0408] Note that transistor 300 can be either a p-channel or n-channel type. .

[0409] The region in which the channel of the semiconductor region 313 is formed, the region near it, the source region, or In the low-resistance region 314a and low-resistance region 314b, which are rain regions, silicon It is preferable that it contains semiconductors such as semiconductor systems, and it is preferable that it contains single-crystal silicon. These are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium hydrogen). It may be formed from a material containing (aluminum arsenide), GaAlAs (gallium aluminum arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, silicon with controlled effective mass is used. Alternatively, by using GaAs and GaAlAs, transistor 30 0 is HEMT (High Electron Mobility Transistor) ) is also acceptable.

[0410] Low-resistance regions 314a and 314b are semiconductor regions applied to semiconductor region 313. In addition to the main material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that impart conductivity.

[0411] The conductor 316, which functions as a gate electrode, imparts n-type conductivity to arsenic, phosphorus, etc. Semiconductor materials such as silicon containing elements, or elements that impart p-type conductivity, such as boron. Conductive materials such as cellulose, metallic materials, alloy materials, or metal oxide materials can be used.

[0412] Furthermore, since the work function is determined by the material of the conductor, the material of the conductor must be selected accordingly. This allows you to adjust the threshold voltage of the transistor. Specifically, by using nitride in the conductor... It is preferable to use materials such as tan or tantalum nitride. Furthermore, both conductivity and embedding properties are desirable. To achieve this, metal materials such as tungsten and aluminum are used as laminates in the conductive material. This is preferable, and using tungsten is particularly preferable in terms of heat resistance.

[0413] Note that the transistor 300 shown in Figure 28 is just one example, and its structure is not limited to that example. Appropriate transistors should be used depending on the configuration and driving method. For example, in semiconductor devices, OS transistors... When using a unipolar circuit consisting only of transistors, the configuration of transistor 300 is as shown in Figure 29. The configuration should be the same as that of transistor 500, which uses an oxide semiconductor. Details about the Transistor 500 will be described later.

[0414] The transistor 300 is covered by insulators 320, 322, 324, and The bodies 326 are arranged in a series of stacked units.

[0415] As insulators 320, 322, 324, and 326, for example, oxidative Silicon, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, acid Aluminum nitride, aluminum nitride oxide, aluminum nitride, etc., can be used.

[0416] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials in which the nitrogen content is higher than the oxygen content.

[0417] The insulator 322 provides a step created by the transistor 300 and the like located below it. It may also function as a planarizing film that flattens the surface. For example, the upper surface of the insulator 322 is To improve flatness, the surface is flattened using a planarization treatment such as chemical mechanical polishing (CMP). It's fine if you do that.

[0418] Furthermore, the insulator 324 receives the transistor from the substrate 311 or the transistor 300, etc. A barrier film is used in the region where the TA500 is provided to prevent the diffusion of hydrogen and impurities. It is preferable that they be present.

[0419] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD A semiconductor can be used. Here, a semiconductor having an oxide semiconductor such as transistor 500 can be used. The diffusion of hydrogen into the semiconductor element may degrade the characteristics of that semiconductor element. So, a film that suppresses hydrogen diffusion is placed between transistor 500 and transistor 300. It is preferable to use it. Specifically, a membrane that suppresses hydrogen diffusion is one in which the amount of hydrogen desorption is small. It will be called a membrane.

[0420] The amount of hydrogen desorption can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. Yes, it is possible. For example, the amount of hydrogen desorption from insulator 324 can be determined by TDS analysis when the film surface temperature is In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is the area of ​​the insulator 324. Converted to a single win, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 a toms / cm 2 The following is acceptable.

[0421] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, The relative permittivity of the edge material 326 is preferably less than 4, and more preferably less than 3. Also, for example, an insulator... The relative permittivity of 326 is preferably 0.7 times or less, and preferably 0.6 times or less, than the relative permittivity of the insulator 324. This is more preferable. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wiring is reduced. It can be reduced.

[0422] Furthermore, insulators 320, 322, 324, and 326 contain capacitive elements 6 A conductor 328 and a conductor 330, etc., which are connected to transistor 500, are embedded. Furthermore, conductors 328 and 330 have the function of a plug or wiring. Furthermore, a conductor that functions as a plug or wiring may combine multiple structures into a single unit. The symbol may be assigned. Also, in this specification, etc., wiring and plastics that connect to the wiring The and may be a single unit. That is, when a part of the conductor functions as wiring, and In some cases, a portion of the conductive material may function as a plug.

[0423] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials, composite materials, etc. Conductive materials such as gold, metal nitride, or metal oxide are used in a single layer or in a laminated form. It is possible to have both heat resistance and conductivity with high melting point materials such as tungsten and molybdenum. It is preferable to use a material, and it is preferable to use tungsten. Alternatively, aluminum. It is preferable to form it with a low-resistance conductive material such as copper. This can reduce wiring resistance.

[0424] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, as shown in Figure 28 Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring to connect to the transistor 300. The conductor 356 is provided using the same material as the conductors 328 and 330. It is possible.

[0425] Furthermore, for example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, it is preferable to include an insulator 350 that has barrier properties against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0426] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. It would be good to do so. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be made It is possible to suppress the diffusion of hydrogen from transistor 300 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen has barrier properties against hydrogen It is preferable that the structure is in contact with an insulator 350 having the following properties.

[0427] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, as shown in Figure 28. Insulators 360, 362, and 364 are arranged in a sequential stack. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. Conductor 366 has the function of a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0428] Furthermore, for example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0429] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, as shown in Figure 28. Insulators 370, 372, and 374 are arranged in a sequential stack. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0430] Furthermore, for example, insulator 370, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 376 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 370 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0431] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, as shown in Figure 28 Insulators 380, 382, ​​and 384 are arranged in a sequential stack. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0432] For example, insulator 380, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 386 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 380 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0433] In the above, a wiring layer containing a conductor 356, a wiring layer containing a conductor 366, and a conductor 376 A wiring layer including and a wiring layer including the conductor 386 have been described, but this embodiment is not applicable. The semiconductor device is not limited to this. A wiring layer similar to a wiring layer containing conductor 356 The number of layers may be three or less, or the wiring layers similar to the wiring layer containing the conductor 356 may be made five or more layers. That's good too.

[0434] Insulator 384 has insulators 510, 512, 514, and 516. They are arranged in a stack in order. Insulator 510, insulator 512, insulator 514, and insulation It is preferable that one of the components 516 is a material that has barrier properties against oxygen and hydrogen. .

[0435] For example, the insulator 510 and the insulator 514 are, for example, a substrate 311 or a transistor Hydrogen and impurities spread from the area where transistor 300 is installed to the area where transistor 500 is installed. It is preferable to use a film that has barrier properties to prevent dispersion. Therefore, insulator 324 Similar materials can be used.

[0436] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to have a semiconductor device having an oxide semiconductor such as transistor 500. Furthermore, hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. This is preferable. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that has a low rate of hydrogen desorption. ru.

[0437] Furthermore, as films having barrier properties against hydrogen, for example, insulator 510 and insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0438] In particular, aluminum oxide is a source of oxygen and hydrogen, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both water and other impurities from passing through the film. Aluminum oxide is susceptible to hydrogen, moisture, and other impurities during and after the transistor manufacturing process. This prevents contamination of the transistor 500 with pure material. This can suppress the release of oxygen from the oxides that make up the transistor 5. It is suitable for use as a protective film for 00.

[0439] Furthermore, for example, the same material as the insulator 320 is used for insulators 512 and 516. It is possible to do so by applying materials with relatively low dielectric constants to these insulators. This can reduce parasitic capacitance between wirings. For example, insulator 512 and insulator For 516, silicon oxide films or silicon oxide nitride films can be used.

[0440] Furthermore, insulators 510, 512, 514, and 516 contain a conductive material 5 18, and a conductor (for example, conductor 503) that constitutes the transistor 500 is embedded. The conductor 518 is connected to the capacitive element 600 or the transistor 300. It functions as a plug or wiring. Conductor 518 is connected to conductor 328 and conductor 3 It can be provided using the same materials as in 30.

[0441] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is oxygen, hydrogen, And preferably it is a conductor that has barrier properties against water. With this configuration, The ZISTA 300 and Transistor 500 have barrier properties against oxygen, hydrogen, and water. The layers can be separated, and hydrogen can be diffused from transistor 300 to transistor 500. It can be suppressed.

[0442] A transistor 500 is provided above the insulator 516.

[0443] As shown in Figures 30A and 30B, the transistor 500 is an insulator 514 and an insulating A conductor 503 is arranged to be embedded in the body 516, and the insulator 516 and the conductor 50 An insulator 520 placed on top of 3, an insulator 522 placed on top of insulator 520, and An insulator 524 placed on the edge 522, and an oxide 53 placed on the insulator 524 0a, oxide 530b placed on oxide 530a, and on oxide 530b, Conductors 542a and 542b are positioned separately, and conductor 542a and conductor 54 An insulating layer is placed on 2b and superimposed between the conductor 542a and the conductor 542b, with an opening formed therein. The edge 580, the oxide 530c arranged on the bottom and sides of the opening, and the shape of the oxide 530c An insulator 550 arranged on the forming surface, and a conductor 560 arranged on the forming surface of the insulator 550, It holds.

[0444] Furthermore, as shown in Figures 30A and 30B, oxide 530a, oxide 530b, and conductive An insulator 544 is placed between the body 542a and the conductor 542b and the insulator 580. This is preferable. Also, as shown in Figures 30A and 30B, the conductor 560 is an insulator 5 A conductor 560a is provided inside 50, and is embedded inside the conductor 560a It is preferable to have a conductor 560b provided. Also, see Figures 30A and 30B As shown, an insulator 574 is placed on top of an insulator 580, a conductor 560, and an insulator 550. It is preferable that it be placed there.

[0445] In the following, oxides 530a, 530b, and 530c are summarized. It is sometimes referred to as oxide 530.

[0446] Furthermore, in transistor 500, in the region where the channel is formed and in its vicinity, acid The following describes a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated. However, the present invention is not limited thereto. For example, a single layer of oxide 530b, oxidation Two-layer structure of substance 530b and oxide 530a, two-layer structure of oxide 530b and oxide 530c, Alternatively, a configuration with a stacked structure of four or more layers may be used. In addition, in transistor 500, Although the electric body 560 is shown as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a multilayer structure of three or more layers. Good. Also, the transistor 500 shown in Figures 28 and 30A is just one example, and its structure is not limited to that. It is not necessary to use a specific transistor; instead, an appropriate transistor should be used depending on the circuit configuration and driving method.

[0447] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductor 542a and The conductor 542b functions as either a source electrode or a drain electrode, respectively. Furthermore, the conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. It is formed to be embedded in the region. Conductor 560, Conductor 542a and Conductor 5 The placement of 42b is self-aligned with the opening of the insulator 580. In the inverter 500, the gate electrode is positioned between the source electrode and the drain electrode in a self-aligned manner. It can be positioned in this way. Therefore, the conductor 560 can be positioned with a margin. Since it can be formed without any issues, the occupied area of ​​transistor 500 can be reduced. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0448] Furthermore, the conductor 560 is self-aligned in the region between conductor 542a and conductor 542b. As a result, the conductor 560 has a region that overlaps with the conductor 542a or the conductor 542b. It does not have. As a result, between the conductor 560 and the conductors 542a and 542b The parasitic capacitance can be reduced. Therefore, the switching speed of transistor 500 This improves the degree of performance and allows for high frequency characteristics.

[0449] The conductor 560 may function as the first gate (also called the top gate) electrode. Furthermore, the conductor 503 functions as a second gate (also called a bottom gate) electrode. There are cases where this is the case. In that case, the potential applied to conductor 503 is the same as the potential applied to conductor 560. By changing them independently and without linking them, the threshold voltage of transistor 500 is controlled. This can be achieved by applying a negative potential to the conductor 503, which allows the transistor 5 It becomes possible to increase the threshold voltage of 00 to greater than 0V and reduce the off-current. However, Therefore, applying a negative potential to conductor 503 is better than not applying a negative potential to conductor 560 The drain current can be reduced when the applied potential is 0V.

[0450] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the conductor 560 generates The electric field and the electric field generated from the conductor 503 connect, and channels are formed in the oxide 530. It can cover the gel-forming region. In this specification, the first gate electrode and the second gate The electric field of the electrode electrically surrounds the channel formation region, creating a transistor structure. This is called a surrounded channel (S-channel) structure.

[0451] Furthermore, the conductor 503 has the same configuration as the conductor 518, and the insulators 514 and 5 A conductor 503a is formed in contact with the inner wall of the 16 openings, and a conductor 503b is formed further inside. This has been done. In addition, in transistor 500, conductors 503a and 503b are combined. Although the present invention descri...

Claims

[Claim 1] A semiconductor device having a first circuit and a second circuit, The first circuit has a first holding node, The second circuit has a second holding node, The first circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The first circuit has the function of holding a first potential corresponding to the first data in the first holding node. The second circuit has the function of holding a second potential corresponding to the first data in the second holding node. The first circuit is, The function includes outputting a current corresponding to the first potential to the first input wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, The function includes outputting a current corresponding to the first potential to the second input wiring when a low potential is input to the first input wiring and a high potential is input to the second input wiring, A function that, when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, does not output a current corresponding to the first potential to the first wiring and the second wiring. It has, The second circuit is, The function includes outputting a current corresponding to the second potential to the second input wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, The function includes outputting a current to the first input wiring corresponding to the second potential when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring, A function that, when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, does not output a current corresponding to the second potential to the first wiring and the second wiring. Having, Semiconductor equipment.

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