Semiconductor equipment

Abstract

This invention provides a semiconductor memory device that stores data by using a transistor with low leakage current between the source and drain in the off state as the writing transistor. [Solution] The semiconductor memory device is formed using a matrix of multiple memory cells, each of which the drain of a write transistor Wtr, the gate of a read transistor Rtr, and one electrode of a capacitor C are connected. The gate of the write transistor is connected to the write word line Qn, the source of the write transistor and the source of the read transistor are connected to the bit line Rm, and the drain of the read transistor is connected to the read word line. Here, the conductivity types of the write transistor and the read transistor are different. To increase the integration density, the bias line Sn is replaced with the read word line of another row, or the memory cells are connected in series to form a NAND structure, and the read word line and the write word line are shared.

Description

[Technical Field]

[0001] This invention relates to a memory device using semiconductors. [Background technology]

[0002] There are many types of memory devices that use semiconductors. For example, dynamic random-access memory (DRAM) Access memory (DRAM) and static random-access memory (SRAM) , electronically erasable programmable read-only memory (EEPROM) and flat These include Shumemori, etc.

[0003] DRAM stores data by holding an electric charge in a capacitor located in the memory cell. However, transistors that have traditionally been used for switching are in the off state. However, a small leakage current occurs between the source and drain, so the data is stored for a relatively short time (long It is lost within tens of seconds at most. Therefore, the data is regenerated at regular intervals (generally every tens of milliseconds). It needs to be written to (refreshed).

[0004] Furthermore, SRAM stores data using the bistable state of a flip-flop circuit. M's flip-flop circuit usually uses a CMOS inverter, but one memory cell Because it uses six transistors, the integration density is lower than that of DRAM. Also, the power supply If the data is not provided, it will be lost.

[0005] On the other hand, EEPROM and flash memory use something called a floating gate. By placing it between the channel and the gate and storing charge in the floating gate, data can be collected. It retains the charge stored in the floating gate when the power supply to the transistor is cut off. Since they are retained even later, these memories are called non-volatile memories. Flash memory Regarding flash memory, for example, reference may be made to Patent Document 1.

[0006] In this specification, in particular, memories having a floating gate, such as EEPROM and flash memory, are referred to as floating gate type non-volatile memories (FGNVM). In FGNVM, since multi-stage data can be stored in one memory cell, the storage capacity can be increased. In addition, since the NAND type flash memory can significantly reduce the number of contact holes, the integration degree can be increased to a certain extent.

[0007] However, conventional FGNVM requires a high voltage when injecting or removing charges into the floating gate, and due to this, deterioration of the gate insulating film cannot be avoided, and unlimited writing and erasing cannot be repeated.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] As described above, conventional semiconductor memory devices have their advantages and disadvantages, and none of them fully satisfy all the requirements necessary for actual devices. In a memory device, low power consumption is required. If the power consumption is large, the device for supplying power must be made large, and also, the driving time with a battery becomes short. Moreover, due to the heat generation of the semiconductor element, The characteristics may deteriorate, and in some cases, the circuit may even be destroyed. Furthermore, in memory devices, It is preferable that there is no limit on the number of rewrites, and it is desirable that it can be rewritten more than 1 billion times. Of course, a high degree of integration is also necessary.

[0010] In this respect, DRAM constantly generates leakage current and undergoes refresh cycles, thus consuming power. There were difficulties in terms of power. On the other hand, SRAM has six transistors in one memory cell. This presents another problem: the integration density cannot be increased. Furthermore, FGNVM consumes power. While there were no issues in terms of power or integration density, the number of rewrite cycles was less than 100,000.

[0011] In light of the above, the power used for memory retention in memory cells is to be reduced compared to DRAM. The number of transistors used in a memory cell must be five or less, and the number of rewrite cycles must be 1 million. The first challenge is to overcome the three conditions mentioned above simultaneously. To retain data for 10 hours or more, preferably 100 hours or more, without power supply. And, to overcome two conditions simultaneously: the number of rewrites to be more than 1 million. This becomes the second challenge. Note that in this specification, data retention time refers to the time the data is retained in the memory cell. This is defined as the time at which the accumulated charge becomes 90% of the initial charge.

[0012] In addition to addressing the above-mentioned problems, the present invention provides a novel semiconductor device, particularly a semiconductor memory device. The objective is to develop a new method for driving semiconductor devices, particularly semiconductor memory devices. The objective is to provide a method for operation. Furthermore, a method for fabricating a novel semiconductor device, in particular a semiconductor device. The objective is to provide a method for manufacturing a body memory device. The present invention addresses at least the above problem. Problem solved. [Means for solving the problem]

[0013] The present invention will now be described, but the terms used in this specification will be briefly explained. Regarding the source and drain of a transistor, their structure and function are the same or equivalent. Furthermore, even if the structures are different, the potential and polarity applied to them are not constant. For reasons such as the above, in this specification, when either one is referred to as a source, for convenience it means the other The source and the drain will be referred to as the drain and will not be distinguished in any particular way. Therefore, in this specification, the source and It is also possible to interpret what is being done as draining.

[0014] Furthermore, in this specification, "(in the matrix) orthogonal" means intersecting at a right angle. In addition to meaning, even from a physical perspective, the circuit diagram is the simplest representation. It means that they are orthogonal, and "(in a matrix) they are parallel" means that the two lines Even if lines are arranged to physically intersect, in the simplest representation of a circuit diagram, they are parallel. It means "a row."

[0015] One aspect of the present invention is a transistor with low source-drain leakage current in the off state. This is used as the write transistor, and another transistor (the read transistor) and A single memory cell is formed with a capacitor. The conductivity type of the read transistor is the same as that of the write transistor. The conduction type of the transistor should be different. For example, the writing transistor should be an N-channel type. Therefore, the readout transistor will be a P-channel type. Also, the wiring to connect these and Then, at least three types of wiring are used: a write word line, a bit line, and a read word line. Prepare it.

[0016] Then, the drain of the write transistor is connected to the gate and capacitor of the read transistor. Connect to one of the electrodes of the lower transistor. Furthermore, the gate of the writing transistor is connected to the writing word. Connect the source of the write transistor and the source of the read transistor to the bit line. Connect the other electrode of the capacitor to the readout word line.

[0017] The off state of the writing transistor (in the case of an N-channel type, the gate potential is the same as the source and gate potential) The leakage current between source and drain (at a temperature lower than either rain) is measured at the operating temperature. (For example, at 25℃) 1 × 10 -20 A or less, preferably 1 × 10 -21 A or below At 85℃, 1 × 10 -20 It is desirable that it be A or less. In typical silicon semiconductors, It is difficult to achieve such low leakage currents, but oxide semiconductors are preferred under favorable conditions. This can be achieved in transistors obtained by processing. Therefore, the writing transistor It is preferable to use an oxide semiconductor as the material for the t. Of course, by some method In silicon semiconductors and other semiconductors, the leakage current can be reduced to the above value or less. If it is possible, then there is no reason to prevent its use.

[0018] Various known materials can be used as oxide semiconductors, but the band gap is 3 A voltage of 3 or more electron volts, preferably 3 or more electron volts and less than 3.6 electron volts, is desirable. Furthermore, the electron affinity is 4 electron volts or more, preferably 4 electron volts or more and 4.9 electrons. It is preferable that the voltage is less than volt. In particular, oxides containing gallium and indium are suitable for this purpose. It is suitable for the purpose of clarity. In such materials, furthermore, the carrier concentration derived from the donor or acceptor is less than 1×10 -14 cm -3 −, preferably less than 1×10 -11 c m -3 −, which is desirable.

[0019] As for the read transistor, there is no limit on the leakage current between the source and the drain in the off state, but it is preferable that the leakage current is small because the power consumption can be reduced. Also, in order to increase the read speed, it is desirable to operate at high speed. Specifically, the switching speed is preferably 10 nsec or less. Also, for the write transistor and the read transistor, it is required that the gate leakage current (the leakage current between the gate and the source or the gate and the drain) is extremely low, and it is also required that the capacitor has a low internal leakage current ( the leakage current between the electrodes). It is desirable that any leakage current is 1×10 A or less, preferably 1×10 A or less at the temperature during use ( for example, 25 °C). -20 A or less, preferably 1×10 -21 A or less, which is desirable.

[0020] Also, the potential of the gate of the read transistor changes according to the potential of the read word line, and as a result, the gate capacitance of the read transistor may fluctuate. That is, the gate capacitance may be larger when the read transistor is in the on state than when it is in the off state. If the fluctuation of the gate capacitance is larger than the capacitance of the capacitor, it causes problems in operating the memory cell. Therefore, the capacitance of the capacitor is greater than or equal to the gate capacitance of the read transistor, preferably

[0021] higher than the gate capacitance of the read transistor. It is good to make it more than twice as fast. Also, for the purpose of high-speed operation of semiconductor memory devices, The capacity of the pacita should preferably be 10 fF or less.

[0022] The write word lines, bit lines, and read word lines form a matrix, but the matrix For the drive to work, the write word line and the bit line must be perpendicular, and the write word line and the read It is desirable for the leading words to be parallel.

[0023] Figure 1(A) shows an example of a memory cell having the above structure. Here, the nth row and mth column Let's explain using a memory cell as an example. n and m can be natural numbers. In Figure 1(A), writing... Transistor WTr(n,m), readout transistor RTr(n,m), and capacitor C A memory cell consisting of (n,m) is shown. Here, the writing transistor WTr(n The drain of ,m) is connected to the gate of the readout transistor RTr(n,m) and capacitor C It is connected to one of the electrodes (n,m).

[0024] Furthermore, the gate of the writing transistor WTr(n,m) is connected to the writing word line Qn. Source and readout transistor RTr(n,m) of the input transistor WTr(n,m) The source is on the bit line Rm, and the other electrode of the capacitor C(n,m) is on the readout word line P Each is connected to n.

[0025] Furthermore, the drain of the readout transistor RTr(n,m) is connected to the bias wire Sn. In Figure 1(A), the write word line Qn, the read word line Pn, and the bias line Sn are shown. They are parallel. And the write word line Qn and the bit line Rm are orthogonal.

[0026] Figure 1(B) illustrates the area around the memory cell at row n, column m (where n and m are natural numbers greater than or equal to 2). As is clear from the diagram, three wires are needed per row and one wire per column. Therefore, an N x M matrix requires (3N+M) wires.

[0027] In the memory cell shown in Figure 1(A), by applying an appropriate potential to the write word line Qn... Then, the writing transistor WTr(n,m) is turned ON. At that time, the bit line Rm The potential causes charge to be injected into the drain of the writing transistor WTr(n,m). The amount of charge injected at that time is the potential of the bit line Rm and the readout transistor RTr(n,m). Since it is determined by the gate capacitance, the capacitance of capacitor C(n,m), etc., under the same conditions... If so, the results will be almost the same, with little variation. In this way, the data is written. ru.

[0028] Next, by applying another appropriate potential to the write word line Qn, the write transient The writing transistor WTr(n,m) is turned off. Even in this case, the writing transistor WTr( The charge on the drain (n,m) remains unchanged. When reading, the readout word line P Apply an appropriate potential to the n, bias wire Sn, etc., and the readout transistor RTr(n,m) By monitoring whether such a state occurs, it is possible to know the data that has been written. Cut.

[0029] In the above configuration, adjacent rows may share a bias line. Figure 5 shows the above structure. An example of a memory cell is illustrated. Here, the memory cell in the (2n-1)th row and mth column is adjacent to Let's explain using a memory cell in the 2nth row and mth column (where n and m are natural numbers) as an example.

[0030] Figure 5 shows the writing transistor WTr(2n-1,m) and the reading transistor RTr The notation for the (2n-1)th row and mth column consists of (2n-1,m) and capacitor C(2n-1,m). Memory cell, write transistor WTr(2n,m) and read transistor RTr(2 The memory cell in the 2n row and m column is shown, consisting of n,m and capacitor C(2n,m). .

[0031] The drain of the writing transistor WTr(2n-1,m) is connected to the reading transistor RTr. The gate of (2n-1,m) and one electrode of capacitor C(2n-1,m) are connected. Similarly, the drain of the write transistor WTr(2n,m) is the same as the read transistor. Connected to the gate of the zistor RTr(2n,m) and one electrode of the capacitor C(2n,m). It is being done.

[0032] Furthermore, the gate of the writing transistor WTr(2n-1,m) is on the writing word line Q2 At n-1, the gate of the writing transistor WTr(2n,m) is connected to the writing word line Q2n. The other electrode of capacitor C(2n-1,m) is connected to the readout word line P2n-1. The other electrode of the passiter C(2n,m) is connected to the readout word line P2n, and the readout transistor... Drain of RTr(2n-1,m) and drain of readout transistor RTr(2n,m) The bias wire Sn is connected to the source of the writing transistor WTr(2n-1,m), and the writing is done via the bias wire Sn. Source of transistor WTr(2n,m), readout transistor RTr(2n-1, The source of m) and the source of the read transistor RTr(2n,m) are connected to the bit line Rm, They are all connected.

[0033] As is clear from the above, five wires are needed for every two rows and one wire for every column, so 2 A matrix of N rows and M columns requires (5N+M) wiring. (Semiconductor memory device shown in Figure 1) Therefore, (6N+M) wires are needed for a matrix of the same size. In this way, adjacent By sharing the bias wire in the "ru" row, the number of wires can be reduced compared to the configuration in Figure 1. .

[0034] Furthermore, the bias line in the configuration shown in Figure 1 above may be replaced with an adjacent write word line. Figure 6(A) illustrates an example of a memory cell having the above structure. Here, row n, column m Let's explain using a memory cell (where n and m are natural numbers) as an example. In Figure 6(A), write transition The transistor WTr(n,m), the readout transistor RTr(n,m), and the capacitor C(n,m) A memory cell consisting of ) is shown.

[0035] The drain of the writing transistor WTr(n,m) is connected to the reading transistor RTr(n, It is connected to the gate of (m) and one electrode of the capacitor C(n,m). Furthermore, the book The gate of the writing transistor WTr(n,m) is connected to the writing word line Qn, and the writing transistor The source of transistor WTr(n,m) and the source of read transistor RTr(n,m) are The drain of the read transistor RTr(n,m) is on the bit line Rm, and the write line is one line below. The other electrode of capacitor C(n,m) is connected to the readout word line Pn, with the word line Qn+1 connected to the other electrode. They are each connected.

[0036] Figure 6(B) illustrates the area around the memory cell at row n, column m. As is clear from the figure... Since two wires are needed per row and one wire per column, the edges of the matrix also need to be wired. Considering this, an N x M matrix requires (2N + M + 1) wires. By substituting the bias line in the configuration of Figure 1 with the adjacent writing word line, This allows for an even greater reduction in the number of wires compared to the configuration shown in Figure 1.

[0037] Another aspect of the present invention involves a write transistor similar to that used in Figure 1, and a read transistor. Semiconductors consisting of memory units formed using multiple transistors and capacitors. This is a physical memory device. Here, the conductivity types of the writing transistor and the reading transistor are They should be different from each other; for example, if the writing transistor is an N-channel type, then the reading transistor is different. The transistor is a P-channel type.

[0038] In other words, the drain of the first writing transistor is connected to one electrode of the first capacitor, It is connected to the gate of the first read transistor and the drain of the second write transistor. The input is connected to one electrode of the second capacitor and the gate of the second readout transistor. To be continued.

[0039] Furthermore, the drain of the first writing transistor is connected to the source of the second writing transistor. Connect the drain of the first readout transistor to the source of the second readout transistor. It connects to the first write transistor. Furthermore, the gate of the first write transistor is connected to the first write word line. The gate of the second write transistor connects to the second write word line, and the first capacitor The other electrode of the lower capacitor is connected to the first readout word line, and the other electrode of the second capacitor is connected to the Connect each to one of the two read word lines.

[0040] Furthermore, the source of the first write transistor and the source of the first read transistor are B It may also be connected to the bit line. Note that between the source and bit line of the first writing transistor, Alternatively, either the source of the first readout transistor or the bit line, or One or more transistors may be inserted into both sides.

[0041] First write word line, second write word line, first read word line, second read The branching word lines are parallel to each other and perpendicular to the bit lines.

[0042] Figure 16(A) shows an example of a memory unit having the above structure. The unit has one write transistor, one read transistor, and one capacitor. It has multiple unit memory cells. That is, a write transistor WTr1 and a read transistor The first memory cell consists of a zista RTr1 and a capacitor C1, and the writing transistor WTr The second memory cell consists of 2, a read transistor RTr2, and a capacitor C2, and write The third component consists of transistor WTr3, readout transistor RTr3, and capacitor C3. A memory unit consisting of three memory cells is shown.

[0043] The drain of the write transistor in each memory cell is connected to one electrode of the capacitor. These transistors and capacitors are connected to the gate of the readout transistor. The potential at the connected intersection is related to the on / off state of the readout transistor, therefore, These intersections are called nodes F1, F2, and F3.

[0044] The drain of the writing transistor WTr1 is connected to the source of the writing transistor WTr2. Next, the drain of read transistor RTr1 is connected to the tray of read transistor RTr2. Connect to the . Furthermore, the drain of the writing transistor WTr2 is connected to the writing transistor Connect the source of WTr3 and the drain of the read transistor RTr2 to the read transistor Connect to the source of the generator RTr3.

[0045] In this example, the drain of the readout transistor RTr3 is connected to the bias wire S. One or more transistors are placed between the drain of the protruding transistor RTr3 and the bias wire S. It may also have a source for the writing transistor WTr1 and a read transistor R The source of Tr1 is connected to the bit line R. The writing transistors WTr1, WTr2, The gates of WTr3 are connected to the write word lines Q1, Q2, and Q3, respectively. The other electrodes of C1, C2, and C3 are connected to the readout word lines P1, P2, and P3.

[0046] The writing word lines Q1, Q2, and Q3, and the reading word lines P1, P2, and P3 are parallel to each other. It is also perpendicular to the bit line R. Furthermore, the bias line S is always kept at a constant potential. If present, it does not need to be parallel or perpendicular to other wiring. However, the degree of integration In terms of increasing performance, it is preferable for the bit line to be perpendicular to the bit line.

[0047] In this way, the three memory cells share the contacts provided between the bit lines and the memory cells. By doing so, the contact area of ​​that part per unit storage cell can be reduced. This allows for improved integration density. In Figure 16(A), the memory unit has three memory cells. An example has been shown, but a single memory unit may be composed of more memory cells. For example Alternatively, one memory unit may be composed of 16, 32, or other memory cells.

[0048] This structure is similar to the NAND structure of flash memory. Figure 16(A) By connecting memory cells in series as shown, more memory cells can be used on a single bit line. The contacts provided between the memory cells can be shared, and the surface area per unit memory cell The product can be reduced. For example, when the minimum processing line width is F, the single in semiconductor memory device Area per memory cell is 12F 2 It can be reduced to, or even less.

[0049] The circuit diagram shown in Figure 16(A) represents a single memory unit used in a semiconductor memory device. However, semiconductor memory devices are obtained by arranging these storage units in a matrix. (Figure) An example is shown in 19. Here, the nth row, (m-1)th column, the nth row, mth column, the nth row, (m+ 1) Column, row n, column (m+2), row (n+1), column (m-1), row (n+1), column m The eight memory units are: the (n+1)th row, the (m+1)th column, the (n+1)th row, the (m+2)th column, and so on. The knit shows 24 memory cells.

[0050] The memory unit in row n, column m has write word lines Q1n, Q2n, Q3n, and read word lines Q1n, Q2n, Q3n. Word lines P1n, P2n, P3n, bias line Sn, and bit line Rm are provided. The same applies to billion units.

[0051] Another aspect of the present invention is a writing transistor similar to that shown in Figure 16(A), and a reading transistor. A memory unit formed using multiple transistors and capacitors. This is a semiconductor memory device. That is, the drain of the first writing transistor is the first Connect one electrode of the capacitor and the gate of the first readout transistor, and the second The drain of the write transistor is connected to one electrode of the second capacitor, and the second read transistor The gate of the transistor is connected, and the drain of the third writing transistor is connected to the third capacitor. It is connected to one electrode of the passiter and to the gate of the third readout transistor.

[0052] Furthermore, the drain of the first writing transistor is connected to the source of the second writing transistor. Connect the drain of the first readout transistor to the source of the second readout transistor. Connect to the third write transistor. Similarly, the drain of the second write transistor is connected to the third write transistor. Connect the source of the transistor, and the drain of the second readout transistor is connected to the third readout transistor. Connect to the source of Zista.

[0053] Furthermore, the gate of the first write transistor connects to the first write word line, and the first key The other electrode of the CAPASITA and the gate of the second writing transistor are connected to the second writing word The other electrode of the second capacitor and the gate of the third writing transistor are connected by a wire. Connect to the writing word line.

[0054] Furthermore, the source of the first write transistor and the source of the first read transistor are B It may also be connected to the bit line. Note that between the source and bit line of the first writing transistor, Alternatively, either the source of the first readout transistor or the bit line, or One or more transistors may be inserted into both sides.

[0055] The first writing word line, the second writing word line, and the third writing word line are relative to each other. They are parallel and perpendicular to the bit lines.

[0056] Figure 16(B) illustrates an example of a memory unit having the above structure. In Figure 16(B), The memory unit is equipped with one write transistor, one read transistor, and one capacitor. It has multiple unit memory cells. That is, a write transistor WTr1 and a read transistor A first memory cell consisting of a transistor RTr1 and a capacitor C1, and a writing transistor W The second memory cell consists of Tr2, read transistor RTr2, and capacitor C2, write The unit consists of a load transistor WTr3, a readout transistor RTr3, and a capacitor C3. A memory unit consisting of three memory cells, referred to as "3 memory cells," is shown.

[0057] The drain of the write transistor and one electrode of the capacitor in each memory cell The gate of the readout transistor is connected. These transistors and capacitors The potential at the connected intersection is related to the on / off state of the readout transistor, therefore, These intersections are called nodes F1, F2, and F3.

[0058] The drain of the writing transistor WTr1 is connected to the source of the writing transistor WTr2. Next, the drain of read transistor RTr1 is connected to the tray of read transistor RTr2. Connect to the . Furthermore, the drain of the writing transistor WTr2 is connected to the writing transistor Connect the source of WTr3 and the drain of the read transistor RTr2 to the read transistor Connect to the source of the generator RTr3.

[0059] In this example, the drain of the readout transistor RTr3 is connected to the bias wire S. One or more transistors are placed between the drain of the protruding transistor RTr3 and the bias wire S. It may also have a source for the writing transistor WTr1 and a read transistor R The source of Tr1 is connected to the bit line R. The writing transistors WTr1, WTr2, The gates of WTr3 are connected to the write word lines Q1, Q2, and Q3, respectively. The other electrodes of C1 and C2 are also connected to the writing word lines Q2 and Q3, respectively. The other electrode of capacitor C3 is connected to the readout word line P.

[0060] The writing word lines Q1, Q2, Q3 and the reading word line P are parallel to each other, and also, It is perpendicular to the wire R. Furthermore, if the bias wire S is kept at a constant potential, then the other It is not necessary to run the wiring parallel to or perpendicular to it. However, in terms of increasing the density of integration, It is preferable for the line to be perpendicular to the grid line.

[0061] Similar to the memory unit shown in Figure 16(A), there are three memory cells, bit lines and memory cells By sharing the contacts provided between them, the contacts in that part per unit storage cell The cycle area can be reduced, and the density can be increased. More memory A single bit line in a cell can share a contact provided between it and the memory cell. This allows for a reduction in the area per unit memory cell.

[0062] In addition, the configuration shown in Figure 16(B) requires the reading that is necessary in the configuration shown in Figure 16(A). Furthermore, substituting some of the word lines with handwritten word lines also reduces the area required. Due to effects such as these, for example, the area per unit storage cell in a semiconductor memory device can be increased by 9 F 2 It can be reduced to, or even less.

[0063] The above describes several configurations as means of solving the problem, but this specification does not describe other solutions. The steps are also disclosed. Furthermore, the above configuration and other solutions disclosed herein are also disclosed in the field of the United States. The problem can be solved by making obvious changes. Therefore, the means of solving the problem is as described above. It is not limited to just three configurations. [Effects of the Invention]

[0064] By adopting any of the above configurations, at least one of the aforementioned problems can be solved. Regarding the number of rewrites, in the above configuration, all write operations are write-through Since this is done by switching the inverter on and off, degradation of the insulating film cannot occur. That is, as described above. A semiconductor memory device with this configuration has virtually no rewrite limitations.

[0065] Furthermore, the semiconductor memory device with the above configuration exhibits excellent characteristics in terms of the data storage period. This shows the leakage current and gate current between the source and drain of the transistor used in the off state. By setting the leak current and the internal leakage current of the capacitor to the above conditions, the charge can be measured over 10 hours. Preferably, it can be maintained for 100 hours or more. Furthermore, by improving the conditions, 1 It can be retained for months or more, or even more than a year.

[0066] If the charge decreases due to leakage, a refresh can be performed as with conventional DRAM. However, the interval is determined by the period over which the charge can be held as described above. Because the charge is retained for a certain period, the refresh interval is, for example, once a month. This will only happen once a year. The frequent refreshes required with conventional DRAM are no longer necessary. Therefore, it results in a semiconductor memory device with lower power consumption.

[0067] Furthermore, in the semiconductor memory device with the above configuration, the data is erased when the data is read. This does not happen. Traditionally, such features could be achieved with SRAM, but the above structure Modern semiconductor memory devices use a number of transistors in a single memory cell that is different from conventional SRA It is less than M, five or fewer, typically two. Moreover, one of the transistors If formed using a thin-film oxide semiconductor, it can be formed by stacking on top of a conventional silicon semiconductor. Therefore, the density of integration can be improved.

[0068] Regarding integration density, in the semiconductor memory device with the above configuration, the absolute value of the capacity required for the storage cell This can be reduced. For example, in DRAM, the capacity of the memory cell is equal to the wiring capacity. A capacity of at least 30 fF was required, as anything less than the same or greater capacity would cause operational problems. However, since capacity is proportional to area, increasing the density of a single memory cell increases the surface area of ​​the cell. The product becomes smaller, making it impossible to secure the required capacity. Therefore, DRAM uses special shapes and It was necessary to use materials to create a large volume.

[0069] In contrast, in the semiconductor memory device with the above configuration, the capacitance of the capacitor is the read transistor. It can be determined by the relative ratio with the gate capacitance of the zistor. In other words, even if the integration density increases This means that the gate capacitance of the readout transistor will be smaller, The capacity required for the pacita decreases at the same rate. Therefore, even if the density of integration increases, Capacitors with essentially the same structure can be used.

[0070] Furthermore, the semiconductor memory device having the above configuration is required when writing or erasing with FGNVM. It does not require the high voltage necessary. Among FGNVMs, so-called flash memory (especially NA ND) had an advantage over SRAM and DRAM in terms of integration density, but even partial data rewriting To perform this operation, it was necessary to use a high voltage to erase a certain area all at once. In a semiconductor memory device having the above configuration, writing (rewriting) is done row by row. It can be completed with the minimum necessary operations.

[0071] Furthermore, in FGNVM, charge injection into the floating gate during writing is one-sided. Because it was a passage and occurred in a non-equilibrium state, there was a large variation in the amount of charge. The amount of charge held in the gate allows for the storage of data at multiple stages, but Considering variations in load volume, around 4 levels (2 bits) was common. To store the data, a higher voltage was required.

[0072] In contrast, in the configuration described above, charge accumulation in the capacitor is reversible. Therefore, the variation is small, for example, the readout transistor due to charge injection The variation in the voltage can be reduced to 0.5 volts or less. Therefore, in a narrower voltage range, This allows a large amount of data to be stored in a single memory cell, and consequently, the voltage for writing and reading it is reduced. It can also be made lower. For example, when writing or reading 4-bit (16 levels) data, The voltage used can be 10 volts or less. [Brief explanation of the drawing]

[0073] [Figure 1] This figure shows an example of a semiconductor memory device according to the present invention. [Figure 2] This figure illustrates an example of a driving method (writing) for a semiconductor memory device according to the present invention. [Figure 3] This figure illustrates an example of a driving method (readout) for a semiconductor memory device according to the present invention. [Figure 4] This figure illustrates an example of a driving method for a semiconductor memory device according to the present invention. [Figure 5] This figure shows an example of a semiconductor memory device according to the present invention. [Figure 6] This figure shows an example of a semiconductor memory device according to the present invention. [Figure 7] This figure shows an example of the wiring layout of the semiconductor memory device of the present invention. [Figure 8] This figure shows an example of the manufacturing process for the semiconductor memory device of the present invention. [Figure 9] This figure shows an example of the manufacturing process for the semiconductor memory device of the present invention. [Figure 10] This figure shows an example of the wiring layout of the semiconductor memory device of the present invention. [Figure 11] This figure illustrates an example of a driving method for a semiconductor memory device according to the present invention. [Figure 12] This figure illustrates an example of a driving method (writing) for a semiconductor memory device according to the present invention. [Figure 13] This figure illustrates an example of a driving method (readout) for a semiconductor memory device according to the present invention. [Figure 14] This figure illustrates an example of a driving method (writing) for a semiconductor memory device according to the present invention. [Figure 15] This figure illustrates an example of a driving method (readout) for a semiconductor memory device according to the present invention. [Figure 16] This figure shows an example of a semiconductor memory device according to the present invention. [Figure 17] This figure illustrates an example of a driving method (writing) for a semiconductor memory device according to the present invention. [Figure 18] This figure illustrates an example of a driving method (readout) for a semiconductor memory device according to the present invention. [Figure 19] This figure shows an example of a semiconductor memory device according to the present invention. [Figure 20] This figure illustrates an example of a driving method (writing) for a semiconductor memory device according to the present invention. [Figure 21] This figure illustrates an example of a driving method (readout) for a semiconductor memory device according to the present invention. [Figure 22] This figure shows an example of the wiring layout of the semiconductor memory device of the present invention. [Figure 23] This figure shows an example of the wiring layout of the semiconductor memory device of the present invention. [Figure 24] This figure shows an example of the manufacturing process for the semiconductor memory device of the present invention. [Modes for carrying out the invention]

[0074] The embodiments will be described below with reference to the drawings. However, the embodiments may differ in many ways. It is possible to implement it in any manner, and without deviating from its purpose and scope, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is The following descriptions of embodiments are not to be interpreted as being limited to the following.

[0075] Furthermore, the structures, conditions, and other items disclosed in the following embodiments may also apply to other embodiments. They can be combined as appropriate. Note that in the configuration described below, similar items refer to... The same reference numeral is used across different drawings to indicate the same part or part having a similar function. Detailed explanations may be omitted.

[0076] Furthermore, in the following embodiments, for ease of understanding, the timing, width, height, etc. of the pulses are omitted. Although it is written so that it is a constant value, in the spirit of the present invention, it is not necessarily the case that the pulse is It is easy to understand that the timing does not need to be perfectly synchronized, nor do they need to have a fixed width or height. .

[0077] (Embodiment 1) In this embodiment, using Figure 4, the dynamics of the semiconductor memory device shown in Figures 1(A) and (B) are demonstrated. Let's explain an example of the work. Note that the specific numerical values ​​for electric potential are given below, but these are... The purpose is to help understand the technical concept. Needless to say, those values ​​are transistors. It may be modified depending on various characteristics such as capacitors, or at the discretion of the implementer. Furthermore, the semiconductor memory device shown in Figure 1 can also process data by methods other than those described below. It can be written to or read from.

[0078] Here, the writing transistor WTr(n,m) is an N-channel type, and the reading transistor Let the RTr(n,m) be a P-channel type. The writing transistor WTr(n,m) is: When the gate potential becomes 1V or more higher than the potential of either the source or the drain, Let's define "on" as (current flows) and "off" as (no current flows) in all other cases. The readout transistor RTr(n,m) is such that the gate potential is such that the source or drain potential is such that It is defined as turning on (allowing current to flow) when the potential of either of the other two voltages becomes 1V or more lower, and otherwise Assume that it is OFF (no current flows).

[0079] Furthermore, of the gate capacitance of the readout transistor RTr(n,m), the gate bias is The fluctuations in this value can be considered negligible compared to the capacitance of capacitor C(n,m). , the parasitic capacitance of the writing transistor WTr(n,m) and the reading transistor RTr(n Parasitic capacitance of ,m), and other parasitic capacitances between wires, etc., all capacitances not shown in the diagram are considered to be 0. Let's consider this. Also, in Figure 4, a circle is placed next to a transistor that is ON, and a circle is placed next to a transistor that is OFF. Transistors are represented by an "X" mark superimposed on the transistor symbol. Under certain conditions Items that can be turned on may be indicated separately in the diagram.

[0080] During writing, as shown in Figure 4(A), the reading word line Pn and the bias line Sn are connected. The voltage is set to 0V. Also, the potential of the bit line Rm is 0V, +1V, depending on the data being written. The voltage will take four values: +2V, +3V, and the potential of the writing word line Qn. When the voltage is set to +4V, the writing transistor WTr(n,m) turns on, and the writing process The potential of the drain of the transistor WTr(n,m) is the source of the writing transistor (i.e., Then, it approaches the potential of the bit line Rm. Here, the potential becomes equal to that of the bit line Rm. do.

[0081] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is, It is equal to the potential of the drain of transistor WTr(n,m). That is, the readout transistor The gate potential of the transistor RTr(n,m) is 0V or higher, and the readout transistor RTr( It is the same potential as the source (i.e., bit line Rm) of n,m.

[0082] Also, the drain of the readout transistor RTr(n,m) (i.e., the bias wire Sn) The potential is 0V. Therefore, the voltage at the gate of the readout transistor RTr(n,m) The position is the same as or higher than the potential of the source and drain, so the readout transistor RTr(n,m ) is in the off state. In this way, data can be written.

[0083] Also, turn off the read transistor RTr(n,m) whenever possible, including during writing. The state is defined as the gate to the source of the readout transistor RTr(n,m) This is effective in reducing leakage current from the gate to the drain. Generally, such a The current increases when the device is on and becomes very low when it is off.

[0084] Since this type of leakage current is the leakage of charge held in the capacitor C(n,m), A large amount of data means a decrease in data retention time. In this embodiment, the readout The transistor RTr(n,m) is only turned on during readout, thus preserving the data. It excels in terms of durability.

[0085] Next, when writing to a row other than the nth row, as shown in Figure 4(B), The potential of the word line Qn is set to -3V. Also, the potential of the read word line Pn is set to +3V. The potential of the bias line Sn is set to 0V. On the other hand, the potential of the bit line Rm is set to the potential of the write operation. Depending on the data written to the line, it takes on one of four values: 0V, +1V, +2V, or +3V.

[0086] The potential of the drain of the writing transistor WTr(n,m) is the same as the potential of the read word line Pn. Because it is connected via capacitor C(n,m), the potential of the read word line Pn fluctuates ( In other words, the voltage increases by 3V due to the rise from 0V in Figure 4(A) to +3V in Figure 4(B). In other words, depending on the data written, one of the following voltages will be used: +3V, +4V, +5V, or +6V. It becomes a value.

[0087] Also, in this state, the source (bit line Rm) of the writing transistor WTr(n,m) The potential (0 to +3V) and the potential (+3V) of the drain of the writing transistor WTr(n,m) The gate potential (-3V) of the writing transistor WTr(n,m) is greater than ~+6V. Because the value is low, the writing transistor WTr(n,m) is turned off.

[0088] Furthermore, the source of the readout transistor RTr(n,m) (i.e., the bit line Rm) The potential (0 to +3V) and the drain of the readout transistor RTr(n,m) The potential of the readout transistor RTr(n,m) is greater than the potential of the bias wire Sn (0V). Because the gate potential (+3 to +6V) is high, the readout transistor RTr(n,m) is O It becomes Fu.

[0089] Next, we will explain the reading process. As shown in Figure 4(C), the writing word line Qn and the The potential of the IAS line Sn is set to -3V. The potential of the readout word line Pn is set to 0V. In this state, the potential of the drain of the writing transistor WTr(n,m) is written Depending on the data, the voltage will be either 0V, +1V, +2V, or +3V, and the voltage of the bit line Rm will be... If the voltage is between -3V and 0V, the writing transistor WTr(n,m) and the reading transistor Both the RTr(n,m) transistors are off. That is, for lines that are not to be read, In this way, the write transistor and read transistor are turned off.

[0090] On the other hand, for the row to be read, the potential of the read word line Pn is set to -3V. The gate potential of the readout transistor RTr(n,m) corresponds to the written data. Therefore, it will be one of -3V, -2V, -1V, or 0V. Also, the potential of the bit line Rm is - Let's assume it's 3V. In this case, if the potential of the bias wire Sn is -3V, then the readout transistor... RTr(n,m) is off.

[0091] However, as shown in Figure 4(D), when the potential of the bias wire Sn becomes -2V, the readout If the gate potential of the transistor RTr(n,m) is -3V, then the readout transistor R Tr(n,m) will be in the ON state.

[0092] When the readout transistor RTr(n,m) is turned ON, electricity is supplied to the bit line Rm. Since a current flows, by detecting this current, the readout transistor RTr(n,m) It can be determined that it is in the ON state. Alternatively, the end of the bit line Rm is a capacitor. Therefore, the initial potential (-3V) approaches the potential of the bias wire Sn, so still, We can determine that the readout transistor RTr(n,m) is in the ON state.

[0093] Similarly, as shown in Figure 4(E), when the potential of the bias wire Sn becomes -1V, the readout When the gate potentials of transistor RTr(n,m) are -3V and -2V, the readout The transistor RTr(n,m) turns on.

[0094] Furthermore, as shown in Figure 4(F), when the potential of the bias wire Sn becomes 0V, the readout trace... When the gate potentials of the inverter RTr(n,m) are -3V, -2V, and -1V, the reading The output transistor RTr(n,m) turns on.

[0095] Even when the bias wire potential is set to 0V, the readout transistor RTr(n,m) remains off. Therefore, it can be inferred that the gate potential of the readout transistor RTr(n,m) was 0V. It can be measured.

[0096] In this way, four levels of data (2 bits) can be written and read. In this way, even more data, for example, 8 levels of data (3 bits), 16 levels of data It can write and read data (4 bits).

[0097] The above explanation does not include parasitic capacitance or the gate capacitance of the readout transistor RTr(n,m). Although the capacity of Pasita C(n,m) was ignored, these were taken into consideration in actual memory cells. Above, it is necessary to determine the potential to be applied.

[0098] The gate capacitance of the readout transistor RTr(n,m) changes significantly between the ON and OFF states. Because it moves, the gate potential of the readout transistor RTr(n,m) is affected. The capacitance of capacitor C(n,m) is the gate capacitance of the readout transistor RTr(n,m). The larger the ratio to, the greater the effect, so preferably, the capacitor C(n,m The capacitance of the readout transistor RTr(n,m) should be at least twice the gate capacitance of the readout transistor RTr(n,m). .

[0099] Furthermore, by using multiple levels of charge to hold in the memory cell, multi-level data (multi-value) can be created. To store data, it is necessary that the variation in the amount of charge held is small. The semiconductor memory circuit and semiconductor memory device shown in the embodiment have a variable amount of charge that can be held. Because it has minimal wobble, it is suitable for this purpose.

[0100] (Embodiment 2) In this embodiment, the method for writing to and reading from a semiconductor memory device as shown in Embodiment 1 is used. Regarding the method, we will explain the timing of the signals applied to various wires. First, writing The method will be explained using Figure 2.

[0101] As described in Embodiment 1, the bit lines (··, Rm-1, Rm, Rm+1, ··) A signal corresponding to the data is applied. Here, the potential of the bit line is above VRM and below VRH. This shall be the case. Also, the writing word line (for example, Qn) of the row containing the memory cell to be written to. A signal is sequentially applied to turn on the writing transistor, and the same row The read word line (e.g., Pn) and bias line (e.g., Sn) are each suitable A signal is applied that results in a critical potential. The potential of the write word line at this time is VQH. Let VPM be the potential of the readout word line and VSM be the potential of the bias line.

[0102] On the other hand, for the other line's write word line, the write transistor is turned off. A signal is applied, and the readout word line and bias line are each at the appropriate potential. A signal like this is applied. At this time, the potential of the write word line is VQL, and the read word line is VQL. Let the potential of the D line be VPM, and the potential of the bias line be VSH.

[0103] Here, in order to turn off the readout transistor, the potential VPH of the readout word line is The voltage must be greater than or equal to (VPM + (VRH - VRM)), and the bias wire potential VSH must be It is preferable that the potential is less than or equal to (VRM + (VPH - VPM)). For example, the potential of the bit line. However, if we take four values: VRM, VRM+α, VRM+2α, and VRM+3α (α>0) Therefore, since VRH = VRM + 3α, the potential VPH of the readout word line is (VP It is preferable that it is M+3α or higher.

[0104] In Embodiment 1, VRM=0[V], α=1[V], VPM=0[V], VSM=0[ V[V], VPH=+3[V], VSH=0[V], and the above conditions are satisfied. Embodiment In case 1, the bias line potential (VSM, VSH) is always kept at 0V during writing. When VSM=VSH=0, there are cases where data is written to the row in question and cases where it is not written. It may be varied depending on the circumstances.

[0105] Figure 2 shows the signal timing chart taking the above into consideration. Figure 2 shows the write word line (Q n-1, Qn, Qn+1), bit lines (Rm-1, Rm, Rm+1), read word lines Examples of pulses applied to (Pn-1, Pn, Pn+1) are shown. The magnitude of the pulse height and amplitude are also shown. This is a conceptual matter. The pulse duration is determined by considering the characteristics of the writing transistor. Just set it.

[0106] In the diagram, the pulses applied to the writing word lines (Qn-1, Qn, Qn+1) overlap. Although we try to avoid this, for example, the time during which a pulse is applied to the write word line Qn-1 A portion of this may overlap with the time when a pulse is applied to the write word line Qn. Also, VQL This must be below the threshold of the writing transistor, and in Embodiment 1, It was set to -3 volts. Also, VQH must be above the threshold value of the writing transistor. This is essential, and in Embodiment 1, it was set to +4 volts. However, it can also take values ​​other than these. It is possible.

[0107] The signal applied to the bit lines (Rm-1, Rm, Rm+1) consists of multiple pulses, The height can be varied. Here, we will use VRM, VRM+α, VRM+2α, The system consists of four stages: VRM + 3α (α > 0). These pulses correspond to the pulses on the written word line. Instead of being perfectly synchronized with the write word line, the pulse starts and a certain amount of time (τ) It is preferable to start after setting (1), and also after the pulse on the write word line has finished. It is preferable to terminate the process after a certain period of time (τ2). Here, τ1 < τ2. While it is acceptable to set τ1 > τ2, it is preferable to set τ1 = τ2 for circuit design purposes. It seems so.

[0108] Additionally, pulses applied to the read word lines (Pn-1, Pn, Pn+1) are also applied to the write word lines. The pulse applied to the do line should be synchronized or slightly delayed. To ensure that the potential of the sta's drain is set to the desired value, the read word line (Pn- The pulse applied to 1, Pn, Pn+1) is the same as the pulse applied to the write word line of the same row. It is preferable to terminate the process after a certain period of time has elapsed following the completion of the first step.

[0109] In this way, the potential of the drain of the write transistor in each memory cell is determined. The potential determines the amount of charge generated at the drain of each writing transistor. The charge amounts corresponding to the potentials VRL, VRL+α, VRL+2α, and VRL+3α are, respectively Assuming Q0, Q1, Q2, and Q3, the charge amounts of each memory cell are as shown in Table 1. As a transistor, one with low leakage current between the source and drain in the off state is used. As a result, these charges will be released after the power supply to this semiconductor memory device is cut off. Furthermore, it can be retained for a considerable period of time (more than 10 hours).

[0110] [Table 1]

[0111] Next, the reading method will be explained using Figures 3(A) and (B). In Figure 3(B) The principle of one example of a method for reading data is shown below. As shown in Figure 3(B), the bit line At the end of Rm, there is a capacitor 13, and a means 11 for measuring the potential of the electrodes of the capacitor 13. Means 12 for applying potential to the capacitor 13 and a switch 14 are provided.

[0112] Initially, with switch 14 in the ON state, the capacitor 13 is supplied with potential by means 12. The potential of the electrode on the memory cell side of capacitor 13 (upper side of the diagram) (i.e., the potential of the bit line Rm) Let ) be a specific potential VRL. Then, turn switch 14 to the OFF state. After that, what If the potential of the bit line Rm fluctuates due to various circumstances, the potential of the capacitor electrodes can be measured. The potential fluctuations can be observed using means 11. Once the series of operations is complete, the bit line Let VRL be the potential of Rm.

[0113] In the row where reading is performed, the reading transistor is turned on by the potential of the bias line. It turns on and off. For example, as shown in Figure 3(A), the bias line Sn-1 , pulses of three types of heights (VS1, VS2, VS3) are sequentially input to Sn, Sn+1.

[0114] In Embodiment 1, as is clear from the description related to FIGS. 4(D) to (F), depending on the potential of the gate of the read transistor and the potential of the bias line, the read transistor can be in an on state or an off state. Here, for a pulse of height VS1, when the charge held in the memory cell is Q0, the read transistor turns on. For a pulse of height VS2, when the charge held in the memory cell is Q0 and Q1, the read transistor turns on. For a pulse of height VS3, it is assumed that the read transistor turns on when the charge held in the memory cell is Q0, Q1, and Q2.

[0115] If the read transistor turns on, the potential of the bit line approaches or becomes the same as the potential of the bias line. By measuring this variation with measuring means 1 for measuring the potential of the electrode of the capacitor in FIG. 3(B), it is possible to observe whether the read transistor has turned on or not.

[0116] For example, when pulses of three different heights are applied to the same memory cell, if the charge held in the memory cell is Q0, the potential of the capacitor varies in response to pulses of all heights. That is, three pulses are observed.

[0117] However, if the charge held in the memory cell is Q1, it does not respond to the lowest pulse and responds to the remaining two pulses, so two pulses are observed. Similarly, if the charge held in the memory cell is Q2, it responds only to the highest pulse, so one pulse is observed. ​​​​​If a pulse is observed and the charge held in that memory cell is Q3, then every pulse is There was no response, and no pulses were observed.

[0118] In this way, by recording how many pulses occurred in each memory cell, the data is written to the memory cell. The information that was embedded can be obtained. For example, according to Figure 3(A), the (n+1)th row The memory cell in column (m-1) generates three pulses during a series of reads. Because the retained charge was Q0, all of the charge applied to the bias line Sn In response to a pulse, it turns ON, and the potential of the bit line Rm becomes equal to the potential of the bias line Sn. Or, it was because the value was close to that.

[0119] Conversely, the memory cell at row n, column m did not generate a single pulse. Because the charge amount of the terminal Q3 was the largest, it did not turn on even with the highest pulse of VS3. Because there was none. In this way, when the pulses emitted by each memory cell are aggregated, the result is as shown in Table 2. This is how it works. In this way, the data stored in each memory cell can be read. The above example shows how to read data row by row, but in a similar way, It is also possible to read only the data from specific memory cells.

[0120] [Table 2]

[0121] Furthermore, the amount of charge held in the memory cell can be determined by the number of pulses generated as described above. Alternatively, the voltage can be directly measured and determined. For example, as shown in Figure 3(C), If the potential of the word line Pn is -3V and the potential of the writing word line Qn is -3V, then writing Transistor WTr(n,m) is in the off state, and readout transistor RTr(n,m) The gate potential of the ) will be between -3V and 0V.

[0122] Furthermore, capacitor 13 shown in Figure 3(B) is connected to the end of bit line Rm, and bit line Rm Let's assume the potential was 0V. Also, let's assume that the potential of the bias wire Sn was initially 0V. In this state, the gate potential of the readout transistor RTr(n,m) is -3V, -2 If V is -1V, the readout transistor RTr(n,m) is in the ON state, Since the potentials of the s and drain are equal, no current flows. Also, the readout transistor RTr If the gate potential of (n,m) is 0V, then the readout transistor RTr(n,m) is O It is in a state of [unclear].

[0123] Next, when the potential of the bias line Sn is lowered to -3V, the readout transistor RTr(n, When the gate potential of m) is other than 0V, the readout transistor RTr(n,m) Current flows between the terminal and the drain. However, the termination of the bit line Rm is capacitor 13. Then, when the potential of the bit line Rm reaches a certain value, no current flows.

[0124] For example, suppose the gate potential of the readout transistor RTr(n,m) is -2V. Then, the potential of the bit line Rm decreases from 0V. At the second level, the gate potential (-2V) of the readout transistor RTr(n,m) is equal to the source voltage. Since it is 1V lower than (-1V), the readout transistor RTr(n,m) is in the ON state. Yes. However, when the potential of bit line Rm further decreases, the potential of the gate (-2V) of read transistor RTr( n,m) and the potential of the source (less than -1V, which is the potential of bit line Rm) result in a difference of less than 1V, causing it to turn off. As a result, the charge amount of bit line Rm does not change , and the potential of bit line Rm becomes almost constant.

[0125] In this case, the potential of bit line Rm is lower than -1V, but before it drops to -2V, read transistor RTr(n,m) turns off. Therefore, the potential of bit line Rm is -2V or higher and less than -1V. The potential of bit line Rm at this time can be detected by means 11 for measuring the potential in Fig. 3(B). That is, if the potential of bit line Rm is -2V or higher and less than -1V, it can be inferred that the potential of the gate of read transistor RTr(n,m) was -2V. From this, the data written in this memory cell can be known. Similarly, if the potential of the gate of read transistor RTr(n,m) is -3V or -1V, the potential of bit line Rm is -3V or higher and less than -2V, and -1V or higher and less than 0V, respectively. If the potential of the gate of read transistor RTr(n,m) is 0V, read transistor

[0126] RTr(n,m) maintains the off state, so the potential of bit line Rm does not change from 0V. Even in this way, the charge amount at the time of writing can be known.

[0127] (Embodiment 3) In this embodiment, examples of the shape and manufacturing method of the semiconductor memory device described in Embodiments 1 and 2 will be described. In this embodiment, write transistor WTr is made of zinc and indium Using a zinc-containing oxide semiconductor, the readout transistor RTr is a single crystal silicon Recon semiconductors are used. Therefore, the writing transistor WTr is the same as the read transistor. It is installed in a stacked configuration on top of the RTr.

[0128] In other words, an insulated gate using a single-crystal silicon semiconductor provided on a single-crystal silicon substrate. A type transistor is used as the readout transistor RTr, and on top of it, an oxide semiconductor is used A transistor is formed and used as the writing transistor (WTr). This section describes an example of forming a semiconductor memory device on a single-crystal silicon substrate, but other It is also possible to install it on a substrate.

[0129] Figure 7 shows an example of the storage cell layout of the semiconductor memory device according to this embodiment. Figure 7(A) This shows the main wiring, electrodes, etc., provided on a single-crystal silicon substrate. Element isolation region 1 on the substrate. O2 is formed. Conductive materials and doped silicon are used on the substrate. Regions 106a and 106b are formed, and a part of them is the source of the readout transistor RTr. This becomes the drain. Part of the conductive region 106b becomes the bias line. Conductive region 106a, 106b is isolated by the read gate 110 of the read transistor RTr. A first connecting electrode 111 is provided in the sexual region 106a.

[0130] Figure 7(B) shows a transistor using an oxide semiconductor formed on top of the circuit in Figure 7(A). The central main wiring and electrodes are shown. Island-shaped oxide semiconductor region 112 and first wiring 114 a and 114b are formed. Here, the first wiring 114a is the write word line, and the first wiring 1 14b becomes the read word line. Part of the first wiring 114a is oxide semiconductor region 112 and They overlap and form the gate electrode of the writing transistor WTr. Also, oxide semiconductor region 1 12 connects to the lower read gate 110. The first wiring 114b is connected to the read gate A capacitor is formed in the overlapping area with 110. Also, oxide semiconductor region 11 A second connecting electrode 117 is provided for connecting from 2 to an upper layer (for example, a bit line). .

[0131] The readout gate 110 forms an ohmic contact with the oxide semiconductor that will be formed later. The material is preferable. Such a material is one whose work function W is equal to the electron affinity of an oxide semiconductor. A material whose energy difference φ (the energy difference between the lower limit of the conductivity band of an oxide semiconductor and the vacuum level) is approximately the same as or smaller than φ The material can be given as follows: That is, it is sufficient that the relationship W < φ + 0.3 [electron volts] is satisfied. For example Examples include titanium, molybdenum, and titanium nitride.

[0132] When Figures 7(A) and (B) are superimposed, the result is as shown in Figure 7(C). Here, the superimposed figures are They are intentionally slightly offset and overlapped so that their shape can be seen. Furthermore, oxide semiconductors are used. The second wiring 118 (bit line, etc.) formed on top of the transistor is also shown in the diagram.

[0133] Note that points A and B in Figures 7(A) to (C) represent the same position. The design rules can be selected by the implementer as appropriate, but in terms of increasing the degree of integration, each transition The channel width of the sta is 10 nm to 0.1 μm, and the channel length is 10 nm to 0.1 μm. The following is preferable.

[0134] The following describes the method for manufacturing a semiconductor memory device with the above structure. Figures 8 and 9 are shown below. This is a cross-section connecting points A and B in 7. In this embodiment, n-type single crystal silicon is used as the substrate. Although a substrate is used, n-type wells are formed on a p-type single-crystal silicon substrate, and this implementation is carried out on top of it. A transistor of the form shown may be provided. The manufacturing process will be described below according to the numbers in the figure. ru.

[0135] <Figure 8(A)> First, using known semiconductor manufacturing techniques, on an n-type single-crystal silicon substrate 101, Figure 8(A As shown in the example, the element isolation region 102 is made of conductive silicon or the like doped in the p-type Sexual region 106a, 106b, first gate insulating film 103, dummy gate 104, first interlayer insulating film A border 107 is formed. In Figure 8(A), two dummy gates 104 are shown. As is clear from Figure 7, these are a continuous sequence.

[0136] Side walls may be provided on the sides of the dummy gate 104, as shown in Figure 8(A). Polycrystalline silicon is preferable for the dummy gate 104. The thickness of 3 is preferably 10 nm or more in order to suppress leakage current. The first gate is designed to have a smaller gate capacitance than the capacitance of the capacitor that will be formed afterward. It is preferable to use a material with a relatively low dielectric constant, such as silicon oxide, as the dielectric of the insulating film 103. It's nice.

[0137] Conductive regions 106a and 106b are provided with silicide regions 105a and 105b on their surfaces. A structure that enhances conductivity may also be used. Furthermore, as explained in relation to Figure 7(A), The conductive region 106b becomes part of the bias line.

[0138] The first interlayer insulator 107 may be single-layer or multi-layer, and the channel of the transistor may be strained. It may include a stress liner to provide the necessary properties. The top layer film is coated by a spin coating method. Making the film flat is advantageous in subsequent processes. For example, the first interlayer insulator 107 As a result, a silicon nitride film is formed by plasma CVD, and then a spin coating method is applied to it. A multilayer film with a more flat silicon oxide film may also be used.

[0139] <Figure 8(B)> If the surface of the first interlayer insulator 107 is sufficiently flat, dry etching can be performed. The first interlayer insulator 107 is etched, and when the top surface of the dummy gate 104 is exposed, it is dried. Discontinue etching. Instead of dry etching, use chemical mechanical polishing (CMP). Alternatively, you can first flatten the surface of the first interlayer insulator 107 using the CMP method, and then dryer The etching can be further advanced using the etching method. Alternatively, the dry etching method can be used. After etching the interlayer insulator to a certain extent, a planarization treatment may be performed using the CMP method. Thus This yields a first interlayer insulator 107a having a flat surface.

[0140] <Figure 8(C)> Next, the dummy gate 104 is selectively etched to form the opening 108. When polycrystalline silicon is used as the material for gate 104, 2 to 40% is preferred. Alternatively, 20 to 25% TMAH (tetramethylammonium hydroxide) can be used. Furthermore, the first interlayer insulator 107a having a flat surface reaches the silicide region 105a. An opening 109 is also formed.

[0141] <Figure 8(D)> A single-layer or multi-layer film of conductive material is deposited. The conductive material is an oxide that will be formed later. A material that forms ohmic contact with a semiconductor is preferred. Furthermore, this conductive film is readout Since it is also the gate electrode of a lampistor (in this case, a P-channel type), it determines its threshold. In this regard, it is preferable to have appropriate material properties such as work function. If the requirements cannot be met, a multi-layered film can be used, and each layer should be designed to satisfy the respective conditions. For example, a multilayer film of titanium nitride and tantalum nitride can be used as the conductive material.

[0142] Next, the conductive material film is planarized and etched using the CMP method. This process is necessary to create a flat surface. It is best to stop when the first interlayer insulator 107a, which has a surface, appears. Thus, Figure 8(D As shown in the diagram, the read gate 110 and the first connecting electrode 111 of the read transistor are It is formed. Subsequently, it is contained near the surface of the first interlayer insulator 107a which has a flat surface. To reduce hydrogen content, a surface treatment using fluorine-containing plasma is performed. (Flat surface) If the hydrogen concentration of the first interlayer insulator 107a is sufficiently low, no treatment is necessary. Hydrogen concentration in the region 100 nm from the surface of the first interlayer insulator 107a having a smooth surface. is 1 x 10 18 cm -3 Less than 1 × 10 16 cm -3 It's best to use "less than".

[0143] <Figure 9(A)> Oxide semiconductor films with a thickness of 3 to 30 nm are formed by sputtering. The manufacturing method does not have to be sputtering. The oxide semiconductor preferably contains gallium and indium. It seems that in order to improve the reliability of semiconductor memory devices, the hydrogen concentration in the oxide semiconductor film should be... 1 x 10 18 cm -3 Less than 1 × 10 16 cm -3 It's best to use "less than".

[0144] This oxide semiconductor film is etched to form island-shaped oxide semiconductor regions 112. To improve the properties, the oxide semiconductor region 112 may be subjected to heat treatment. Thus, the readout gate 110 and oxide semiconductor region 112 and first connecting electrode 111 and oxide semiconductor region A structure is obtained in which 112 makes contact.

[0145] Subsequently, the second gate insulating film 113 is formed by a known film deposition method such as sputtering. To reduce flow, the thickness of the second gate insulating film 113 is preferably 10 nm or more, and The hydrogen concentration in the gate insulating film is 1 × 10⁻⁶ -18 cm -3 Less than 1 × 10 16 cm -3 It's best to use "less than".

[0146] As gate insulating films, silicon oxide, aluminum oxide, hafnium oxide, lanthanum oxide, Aluminum nitride or similar materials are suitable. These can be used not only as single-layer films but also as multilayer films. The second gate insulating film 113 is formed by the read gate 110 and the first wiring 114b. It is also the dielectric of the capacitor, and its capacitance is read from the gate capacitance of the transistor. To further increase the dielectric constant, it is preferable to use a material with a relative permittivity of 10 or higher. Heat treatment may be performed after formation to improve the properties of the oxide semiconductor region 112.

[0147] <Figure 9(B)> Conductive material is used to connect the first wiring 114a (write word line) and the first wiring 114b (read line). It forms a word line. Part of the first wiring 114a is a transistor using an oxide semiconductor. This will become the gate electrode. The material for the first wiring 114a and 114b is an oxide with a work function. Materials with an electron affinity 0.5 electron volts or more higher than that of semiconductors are preferred. For example, tungsten These include gold, platinum, and p-type silicon.

[0148] Between the read gate 110 and the first wiring 114b, the second gate insulating film 113 is used as a dielectric. A capacitor is formed. The capacitance of this capacitor is determined by the read gate 110 and the first wiring. It is defined by the overlap of 114b, and the area of ​​that overlapping region is 100 nm. 2 The above is 0.01 μm 2 The following is preferable.

[0149] In Figure 9(B), one end of the first connecting electrode 111 and the gate electrode of the writing transistor are shown. One end of the first wiring 114a, and one end of the read gate 110 and the other end of the first wiring 114a The edges are shown to match perfectly. However, in reality, the precision of mask alignment is Depending on the angle, the first wiring 114a is either on the left side (first connecting electrode 111 side) or the right side (reading) as shown in the diagram. It may shift towards the side of the overhang gate 110. In that case, on the opposite side of the shift, the first distribution The wire 114a and either the first connecting electrode 111 or the read gate 110 electrode Because there is an offset between the two points, the resistance of the transistor increases when it is in the ON state.

[0150] To prevent this, the width of the first wiring 114a is increased so that it overlaps even with slight misalignment. One possible method is to connect the first wiring 114a and the first connecting electrode 111 and the read gate 11 Parasitic capacitance with zero occurs, which is disadvantageous for high-speed operation. Also, the width of the wiring Making it larger contradicts the principle of narrowing down design rules.

[0151] To solve these problems, the first wiring 114a is used as a mask in the oxide semiconductor region. The goal is to form an n-type region in a self-consistent manner. To achieve this, known ion implantation methods can be used. Ions of elements that are more easily oxidized than oxide semiconductors are implanted. Such elements include Examples include titanium, zinc, magnesium, silicon, phosphorus, and boron. Generally, boron and Phosphorus is readily available because it is used in conventional semiconductor processes, and in particular, as mentioned above... To inject into such a thin second gate insulating film 113 and oxide semiconductor region 112, more than boron is needed. Phosphorus, with its high atomic weight, is preferable.

[0152] It is desirable that these ions contain as little hydrogen as possible. The hydrogen concentration is preferably 0.1% or less. Hydrogen acts as a donor for oxide semiconductors. It is known that if hydrogen is present in the ions, the hydrogen injected into the oxide semiconductor It migrates through oxide semiconductors, degrading the reliability of the device.

[0153] In oxide semiconductors, implanted ions combine with oxygen, creating an oxygen vacancy, resulting in an n-type structure. It becomes conductive. The difference from silicon semiconductors is that silicon semiconductors undergo ion implantation. Later, heat treatment is necessary to restore crystallinity, but in many oxide semiconductors, The advantage is that high conductivity can be obtained without heat treatment.

[0154] Thus, regions 115a and 115b exhibit n-type conductivity within the oxide semiconductor region 112. These regions are formed. The carrier (electron) concentration in these regions is 1 × 10⁻⁶. -19 cm -3 That's all. It is preferable to set the ion implantation conditions accordingly. With this, the basic device structure is complete. ru.

[0155] <Figure 9(C)> Subsequently, a second interlayer insulator 116 consisting of a single-layer or multi-layer thin film is formed. The surface is flattened to form a contact hole that reaches the region 115a exhibiting n-type conductivity. Then, the second connecting electrode 117 is embedded. After that, the second wiring 118 (bit wire) is formed. Similar wiring may be formed parallel to the first wirings 114a and 114b. Thus, Figure 9( As shown in C), write transistor 119, read transistor 120, A memory cell for a semiconductor memory device having CAPAS121 is fabricated.

[0156] (Embodiment 4) In this embodiment, an example of a semiconductor memory device shown in Figure 5 will be explained using Figure 10. In this embodiment, the writing transistor WTr contains gallium and indium. An oxide semiconductor is used, and a single-crystal silicon semiconductor is used as the readout transistor RTr. Therefore, the write transistor WTr is stacked on top of the read transistor RTr. They are arranged in layers.

[0157] In other words, an insulated gate using a single-crystal silicon semiconductor provided on a single-crystal silicon substrate. A type transistor is used as the readout transistor RTr, and on top of it, an oxide semiconductor is used A transistor is formed and used as the writing transistor (WTr). Now, let's explain an example using a single-crystal silicon semiconductor as the readout transistor (RTr). However, it is also possible to use other semiconductors.

[0158] Figure 10 shows an example of the storage cell layout of the semiconductor memory device of this embodiment. ) indicates the main wiring, electrodes, etc. provided on the single-crystal silicon substrate. Figure 10(A) shows The areas 200a and 200b enclosed by the dotted lines are each occupied by one memory cell. This indicates a region. For example, region 200a occupies the storage cell in the (2n-1)th row and mth column of Figure 5. This corresponds to the area, and area 200b corresponds to the area occupied by the memory cell in the 2nth row and mth column of Figure 5. It is correct.

[0159] An element isolation region 202 is formed on the substrate. In addition, conductive material and doping are applied to the substrate. Conductive regions 206a and 206b are formed using coated silicon. A portion of it is readable. This is the drain and source of the protruding transistor RTr. Wiring continues from conductive region 206a. These are the bias lines (··, Sn, Sn+1, ··). Conductive regions 206a and 206b are It is separated by the read gate 210. The conductive region 206b has the first connecting electrode 211. It is provided and connected to the circuitry above.

[0160] Figure 10(B) shows a transient using an oxide semiconductor formed on top of the circuit in Figure 10(A). This shows the main wiring and electrodes centered around the t. It includes island-shaped oxide semiconductor regions 212 and conductive material The first wiring 214 is formed by the material. The first wiring 214 is, for example, a written word. Line (··, Q2n-1, Q2n, Q2n+1, ··), read word line (··, P2n (-1, P2n, P2n+1, ...)

[0161] A portion of the writing word line overlaps with the oxide semiconductor region 212, and the writing transistor W It becomes the gate electrode of Tr. Also, the oxide semiconductor region 212 is the readout gate 21 of the lower layer. Connect to 0. The read word line, at the portion overlapping with the read gate 210, It forms a japashita.

[0162] The oxide semiconductor region 212 is connected by the first connecting electrode 211 to the readout transistor RTr It connects to the source (conductive region 206b). Also, from the oxide semiconductor region 212 to the upper layer ( A second connecting electrode 217 is provided for connection to the bit line. If it is placed at the same position as the first connecting electrode 211 that connects the lower layer and the oxide semiconductor region 212, This is preferable for reducing the area of ​​the memory cell.

[0163] When Figures 10(A) and (B) are superimposed, the result is as shown in Figure 10(C). Furthermore, they are intentionally slightly offset and overlapped so that the overlap is visible. A second wiring 218 made of conductive material formed on top of the transistor is also shown in the diagram. The second wiring 218 is a bit wire (··, Rm-1, Rm, Rm+1, ··), and the second connection The subsequent electrode 217 connects to the oxide semiconductor region 212.

[0164] To fabricate a semiconductor memory device with the structure described above, the method shown in Embodiment 3 can be used. good.

[0165] (Embodiment 5) In this embodiment, the semiconductor shown in Figures 1(A) and (B) is used in a different manner than in Embodiment 1. An example of operating a body memory circuit will be explained using Figure 11. Note that the potential is as follows: The specific figures listed below are intended to aid in understanding the technical concept of this invention. Needless to say, these values ​​depend on various characteristics of transistors, capacitors, etc. It may be changed at the discretion of the implementer.

[0166] Here, the writing transistor WTr(n,m) is an N-channel type, and the reading transistor Let the RTr(n,m) be a P-channel type. The writing transistor WTr(n,m) is: When the gate potential becomes 1V or more higher than the potential of either the source or the drain, Assume that it is ON, and everything else is OFF. Also, the readout transistor RTr(n ,m) is when the gate potential is 1V or more higher than the potential of either the source or the drain. It is assumed that it turns on when the value is low, and off otherwise.

[0167] Furthermore, of the gate capacitance of the readout transistor RTr(n,m), the gate bias is The fluctuations in this value can be considered negligible compared to the capacitance of capacitor C(n,m). , the parasitic capacitance of the writing transistor WTr(n,m) and the reading transistor RTr(n Parasitic capacitance of ,m), and other parasitic capacitances between wires, etc., all capacitances not shown in the diagram are considered to be 0. Think about it.

[0168] Also, in Figure 11, transistors that are ON are marked with a circle, and transistors that are OFF are marked with a circle. Zista is represented by a symbol with an "x" overlaid. For features that turn on under specific conditions, see below. It may also be included in the diagram.

[0169] <Figure 11(A)> (Writing to the nth row) During writing, as shown in Figure 11(A), the read word line Pn and the bias line Sn The potential is set to 0V. The potential of the bit line Rm is 0V, +1V, depending on the data being written. The voltage will take four values: V, +2V, and +3V. The power of the writing word line Qn When the voltage is set to +4V, the writing transistor WTr(n,m) turns on and writes. The potential of the drain of transistor WTr(n,m) is the source of the writing transistor (sun This approaches the potential of the bit line Rm. Here, the potential becomes equal to that of the bit line Rm. Let's assume that.

[0170] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is, It is equal to the potential of the drain of transistor WTr(n,m). That is, the readout transistor The gate potential of the transistor RTr(n,m) is 0V or higher, and the readout transistor RTr( It is the same potential as the source (i.e., bit line Rm) of n,m.

[0171] Also, the drain of the readout transistor RTr(n,m) (i.e., the bias wire Sn) The potential is 0V. Therefore, the voltage at the gate of the readout transistor RTr(n,m) The position is the same as or higher than the potential of the source and drain, so the readout transistor RTr(n,m ) is in the off state. In this way, data can be written.

[0172] <Figure 11(B)> (Writing to rows other than row n) Next, when writing to a row other than the nth row, as shown in Figure 11(B), The potential of the incoming word line Qn is set to 0V. Also, the potential of the readout word line Pn is set to +3V. The potential of the bias line Sn is set to 0V. On the other hand, the potential of the bit line Rm is set to the potential of the write operation. Depending on the data written to the line, it takes on one of four values: 0V, +1V, +2V, or +3V.

[0173] The potential of the drain of the writing transistor WTr(n,m) is the same as the potential of the read word line Pn. Because it is connected via capacitor C(n,m), the potential of the read word line Pn fluctuates ( In other words, the increase from 0V in Figure 11(A) to +3V in Figure 11(B) results in a 3V increase. In other words, depending on the data written, it will be either +3V, +4V, +5V, or +6V. It will be that value.

[0174] Also, in this state, the source (bit line Rm) of the writing transistor WTr(n,m) The potential (0 to +3V) and the potential (+3V) of the drain of the writing transistor WTr(n,m) Because the gate potential of the writing transistor WTr(n,m) is lower than ~+6V, The writing transistor WTr(n,m) is turned off.

[0175] Furthermore, the potential of the source (bit line Rm) of the readout transistor RTr(n,m) is (0~ (+3V) or the potential of the drain (bias wire Sn) of the readout transistor RTr(n,m) Because the gate potential of the readout transistor RTr(n,m) is higher than (0V), The protruding transistor RTr(n,m) is turned off.

[0176] <Figure 11(C)> (Readout) Next, we will explain the reading process. As shown in Figure 11(C), the writing word line Qn The potential is set to 0V. Also, the potentials of the readout word line Pn and the bias line Sn are set to +3V. In this state, the potential of the drain of the writing transistor WTr(n,m) is... Depending on the data entered, the bit line will be either +3V, +4V, +5V, or +6V. If the potential of Rm is between 0V and +3V, the writing transistor WTr(n,m) and the reading transistor are used. The output transistors RTr(n,m) are both off. That is, for lines that are not to be read... Then, the write transistor and read transistor are turned off in this manner.

[0177] <Figure 11(D)> (Readout) On the other hand, for the row to be read, the potential of the bias wire Sn should be greater than +3 volts. Example For example, as shown in Figure 11(D), when the potential of the bias wire Sn is +4V, the readout trace If the gate potential of transistor RTr(n,m) is +3V, then the readout transistor RT r(n,m) is turned on.

[0178] If the potential of the bit line is set to +3V beforehand, then current will flow through the bit line Rm, By detecting this, it is determined that the readout transistor RTr(n,m) is in the ON state. This allows us to know that. Alternatively, if the end of the bit line Rm is a capacitor, then Since it approaches the potential of the IAS line Sn, the readout transistor RTr(n,m) is indeed O It is possible to know that it is in a certain state.

[0179] <Figure 11(E)> (Readout) Similarly, as shown in Figure 11(E), when the potential of the bias wire Sn becomes +5V, the reading is If the gate potentials of transistor RTr(n,m) are +3V and +4V, then the readout The lunger RTr(n,m) is turned on.

[0180] <Figure 11(F)> (Readout) Furthermore, as shown in Figure 11(F), when the potential of the bias wire Sn becomes +6V, the reading is performed. If the gate potentials of transistor RTr(n,m) are +3V, +4V, and +5V, then the reading The output transistor RTr(n,m) turns on.

[0181] Even when the bias wire Sn is set to +6V, the readout transistor RTr(n,m) remains off. If it remains as is, the potential of the drain of the writing transistor WTr(n,m) (=readout) It can be inferred that the gate potential of transistor RTr(n,m) was +6V.

[0182] In this way, four levels of data (2 bits) can be written and read. In this way, even more data, for example, 8 levels of data (3 bits), 16 levels of data It is possible to write and read data (4 bits). In this embodiment, as described above, Writing and reading can be performed using only positive potential.

[0183] The above explanation does not include parasitic capacitance or the gate capacitance of the readout transistor RTr(n,m). Although the capacity of Pasita C(n,m) was ignored, these were taken into consideration in actual memory cells. Above, it is necessary to determine the potential to be applied. The gauge of the readout transistor RTr(n,m) The capacitance fluctuates significantly between the ON and OFF states, so the read transistor RTr(n The gate potential of the readout transistor RTr(n,m) is affected. The larger the ratio of the capacitance to the capacitance C(n,m), the greater the effect. Therefore, preferably, the capacitance of capacitor C(n,m) is the capacitance of the read transistor RTr(n, It is recommended to set the gate capacity to more than twice that of m).

[0184] (Embodiment 6) In this embodiment, an example of operating the semiconductor memory circuit shown in Figure 5 is shown in Figures 12 and This will be explained using Figure 13. Here, the writing transistor WTr(2n-1,m) and WTr(2n,m) is an N-channel type, and the readout transistor RTr(2n-1,m) Let RTr(2n,m) be a P-channel type.

[0185] The writing transistors WTr(2n-1,m) and WTr(2n,m) have a gate potential of It is assumed that it turns on when the potential of either the source or the drain becomes 1V or more higher than the potential of either source or drain. Otherwise, it is assumed to be off. Also, the readout transistor RTr(2n-1,m), RTr(2n,m) is a gate potential that is the potential of either the source or the drain. It is assumed that the device turns on when the voltage drops by more than 1V, and is off otherwise.

[0186] Also, the gate capacitance of the readout transistors RTr(2n-1,m) and RTr(2n,m) Of these, the portion that fluctuates due to the gate bias is insignificant compared to the capacitance of capacitor C(n,m). It is assumed that it can be seen. Furthermore, the writing transistor WTr(2n-1,m), WTr( Parasitic capacitance of 2n,m) and readout transistor RTr(2n-1,m), RTr(2n, All capacitances not shown in the diagram, such as parasitic capacitance of m) and parasitic capacitance between wiring, are assumed to be 0. Let's think about it.

[0187] Furthermore, in Figures 12 and 13, transistors that are ON are marked with a circle, and those that are OFF are marked with a circle. Transistors are represented by a symbol with an "x" superimposed on it. These are those that turn on under specific conditions. Further details may be provided separately.

[0188] <Figure 12(A)> (Writing to the (2n-1)th row) When writing to the (2n-1)th row, as shown in Figure 12(A), the read word line P The potentials of 2n-1, the write word line Q2n, and the bias line Sn are set to 0V. The potential of the do line P2n should be +3V. The potential of the bit line Rm should be determined according to the data being written. It is assumed that the voltage will take on four values: 0V, +1V, +2V, and +3V. The potential of the drain of the feed transistor WTr(2n,m) is set to +3V.

[0189] Then, if the potential of the writing word line Q2n-1 is set to +4V, the writing transistor When WTr(2n-1,m) is turned on, the writing transistor WTr(2n-1,m) The drain potential is close to the potential of the source of the writing transistor (i.e., the bit line Rm). Here, we assume that it is equal to the potential of the bit line Rm.

[0190] On the other hand, at this stage, the gate potential of the readout transistor RTr(2n-1,m) is, It is equal to the potential of the drain of the feed transistor WTr(2n-1,m). That is, the reading The gate potential of the output transistor RTr(2n-1,m) is 0V or higher, and the readout The potential is the same as the potential of the source (i.e., the bit line Rm) of the lampistor RTr(2n-1,m). be.

[0191] Also, the drain of the readout transistor RTr(2n-1,m) (i.e., the bias wire) The potential of Sn is 0V. Therefore, the readout transistor RTr(2n-1,m) The gate potential is the same as or higher than the source and drain potentials, so the readout transistor R Tr(2n-1,m) is in the off state.

[0192] Furthermore, the gate potential (0V) of the writing transistor WTr(2n,m) is, The potential of the bit line Rm (i.e., between 0V and +3V) and the potential of the drain (+3V) Since it is lower than ), the writing transistor WTr(2n,m) is in the off state. Also, The gate of the read transistor RTr(2n,m) (i.e., the write transistor W The potential (+3V) of the drain of Tr(2n,m) is equal to the potential of its source (i.e., the bit line R). Since it is higher than the potential of m) (0V or more and +3V or less) and the drain potential (0V), it is indeed higher. It is in the off state. In this way, data is written to the memory cell of the (2n-1)th row. It is possible.

[0193] <Figure 12(B)> (Writing to the 2nth row) Next, when writing the 2nth row, as shown in Figure 12(B), the writing process is performed. The potentials of the code line Q2n-1 and the read word line P2n are set to 0V. The potential of the word line P2n-1 is set to +3V, and the potential of the bias line Sn is set to 0V. On the other hand, the bit The potential of line Rm is one of four values, 0V, +1V, +2V, and +3V, depending on the data being written. Take it.

[0194] The potential of the drain of the writing transistor WTr(2n-1,m) is the read word line P Since it is connected via 2n-1 and capacitor C(2n-1,m), it is a read word line. The potential fluctuation of P2n-1 (i.e., from 0V in Figure 12(A) to +3V in Figure 12(B)) The voltage increases by 3V due to the increase in voltage. In other words, depending on the data written, it will be +3V, +4V. The value will be either +5V or +6V.

[0195] Then, if the potential of the writing word line Q2n is set to +4V, the writing transistor WT When r(2n,m) is turned on, the drain of the writing transistor WTr(2n,m) is turned on. The voltage approaches the potential of the source of the writing transistor (i.e., the bit line Rm). This is assumed to be equal to the potential of the bit line Rm.

[0196] On the other hand, at this stage, the gate potential of the read transistor RTr(2n,m) is the same as the write potential. The potential is equal to the drain potential of transistor WTr(2n,m). That is, the readout transistor The gate potential of transistor RTr(2n,m) is 0V or higher, and the readout transistor R This is the same potential as the source of Tr(2n,m) (i.e., the bit line Rm).

[0197] Also, the drain of the readout transistor RTr(2n,m) (i.e., the bias wire Sn The potential of ) is 0V. Therefore, the voltage of the readout transistor RTr(2n-1,m) Since the potential of the source and drain is the same as or higher than the potential of the readout transistor RTr (2n,m) is in the off state. Also, the writing transistor WTr(2n-1,m) The readout transistor RTr(2n-1,m) is also in the off state. In this way, the second Data can be written to n rows of memory cells.

[0198] <Figure 12(C)> (Writing to other lines) Next, when writing to lines other than those mentioned above, write as shown in Figure 12(C) The potentials of the word lines Q2n-1 and Q2n are set to 0V. Also, the read word line P2n- 1. Set the potential of P2n to +3V and the potential of the bias line Sn to 0V. On the other hand, the bit line Rm The potential is 0V, +1V, +2V, depending on the data being written to the line where the writing is performed. It takes four values ​​of +3V.

[0199] The potential of the drain of the writing transistor WTr(2n,m) is the same as the potential of the read word line P2n. Since it is connected via capacitor C(2n,m), the potential of the read word line P2n Due to the fluctuation (i.e., the rise from 0V in Figure 12(B) to +3V in Figure 12(C)), 3 V increases. That is, depending on the data written, it becomes +3V, +4V, +5V, +6V. The potential of the drain of the writing transistor WTr(2n-1,m) will be one of the following values. Similarly, this will be one of the following values: +3V, +4V, +5V, or +6V.

[0200] Furthermore, in this state, the writing transistors WTr(2n-1,m) and WTr(2n The potential (0 to +3V) of the source (bit line Rm) and the writing transistor WTr ( The potential of the drains of 2n-1,m and WTr(2n,m) is greater than (+3 to +6V). Writing transistor WTr(2n-1,m) and writing transistor WTr(2n, Because the gate potential (0V) of (m) is low, the writing transistor WTr(2n-1,m) And WTr(2n,m) will be turned off.

[0201] Furthermore, the readout transistors RTr(2n-1,m) and RTr(2n,m) The potential (0 to +3V) of the bit line Rm and the readout transistor RTr(2n-1,m ) and the drain of RTr(2n,m) (potential of bias wire Sn (0V)) Gate potentials of readout transistors RTr(2n-1,m) and RTr(2n,m) Because the (+3~+6V) is high, the readout transistor RTr(2n-1,m) and the readout The output transistor RTr(2n,m) is turned off.

[0202] <Figure 13(A)> (Readout) Next, we will explain the reading process. As shown in Figure 13(A), the reading word line P2n -1, the potential of P2n is 0V, the writing word lines Q2n-1, Q2n, and bias line Sn are at the same voltage. The voltage is set to -3V. In this state, the readout transistor RTr(2n-1,m) and R The gate potential of Tr(2n,m) is 0V, +1V, +2V depending on the data written. The voltage will be either V or +3V.

[0203] If the potential of the bit line Rm is between -3V and 0V, the writing transistor WTr(2n -1,m), WTr(2n,m) readout transistor RTr(2n-1,m), RTr Both (2n,m) are off. That is, for lines that are not to be read, in this way, Turn off the transistor in that row.

[0204] <Figure 13(B)> (Reading from the 2nth row [1]) Next, set the potential of the read word line P2n to -3V and the potential of the bit line Rm to -3V. As a result, the gate potential of the readout transistor RTr(2n,m) is equal to the written data. Depending on the device, the voltage will be either -3V, -2V, -1V, or 0V. In this state, writing is possible. With both transistor WTr(2n,m) and readout transistor RTr(2n,m) turned off. Yes, it exists. However, if the potential of the bias wire Sn is varied, the readout transistor RT It is also possible to turn on r(2n,m). For example, as shown in Figure 13(B), When the potential of the IAS wire Sn becomes -2V, the readout transistor RTr(2n,m) When the potential of the terminal is -3V, the readout transistor RTr(2n,m) turns ON. ru.

[0205] <Figure 13(C)> (Reading from the 2nth row [2]) Similarly, as shown in Figure 13(C), when the potential of the bias wire Sn becomes -1V, the reading is If the gate potentials of transistor RTr(2n,m) are -3V and -2V, then the reading The output transistor RTr(2n,m) turns on.

[0206] <Figure 13(D)> (Reading from the 2nth row [3]) Furthermore, as shown in Figure 13(D), when the potential of the bias wire Sn becomes 0V, the readout When the gate potentials of the transistor RTr(2n,m) are -3V, -2V, and -1V, The readout transistor RTr(2n,m) is turned on.

[0207] Even when the bias wire Sn is set to 0V, the readout transistor RTr(2n,m) remains off. If it remains as is, the gate potential of the readout transistor RTr(2n,m) will be 0V. It can be inferred that this was the case.

[0208] Similarly, the data in the (2n-1)th row of the memory cell can also be read. In the above example, I have shown an example of writing and reading data in four stages (2 bits), but similarly, further... A large amount of data, for example, 8 levels of data (3 bits), 16 levels of data (4 bits) It can be written to and read from. In the above explanation, parasitic capacitance and read transistor RTr( The gate capacitance of n,m was ignored in relation to the capacitance of capacitor C(n,m), but in reality... In memory cells, it is necessary to determine the potential to apply after taking these factors into consideration.

[0209] (Embodiment 7) In this embodiment, we will describe an example of operating the semiconductor memory circuit shown in Figures 6(A) and (B). This will be explained using Figures 14 and 15. The specific numerical values ​​for potential are as follows: The reason for listing these points is to aid in understanding the technical concept of this invention. Needless to say, These values ​​depend on the various characteristics of transistors and capacitors, or on the implementer. Subject to change depending on circumstances.

[0210] Here, the writing transistor WTr is an N-channel type, and the reading transistor RTr is It will be a P-channel type. The writing transistor WTr will have a gate potential that is either the source or It is assumed that it turns on when the potential is 1V or more higher than the potential of either of the drains, otherwise Assume that it is off. Also, the readout transistor RTr has a gate potential that is at the source. It is assumed that it turns on when the potential of either of the drains becomes 1V or more lower, otherwise Assume it is off.

[0211] Furthermore, the gate capacitance of the readout transistor RTr is affected by the gate bias. The portion that is negligible compared to the capacitance of capacitor C is assumed to be negligible. Furthermore, the write transient Parasitic capacitance of the WTr, parasitic capacitance of the readout transistor RTr, and other parasitic capacitances between wirings. All capacities not shown in the diagram should be considered as 0.

[0212] Furthermore, in Figures 14 and 15, transistors that are ON are marked with a circle, and those that are OFF are marked with a circle. Transistors are represented by a symbol with an "x" superimposed on it. These are those that turn on under specific conditions. This will be described separately. In the following explanation, the memory cell in the (n-1)th row and column m and the nth row and m Let's explain by focusing on the memory cells in the columns.

[0213] <Figure 14(A)> (Writing to the (n-1)th row) When writing to the (n-1)th row of memory cells, as shown in Figure 14(A), the read-through The potential of the code line Pn-1 and the write word lines Qn and Qn+1 is 0V, and the read word line Pn The potential of Pn+1 is set to +4V. Also, the potential of the bit line Rm depends on the data being written. The voltage will take on four levels: 0V, +1V, +2V, and +3V. The drain of the transistor WTr(n,m) (i.e., the readout transistor RTr(n,m) Assume that the potential of the gate of the device was initially between +4V and +7V.

[0214] Then, if the potential of the writing word line Qn-1 is set to +4V, then the writing transistor W Tr(n-1,m) turns on, and the programmer WTr(n-1,m) is slaved. The potential of the bit line Rm approaches the potential of the source of the writing transistor. Here, we assume that the potential is equal to that of the bit line Rm.

[0215] On the other hand, at this stage, the gate potential of the readout transistor RTr(n-1,m) is, It is equal to the potential of the drain of the integrated transistor WTr(n-1,m). That is, readout. The gate potential of transistor RTr(n-1,m) is the readout transistor RTr(n This is the same potential as the source (i.e., bit line Rm) at -1,m).

[0216] Also, the drain of the read transistor RTr(n-1,m) (i.e., the write wire The potential of the line Qn is 0V. Therefore, the readout transistor RTr(n-1,m The gate potential of the ) is the same as or higher than the source and drain potentials, so the readout transistor RTr(n-1,m) is in the off state.

[0217] Note that the gate potential (0V) of the writing transistor WTr(n,m) is its source ( In other words, the potential of the bit line (Rm) is the same as or lower than the potential of the drain (+4 to +7V) (0 to +3V). Therefore, the writing transistor WTr(n,m) is in the off state, and the reading transistor The gate potential (+4 to +7V) of the RTr(n,m) is determined by its source (i.e., the bit line). Potential of Rm) (0 to +3V), potential of drain (i.e., write word line Qn+1) Since it is higher than (0V), the readout transistor RTr(n,m) is also in the off state. In this way, data can be written to the memory cell of the (n-1)th row.

[0218] <Figure 14(B)> (Writing to the nth row) When writing to the nth row of memory cells, as shown in Figure 14(B), the read word line P The potential of n and the writing word lines Qn-1 and Qn+1 is 0V, and the reading word line Pn-1 and P The potential of n+1 is set to +4V. Also, the potential of the bit line Rm depends on the data being written. It will take on four values: 0V, +1V, +2V, and +3V.

[0219] Because the potential of the read word line Pn-1 rose by 4V, the read transistor RTr(n The gate of the writing transistor WTr(n-1,m) (i.e., the drain of the writing transistor WTr(n-1,m)) The potential of ) also rises similarly, becoming between +4V and +7V.

[0220] Then, if the potential of the writing word line Qn is set to +4V, the writing transistor WTr When (n,m) is turned on, the potential of the drain of the writing transistor WTr(n,m) is The potential approaches that of the source of the feed transistor (i.e., the bit line Rm). Here, Assume that the potential is equal to that of the wire Rm.

[0221] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is, It is equal to the potential of the drain of transistor WTr(n,m). That is, the readout transistor The gate potential of transistor RTr(n,m) is the saw of the readout transistor RTr(n,m). It is the same potential as the bit line Rm.

[0222] Also, the drain of the read transistor RTr(n,m) (i.e., the write word line) The potential at Qn+1) is 0V. Therefore, the readout transistor RTr(n,m) The gate potential (the potential of the bit line Rm) is the same as or higher than the source and drain potentials, so read The off-axis transistor RTr(n,m) is in the off state.

[0223] Note that the gate potential (0V) of the writing transistor WTr(n-1,m) is... The potential of the bit line Rm (i.e., the potential of the drain (0 to +3V) is the same as the potential of the drain (+4 to +7V)). Because the voltage is low, the writing transistor WTr(n-1,m) is in the off state, and the reading transistor The gate potential (+4 to +7V) of the transistor RTr(n-1,m) is equal to its source (i.e., The potential of the bit line Rm (0 to +3V), the drain (i.e., the write word line Qn) Since the potential (+4V) is the same as or higher than that, it is in the off state. In this way, the nth row of memory Data can be written to the log.

[0224] <Figure 14(C)> (Writing to the (n+1)th row) When writing to the (n+1)th row of memory cells, as shown in Figure 14(C), the read-through The code line Pn+1 and the write word line Qn-1, the potential of Qn is 0V, and the read word line Pn The potential of -1 and Pn is set to +4V. Also, the potential of the bit line Rm depends on the data being written. It will take on four values: 0V, +1V, +2V, and +3V.

[0225] Because the potential of the read word line Pn increased by 4V, the read transistor RTr(n,m The potential of the gate (i.e., the drain of the writing transistor WTr(n,m)) is also the same. It rises in a certain way, becoming between +4V and +7V.

[0226] Then, by setting the potential of the writing word line Qn+1 to +4V, the (n+1) You can write data to the memory cells of a row.

[0227] At this stage, the gate potential (0V) of the writing transistor WTr(n,m) is... The potential of the rain (+4 to +7V) and the potential of the source (i.e., the bit line Rm) (0 to +3V) Since it is equal to or lower than ), the writing transistor WTr(n,m) is in the off state.

[0228] Furthermore, the gate potential (+4 to +7V) of the readout transistor RTr(n,m) is The potential (+4V) of the rain (i.e., the written word line Qn+1) and the source (i.e., The potential of the bit line Rm is equal to or higher than (0 to +3V), so the readout transistor RTr( n,m) is also in the off state.

[0229] Furthermore, the gate potential (0V) of the writing transistor WTr(n-1,m) is... The potential of the bit line (Rm) (0 to +3V) and the drain (+4 to +7V) are the same. Because the direct current is low, the writing transistor WTr(n-1,m) is in the off state, and the reading transistor The gate potential (+4 to +7V) of the transistor RTr(n-1,m) is the same as its source (i.e., The potential of the bit line Rm (0 to +3V), the drain (i.e., the write word line Q) Since the potential of (n) is higher than (0V), it is in the off state. In this way, the (n+1)th row Data can be written to the memory cell.

[0230] <Figure 14(D)> (Writing to other rows) When writing to memory cells in rows other than those mentioned above, as shown in Figure 14(D), the writing tool The potentials of the do line Qn-1, Qn, and Qn+1 are set to 0V, and the read word lines Pn-1, Pn, and Pn+ The potential of point 1 is set to +4V. Also, the potential of bit line Rm is set to the value of the line on which writing is performed. Depending on the data being recorded, the voltage will take one of four values: 0V, +1V, +2V, or +3V.

[0231] In this state, the gate potential (0V) of the writing transistor WTr(n,m) is The potential of the rain (+4 to +7V) and the potential of the source (i.e., the bit line Rm) (0 to +3V) Since it is equal to or lower than ), the writing transistor WTr(n,m) is in the off state.

[0232] Furthermore, the gate potential (+4 to +7V) of the readout transistor RTr(n,m) is The potential (0V) of the rain (i.e., the written word line Qn+1) and the source (i.e., the bit Since the potential of the wire Rm is higher (0 to +3V), the readout transistor RTr(n,m) It is also in the off state.

[0233] Furthermore, the gate potential (0V) of the writing transistor WTr(n-1,m) is... The potential of the bit line (Rm) (0 to +3V) and the drain (+4 to +7V) are the same. Because the direct current is low, the writing transistor WTr(n-1,m) is in the off state, and the reading transistor The gate potential (+4 to +7V) of the transistor RTr(n-1,m) is the same as its source (i.e., The potential of the bit line Rm (0 to +3V), the drain (i.e., the write word line Q) Since the potential is higher than (0V) at point n), it is in the off state.

[0234] <Figure 15(A)> (Readout) Next, we will explain how to read data. The following describes how to read data from the nth row of a memory cell. However, the same process can be used to read memory cells in other rows. (Figure) As shown in 15(A), the potentials of the writing word lines Qn-1, Qn, and Qn+1 are set to 0V. Furthermore, the potentials of the read word lines Pn-1, Pn, and Pn+1 are set to +3V.

[0235] In this state, the potential of the drain of the writing transistor WTr(n,m) is written Depending on the data, the voltage will be either +3V, +4V, +5V, or +6V, and the bit line Rm If the potential is between 0V and +3V, the writing transistor WTr(n,m) is used, and the reading transistor is used. Both transistors RTr(n,m) are off. Similarly, the writing transistor WTr( n-1,m), the readout transistor RTr(n-1,m) is also off. That is, the readout transistor is also off. For lines that do not extend beyond the designated area, the write transistor and read transistor are used in this manner. Turn it off.

[0236] <Figure 15(B)> (Readout) On the other hand, for the row to be read, the potential of the read word line Pn should be less than +3 volts. For example, as shown in Figure 15(B), with the potential of the bit line Rm set to +3V, The potential of the protruding word line Pn is set to +2V. At this time, the readout transistor RTr(n The gate potential of ,m) will be between +2V and +5V, and in particular, when it is +2V, Since it is lower than the potential (+3V) of the bit line Rm, the readout transistor R Tr(n,m) is turned on.

[0237] During the writing process, four different potentials were applied: 0V, +1V, +2V, and +3V. The device turns on when a 0V potential is applied during writing. The fact that the ristor RTr(n,m) is turned on means that, as in other embodiments, various people It can be found out by law.

[0238] <Figure 15(C)> (Readout) Similarly, as shown in Figure 15(C), when the potential of the read word line Pn becomes +1V, The gate potential of the readout transistor RTr(n,m) will be between +1V and +4V. In the cases of +1V and +2V, the readout transistor RTr(n,m) is turned on. This is the result. Here, it turns on when a potential of 0V or +1V is applied during writing. This is the case.

[0239] <Figure 15(D)> (Readout) Furthermore, as shown in Figure 15(D), if the potential of the read word line Pn becomes 0V, the read The gate potential of the output transistor RTr(n,m) will be between 0V and +3V. In the cases of 0V, +1V, and +2V, the readout transistor RTr(n,m) is ON. This is how it works. Here, it turns on when a potential of 0V, +1V, or +2V is applied during writing. This is the case.

[0240] Even if the potential of the read word line Pn is set to 0V, the read transistor RTr(n,m) If it remains off, the gate potential of the readout transistor RTr(n,m) is +3V. It can be inferred that this was the case. This is the case when a potential of +3V was applied during writing.

[0241] In the above process, the writing transistors WTr(n,m), WTr(n-1,m), The readout transistor RTr(n-1,m) remains in the off state. In this way, the four steps It can write and read data (2 bits). Of course, in the same way, even more Data, for example, 8 levels of data (3 bits), 16 levels of data (4 bits) can be written. Readable.

[0242] The above explanation does not include parasitic capacitance or the gate capacitance of the readout transistor RTr(n,m). Although the capacity of Pasita C(n,m) was ignored, these were taken into consideration in actual memory cells. Above, it is necessary to determine the potential to be applied.

[0243] (Embodiment 8) In this embodiment, an example of the operation of the semiconductor memory circuit shown in Figure 16(A) is shown in Figure 17(A). This will be explained using Figure 18. Note that specific numerical values ​​for potential are given below, but... The purpose is to help understand the technical concept. Needless to say, those values ​​are transients It can be modified depending on the various characteristics of the staccato and capacitor, or at the discretion of the implementer. Furthermore, the semiconductor memory device shown in Figure 16(A) can also be used by methods other than those described below. It can write or read data.

[0244] Here, the writing transistors WTr1, WTr2, and WTr3 are of an N-channel type, and the reading transistors The transistors RTr1, RTr2, and RTr3 are of the P-channel type. Also, the writing A transistor is defined as having a gate potential that is 1% lower than the lower of the source or drain potential. It is assumed that the device turns on when the value exceeds V, and is off otherwise. A zista has a gate potential that is 1V lower than the higher of the source or drain potential. When the value is low or high, it is considered "on," and otherwise, it is considered "off."

[0245] Furthermore, the portion of the gate capacitance of the readout transistor that fluctuates due to the gate bias is The capacitance of capacitor C is to be considered negligible. Furthermore, the writing transistor WT Parasitic capacitance of r, parasitic capacitance of the read transistor RTr, and other parasitic capacitances between wirings, etc. All capacities not shown in the diagrams should be considered as 0. Also, in Figures 17 and 18, A circle is marked on transistors that are in the "on" state, and an "X" is marked on transistors that are in the "off" state. The symbol is superimposed on the transistor symbol. For those that turn on under specific conditions, the symbol is shown in the diagram. Further details may be provided separately. In the following example, the potential of the bias wire S is assumed to be 0V at all times.

[0246] First, let's explain how to write to this memory unit. Writing is done using the rightmost memory cell. Start with the letter. When writing, as shown in Figure 17(A), read word lines P1, P 2. Set the potential of P3 to 0V. Also, the potential of bit line R is set to 0V depending on the data being written. It will take on four values: V, +1V, +2V, and +3V.

[0247] Then, if the potential of the writing word lines Q1, Q2, and Q3 is set to +4V, the writing transistor The generators WTr1, WTr2, and WTr3 are turned on, and the writing transistor WTr3 is activated. The potential at Rain (i.e., the potential at node F3) approaches the potential at bit line R. Here, Assume that the potential is equal to that of the bit line R.

[0248] Meanwhile, at this stage, the readout transistors RTr1, RTr2, and RTr3 are in the off state. Yes. And, as shown in Figure 17(B), the potential of the writing word line Q3 is set to 0V. As a result, the writing transistor WTr3 is turned off, and node F3 receives the previous bit... The potential of the T-wire R is maintained. In this way, data is written to the rightmost memory cell. It is possible.

[0249] Next, data is written to the central memory cell. In the state shown in Figure 17(B), the potential of node F2. This becomes equal to the potential of the bit line R. Then, the potential of the write word line Q2 is set to 0V. (See Figure 17(C)) and the writing transistor WTr2 is turned off, so node F2 Then, the potential of the previous bit line R is retained. In this way, data is stored in the central memory cell. You can write to it.

[0250] In this way, data can be written to all memory cells. (Memory unit) If the operation of writing to the internal storage unit is not required (if data is not written to a storage unit other than the storage unit in question) When writing data, etc., the potential of the read word line P1 should be set to +3V, as shown in Figure 17(D). This is a good approach. At this time, the potential of node F1 will be between +3V and +6V. Bit line R Since the potential is between 0V and +3V, the readout transistor RTr1 remains in the off state. It can be done.

[0251] Next, we will explain the reading process using Figure 18. First, we read rows other than those in the storage unit in question. When outputting, as shown in Figure 18(A), write word lines Q1, Q2, Q Let the potential of point 3 be 0V, and the potentials of the read word lines P1, P2, and P3 be +4V. The writing transistors WTr1, WTr2, and WTr3 are turned off. Also, node F1 The potentials of F2 and F3 are between +4V and +7V. And the potential of bit line R is... As explained below, the voltage is between 0V and +4V, so the readout transistors RTr1 and RT r2 and RTr3 can remain off.

[0252] To read from the memory unit, as shown in Figure 18(B), the write tool Set the potentials of the D lines Q1, Q2, and Q3 to 0V, and the potentials of the read word lines P1, P2, and P3 to 0V. Also, the potential of the bit line is set to +4V. In this case, the writing transistor WT r1, WTr2, and WTr3 will be turned off, but the potential of nodes F1, F2, and F3 will be 0V or higher. The voltage is 3V or less, and the readout transistors RTr1, RTr2, and RTr3 are turned on. Therefore, current flows between the bit line R and the bias line S.

[0253] If the termination of bit line R is a capacitor, then a current will be generated between bit line R and bias line S. As current flows, the initial potential (+4V) approaches the potential of the bias wire S (0V). The final potential is determined by the minimum potential of nodes F1, F2, and F3, but in any case, The potential of the wire R will fluctuate between 0V and +4V.

[0254] In the following, we will assume that we are reading data from the central memory cell of the memory unit. Figure 18 As shown in (C), when the potential of the read word line P2 is increased to +1V, the node F2 The potential will be either +1V, +2V, +3V, or +4V depending on the data written. Here, if the potential of node F2 is +4V, the readout transistor RTr2 is off. Therefore, no current flows between the bit line R and the bias line S.

[0255] At this stage, the potential of node F2 is +4V because the potential of the bit line is positive during writing. This is the case when the voltage is 3V. That is, when the potential of the read word line P2 is +1V. If the read transistor RTr2 is off, the potential of the bit line R during writing is +3 It turns out that the value was V. In this way, we can find out the value of the data that is being held.

[0256] Furthermore, as shown in Figure 18(D), if the potential of the readout word line P2 is increased to +2V, The potential of node F2 is +2V, +3V, +4V, or +5V depending on the data written. It will be one of the following. Here, if the potential of node F2 is +4V or +5V, the readout transistor Since the zista RTr2 is turned off, no current flows between the bit line R and the bias line S. .

[0257] This can be detected to determine the value of the data. In other words, at this stage, the readout The gate potential of the transistor RTr2 is +4V or +5V during writing. When the potential of bit line R is +2V or +3V, the read word line P2 When the potential was +1V (i.e., the state shown in Figure 18(C)), it was in the ON state, but when it reached +2V... If it turns off, then the potential of bit line R was +2V at the time of writing. It is.

[0258] Similarly, as shown in Figure 18(E), if the potential of the readout word line P2 is increased to +3V, The potential of node F2 is +3V, +4V, +5V, or +6V depending on the data written. It will be one of the following. Here, if the potential of node F2 is +4V, +5V, or +6V, then read out As transistor RTr2 turns off, current flows between the bit line R and the bias line S. It disappears. In other words, when writing, the potential of the bit line is either +1V, +2V, or +3V. This is the case if that were the case.

[0259] If the bit line potential was 0V during writing, the potential of the read word line P2 should be When set to +3V, the potential of node F2 is +3V, and it remains ON. Even if the potential of the read word line P2 is +3V, current flows between the bit line R and the bias line S. If this occurs, it indicates that the potential of the bit line was 0V at the time of writing.

[0260] The above describes a method for determining the data value by gradually changing the potential of the readout word line P2. However, the data value can also be determined by measuring the electric potential. For example, Figure 18(F As shown in ( ), a capacitor is placed at the end of the bit line, and the potential on the memory cell side is set to 0V. .

[0261] Additionally, the potential of the write word lines Q1, Q2, and Q3 and the read word lines P1 and P3 should be -3V. In this state, the potential of both nodes F1 and F3 is between -3V and 0V, so By setting the potential of the F2 appropriately, the readout transistors RTr1 and RTr 2. Turn on RTr3 and bring the potential of the bit line R close to the potential of the bias line S (0V). This is possible. For example, if node F2 is 0V or less, the potential of the capacitor on bit line R is The voltage will be between 0V and less than +1V.

[0262] First, assuming the read word line P2 is +3V, the potential of node F2 is between +3V and +6V. Since it is below V, the readout transistor RTr2 is off at this stage. However, Next, when the potential of the read word line P2 is lowered to 0V, the potential of node F2 becomes greater than 0V and up to +3V. The following occurs, and the readout transistor RTr2 turns on.

[0263] As explained earlier, if the potential at node F2 is 0V, then the potential of the capacitor on bit line R is... The voltage will be between 0V and +1V. Here, the potential of node F2 becomes 0V when writing. This is the case when the potential of the bit line is 0V.

[0264] Similarly, if the potential of node F2 is +1V, then the potential of the capacitor on bit line R is +1V or higher. If the voltage above is less than +2V and the potential at node F2 is +2V, then the potential of the capacitor on bit line R is + If the voltage is between 2V and +3V, and the potential at node F2 is +3V, then the voltage of the capacitor on bit line R is... The voltage will be between +3V and +4V. And in each case, the bit during writing The potential of the bit line can be determined. That is, by measuring the potential of the capacitor R on the bit line, Therefore, the potential of node F2 can be determined, and from that, the potential of the bit line during writing can be determined. It is possible to know.

[0265] In this way, four levels of data (2 bits) can be written and read. In this way, even more data, for example, 8 levels of data (3 bits), 16 levels of data It can write and read data (4 bits).

[0266] The above explanation does not include parasitic capacitance or the gate capacitance of the readout transistor RTr(n,m). Although the capacity of Pasita C(n,m) was ignored, these were taken into consideration in actual memory cells. Above, it is necessary to determine the potential to be applied.

[0267] The gate capacitance of the readout transistor RTr(n,m) changes significantly between the ON and OFF states. Because it moves, the gate potential of the readout transistor RTr(n,m) is affected. The capacitance of capacitor C(n,m) is the gate capacitance of the readout transistor RTr(n,m). The larger the ratio to, the greater the effect, so preferably, the capacitor C(n,m The capacitance of the readout transistor RTr(n,m) should be at least twice the gate capacitance of the readout transistor RTr(n,m). .

[0268] (Embodiment 9) In this embodiment, the shape and manufacturing method of the semiconductor memory device described in Embodiment 8 are as follows: Let me explain. In this embodiment, the writing transistor contains gallium and indium. The oxide semiconductor is used, and the readout transistor is a single-crystal silicon semiconductor. Therefore, the writing transistor is stacked on top of the reading transistor. For detailed information regarding the manufacturing method, please refer to known semiconductor manufacturing techniques or Embodiment 3. You should refer to this.

[0269] Figure 22 shows an example layout of the storage unit of the semiconductor memory device according to this embodiment. In this configuration, the unit memory unit has four memory cells.

[0270] Figure 22(A) shows the main wiring, electrodes, etc., provided on the single-crystal silicon substrate. An element isolation region 302 is formed. Conductive material (silicide, etc.) and doping are applied to the substrate. A conductive region 306 is formed using silicon. A portion of the conductive region 306 is readable. It becomes the source and drain of the protruding transistor. Also, a part of the conductive region 306 is a via It also forms part of the S wire S. The conductive region 306 is the read gate 31 of the read transistor. Some parts are separated by zeros. A first connecting electrode 311 is provided in part of the conductive region 306. It is possible.

[0271] By using the conductive region 306 to form the bias line S, the integration density can be increased. However, in that case, the bias line S is parallel to the write word line and the read word line. It is preferable that it is a row (i.e., perpendicular to the bit line). Note that as shown in the figure, The bias line S is shared with the adjacent memory unit (the memory unit to the right of the bias line S). Having it allows for increased integration.

[0272] As for the material of the read gate 310 and the first connecting electrode 311, the material is as shown in Embodiment 3 (or Figure Using materials such as those used for the read gate 110 and the first connecting electrode 111 as described in 8) That's all you need to do.

[0273] Figure 22(B) shows a transient using an oxide semiconductor formed on top of the circuit in Figure 22(A). This shows the main wiring and electrodes centered around the ta. Multiple island-shaped oxide semiconductor regions 312 and multiple The first wiring 314 is formed by the writing word lines Q1, Q2, Q3, Q4, or the reading word lines P1, P2, P3, P4.

[0274] Part of the first wiring 314 overlaps with the oxide semiconductor and the gate electrode of the writing transistor. The oxide semiconductor region 312 also contacts the lower layer readout gate 310. A portion of the wiring 314 overlaps with the read gate 310, forming a capacitor. Also, acid A portion of the ionized semiconductor region 312 has a second connection for connecting to the upper layer (e.g., bit line R). A follow-up electrode 317 is provided.

[0275] When Figures 22(A) and (B) are superimposed, the result is as shown in Figure 22(C). Furthermore, they are intentionally slightly offset and overlapped so that the overlap is visible. The second wiring 318 formed on the transistor is also shown in the diagram. The part becomes the bit line R. Note that points A and B in Figures 22(A) to (C) indicate the same position. That is the case.

[0276] In Figure 22, the conductive region 306 has a width, and the first wiring 314 is processed with the minimum processing line width F. That is, the line width and line spacing are F. In that case, the size of the unit memory cell is 12F. 2 Therefore, since each memory cell also shares a portion of the memory unit, in reality, the memory cells The area per floor is 12F 2 It becomes larger. The memory unit shown in Figure 22 has four memory cells Although a space is provided, if the number of memory cells in the memory unit is increased, the surface area per memory cell will be The total is 12F 2 Approaching.

[0277] (Embodiment 10) In this embodiment, an example of the operation of the semiconductor memory circuit shown in Figure 16(B) is shown in Figure 20(B). This will be explained using Figure 21. Note that specific numerical values ​​for potential are given below, but... The purpose is to help understand the technical concept. Needless to say, those values ​​are transients It can be modified depending on the various characteristics of the staccato and capacitor, or at the discretion of the implementer. Furthermore, the semiconductor memory device shown in Figure 16(B) can also be manufactured by methods other than those described below. It can write or read data.

[0278] Here, the writing transistors WTr1, WTr2, and WTr3 are of an N-channel type, and the reading transistors The transistors RTr1, RTr2, and RTr3 are of the P-channel type. Also, the writing A transistor has a gate potential that is 1V lower than the potential of either the source or the drain. It is assumed that it turns on when the value exceeds a certain level, and off otherwise. Also, read transition The sta is defined as the gate potential being 1V or more lower than the potential of either the source or the drain. It will turn on when it gets dark, and off otherwise.

[0279] Furthermore, the portion of the gate capacitance of the readout transistor that fluctuates due to the gate bias is The capacitance of capacitor C is to be considered negligible. Furthermore, the writing transistor WT Parasitic capacitance of r, parasitic capacitance of the read transistor RTr, and other parasitic capacitances between wirings, etc. All capacities not shown in the diagrams should be considered as 0. Also, in Figures 20 and 21, ON A circle is marked on transistors that are in the "on" state, and an "X" is marked on transistors that are in the "off" state. The symbol is superimposed on the transistor symbol. For those that turn on under specific conditions, the symbol is shown in the diagram. Further details may be provided separately. In the following example, the potential of the bias wire S is assumed to be 0V at all times.

[0280] Writing begins from the rightmost memory cell. During writing, as shown in Figure 20(A) The potential of the write word lines Q1, Q2, and Q3 is set to +4V, and the potential of the read word line P is set to -4V. Let V be the potential of the bit line R. Also, the potential of the bit line R is 0V, +1V, or +2V depending on the data being written. It will take four values, including +3V.

[0281] In this state, the writing transistors WTr1, WTr2, and WTr3 are turned on, and The potential of F3 approaches the potential of bit line R. Here, it becomes equal to the potential of bit line R. Let's assume that.

[0282] Meanwhile, at this stage, the readout transistors RTr1, RTr2, and RTr3 are in the off state. Yes. And, as shown in Figure 20(B), the potential of the writing word line Q3 is set to -4V. Then, the writing transistor WTr3 turns off, so at node F3, the previous bit... The potential of the T-wire R is maintained. In this way, data is written to the rightmost memory cell. It is possible.

[0283] Next, the data is written to the central memory cell. In the state shown in Figure 20(B), the potential of node F2 is This becomes equal to the potential of the bit line R. Then, the potential of the write word line Q2 is set to -4V. (See Figure 20(C)) The writing transistor WTr2 is turned off, and at node F2 The potential of the previous bit line R is retained. In this way, data is written to the central memory cell. It is possible to write the data. Similarly, write the data sequentially to all memory cells. It can be filled.

[0284] If writing to the memory unit is not required, as shown in Figure 20(D), The potentials of the writing word lines Q1, Q2, and Q3 are set to 0V, and the potential of the reading word line P is set to 0V. This is good. At this time, the potential of node F1 will be between +4V and +7V. Since the voltage is between 0V and +3V, the readout transistors RTr1, RTr2, and RTr 3 can remain in the off state.

[0285] Next, we will explain the reading process using Figure 21. First, we read rows other than those in the memory unit in question. When outputting, as shown in Figure 21(A), write word lines Q1, Q2, Q Let the potential of point 3 be 0V, and the potential of the read word line P be 0V. Then, the write transistor The zistas WTr1, WTr2, and WTr3 will be turned off. Also, the power to nodes F1, F2, and F3 will be turned off. The voltage range is between +4V and +7V. And the potential of the bit line R is as will be explained later. Since the voltage is between 0V and +4V, the readout transistors RTr1, RTr2, and RTr3 are It can remain off.

[0286] To read from the memory unit, as shown in Figure 21(B), the write tool The potentials of lines Q1, Q2, and Q3 are set to -4V, and the potential of the read word line P is set to -4V. The potential of the bit line is set to +4V. In this case, the writing transistors WTr1 and WT are used. r2 and WTr3 will be turned off. Also, the potential of nodes F1, F2, and F3 will be between 0V and +3V. Since it is below, the readout transistors RTr1, RTr2, and RTr3 are turned on. Therefore, current flows between the bit line R and the bias line S.

[0287] If the termination of bit line R is a capacitor, then a current will be generated between bit line R and bias line S. As current flows, the initial potential (+4V) approaches the potential of the bias wire S (0V). The final potential is determined by the minimum potential of nodes F1, F2, and F3, but in any case, The potential of the wire R will fluctuate between 0V and +4V.

[0288] In the following, we will assume that we are reading data from the central memory cell of the memory unit. Figure 21 As shown in (C), when the potential of the write word line Q3 is raised to -3V, node F2 The potential will be either +1V, +2V, +3V, or +4V depending on the data written. Here, if the potential of node F2 is +4V, the readout transistor RTr2 is off. Therefore, no current flows between the bit line R and the bias line S.

[0289] At this stage, the potential of node F2 is +4V because the potential of the bit line is positive during writing. This is the case when the voltage is 3V. That is, when the potential of the writing word line Q3 is +1V. If the read transistor RTr2 is off, the potential of the bit line R during writing is +3 It turns out the value was V. In this way, we can find out the value of the data.

[0290] Furthermore, as shown in Figure 21(D), if the potential of the writing word line Q3 is raised to -2V, The potential of node F2 is +2V, +3V, +4V, or +5V depending on the data written. It will be one of the following. Here, if the potential of node F2 is +4V or +5V, the readout transistor Since the zista RTr2 is turned off, no current flows between the bit line R and the bias line S. The potential of node F2 becomes +4V or +5V when the bit line potential is +2V during writing. This is the case when the voltage is +3V.

[0291] Similarly, as shown in Figure 21(E), if the potential of the writing word line Q3 is raised to -1V, The potential of node F2 is +3V, +4V, +5V, or +6V depending on the data written. It will be one of the following. Here, if the potential of node F2 is +4V, +5V, or +6V, then read out As transistor RTr2 turns off, current flows between the bit line R and the bias line S. It disappears. In other words, when writing, the potential of the bit line is either +1V, +2V, or +3V. This is the case if that were the case.

[0292] If the bit line potential was 0V during writing, the potential of the writing word line Q3 will be When the voltage is set to -1V, the potential of node F2 is +3V, and it remains ON. In other words, even if the potential of the writing word line Q3 is -1V, current will still flow between the bit line R and the bias line S. If current flows, it indicates that the potential of bit line R was 0V at the time of writing.

[0293] Furthermore, in Embodiment 8, the potential is measured using the same method as described with reference to Figure 18(F). This method also allows us to read multi-valued data.

[0294] In this way, four levels of data (2 bits) can be written and read. In this way, even more data, for example, 8 levels of data (3 bits), 16 levels of data It can write and read data (4 bits).

[0295] The above explanation does not include parasitic capacitance or the gate capacitance of the readout transistor RTr(n,m). Although the capacity of Pasita C(n,m) was ignored, these were taken into consideration in actual memory cells. Above, it is necessary to determine the potential to be applied.

[0296] The gate capacitance of the readout transistor RTr(n,m) changes significantly between the ON and OFF states. Because it moves, the gate potential of the readout transistor RTr(n,m) is affected. The capacitance of capacitor C(n,m) is the gate capacitance of the readout transistor RTr(n,m). The larger the ratio to, the greater the effect, so preferably, the capacitor C(n,m The capacitance of the readout transistor RTr(n,m) should be at least twice the gate capacitance of the readout transistor RTr(n,m). .

[0297] (Embodiment 11) In this embodiment, the shape and manufacturing method of the semiconductor memory device described in Embodiment 10 are as follows: Let me explain further. Figure 23 shows the layout of the storage unit of the semiconductor memory device of this embodiment. Let's look at an example. In this embodiment, the unit memory unit has four memory cells.

[0298] Figure 23(A) shows the main wiring, electrodes, etc., provided on a single-crystal silicon substrate. An element isolation region 402 is formed. In addition, conductive materials or doped silicon are used. A conductive region 406 is formed, and a part of it is the source and drain of the readout transistor. Yes. Part of the conductive region 406 becomes part of the bias line S. The conductive region 406 is read out There is a portion separated by the transistor's readout gate 410. Conductive region 406 A first connecting electrode 411 is provided in part of it. In this embodiment, the first connecting electrode 411 is The integration density can be increased by sharing with adjacent memory units. Read gate 410 As for the material of the first connecting electrode 411, the same material as the read gate 310 and the first connection electrode shown in Embodiment 9. Any device that satisfies the condition of having one connecting electrode 311 should be used.

[0299] Figure 23(B) shows a transient using an oxide semiconductor formed on top of the circuit in Figure 23(A). This shows the main wiring and electrodes centered around the ta. Multiple island-shaped oxide semiconductor regions 412 and multiple The first wiring 414 is formed by the writing word lines Q1, Q2, Q3, Q4, or the read word line P.

[0300] Part of the first wiring 414 overlaps with the oxide semiconductor and the gate electrode of the writing transistor. The oxide semiconductor region 412 is in contact with the lower layer readout gate 410. A portion of the wiring 414 overlaps with the read gate 410, forming a capacitor. Also, acid The ionized semiconductor region 412 has a second connecting electrode for connecting to the upper layer (e.g., bit line R). 417 will be established.

[0301] When Figures 23(A) and (B) are superimposed, the result is as shown in Figure 23(C). Furthermore, they are intentionally slightly offset and overlapped so that the overlap is visible. The second wiring 418 formed on the transistor is also shown in the diagram. The part becomes the bit line R.

[0302] Points A and B in Figures 23(A) through (C) represent the same location. In Figure 23, The width of the conductive region 406 is machined with a minimum machining line width F. That is, the line width and line spacing are F. Yes, in that case the size of the unit memory cell is 9F. 2 This is how it works. Each memory cell in the memory unit is... Because some parts are shared, in reality, the area per memory cell is 9F 2 It will get bigger. The memory unit shown in Figure 23 has four memory cells, but within the memory unit If you increase the number of memory cells, the area per memory cell will be 9F 2 Approaching.

[0303] The following describes the method for manufacturing a semiconductor memory device with the above structure. Figure 24 shows the same point as in Figure 23. This is a cross-sectional view of the process connecting point A and point B. The manufacturing process will be explained below according to the numbers in the figure.

[0304] <Figure 24(A)> First, using known semiconductor manufacturing techniques, an element isolation device is created on an n-type single-crystal silicon substrate 401. Region 402, conductive region 406 made of p-type doped silicon region, first gate An insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. Dummy gate 4 A side wall may be provided on the side of 04 as shown in the figure. The conductive region 406 Alternatively, a structure may be provided on its surface to enhance conductivity.

[0305] <Figure 24(B)> Using the method described in Embodiment 3, the read gate 410 of the read transistor, After embedding and forming the first connecting electrode 411, an oxide semiconductor region 412 is formed. The oxide semiconductor region has a thickness of 30-50 nm, and the second gate insulating film 4 is formed thereafter. To make it several times larger than 10nm with a thickness of 13, in order to reduce the step, oxide semiconductor The edges of region 412 are machined to a tapered shape. The taper angle at the edge of the oxide semiconductor region is 30° A degree of 60 degrees would be appropriate.

[0306] <Figure 24(C)> Multiple first wirings 414 are formed using a conductive material. The first wirings 414 are used to write words. These are lines Q1, Q2, Q3, etc. Part of the writing word lines Q1, Q2, and Q3 are oxide semiconductors. This forms the gate electrode of a transistor. Furthermore, region 415 exhibits n-type conductivity, A two-layer insulator 416, a second connecting electrode 417, and a second wiring 418 are formed. This is the bit line R. Thus, as shown in Figure 24(C), the writing transistor A semiconductor having 419a, 419b, readout transistor 420, and capacitor 421. The memory cells for the Mori device are fabricated.

[0307] As shown in the figure, the write word line Q2 is connected to the electrodes of capacitor 421 and write It is formed as the gate electrode of transistor 419b. Part of capacitor 421 (that is, (The oxide semiconductor region between the write word line Q2 and the read gate 410) 412 is not doped, but its thickness is less than 50 nm, so more than half of it It functions as a weak n-type conductor. [Explanation of Symbols]

[0308] 11 Means for measuring electric potential 12 Means of applying electric potential 13 Capacitors 14 switches 101 Single-crystal silicon substrate 102 Element isolation region 103 First gate insulating film 104 Dummy Gate 105a Silicide region 105b Silicide region 106a Conductive area 106b Conductive region 107 First interlayer insulator 107a First interlayer insulator having a flat surface 108 Opening 109 Opening 110 Read gate 111 First connecting electrode 112 Oxide Semiconductor Region 113 Second gate insulating film 114a First wiring 114b 1st wiring Region exhibiting 115a n-type conductivity 115b Region exhibiting n-type conductivity 116. Second layer insulator 117 Second connecting electrode 118 2nd wiring 119 Writing transistors 120 Readout Transistors 121 Capacitors 200a Unit memory cell area 200b Unit memory cell area 202 Element isolation region 206a Conductive region 206b Conductive region 210 Read gate 211 First connecting electrode 212 Oxide Semiconductor Region 214 1st wiring 217 Second connecting electrode 218 2nd wiring 302 Element isolation region 306 Conductive area 310 Read gate 311 First connecting electrode 312 Oxide Semiconductor Region 314 1st wiring 317 Second connecting electrode 318 2nd wiring 401 Single-crystal silicon substrate 402 Element isolation region 403 First gate insulating film 404 Dummy Gate 406 Conductive region 407 First interlayer insulator 410 Read gate 411 First connecting electrode 412 Oxide Semiconductor Region 413 Second gate insulating film 414 1st wiring 415 n-type conductive region 416 Second interlayer insulator 417 Second connecting electrode 418 2nd wiring 419a Writing transistor 419b Writing transistor 420 Readout Transistors 421 Capacitors P Readout Word Line Q: Word lines for writing R bit line S bias line WTr Programming Transistor RTr Readout Transistor C Capacitor

Claims

1. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a fourth transistor having an oxide semiconductor in its fourth channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. Either the source or drain of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the fourth transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region in contact with the side surface of the first conductive film, A second insulating film having a region in contact with the first insulating film, An oxide semiconductor film having a region positioned above the second insulating film, and comprising the second channel-forming region and the fourth channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, and having the function of a gate insulating film for the second transistor and the function of a gate insulating film for the fourth transistor, A second conductive film having a region positioned above the third insulating film and functioning as the gate of the second transistor, A third conductive film having a region positioned above the third insulating film and functioning as the gate of the fourth transistor, A fourth conductive film having a region in contact with the oxide semiconductor film, The fourth conductive film is always electrically connected to the other of the source or drain of the first transistor. The semiconductor device wherein the second channel formation region does not have a region that overlaps with the first conductive film.

2. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a fourth transistor having an oxide semiconductor in its fourth channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. Either the source or drain of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the fourth transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region in contact with the side surface of the first conductive film, A second insulating film having a region in contact with the first insulating film, An oxide semiconductor film having a region positioned above the second insulating film, and comprising the second channel-forming region and the fourth channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, and having the function of a gate insulating film for the second transistor and the function of a gate insulating film for the fourth transistor, A second conductive film having a region positioned above the third insulating film and functioning as the gate of the second transistor, A third conductive film having a region positioned above the third insulating film and functioning as the gate of the fourth transistor, A fourth conductive film having a region in contact with the oxide semiconductor film, The fourth conductive film is always electrically connected to the other of the source or drain of the first transistor. The second channel-forming region does not have a region that overlaps with the first conductive film. The semiconductor device has a laminated structure in which the second insulating film comprises an insulating film having nitrogen and silicon, and an insulating film having oxygen and silicon.

3. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a fourth transistor having an oxide semiconductor in its fourth channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. Either the source or drain of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the fourth transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region in contact with the side surface of the first conductive film, A second insulating film having a region in contact with the first insulating film, An oxide semiconductor film having a region positioned above the second insulating film, and comprising the second channel-forming region and the fourth channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, and having the function of a gate insulating film for the second transistor and the function of a gate insulating film for the fourth transistor, A second conductive film having a region positioned above the third insulating film and functioning as the gate of the second transistor, A third conductive film having a region positioned above the third insulating film and functioning as the gate of the fourth transistor, A fourth conductive film having a region in contact with the oxide semiconductor film, The fourth conductive film is always electrically connected to the other of the source or drain of the first transistor. The second channel-forming region does not have a region that overlaps with the first conductive film. The second channel formation region does not have a region that overlaps with the fifth conductive film which functions as the gate of the third transistor. The semiconductor device wherein the fourth channel formation region does not have a region that overlaps with the fifth conductive film.

4. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a fourth transistor having an oxide semiconductor in its fourth channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. Either the source or drain of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the fourth transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region in contact with the side surface of the first conductive film, A second insulating film having a region in contact with the first insulating film, An oxide semiconductor film having a region positioned above the second insulating film, and comprising the second channel-forming region and the fourth channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, and having the function of a gate insulating film for the second transistor and the function of a gate insulating film for the fourth transistor, A second conductive film having a region positioned above the third insulating film and functioning as the gate of the second transistor, A third conductive film having a region positioned above the third insulating film and functioning as the gate of the fourth transistor, A fourth conductive film having a region in contact with the oxide semiconductor film, The fourth conductive film is always electrically connected to the other of the source or drain of the first transistor. The second channel-forming region does not have a region that overlaps with the first conductive film. The second channel formation region does not have a region that overlaps with the fifth conductive film which functions as the gate of the third transistor. The fourth channel-forming region does not have a region that overlaps with the fifth conductive film. The semiconductor device has a laminated structure in which the second insulating film comprises an insulating film having nitrogen and silicon, and an insulating film having oxygen and silicon.

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