Insulated gate semiconductor device

Abstract

To provide an insulated gate semiconductor device that can suppress the decrease in breakdown resistance. [Solution] The device comprises a drift layer of a first conductivity type, a base region 5 of a second conductivity type provided on the upper side of the drift layer, a main electrode region 6 of the first conductivity type provided on the upper side of the base region, a plurality of trenches 8 that penetrate the main electrode region and the base region and are arranged with a first spacing in a plan view, a gate electrode 10 embedded inside the trench with a gate insulating film interposed therebetween and forming an inversion layer in a region away from the interface with the trench in the base region according to the applied voltage, an interlayer insulating film 11 that covers the gate electrode and has an opening 11a through which the main electrode region is exposed, and a contact electrode 12 embedded inside the opening, with its lower surface in contact with the main electrode region, and the width of its upper surface wider than the width of the main electrode region in the direction of the trench arrangement.

Description

[Technical Field]

[0001] This disclosure relates to an insulated gate type semiconductor device. [Background technology]

[0002] Non-patent document 1 and patent document 1 below describe a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) with a trench gate structure in which FinFET unit cells (functional units of the element) are arranged. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6631632 [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] However, in Non-Patent Document 1 and Patent Document 1 mentioned above, the fin width (the width between adjacent gate trenches) is narrow. Therefore, the breakdown withstand capability when a large current is passed through may be lower compared to a normal FET with a wider gate trench width.

[0006] The present disclosure has been made in view of such circumstances, and an object thereof is to provide an insulated gate semiconductor device capable of suppressing a decrease in breakdown voltage.

Means for Solving the Problems

[0007] In order to solve the above problems, an insulated gate semiconductor device according to an aspect of the present disclosure includes a drift layer of a first conductivity type, a base region of a second conductivity type provided on the upper surface side of the drift layer, a main electrode region of the first conductivity type provided on the upper surface side of the base region, a plurality of trenches penetrating through the main electrode region and the base region and arranged at a first interval in a plan view, a gate electrode embedded inside the trench with a gate insulating film interposed therebetween and forming an inversion layer in a region separated from the interface with the trench in the base region according to an applied voltage, an interlayer insulating film having an opening that covers the gate electrode and exposes the main electrode region, and a contact electrode embedded inside the opening, having a lower surface in contact with the main electrode region, and having a width of an upper surface wider than a width of the main electrode region in an arrangement direction of the trenches.

[0008] Further, the width of the upper surface of the contact electrode may be larger than the width of the lower surface of the contact electrode.

[0009] Further, when viewed in cross section, a side surface of the contact electrode may linearly connect the upper surface and the lower surface.

[0010] Further, when viewed in cross section, a side surface of the contact electrode may connect the upper surface and the lower surface in a curved shape that expands outward.

[0011] Further, the first interval may be 0.3 μm or less.

[0012] Further, the drift layer, the base region, and the main electrode region may be made of silicon carbide or silicon.

[0013] Note that the above summary of the disclosure does not enumerate all the necessary features of the present disclosure. Also, sub - combinations of these feature groups can also be disclosed.

Advantages of the Invention

[0014] According to the present disclosure, an insulated - gate semiconductor device capable of suppressing a decrease in breakdown voltage can be provided.

Brief Description of the Drawings

[0015] [Figure 1] It is a diagram for explaining the positional relationship in plan view of a gate electrode, a source region, and a base contact region included in the insulated - gate semiconductor device according to the first embodiment. [Figure 2] It is a longitudinal cross - sectional view showing a cross - sectional configuration when viewed in cross - section along the cutting line A - A of FIG. 1. [Figure 3] It is a longitudinal cross - sectional view showing an enlarged part of one unit cell of FIG. 2. [Figure 4] It is a diagram for explaining the positional relationship in plan view of a contact electrode and an inter - layer insulating film included in the insulated - gate semiconductor device according to the first embodiment. [Figure 5] It is a longitudinal cross - sectional view showing the cross - sectional configuration of the contact electrode 12 according to the first modification of the first embodiment.

Modes for Carrying Out the Invention

[0016] Hereinafter, the first embodiment of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of each layer, etc. may be different from the actual ones. Also, there may be parts where the dimensional relationships and ratios are different between the drawings. Further, the first embodiment shown below exemplifies an apparatus and a method for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the material, shape, structure, arrangement, etc. of the components as the following.

[0017] In this specification, the source region of a field-effect transistor (FET) is "one main electrode region (first main electrode region)" which can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main electrode region" can be selected as the cathode region. The drain region of an FET is "the other main electrode region (second main electrode region)" of the semiconductor device which can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main electrode region," it means either the first main electrode region or the second main electrode region which is reasonable according to the common technical knowledge of those skilled in the art.

[0018] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0019] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0020] [First Embodiment] <Structure of an insulated gate semiconductor device> Figures 1 to 4 are diagrams showing configuration examples of an insulated gate semiconductor device (MISFET) according to Embodiment 1 of the present disclosure. The insulated gate semiconductor device according to the first embodiment is a power device and includes a trench gate type FET as an active element. The semiconductor layer of the insulated gate semiconductor device according to the first embodiment may be made of, for example, silicon carbide (SiC), or may be made of, for example, silicon (Si). The fact that the semiconductor layer of the insulated gate semiconductor device is made of SiC or Si may mainly include being configured to include SiC or Si. In the present embodiment, the case where the semiconductor layer of the insulated gate semiconductor device is made of SiC will be described. Also, in the present embodiment, the case where the present technology is applied to a unit cell of a FinFET (fin FET) structure will be described. FIG. 2 illustrates unit cells (functional units of the element) C1, C2, and C3 of the FinFET structure. Each of the unit cells C1, C2, and C3 of the FinFET structure includes a fin portion 15. The number of unit cells is not limited to that in FIG. 2, and a large number are arranged periodically.

[0021] The insulated gate semiconductor device according to the first embodiment includes a drift layer 2 of the first conductivity type (n - -type). The drift layer 2 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to the withstand voltage specification and the like.

[0022] On the upper surface side of the drift layer 2, a current spreading layer (CSL) 3 of the first conductivity type (n-type) with a higher impurity concentration than the drift layer 2 is selectively provided. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The current spreading layer 3 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3The extent is as follows. Note that the current diffusion layer 3 is not necessarily required, and if the current diffusion layer 3 is not provided, the drift layer 2 may be extended to the region of the current diffusion layer 3.

[0023] A base region 5 of the second conductivity type (p-type) is provided on the upper side of the current diffusion layer 3. The lower surface of the base region 5 is in contact with the upper surface of the current diffusion layer 3. If the current diffusion layer 3 is not provided, the lower surface of the base region 5 is in contact with the upper surface of the drift layer 2. The base region 5 is composed of, for example, an epitaxial growth layer made of SiC. The base region 5 may also be a region in which p-type impurities are ion-implanted into the current diffusion layer 3. The impurity concentration of the base region 5 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 18 cm -3 It is approximately as follows.

[0024] On the upper surface of the base region 5, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + A first main electrode region (source region) 6 of type n is selectively provided. The source region 6 is, for example, a region made of SiC formed by ion implanting n-type impurities into the base region 5. The lower surface of the source region 6 is in contact with the upper surface of the base region 5. The impurity concentration of the source region 6 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 5 x 10 18 cm -3 It is approximately as follows.

[0025] Although not shown in Figure 2, the upper surface of base region 5 has a second conductivity type (p) with a higher impurity concentration than base region 5. + A base contact region 7 of type p is selectively provided. The base contact region 7 is, for example, a region made of SiC formed by ion implanting p-type impurities into the base region 5. The lower surface of the base contact region 7 is in contact with the upper surface of the base region 5. The impurity concentration of the base contact region 7 is, for example, 5 × 10⁻¹⁶. 19 cm -3 The above 5 x 10 20 cm -3 It is approximately as follows.

[0026] As shown in Figure 1, the base contact region 7 is provided in contact with the source region 6 along the Y direction. More specifically, the base contact region 7 and the source region 6 are provided alternately along the Y direction. The source region 6 and the base contact region 7 do not necessarily have to be in contact.

[0027] Multiple trenches 8 are provided that penetrate the base contact region 7, source region 6, and base region 5, extending from the upper surfaces of the base contact region 7 and source region 6 in the direction normal to the upper surfaces of the base contact region 7 and source region 6 (depth direction, Z direction). The trenches 8 have a striped planar pattern. For example, the trenches 8 are long in the Y direction in a plan view and are arranged with a gap (first interval) between them in the X direction. The width w2 of the trenches 8 in the arrangement direction (short side direction) is, for example, about 0.3 μm or more and 1.0 μm or less. As shown in Figure 2, the left and right sides of the trenches 8 are in contact with the source region 6, base region 5, and current diffusion layer 3, and the bottom surface of the trenches 8 reaches the current diffusion layer 3. If the current diffusion layer 3 is not provided, the left and right sides of the trenches 8 are in contact with the drift layer 2 instead of the current diffusion layer 3, and the bottom surface of the trenches 8 reaches the drift layer 2. The depth of the trenches 8 is, for example, about 1 μm. The semiconductor regions located between adjacent trenches 8 constitute the fin region 15. The fin region 15 may be, for example, a long stripe in the depth direction and the front direction of the paper in Figure 2. Between adjacent trenches 8 are the base contact region 7, the source region 6, the base region 5, and the current diffusion layer 3. If the current diffusion layer 3 is not provided, the drift layer 2 is located between adjacent trenches 8. The trenches 8 may have a dot-like planar pattern instead of a stripe pattern.

[0028] A gate insulating film 9 is provided along the inner surface of the trench 8, more specifically along the bottom surface and both sides of the trench 8. A gate electrode 10 is embedded inside the trench 8 with the gate insulating film 9 interposed therebetween. The gate insulating film 9 and the gate electrode 10 constitute a trench gate type insulated gate electrode structure (9,10). In the drawing, the upper surface of the gate electrode 10 is at the same depth as the upper surface of the source region 6, but the upper surface of the gate electrode 10 may be slightly recessed and located deeper than the upper surface of the source region 6.

[0029] As the gate insulating film 9, in addition to silicon oxide film (SiO2 film), any single layer film of silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these, can be used. As the material for the gate electrode 10, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used. The thickness of the gate insulating film 9 is, for example, about 30 nm or more and 100 nm or less.

[0030] Inside the current diffusion layer 3, and at the bottom of the trench 8, there is a second conductive type (p + A gate bottom protection region 4 of type (type) is provided. The upper surface of the gate bottom protection region 4 is in contact with the lower surface of the trench 8. The impurity concentration of the gate bottom protection region 4 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 It is approximately as follows.

[0031] The configurations of unit cells C1, C2, and C3 shown in Figure 2 are similar. Therefore, using unit cell C2 as an example, the configuration of the unit cells of the FinFET structure will be further explained with reference to Figure 3. The trench 8, gate insulating film 9, and gate electrode 10 located on the left side of the Fin portion 15 of unit cell C2 are sometimes referred to as trench 8L, gate insulating film 9L, and gate electrode 10L. The trench 8, gate insulating film 9, and gate electrode 10 located on the right side of the Fin portion 15 of unit cell C2 are sometimes referred to as trench 8R, gate insulating film 9R, and gate electrode 10R.

[0032] The width w1 of the fin portion 15 is the distance between trenches 8L and 8R, i.e., the first spacing. The width w1 of the fin portion 15 is also the width of the base region 5, source region 6, and current diffusion layer 3 located between trenches 8L and 8R. The width w1 of the fin portion 15 is, for example, about 0.3 μm or less. More preferably, the width w1 of the fin portion 15 is, for example, about 0.2 μm or less. This small width w1 is one of the characteristics of a FinFET.

[0033] The following describes the operation of a conventional FET with a sufficiently large width w1 and the FinFET shown in Figure 3. First, a gate voltage above a threshold is applied to the gate electrodes 10L and 10R. In a conventional FET, when a gate voltage above a threshold is applied to the gate electrode 10, an inversion layer CH is formed along the interface between the base region 5 and the gate insulating film 9. In contrast, in the FinFET shown in Figure 3, because the width w1 of the Fin portion 15 is sufficiently narrow, the voltage from both the gate electrodes 10L and 10R is applied to the entire base region 5. As a result, an inversion layer CH is formed in the base region 5 in a region (bulk region) away from the interface between the base region 5 and the gate insulating films 9L and 9R. For example, the inversion layer CH is formed at a position approximately 0.05 μm to 0.1 μm away from the interface. Alternatively, for example, the inversion layer CH is formed in the center of the base region 5 in the left-right direction of the paper. Therefore, compared to a conventional FET, in a FinFET, electrons moving within the inversion layer CH are less affected by the interface state density between the gate insulating films 9L and 9R and the base region 5. This allows for increased electron mobility and suppression of conduction resistance (ON resistance). SiC is a compound, and the density of interface states beneath the oxide film is about an order of magnitude higher than that of Si. Therefore, gate-type semiconductor devices constructed using SiC are more susceptible to the influence of interface state density on electron mobility than gate-type semiconductor devices constructed using Si. For this reason, applying a FinFET structure to gate-type semiconductor devices constructed using SiC is a countermeasure against the interface state density.

[0034] An interlayer insulating film 11 is provided on the upper surface of the gate electrode 10. The interlayer insulating film 11 covers the gate electrode 10. The interlayer insulating film 11 is composed of single-layer films such as silicon oxide films doped with boron (B) and phosphorus (P) (BPSG films), silicon oxide films doped with phosphorus (P) (PSG films), undoped silicon oxide films that do not contain phosphorus (P) or boron (B) and are called "NSG", silicon oxide films doped with boron (B) (BSG films), and silicon nitride films (Si3N4 films), or laminates thereof. The thickness of the interlayer insulating film 11 is, for example, about 1 μm or more and 1.5 μm or less. The interlayer insulating film 11 is provided with openings 11a so as to expose the upper surfaces of the source region 6 and the base contact region 7. The openings 11a have a tapered (approximately trapezoidal) cross-sectional shape that widens from the bottom (SiC side) to the top. Furthermore, the opening 11a has a planar pattern that extends in a stripe-like manner in the depth direction and the front direction of the paper in Figure 2. Although the surface of the interlayer insulating film is not shown, it is preferable to cover it with a barrier metal film such as titanium or titanium nitride.

[0035] A contact electrode 12 is embedded inside the opening 11a. The thickness of the contact electrode 12 is, for example, about 1 μm or more and 1.5 μm or less. The thickness of the contact electrode 12 is, for example, about the same as the interlayer insulating film 11. The lower surface of the contact electrode 12 is in contact with the upper surfaces of the source region 6 and the base contact region 7. The contact electrode 12 has a lower layer 12a that is in direct contact with the upper surfaces of the source region 6 and the base contact region 7, and an upper layer 12b that is in contact with the upper surface of the lower layer. The lower layer 12a is a known ohmic metal layer, for example, made of nickel (Ni) or nickel containing silicide. The lower layer 12a may be a single layer or a multilayer film of multiple types of metals. The lower layer 12a makes ohmic contact with the source region 6 and the base contact region 7 with low resistance. The upper layer 12b is made of a conductor such as metal, for example, made of tungsten (W).

[0036] As shown in Figure 3, in a cross-sectional view, the width of the contact electrode 12 is wider than the width of the fin portion 15. More specifically, the width of the upper surface of the contact electrode 12 is wider than the width of the fin portion 15. The contact electrode 12 has a tapered (approximately trapezoidal) cross-sectional shape, with the width increasing from the bottom (SiC side) to the top. In a cross-sectional view, the side surface of the contact electrode 12 connects the upper and lower surfaces of the contact electrode 12 in a straight line.

[0037] As shown in Figure 4, the contact electrode 12 has a striped planar pattern. More specifically, the contact electrode 12 is elongated along the Y direction in a plan view and arranged in a row with spacing between them along the X direction. As shown in Figure 4, the width of the upper surface of the contact electrode 12 is width w3, and the width of the lower surface is width w4. The width w3 of the upper surface is set to be larger than the width w4 of the lower surface (w3>w4). The width w4 of the lower surface is set to be the same width as the width w1 of the Fin portion 15 in order to connect to the Fin portion 15. The width w3 of the upper surface is, for example, about 1.1 times or more the width w4 of the lower surface (w3≧1.1×w4). Alternatively, for example, the width w3 of the upper surface may be about 1.5 times or more the width w4 of the lower surface (w3≧1.5×w4), or about 2 times or more (w3≧2×w4). By setting the widths w3 and w4 to these sizes, the thickness of the wiring can be increased while still connecting the lower surface of the contact electrode 12 to the source region 6.

[0038] Furthermore, the width w3 of the upper surface of the contact electrode 12 is less than half the pitch w5 of the unit cell C2 (w3 < 0.5 × w5). By setting the width w3 to such dimensions, the interlayer insulating film 11 is exposed between the contact electrodes 12. The pitch w5 of the unit cell C2 is the sum of the width w1 of the fin portion 15 and the width w2 of the trench 8 (w5 = w1 + w2).

[0039] A first main electrode (source electrode) 13 is provided so as to cover the interlayer insulating film 11 and the upper surface of the contact electrode 12. The source electrode 13 is in contact with the contact electrode 12 and is electrically connected to it. The source electrode 13 is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-silicon-copper (Al-Si-Cu), or aluminum-copper (Al-Cu). Since the interlayer insulating film 11 is exposed between the contact electrodes 12, the adhesion between the source electrode 13 and the substrate can be improved.

[0040] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + A second main electrode region (drain region) 1 of type 4H-SiC is provided. The drain region 1 is made of a semiconductor substrate (SiC substrate) made of, for example, 4H-SiC. The impurity concentration of the drain region 1 is, for example, 1 × 10⁻⁶ 19 cm -3 The above is 3 x 10 20 cm -3 The following is an example: The thickness of the drain region 1 is, for example, 30 μm or more and 500 μm or less. A dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0041] A second main electrode (drain electrode) 14 is provided on the lower side of the drain region 1. For the drain electrode 14, a single layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Furthermore, nickel silicide (NiSi) is provided between the drain region 1 and the drain electrode 14 for ohmic contact. x A drain contact layer such as a film may be provided. In this specification, when the term "main electrode" is used, it means either the first main electrode or the second main electrode, which is appropriate according to the common technical knowledge of those skilled in the art.

[0042] During operation of the insulated gate semiconductor device according to the first embodiment, the source electrode 13 is set to ground potential, and a positive voltage is applied to the drain electrode 14. When a positive voltage above a threshold is applied to the gate electrode 10 in this state, an inversion layer (channel) CH is formed in the base region 5, away from the interface between the base region 5 and the trench 8, as shown in Figure 3, and the device enters an ON state. In the ON state, current flows from the drain electrode 14 to the source electrode 13 via the drain region 1, drift layer 2, current diffusion layer 3, the inversion layer CH in the base region 5, the source region 6, and the contact electrode 12. On the other hand, when the voltage applied to the gate electrode 10 is below the threshold, the inversion layer CH is not formed in the base region 5, resulting in an OFF state, and no current flows from the drain electrode 14 to the source electrode 13.

[0043] <Main effects of the first embodiment> In the insulated gate semiconductor device according to the first embodiment, the width of the contact electrode 12 is made larger than the width of the source region 6. By increasing the thickness of the contact electrode 12 as wiring, the electrical resistance when current flows through the fin portion 15 and the contact electrode 12 can be suppressed. Therefore, even when a large current flows through the fin portion 15 and the contact electrode 12, the electrical resistance is suppressed, so electric field concentration can be suppressed, and malfunction of parasitic transistors can be suppressed. As a result, the breakdown withstand capability (SW withstand capability, short circuit withstand capability) when a large current flows can be improved.

[0044] Furthermore, according to the insulated gate type semiconductor device of the first embodiment, the width of the upper surface of the contact electrode 12 is made larger than the width of the source region 6. This makes it possible to increase the thickness of the contact electrode 12 as wiring without being constrained by the width of the source region 6.

[0045] Furthermore, according to the insulated gate type semiconductor device of the first embodiment, the width of the upper surface of the contact electrode 12 is made larger than the width of the source region 6. Therefore, by widening the upper surface while connecting the contact electrode 12 to the narrow Fin portion 15, the thickness of the wiring of the contact electrode 12 can be increased.

[0046] <Modification 1 of the first embodiment> In the insulated gate type semiconductor device according to Modification 1 of the first embodiment of this technology, as shown in Figure 5, when viewed in cross-section, the side surface of the contact electrode 12 connects the upper and lower surfaces in a curved shape that widens outward. According to this modification, the thickness of the contact electrode 12 can be increased.

[0047] [Other embodiments] As described above, a first embodiment of this disclosure has been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0048] For example, although an FET was given as an example of a semiconductor device according to the first embodiment, n + Instead of drain region 1 of type p + This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0049] For example, the trench 8 according to the first embodiment had a striped planar pattern, but it may also have a dotted planar pattern.

[0050] Furthermore, the configurations disclosed in the first embodiment can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of Symbols]

[0051] 1…Drain region (SiC substrate) 2…Drift layer 3…Current diffusion layer 4…Gate bottom protection area 5…Base area 6…Source region (first main electrode region) 7…Base contact area 8, 8L, 8R... Trench 9, 9L, 9R… Gate Insulator 10, 10L, 10R… Gate stop 11…Interlayer insulating film 11a...Opening 12… Contact electrodes 12a…lower layer 12b…upper layer 13…Source electrode (first main electrode) 14…Second main electrode (drain electrode) 15...Fin part C1, C2, C3... Unit cells CH... Inversion layer (channel) w1…Width (1st interval) w2, w3, w4... width w5... pitch

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