Insulated gate semiconductor device

Abstract

The present invention provides an insulated gate type semiconductor device that can mitigate the electric field at the termination point and improve voltage resistance. [Solution] The insulated gate semiconductor device comprises a first conductivity type drift layer 2 extending from an active portion 101 containing an active element to a terminal portion 102 surrounding the active portion 101, and a plurality of first conductivity type fin portions 22a to 22f provided spaced apart from each other on the upper surface side of the drift layer 2 of the terminal portion 102 so as to surround the active portion 101.

Description

[Technical Field]

[0001] This disclosure relates to an insulated gate type semiconductor device. [Background technology]

[0002] Patent Document 1 and Non-Patent Document 1 disclose a vertical SiC-MOSFET with a trench gate structure in which unit cells of a finFET structure are arranged. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6631632 specification [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 [Overview of the project] [Problems that the invention aims to solve]

[0005] In the termination section of semiconductor devices as described in Patent Document 1 and Non-Patent Document 1, there is room for improvement in the configuration for mitigating the electric field and improving the breakdown voltage.

[0006] The present disclosure aims to provide an insulated gate semiconductor device that can mitigate the electric field at the termination and improve withstand voltage. [Means for solving the problem]

[0007] To achieve the above object, one aspect of the present disclosure is summarized as an insulated gate semiconductor device including a drift layer of a first conductivity type provided from an active portion including an active element across a terminal portion surrounding the active portion, and a plurality of fin portions of the first conductivity type provided separately from each other on the upper surface side of the drift layer of the terminal portion so as to surround the active portion.

[0008] Further, the active element includes a base region of a second conductivity type provided on the upper surface side of the drift layer, a main region of the first conductivity type provided on the upper surface side of the base region, and a gate electrode embedded via a gate insulating film in a pair of first trenches sandwiching the side surfaces of the base region and the main region. An inversion layer may be formed in a region away from the interface between the base region and the gate insulating film.

[0009] Also, the width of the base region may be 0.2 μm or less.

[0010] Also, the width of the fin portion may be wider toward the outside of the terminal portion.

[0011] Also, the width of the fin portion may be constant from the inside to the outside of the terminal portion.

[0012] Also, the width of the innermost fin portion of the terminal portion may be 0.2 μm or less.

[0013] Also, a second trench may be provided between adjacent fin portions.

[0014] Also, the depth of the second trench may be the same as the depth of the first trench.

[0015] Also, a guard ring layer of the second conductivity type provided directly below the second trench on the upper surface side of the drift layer may be provided.

[0016] Also, the guard ring layer may be in contact with the lower surface of the second trench.

[0017] Also, the guard ring layer may be separated from the lower surface of the second trench.

[0018] Furthermore, a gate insulating film may be provided on the side surface of the second trench.

[0019] Furthermore, a polysilicon layer may be provided on the side surface of the second trench via a gate insulating film.

[0020] Furthermore, a polysilicon layer may be provided on the side of the second trench.

[0021] Furthermore, a field plate may be provided on the upper surface of the fin portion via an insulating film.

[0022] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Effects of the Invention]

[0023] According to this disclosure, it is possible to provide an insulated gate type semiconductor device that can mitigate the electric field at the termination and improve the breakdown voltage. [Brief explanation of the drawing]

[0024] [Figure 1] This is a plan view of an insulated gate type semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view of an insulated gate type semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view along line AA in Figure 2. [Figure 4] This is a cross-sectional view along line BB in Figure 3. [Figure 5] This is a cross-sectional view of an insulated gate type semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view of an insulated gate type semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view of an insulated gate type semiconductor device according to the second embodiment. [Figure 8]This is a cross-sectional view of an insulated gate type semiconductor device according to the third embodiment. [Figure 9] This is a cross-sectional view of an insulated gate type semiconductor device according to the fourth embodiment. [Figure 10] This is a cross-sectional view of an insulated gate type semiconductor device according to the fifth embodiment. [Figure 11] This is a cross-sectional view of an insulated gate type semiconductor device according to the sixth embodiment. [Figure 12] This is a cross-sectional view of an insulated gate type semiconductor device according to the seventh embodiment. [Figure 13] This is a cross-sectional view of an insulated gate type semiconductor device according to the eighth embodiment. [Figure 14] This is a cross-sectional view of an insulated gate type semiconductor device according to the ninth embodiment. [Modes for carrying out the invention]

[0025] The first to ninth embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first to ninth embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0026] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region that is reasonable according to the common technical knowledge of those skilled in the art.

[0027] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0028] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0029] Furthermore, in the following explanation, "approximately identical" or "approximately the same" for impurity concentration, width, depth, or thickness means not only that they are exactly identical, but also that they include a range that includes tolerances due to process variations. The range that includes tolerances is, for example, ±10%.

[0030] (First Embodiment) The insulated gate semiconductor device according to the first embodiment includes a semiconductor chip 100, as shown in Figure 1. In the first embodiment, the case in which the semiconductor chip 100 is made of silicon carbide (SiC) is illustrated. The semiconductor chip 100 has a substantially rectangular planar shape. The semiconductor chip 100 includes an active portion 101 and a termination portion (voltage-resistant structure portion) 102 provided around the active portion 101.

[0031] The active section 101 is located approximately in the center of the semiconductor chip 100 and has a roughly rectangular planar shape. The active section 101 includes an active element, which is a power switching element, and is the region through which the main current (drift current) flows when the active element is turned on.

[0032] The termination portion 102 has an annular (frame-shaped) planar shape that surrounds the active portion 101. The termination portion 102 is a region that relaxes the electric field on the upper surface side of the semiconductor chip 100 and maintains the breakdown voltage. Breakdown voltage is the upper limit voltage at which the insulated gate type semiconductor device according to the first embodiment does not malfunction or break down at the operating voltage.

[0033] Figure 2 shows a vertical cross-section of the active section 101 shown in Figure 1. As shown in Figure 2, the insulated gate type semiconductor device according to the first embodiment is exemplified when the active element of the active section 101 is a trench gate vertical MOSFET (SiC-MOSFET). The insulated gate type semiconductor device according to the first embodiment includes unit cells C1 to C3, which are functional units of the active element. The unit cells C1 to C3 are arranged in the left-right direction in Figure 2. Although three unit cells C1 to C3 are shown in Figure 2, a multi-channel structure in which many more cells are similarly arranged may be configured.

[0034] In the insulated gate type semiconductor device according to the first embodiment, the active part 101 has a first conductivity type (n - The device includes a drift layer 2, which is a semiconductor region of type (X). The drift layer 2 is composed of, for example, an epitaxial growth layer made of silicon carbide (SiC). The impurity concentration and thickness of the drift layer 2 can be adjusted as appropriate according to the withstand voltage specifications, etc. The impurity concentration of the drift layer 2 is, for example, 1 × 10⁻⁶. 15 cm -3Above, 5×10 16 cm -3 or less.

[0035] On the upper surface side of the drift layer 2, a current diffusion layer (CSL) 3, which is a semiconductor region of the first conductivity type (n-type) with a higher impurity concentration than the drift layer 2, is provided. The current diffusion layer 3 is composed of, for example, an epitaxial growth layer made of silicon carbide (SiC). The impurity concentration of the current diffusion layer 3 is, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3 or less. Note that the current diffusion layer 3 does not necessarily have to be provided.

[0036] In each of the unit cells C1 to C3, on the upper surface side of the current diffusion layer 3, a base region 5, which is a semiconductor region of the second conductivity type (p-type), is provided. The base region 5 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the base region 5 is, for example, 1×10 17 cm -3 or more and 1×10 18 cm -3 or less. Note that when the current diffusion layer 3 is not provided, the lower surface of the base region 5 may contact the upper surface of the drift layer 2.

[0037] In each of the unit cells C1 to C3, on the upper surface side of the base region 5, a first main region (source region) 6, which is a semiconductor region of the first conductivity type (n + type), is provided. The source region 6 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the source region 6 is, for example, 1×10 17 cm -3 or more and 5×10 18 cm -3 or less.

[0038] In the direction normal to the upper surface of the source region 6 (depth direction), a trench (hereinafter also referred to as the "active side trench") 8 is provided, which is excavated downward from the upper surface of the source region 6 and penetrates the source region 6 and the base region 5. The lower surface of the active side trench 8 reaches the current diffusion layer 3. The sides of the active side trench 8 are in contact with the source region 6, the base region 5 and the current diffusion layer 3. If the current diffusion layer 3 is not provided, the lower surface of the active side trench 8 reaches the drift layer 2, and the sides of the active side trench 8 are in contact with the source region 6, the base region 5 and the drift layer 2.

[0039] The width w2 of the active trench 8 is, for example, approximately 0.3 μm or more and 1.0 μm or less. The depth d1 of the active trench 8 is, for example, approximately 0.7 μm or more and 1.3 μm or less, and may be, for example, approximately 1 μm. Figure 2 illustrates the case where the side surface of the active trench 8 is a vertical plane, but the side surface of the active trench 8 may have a trapezoidal or inverted trapezoidal tapered cross-section, or it may be a curved surface that is convex outward. Also, Figure 2 illustrates the case where the bottom surface of the active trench 8 is a plane, but the bottom surface of the active trench 8 may be a curved surface that is convex downward. Furthermore, the corner formed by the bottom surface and the side surface of the active trench 8 may have curvature.

[0040] Each of the unit cells C1 to C3 has a mesa portion, which is a semiconductor region sandwiched between adjacent active trenches 8, as an active fin portion 15. The active fin portion 15 includes the source region 6, the base region 5, and the portion sandwiched between adjacent active trenches 8 of the current diffusion layer 3. If the current diffusion layer 3 is not provided, the active fin portion 15 includes the source region 6, the base region 5, and the portion sandwiched between adjacent active trenches 8 of the drift layer 2.

[0041] The width w1 of the active fin portion 15 corresponds to the width of the portion sandwiched between the source region 6, the base region 5, and the adjacent active trenches 8 of the current diffusion layer 3. The width w1 of the active fin portion 15 is narrower than the width w2 of the active trench 8. The width w1 of the active fin portion 15 is, for example, about 500 nm or more and 0.2 μm or less. The width w1 of the active fin portion 15 may be about 0.1 μm or more and 0.2 μm or less, or about 500 nm or more and 0.1 μm or less. By setting the width w1 of the active fin portion 15 to about 0.2 μm or less, the FinFET structure described later can be realized.

[0042] Figure 3 shows a horizontal cross-section viewed from the top side along line AA in Figure 2. The vertical cross-section viewed from the bottom to the top of Figure 3 along line AA in Figure 3 corresponds to Figure 2. As shown in Figure 3, the active trench 8, gate insulating film 9, and gate electrode 10 each have a planar pattern that extends linearly (striped) in one direction (up and down in Figure 3) parallel to each other. Between the active trenches 8, in one direction (up and down in Figure 3), there is a source region 6 and a second conductivity type (p + The source region 6 and the base contact region 7, which are semiconductor regions of type (type), are arranged alternately and periodically. The source region 6 and the base contact region 7 are in contact with each other.

[0043] Figure 4 shows a vertical cross-section of Figure 3, viewed from the bottom to the top along the BB line in Figure 3. As shown in Figure 4, in each of the unit cells C1 to C3, the base contact region 7 is located on the upper side of the base region 5. The depth of the base contact region 7 may be the same as the depth of the source region 6 shown in Figure 2, or it may be deeper or shallower than the depth of the source region 6. The lower surface of the base contact region 7 is in contact with the upper surface of the base region 5. The side surface of the base contact region 7 is in contact with the active side trench 8. The base contact region 7 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the base contact region 7 is higher than the impurity concentration of the base region 5. The impurity concentration of the base contact region 7 is, for example, 5 × 10⁻⁶ 19 cm -3 The above 5 x 1020 cm -3 The extent is as follows: In the cross-section shown in Figure 4, the active fin portion 15 includes the portion sandwiched between the base contact region 7, the base region 5, and the adjacent active trenches 8 of the current diffusion layer 3.

[0044] A gate insulating film 9 is provided along the lower and side surfaces of the active trench 8. A gate electrode 10 is embedded inside the active trench 8 via the gate insulating film 9. The gate insulating film 9 and the gate electrode 10 constitute a trench gate type insulated gate electrode structure (9,10).

[0045] The thickness of the gate insulating film 9 is, for example, approximately 30 nm or more and 100 nm or less. As the gate insulating film 9, a single layer film of any one of the following can be used: silicon oxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these. As the material for the gate electrode 10, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities added, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0046] An insulating film 11, which is an interlayer insulating film, is provided on the upper surface of the gate electrode 10. As the insulating film 11, for example, a single layer of a silicon oxide film (SiO2 film) free of impurities, referred to as an "NSG film," a silicon oxide film with phosphorus added (PSG film), a silicon oxide film with boron added (BSG film), a silicon oxide film with phosphorus and boron added (BPSG film), or a silicon nitride film (Si3N4 film) can be used, or a composite film made by selecting and combining several of these.

[0047] As shown in Figures 2 and 4, the insulating film 11 is provided with an opening (contact hole) 11a that exposes at least a portion of the upper surface of the source region 6 and the base contact region 7. A contact electrode 12 is embedded inside the contact hole 11a. The contact electrode 12 makes low-resistance ohmic contact with the source region 6 and the base contact region 7.

[0048] The contact electrode 12 has a barrier metal layer 12a that is in direct contact with the upper surfaces of the source region 6 and the base contact region 7, and a plug layer 12b whose lower surface is in contact with the upper surface of the barrier metal layer 12a. The barrier metal layer 12a is made of a metal such as titanium nitride (TiN), titanium (Ti), or a TiN / Ti laminated structure with Ti as the lower layer. The barrier metal layer 12a may cover the insulating film 11. Between the source region 6 and the base contact region 7 and the barrier metal layer 12a, nickel silicide (NiSi) is used for ohmic contact. x A silicide layer consisting of the following may be provided. The plug layer 12b is made of a metal such as tungsten (W).

[0049] A first main electrode (source electrode) 13 is provided so as to cover the upper surface of the insulating film 11 and the contact electrode 12. The source electrode 13 is provided separately from the gate wiring layer (not shown) which is electrically connected to the gate electrode 10. The source electrode 13 is made of a metal such as aluminum (Al) or copper (Cu), or an alloy such as aluminum-silicon (Al-Si) or aluminum-copper (Al-Cu).

[0050] As shown in Figure 2, inside the current diffusion layer 3, there is a second conductivity type (p + A gate bottom protection region 4, which is a semiconductor region of type (type), is provided. The gate bottom protection region 4 has the function of mitigating the electric field applied to the gate insulating film 9 on the lower surface of the active trench 8. The impurity concentration of the gate bottom protection region 4 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3The extent is as follows: In Figure 2, the gate bottom protection area 4 may be electrically connected to the base area 5 on the front or back side.

[0051] Figure 2 illustrates a case where the gate bottom protection region 4 is in contact with the lower surface of the active trench 8, but the gate bottom protection region 4 may be separated from the lower surface of the active trench 8. Figure 2 illustrates a case where the width of the gate bottom protection region 4 is the same as the width w2 of the active trench 8, but the width of the gate bottom protection region 4 may be narrower or wider than the width w2 of the active trench 8. If the current diffusion layer 3 is not provided, the gate bottom protection region 4 may be provided inside the drift layer 2. The gate bottom protection region 4 is not necessarily provided.

[0052] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + A second main region (drain region) 1, which is a semiconductor region of type (type), is provided. Drain region 1 is made of a semiconductor substrate (SiC substrate), for example, SiC. The impurity concentration of drain region 1 is, for example, 1 × 10⁻⁶. 19 cm -3 The above is 3 x 10 20 cm -3 The extent is as follows. Furthermore, a buffer layer, dislocation conversion layer, or recombination promotion layer, etc., which is an n-type semiconductor region with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0053] A second main electrode (drain electrode) 14 is provided on the lower side of the drain region 1. For the drain electrode 14, a single layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Between the drain region 1 and the drain electrode 14, nickel silicide (NiSi) is provided for ohmic contact. x A silicide layer consisting of the following may be provided.

[0054] During the switching operation of the insulated gate semiconductor device according to the first embodiment, the source electrode 13 is set to ground potential, a positive voltage is applied to the drain electrode 14, and a positive voltage above a threshold is applied to the gate electrode 10. As a result, an inversion layer (channel) is formed in the base region 5 of each unit cell C1 to C3, and the vertical MOSFET turns on. In the ON state, current flows from the drain electrode 14 to the source electrode 13 via the drain region 1, drift layer 2, the inversion layer of the base region 5, and the source region 6. On the other hand, if the voltage applied to the gate electrode 10 is below the threshold, an inversion layer is not formed in the base region 5, the vertical MOSFET turns off, and no current flows from the drain electrode 14 to the source electrode 13.

[0055] In the insulated gate semiconductor device according to the first embodiment, the vertical MOSFET has a FinFET structure. A FinFET structure is a so-called double gate structure in which the width w1 of the active fin portion 15 sandwiched between adjacent active trenches 8 is narrowed by a predetermined width, and an inversion layer (channel) is formed in the base region 5 sandwiched between adjacent active trenches 8. In a FinFET, when a gate voltage of a threshold or higher is applied to the gate electrode 10, the voltage from both of the pair (two) gate electrodes 10 sandwiching the base region 5 is applied to the entire base region 5. Here, if the width w1 of the active fin portion 15 is 0.1 μm or more and 0.2 μm or less, as shown in Figure 5, in each of the unit cells C1 to C3, one inversion layer 5a is formed not near the interface between the base region 5 and the left and right gate insulating films 9, but in a region away from the interface between the base region 5 and the left and right gate insulating films 9 (bulk region). The inversion layer 5a is formed in a region that is, for example, 0.05 μm or more and 0.1 μm or less from the interface between the base region 5 and the left and right gate insulating films 9. The inversion layer 5a is formed in the horizontal central part of the base region 5.

[0056] Therefore, in the insulated gate semiconductor device according to the first embodiment, compared to the case where an inversion layer is formed near the interface between the base region 5 and the gate insulating film 9, electrons moving within the inversion layer 5a are less affected by the interface state density at the interface between the gate insulating film 9 and the base region 5. This allows for higher electron mobility and suppression of on-resistance.

[0057] In particular, SiC is a compound, and its interface state density is about an order of magnitude higher than that of Si. Therefore, the electron mobility of insulated gate semiconductor devices using SiC is more susceptible to the influence of the interface state density than that of insulated gate semiconductor devices using Si. For this reason, a FinFET structure in which the width w1 of the active side fin portion 15 is 0.1 μm or more and 0.2 μm or less is particularly effective for insulated gate semiconductor devices using SiC.

[0058] Figure 6 shows cross-sections of the active portion 101 and the termination portion 102. The cross-section of the termination portion 102 extends from the inside, which is the active portion 101 side, to the outside, which is the end of the semiconductor chip 100. The left side of Figure 6 is the inside of the termination portion 102, and the right side of Figure 6 is the outside of the termination portion 102. As shown in Figure 6, the insulated gate type semiconductor device according to the first embodiment has a first conductivity type (n) at the termination portion 102. - It includes a drift layer 2 of type (n). On the lower side of the drift layer 2, there is a first conductive type (n + A drain region 1 of type (type) is provided. A drain electrode 14 is provided on the lower surface side of the drain region 1. The drift layer 2, the drain region 1, and the drain electrode 14 are each provided continuously from the active portion 101 to the terminal portion 102.

[0059] In the insulated gate semiconductor device according to the first embodiment, the FinFET structure applied to the active portion 101 is also applied to the termination portion 102. That is, in the termination portion 102, the upper surface side of the drift layer 2 has a first conductivity type (n -Fin portions (hereinafter also referred to as "terminal fin portions") 22a to 22f, which are semiconductor regions of type 101, are provided. The terminal fin portions 22a to 22f have an annular (frame-shaped) planar pattern surrounding the active portion 101. Figure 6 shows six terminal fin portions 22a to 22f as an example, but the number of terminal fin portions 22a to 22f is not particularly limited. There may be five or fewer fin portions similar to the terminal fin portions 22a to 22f in total, or there may be seven or more.

[0060] The terminal fin portions 22a to 22f are spaced apart from each other and arranged concentrically. The widths w11 to w16 of the terminal fin portions 22a to 22f increase from the inside to the outside of the terminal portion 102. The widths w11 to w16 of the terminal fin portions 22a to 22f may increase by a constant value, such as 0.2 μm, from the inside to the outside of the terminal portion 102. The width w11 of the innermost terminal fin portion 22a may be approximately the same as the width w1 of the active fin portion 15, or it may be narrower or wider than the width w1 of the active fin portion 15. The width w11 of the innermost terminal fin portion 22a is, for example, about 0.1 μm or more and 0.2 μm or less. The width w16 of the outermost terminal fin portion 22f is, for example, about 0.8 μm or more and 1.2 μm or less. The widths w11 to w16 of the terminal fin sections 22a to 22f may be constant, or they may become narrower from the inside to the outside of the terminal section 102.

[0061] The spacing s11 to s15 between the terminal fin sections 22a to 22f widens from the inside to the outside of the terminal section 102. The spacing s11 to s15 between the terminal fin sections 22a to 22f may be constant, or it may narrow from the inside to the outside of the terminal section 102.

[0062] The terminal fin portions 22a to 22f are composed of, for example, an epitaxially grown layer made of SiC. The terminal fin portions 22a to 22f may be integrally formed with the drift layer 2. The impurity concentration of the terminal fin portions 22a to 22f may be approximately the same as the impurity concentration of the drift layer 2. The terminal fin portions 22a to 22f can be formed by selectively removing a portion of the upper part of the drift layer 2 after epitaxial growth of the drift layer 2 using photolithography and dry etching techniques.

[0063] Trenches (hereinafter also referred to as "terminal trenches") 21a to 21f are provided between adjacent terminal fin sections 22a to 22f. The width of the terminal trenches 21a to 21f corresponds to the spacing s11 to s15 between the terminal fin sections 22a to 22f. The depth d2 of the terminal trenches 21a to 21f corresponds to the height of the terminal fin sections 22a to 22f. The depth d2 of the terminal trenches 21a to 21f is approximately the same as the depth d1 of the active trench 8 of the active section 101. The terminal trenches 21a to 21f can be formed simultaneously in the process of forming the active trench 8 of the active section 101.

[0064] On the upper surface of the drift layer 2, there are multiple second conductivity types (p + A guard ring layer 23a to 23f, which is a semiconductor region of type 101, is provided. The guard ring layers 23a to 23f have an annular (frame-shaped) planar pattern surrounding the active portion 101. The guard ring layers 23a to 23f are spaced apart from each other with the drift layer 2 in between, and are provided concentrically. Figure 6 shows six guard ring layers 23a to 23f as an example, but the number of guard ring layers 23a to 23f is not particularly limited. For example, there may be five or fewer guard ring layers similar to guard ring layers 23a to 23f in total, or there may be seven or more. The potential of the guard ring layers 23a to 23f may be a floating potential.

[0065] The widths w21 to w26 of the guard ring layers 23a to 23f widen as they move from the inside to the outside of the end portion 102. The widths w21 to w26 of the guard ring layers 23a to 23f may be constant, or they may narrow as they move from the inside to the outside of the end portion 102. The spacing s21 to s25 of the guard ring layers 23a to 23f widens as they move from the inside to the outside of the end portion 102. The spacing s21 to s25 of the guard ring layers 23a to 23f may be constant, or they may narrow as they move from the inside to the outside of the end portion 102.

[0066] For example, the guard ring layers 23a to 23f can be formed simultaneously with the base region 5 of the active portion 101 during the process of forming the base region 5. In this case, the impurity concentration of the guard ring layers 23a to 23f may be approximately the same as the impurity concentration of the base region 5 of the active portion 101. Alternatively, the guard ring layers 23a to 23f can be formed simultaneously with the gate bottom protection region 4 of the active portion 101 during the process of forming the gate bottom protection region 4. In this case, the impurity concentration of the guard ring layers 23a to 23f may be approximately the same as the impurity concentration of the gate bottom protection region 4 of the active portion 101.

[0067] The impurity concentrations in the guard ring layers 23a to 23f may be approximately the same. The impurity concentrations in the guard ring layers 23a to 23f may be different. For example, the impurity concentrations in the guard ring layers 23a to 23f may decrease from the inside to the outside of the terminal portion 102.

[0068] The guard ring layers 23a to 23f are located directly beneath the terminal trenches 21a to 21f. The upper surfaces of the guard ring layers 23a to 23f are in contact with the lower surfaces of the terminal trenches 21a to 21f. The terminal fin sections 22a to 22f are located on the upper surface of the drift layer 2 sandwiched between the guard ring layers 23a to 23f.

[0069] The depth from the top to the bottom of the guard ring layers 23a to 23f is approximately the same. However, the depths from the top to the bottom of the guard ring layers 23a to 23f may differ. For example, the depth from the top to the bottom of the guard ring layers 23a to 23f may be shallower from the inside to the outside of the end portion 102.

[0070] Although not shown in Figure 6, at the outer end of the terminal portion 102, the first conductive type (n + The channel stopper, which is a semiconductor region of type (p), may be provided with an annular (frame-shaped) planar pattern. + It may also be a semiconductor region of type (type).

[0071] At the terminal portion 102, an insulating film 11 is provided so as to cover the upper surfaces of the guard ring layers 23a to 23f and the side and upper surfaces of the terminal fin portions 22a to 22f. Below the insulating film 11 at the terminal portion 102, a field insulating film (not shown), such as a local oxide film (LOCOS film), or a gate insulating film (not shown) may be provided.

[0072] According to the insulated gate semiconductor device of the first embodiment, in the active portion 101, the active element has a FinFET structure, so that an inversion layer 5a is formed in a region away from the interface between the base region 5 and the gate insulating film 9. As a result, the electron mobility is increased and the on-resistance can be reduced compared to the case in which the inversion layer is formed near the interface between the base region 5 and the gate insulating film 9.

[0073] Furthermore, according to the insulated gate semiconductor device of the first embodiment, the FinFET structure applied in the active section 101 is also applied to the termination section 102, by providing termination fins 22a to 22f on the upper surface side of the drift layer 2 in the termination section 102. As a result, the electric field can be mitigated and the breakdown voltage can be improved compared to the case where no termination fins are provided on the upper surface side of the drift layer 2. Therefore, the width from the inside to the outside of the termination section 102 can be shortened.

[0074] Furthermore, since the terminal fin portions 22a to 22f can be formed simultaneously in the same process as the active fin portion 15, the increase in man-hours can be suppressed, resulting in superior cost-effectiveness.

[0075] Furthermore, by providing guard ring layers 23a to 23f directly below the terminal trenches 21a to 21f, the electric field can be further mitigated, and stable voltage resistance can be ensured.

[0076] (Second Embodiment) The insulated gate semiconductor device according to the second embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 7, at the termination portion 102, the p-type guard ring layers 23a to 23f are not in contact with the lower surface of the termination trenches 21a to 21f, but are separated from the lower surface of the termination trenches 21a to 21f via a portion of the drift layer 2.

[0077] The distance d3 between the upper surfaces of the guard ring layers 23a to 23f and the lower surfaces of the terminal trenches 21a to 21f can be set as appropriate. The other configurations of the insulated gate type semiconductor device according to the second embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0078] According to the insulated gate semiconductor device of the second embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fins 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the breakdown voltage can be improved.

[0079] (Third embodiment) The insulated gate semiconductor device according to the third embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 8, the widths w11 to w16 of the terminal side fin portions 22a to 22f are constant at the terminal portion 102.

[0080] The spacing s11 to s15 between the terminal fin portions 22a to 22f may be constant, for example. The widths w21 to w26 between the guard ring layers 23a to 23f may be constant, for example. The spacing s21 to s25 between the guard ring layers 23a to 23f may be constant, for example. The other configurations of the insulated gate type semiconductor device according to the third embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0081] According to the insulated gate semiconductor device of the third embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the breakdown voltage can be improved.

[0082] (Fourth Embodiment) The insulated gate semiconductor device according to the fourth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 9, the gate insulating film 9 is provided on the side surfaces of the terminal trenches 21a to 21f at the terminal portion 102. The gate insulating film 9 is provided only on the side surfaces of the terminal trenches 21a to 21f and not on the lower surfaces of the terminal trenches 21a to 21f. The side surfaces of the terminal fin portions 22a to 22f are in contact with the gate insulating film 9. The gate insulating film 9 of the terminal portion 102 can be formed simultaneously with the gate insulating film 9 of the active portion 101.

[0083] Figure 9 illustrates a case where the gate insulating film 9 is provided on the sides of all terminal trenches 21a to 21f, but the gate insulating film 9 may also be provided only on the sides of a portion of the inner part of the terminal trenches 21a to 21f (for example, terminal trenches 21a and 21b). The other configurations of the insulated gate semiconductor device according to the fourth embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0084] According to the insulated gate semiconductor device of the fourth embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the breakdown voltage can be improved. Furthermore, by providing gate insulating film 9 on the side surfaces of the terminal trenches 21a to 21f, pattern deformation of the terminal fin portions 22a to 22f can be prevented.

[0085] (Fifth embodiment) The insulated gate semiconductor device according to the fifth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 10, a gate insulating film 9 is provided on the side and bottom surfaces of the terminal trenches 21a to 21f at the terminal portion 102. The gate insulating film 9 of the terminal portion 102 can be formed simultaneously with the gate insulating film 9 of the active portion 101. The side surfaces of the terminal fin portions 22a to 22f are in contact with the gate insulating film 9.

[0086] Figure 10 illustrates a case where the gate insulating film 9 is provided on the sides and bottom surfaces of all terminal trenches 21a to 21f. However, the gate insulating film 9 may be provided only on the sides and bottom surfaces of a portion of the inner part of the terminal trenches 21a to 21f (for example, terminal trenches 21a and 21b). The other configurations of the insulated gate semiconductor device according to the fifth embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0087] According to the insulated gate semiconductor device of the fifth embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the breakdown voltage can be improved. Furthermore, by providing gate insulating film 9 on the side and bottom surfaces of the terminal trenches 21a to 21f, pattern deformation of the terminal fin portions 22a to 22f can be prevented.

[0088] (Sixth Embodiment) The insulated gate semiconductor device according to the sixth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 11, the gate insulating film 9 and polysilicon layers 10a to 10f are embedded inside the terminal trenches 21a to 21f at the terminal portion 102.

[0089] The gate insulating film 9 is provided only on the sides of the terminal trenches 21a to 21f, and not on the lower surfaces of the terminal trenches 21a to 21f. The sides of the polysilicon layers 10a to 10f are in contact with the gate insulating film 9. The lower surfaces of the polysilicon layers 10a to 10f are in contact with the upper surfaces of the guard ring layers 23a to 23f. The polysilicon layers 10a to 10f are made of the same material as the gate electrode 10 of the active part 101. The impurity concentration of the polysilicon layers 10a to 10f is approximately the same as the impurity concentration of the gate electrode 10 of the active part 101. The polysilicon layers 10a to 10f can be formed simultaneously with the gate electrode 10 in the process of forming the gate electrode 10 of the active part 101.

[0090] Figure 10 illustrates a case where the gate insulating film 9 and polysilicon layers 10a to 10f are embedded inside all of the terminal trenches 21a to 21f. However, the gate insulating film 9 and polysilicon layers 10a to 10f may be embedded only inside a portion of the inner part of the terminal trenches 21a to 21f (for example, terminal trenches 21a and 21b). The other configurations of the insulated gate semiconductor device according to the sixth embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0091] According to the insulated gate semiconductor device of the sixth embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the breakdown voltage can be improved. Furthermore, by embedding the gate insulating film 9 and polysilicon layers 10a to 10f inside the terminal trenches 21a to 21f, pattern deformation of the terminal fin portions 22a to 22f can be prevented.

[0092] (Seventh Embodiment) The insulated gate semiconductor device according to the seventh embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 12, the gate insulating film 9 and polysilicon layers 10a to 10f are embedded inside the terminal trenches 21a to 21f at the terminal portion 102.

[0093] Gate insulating film 9 is provided on the side and bottom surfaces of the terminal trenches 21a to 21f. Polysilicon layers 10a to 10f are embedded inside the terminal trenches 21a to 21f via the gate insulating film 9. The polysilicon layers 10a to 10f are made of the same material as the gate electrode 10 of the active part 101. The impurity concentration of the polysilicon layers 10a to 10f is approximately the same as the impurity concentration of the gate electrode 10 of the active part 101. The polysilicon layers 10a to 10f can be formed simultaneously with the gate electrode 10 in the process of forming the gate electrode 10 of the active part 101.

[0094] Figure 12 illustrates a case where the gate insulating film 9 and polysilicon layers 10a to 10f are embedded inside all of the terminal trenches 21a to 21f. However, the gate insulating film 9 and polysilicon layers 10a to 10f may be embedded only inside a portion of the inner part of the terminal trenches 21a to 21f (for example, terminal trenches 21a and 21b). The other configurations of the insulated gate semiconductor device according to the seventh embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0095] According to the insulated gate semiconductor device of the seventh embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the breakdown voltage can be improved. Furthermore, by embedding the gate insulating film 9 and polysilicon layers 10a to 10f inside the terminal trenches 21a to 21f, pattern deformation of the terminal fin portions 22a to 22f can be prevented.

[0096] (Eighth embodiment) The insulated gate semiconductor device according to the eighth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 13, polysilicon layers 10a to 10f are embedded inside the terminal trenches 21a to 21f at the terminal portion 102. The sides of the polysilicon layers 10a to 10f are in contact with the sides of the terminal fin portions 22a to 22f.

[0097] The lower surfaces of the polysilicon layers 10a to 10f are in contact with the upper surfaces of the guard ring layers 23a to 23f. The polysilicon layers 10a to 10f are made of the same material as the gate electrode 10 of the active part 101. The impurity concentration of the polysilicon layers 10a to 10f is approximately the same as the impurity concentration of the gate electrode 10 of the active part 101. The polysilicon layers 10a to 10f can be formed simultaneously with the gate electrode 10 in the process of forming the gate electrode 10 of the active part 101.

[0098] Figure 13 illustrates a case where polysilicon layers 10a to 10f are embedded inside all of the terminal trenches 21a to 21f. However, polysilicon layers 10a to 10f may be embedded only inside a portion of the terminal trenches 21a to 21f (for example, terminal trenches 21a and 21b). The other configurations of the insulated gate semiconductor device according to the eighth embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0099] According to the insulated gate semiconductor device of the eighth embodiment, similar to the insulated gate semiconductor device of the first embodiment, by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102, the electric field can be mitigated and the withstand voltage can be improved. Furthermore, by embedding polysilicon layers 10a to 10f inside the terminal trenches 21a to 21f, pattern deformation of the terminal fin portions 22a to 22f can be prevented.

[0100] (Ninth Embodiment) The insulated gate semiconductor device according to the ninth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 6, in that, as shown in Figure 14, a plurality of field plates 31a to 31e are provided on the upper surface side of the insulating film 11 at the terminal portion 102. The field plates 31a to 31e have an annular (frame-shaped) planar pattern surrounding the active portion 101. The field plates 31a to 31e are spaced apart from each other and arranged concentrically.

[0101] The field plates 31a to 31e are made of a metal such as aluminum (Al) or copper (Cu), or an alloy such as aluminum-silicon (Al-Si) or aluminum-copper (Al-Cu). The field plates 31a to 31e may be made of the same material as the source electrode 13 and can be formed simultaneously with the source electrode 13. The field plates 31a to 31e are covered with a protective film 32 made of polyimide or the like. The other components of the insulated gate semiconductor device according to the ninth embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0102] According to the insulated gate semiconductor device of the ninth embodiment, similar to the insulated gate semiconductor device of the first embodiment, the electric field can be mitigated and the breakdown voltage can be improved by providing terminal fin portions 22a to 22f on the upper surface side of the drift layer 2 of the terminal portion 102. Furthermore, the electric field can be further mitigated by providing a plurality of field plates 31a to 31e on the upper surface side of the insulating film 11.

[0103] (Other embodiments) As described above, the first to ninth embodiments of this disclosure have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0104] For example, in the first to ninth embodiments, a trench gate type vertical MOSFET was exemplified as the active element of the active section 101, but the n of the MOSFET+ Instead of drain region 1 of type p + This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0105] Furthermore, while the first to ninth embodiments illustrate the case where the semiconductor chip 100 is composed of silicon carbide (SiC), the invention is not limited thereto. For example, the semiconductor chip 100 may be composed of silicon (Si), or it may be composed of a semiconductor with a wider band gap than Si (wide bandgap semiconductor), such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN).

[0106] Furthermore, the configurations disclosed in the first to ninth embodiments can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of Symbols]

[0107] 1...Drain area 2…Drift layer 3…Current diffusion layer 4…Gate bottom protection area 5…Base area 6…Source area 7…Base contact area 8…Activated trench 9…Gate insulating film 10… Guard Stop 10a~10f...Polysilicon layer 11… Insulating film 11a... Contact hole 12… Contact electrodes 12a... Barrier metal layer 12b... Plug layer 13…Source electrode 14…Drain electrode 15…Active side fin section 21a~21f...Terminal trench 22a~22f...Terminal fin section 23a~23f...Guard ring layer 31a~31e…Field Plate 32...Protective film 100... Semiconductor chips 101...Active part 102...Terminal section C1~C3...Unit cells s11~s15,s21~s25...interval w1, w2, w11~w16, w21~w26... width

Claims

1. A first conductivity type drift layer is provided extending from the active portion containing the active element to the terminal portion surrounding the active portion, A plurality of first conductive fin portions are provided on the upper surface side of the drift layer at the terminal portion, spaced apart from each other, so as to surround the active portion, A semiconductor device equipped with a semiconductor device.

2. The aforementioned active element is A second conductivity type base region provided on the upper surface side of the drift layer, A first conductivity type main region provided on the upper surface side of the base region, A gate electrode embedded in a pair of first trenches sandwiching the sides of the base region and the main region via a gate insulating film, Equipped with, An inversion layer is formed in the region of the base region away from the interface with the gate insulating film. The semiconductor device according to claim 1.

3. The width of the base region is 0.2 μm or less. The semiconductor device according to claim 2.

4. The width of the fin portion widens towards the outside of the end portion. The semiconductor device according to claim 1 or 2.

5. The width of the fin portion is constant from the inside to the outside of the end portion. The semiconductor device according to claim 1 or 2.

6. The width of the innermost fin portion of the terminal end is 0.2 μm or less. The semiconductor device according to claim 1 or 2.

7. A second trench is provided between adjacent fin sections. The semiconductor device according to claim 2.

8. The depth of the second trench is the same as the depth of the first trench. The semiconductor device according to claim 7.

9. The drift layer is further provided with a second conductive guard ring layer located directly below the second trench on the upper surface side of the drift layer. The semiconductor device according to claim 7.

10. The guard ring layer is in contact with the lower surface of the second trench. The semiconductor device according to claim 9.

11. The guard ring layer is separated from the lower surface of the second trench. The semiconductor device according to claim 9.

12. The gate insulating film is provided on the side surface of the second trench. The semiconductor device according to claim 7.

13. A polysilicon layer is provided on the side surface of the second trench via the gate insulating film. The semiconductor device according to claim 12.

14. A polysilicon layer is provided on the side surface of the second trench. The semiconductor device according to claim 7.

15. The fin portion is provided with a field plate attached to its upper surface via an insulating film. The semiconductor device according to claim 1 or 2.

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