Sense amplifier and non-volatile memory device

Abstract

We provide a sense amplifier that improves design flexibility when product design changes are made. [Solution] The sense amplifier (SA1) includes a first MOS transistor (PM1) whose source is connected to a power supply voltage or a low potential application terminal and whose gate is connectable to a first bit line to which a first memory cell is connected; a second MOS transistor (PM2) whose source is connected to the power supply voltage or the low potential application terminal and whose gate is connectable to a second bit line to which a second memory cell is connected or to a reference current source (7); a first switch (SW1) for switching between conduction and interruption between the gate and source of the first MOS transistor; a second switch (SW2) for switching between conduction and interruption between the gate and source of the second MOS transistor; and a latch output unit (5) connected to the drain of the first MOS transistor and the drain of the second MOS transistor, which is capable of latching and outputting data.

Description

Technical Field

[0001] This disclosure relates to a sense amplifier.

Background Art

[0002] Conventionally, there is a non-volatile memory that forms memory cells in each of two transistors and stores data non-volatilely by utilizing the difference in gate threshold voltage between the two memory cells (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In the non-volatile memory as described above, it is desired to improve the design freedom in the case of product design changes.

[0005] A sense amplifier according to one aspect of the present disclosure includes a first MOS transistor composed of a MOSFET, having a source connected to an application terminal of a power supply voltage or a low potential, and a gate configured to be connectable to a first bit line to which a first memory cell is connected; a second MOS transistor composed of a MOSFET, having a source connected to the application terminal of the power supply voltage or the low potential, and a gate configured to be connectable to a second bit line to which a second memory cell is connected or a reference current source; a first switch configured to switch conduction / blocking between the gate and the source of the first MOS transistor; a second switch configured to switch conduction / blocking between the gate and the source of the second MOS transistor; a latch output unit connected to the drain of the first MOS transistor and the drain of the second MOS transistor and configured to be able to latch and output data. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the configuration of a non-volatile memory device according to a comparative example. [Figure 2] Figure 2 is a timing chart showing an example of read operation in a non-volatile memory device according to a comparative example. [Figure 3] Figure 3 is a timing chart showing another example of operation in a non-volatile memory device related to the comparative example. [Figure 4] Figure 4 shows the configuration of a non-volatile memory device according to the first embodiment. [Figure 5] Figure 5 is a timing chart showing an example of a read operation in a non-volatile memory device according to the first embodiment. [Figure 6] Figure 6 shows the configuration of a non-volatile memory device according to the second embodiment. [Figure 7] Figure 7 is a timing chart showing an example of a read operation in a non-volatile memory device according to the second embodiment. [Figure 8] Figure 8 is a timing chart showing an example of a read operation in a non-volatile memory device according to the third embodiment. [Figure 9] Figure 9 is a diagram illustrating capacitors CC1 and CC2. [Figure 10] Figure 10 shows an example waveform illustrating the lead operation when capacitors CC1 and CC2 are not provided. [Figure 11] Figure 11 shows an example waveform illustrating the lead operation when capacitors CC1 and CC2 are provided. [Figure 12] Figure 12 shows the configuration of a non-volatile memory device according to the fourth embodiment.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <Comparative Example> Before describing the embodiments of this disclosure, a comparative example will be described for comparison. This will make the issues to be addressed clearer. Figure 1 is a diagram showing the configuration of a non-volatile memory device 10 according to the comparative example.

[0009] The non-volatile memory device 10 comprises a sense amplifier SA10, a bit line BL1, a bit line BL2, a memory cell M1, and a memory cell M2. The non-volatile memory device 10 may be composed of a semiconductor integrated circuit. The memory cells M1 and M2 are composed of N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors).

[0010] A single memory unit 101 is composed of a pair of memory cells M1 and M2. In the memory unit 101, data of "0" or "1" is stored non-volatilely. The memory unit 101 can store 1 bit of data. The non-volatile memory device 10 can perform program operations (write operations) to store desired data in the memory unit 101, and read operations to read data stored in the memory unit 101.

[0011] Memory cells M1 and M2 have the same structure. Therefore, in the initial state, which is the state immediately after the formation of the semiconductor integrated circuit including the non-volatile memory device 10, memory cells M1 and M2 have the same electrical characteristics (and therefore the same gate threshold voltage). Note that "same" includes cases where the design is the same but there are errors due to actual manufacturing variations. When a program operation is executed starting from the initial state, a difference occurs between the gate threshold voltage of memory cell M1 and the gate threshold voltage of memory cell M2. During the program operation, a hot carrier is injected into either memory cell M1 or M2.

[0012] The non-volatile memory device 10 includes a program circuit 10B. The program operation is executed by the program circuit 10B. The program operation performed by the program circuit 10B may be any of the following program operations. Hereinafter, the gate threshold voltage of the memory cell M1 is represented by the symbol "Vth1", and the gate threshold voltage of the memory cell M2 is represented by the symbol "Vth2". The gate threshold voltages Vth1 and Vth2 have positive voltage values.

[0013] In the first program operation, the program circuit 10B increases the gate threshold voltage Vth1 of the memory cell M1 by injecting hot carriers only into the memory cell M1 among the memory cells M1 and M2. After the execution of the first program operation, "Vth1 > Vth2" is satisfied.

[0014] In the second program operation, the program circuit 10B increases the gate threshold voltage Vth2 of the memory cell M2 by injecting hot carriers only into the memory cell M2 among the memory cells M1 and M2. After the execution of the second program operation, "Vth1 < Vth2" is satisfied.

[0015] The drain of the memory cell M1 is connected to the bit line BL1. The source of the memory cell M1 is connected to the application terminal of the low potential VSS. The low potential VSS is, for example, the ground potential and is lower than the power supply voltage VDDM described later.

[0016] The drain of the memory cell M2 is connected to the bit line BL2. The source of the memory cell M2 is connected to the application terminal of the low potential VSS.

[0017] A plurality of pairs of bit lines BL1 and BL2 are provided. The gates of the memory cells M1 and M2 connected to each pair of bit lines BL1 and BL2 are connected to the same word line WL. A plurality of word lines WL are provided. When a predetermined gate voltage Vgt is applied to one of the plurality of word lines WL, the word line is selected.

[0018] The sense amplifier SA10 is a circuit that reads data from the memory section 101 selected by the selection of the word line WL and bit lines BL1 and BL2. The sense amplifier SA10 comprises MOS transistors PM11 and PM12, clamp transistors NM11 and NM12, NMOS transistors NM13 and NM14, inverters IV11 and IV12, switches SW11 and SW12, switches SW13 and SW14, a read completion signal output circuit 11, bit line selection switches SBL1 and SBL2, a bit line short-circuit switch SSH, bit line pull-down switches SPD1 and SPD2, and a switch control circuit 10A.

[0019] MOS transistors PM11 and PM12 are composed of P-channel MOSFETs. The sources of MOS transistors PM11 and PM12 are connected to the application terminal of the power supply voltage VDDM. The drain of MOS transistor PM11 is connected to the gate of MOS transistor PM12. The drain of MOS transistor PM12 is connected to the gate of MOS transistor PM11.

[0020] Switch SW11 is connected between the drain and source of MOS transistor PM11. When switch SW11 is ON, the drain and source of MOS transistor PM11 are short-circuited. Switch SW12 is connected between the drain and source of MOS transistor PM12. When switch SW12 is ON, the drain and source of MOS transistor PM12 are short-circuited.

[0021] The NMOS transistors NM13 and NM14 are composed of N-channel MOSFETs. The drain of NMOS transistor NM13 is connected to the drain of MOS transistor PM11. The source of NMOS transistor NM13 is connected to the application terminal of the low-potential VSS via switch SW13. The input terminal of inverter IV11 is connected to the drain of MOS transistor PM11. The gate of NMOS transistor NM13 is connected to the output terminal of inverter IV11.

[0022] The drain of NMOS transistor NM14 is connected to the drain of MOS transistor PM12. The source of NMOS transistor NM14 is connected to the application terminal of the low-potential VSS via switch SW14. The input terminal of inverter IV12 is connected to the drain of MOS transistor PM12. The gate of NMOS transistor NM14 is connected to the output terminal of inverter IV12.

[0023] The read completion signal output circuit 11 includes NOR circuits 11A and 11B, and an inverter 11C. The outputs of inverters IV11 and IV12 are input to the first and second input terminals of NOR circuit 11A, respectively. The output of NOR circuit 11A is input to the first input terminal of NOR circuit 11B. The clock CLK is input to the second input terminal of NOR circuit 11B. The output of NOR circuit 11B is input to the third input terminal of NOR circuit 11A. The output of NOR circuit 11A is input to inverter 11C. The read completion signal END is output from inverter 11C. The read completion signal END is a signal that can indicate whether or not reading from the memory unit 101 is complete.

[0024] The inverter IV12 outputs a data signal DATA. The data signal DATA is a signal that can take on a logic level corresponding to the value of the data read from the memory unit 101.

[0025] The clamp transistors NM11 and NM12 are composed of N-channel MOSFETs. A clamp voltage Vclp is applied to the gates of the respective clamp transistors NM11 and NM12. The drain of clamp transistor NM11 is connected to the drain of MOS transistor PM11. The source of clamp transistor NM11 is connected to bit line BL1 via bit line selection switch SBL1. A bit line selection switch SBL1 is provided for each of the multiple bit lines BL1.

[0026] The drain of clamp transistor NM12 is connected to the drain of MOS transistor PM12. The source of clamp transistor NM12 is connected to bit line BL2 via bit line selection switch SBL2. A bit line selection switch SBL2 is provided for each of the multiple bit lines BL2.

[0027] When bit line selection switch SBL1 is turned ON, the corresponding bit line BL1 is selected. When bit line selection switch SBL2 is turned ON, the corresponding bit line BL2 is selected.

[0028] The bit line short-circuit switch SSH is connected between bit lines BL1 and BL2. When the bit line short-circuit switch SSH is ON, bit lines BL1 and BL2 are short-circuited. A bit line short-circuit switch SSH is provided for each of the multiple pairs of bit lines BL1 and BL2.

[0029] Bit line pull-down switch SPD1 is connected between bit line BL1 and the application terminal of low-potential VSS. Bit line pull-down switch SPD2 is connected between bit line BL2 and the application terminal of low-potential VSS. Bit line pull-down switches SPD1 and SPL2 are provided for each of the multiple pairs of bit lines BL1 and BL2.

[0030] The switch control circuit 10A controls the on / off states of switches SW11, SW12, SW13, SW14, bit line selection switches SBL1, SBL2, bit line short-circuit switch SSH, and bit line pull-down switches SPD1, SPD2, respectively.

[0031] Next, an example of read operation in a non-volatile memory device 10 relating to a comparative example of such a configuration will be described. Figure 2 is a timing chart showing an example of read operation in the non-volatile memory device 10. In Figure 2 (and Figure 3), the following waveform examples are shown from top to bottom: clock CLK, drain voltages SAP and SAN of MOS transistors PM11 and PM12 respectively, bit line voltages BLP and BLN of bit lines BL1 and BL2 respectively, data signal DATA, and read completion signal END.

[0032] At the point before timing t1 in Figure 2, sense amplifier SA10 is in a stopped state, switches SW11 and SW12 are ON, and switches SW13 and SW14 are OFF. At this time, all bit line selection switches SBL1 and SBL2 are OFF, all bit line short switch SSH is OFF, and all bit line pull-down switches SPD1 and SPD2 are ON. Also, at this time, word line WL is not selected. As a result, drain voltages SAP and SAN are the power supply voltage VDDM, and bit line voltages BLP and BLN are at the low potential VSS.

[0033] Subsequently, at timing t1, when the clock CLK rises to a high level, the word line WL and bit lines BL1 and BL2 corresponding to the memory section 101 to be read are selected. That is, a read gate voltage Vgt is applied to the word line WL, and the bit line selection switches SBL1 and SBL2 are switched to the ON state. In addition, the corresponding bit line short-circuit switch SSH is turned ON to short-circuit the selected bit lines BL1 and BL2. The read completion signal END also falls to a low level.

[0034] Hereinafter, we assume that memory cell M1 is in a programmed state and memory cell M2 is in an unprogrammed state (the same applies in the description of the embodiments of this disclosure later). Then, a memory cell current Im1 larger than the memory cell current Im2 flowing through memory cell M2 begins to flow through memory cell M1. At this time, the parasitic capacitances C1 and C2 of bit lines BL1 and BL2 are charged, and the bit line voltages BLP and BLN begin to rise. Since bit lines BL1 and BL2 are short-circuited, the bit line voltages BLP and BLN become equal.

[0035] Then, at the falling edge timing t2 of the clock CLK, the bit line voltages BLP and BLN converge to the voltage of the clamp voltage Vclp minus the Vgs (gate-source voltage) of the clamp transistors NM11 and NM12. At this time, the sense amplifier SA10 is activated (readout begins). That is, switches SW11 and SW12 are switched to the off state, and switches SW13 and SW14 are switched to the on state.

[0036] Normally, since the memory cell current Im1 is greater than Im2, the drain voltage SAP drops significantly lower than SAN, causing the drain voltage SAP to become low, the MOS transistor PM12 to turn on, the drain voltage SAN to become high, and the MOS transistor PM11 to turn off. The NMOS transistor NM13 is on, and the NMOS transistor NM14 is off. In this latched state, the data signal DATA becomes low (for example, when reading data "1"). At this time, the read completion signal END rises to a high level, indicating that the read is complete (timing t3).

[0037] When the read completion signal END indicates that the readout is complete, the sense amplifier SA10 stops, and the selection of the word line WL and bit lines BL1 and BL2 is deselected. At this time, the bit line pull-down switches SPD1 and SPD2 are switched to the ON state, and the bit line voltages BL1 and BL2 become low potential VSS.

[0038] However, depending on the magnitude of the memory cell current Im2 and the on-resistance (current capability) of the MOS transistor PM12, the drain voltage SAN may drop to the same level as SAP from the start of reading at timing t2, as shown in Figure 2. In such cases, malfunctions may occur during data reading (for example, incorrectly reading the data "0").

[0039] Figure 3 is a timing chart showing another example of operation in the non-volatile memory device 10 according to the comparative example. Here, from the start of reading at timing t2, the drain voltage SAP drops significantly lower than SAN, and data "1" is read successfully (timing t3). At this time, because the NMOS transistor NM13 is ON, the drain voltage SAP and bit line voltage BLP drop sharply. At timing t3, the read completion signal END rises to a high level, and at timing t3', the sense amplifier SA10 is stopped, the selection of the word line WL and bit lines BL1 and BL2 is deselected, and bit lines BL1 and BL2 are pulled down.

[0040] Then, at timing t4, the clock CLK rises, the word line WL and bit lines BL1 and BL2 are selected, and the bit line voltages BLP and BLN of the selected bit lines BL1 and BL2 begin to rise due to the charging of parasitic capacitances C1 and C2. Subsequently, at timing t5, when the clock CLK falls, the sense amplifier SA10 is activated. At this time, the period TB between timings t4 and t5 is shorter than the bit line convergence time TA between timings t1 and t2. Because the period TB is short, the charging of parasitic capacitances C1 and C2 is insufficient, and when the sense amplifier SA10 is activated at timing t5, a current consisting of the memory cell currents Im1 and Im2, respectively, plus the charging currents of parasitic capacitances C1 and C2, flows through the clamp transistors NM11 and NM12, respectively. As a result, as shown in Figure 3, the drain voltages SAP and SAN drop to roughly the same extent, which may cause data readout malfunctions. In other words, a bit line convergence time TA is necessary to avoid malfunctions, which hinders the acceleration of the cycle time. This issue becomes particularly pronounced as the capacity of non-volatile memory devices increases.

[0041] <First Embodiment> In view of the problems in the above comparative example, the embodiments of the present disclosure described below will be implemented. Figure 4 is a diagram showing the configuration of a non-volatile memory device 1 according to the first embodiment. The non-volatile memory device 1 comprises a sense amplifier SA1, a bit line BL1, a bit line BL2, a memory cell M1, and a memory cell M2. The bit lines BL1, BL2 and the memory cells M1, M2 are the same as in the comparative example described above. The non-volatile memory device 1 also comprises a program circuit 1B, which writes data to the memory unit 101 by performing a program operation on the memory cells M1, M2, similar to the comparative example described above.

[0042] The sense amplifier SA1 comprises MOS transistors PM1 and PM2, capacitors CC1 and CC2, latch circuit 2, latch circuit 3, read completion signal output circuit 4, and clamp transistors NM1 and NM2. The sense amplifier SA1 also includes switches SW1 to SW3 and a switch control circuit 1A. The sense amplifier SA1 also includes bit line selection switches SBL1 and SBL2, a bit line short switch SSH, and bit line pull-down switches SPD1 and SPD2, but their configurations are the same as in the comparative example described above.

[0043] MOS transistors PM1 and PM2 are composed of P-channel MOSFETs. The sources of MOS transistors PM1 and PM2 are connected to the terminals to which the power supply voltage VDDM is applied. The drain of MOS transistor PM1 is connected to one end of capacitor CC1. The other end of capacitor CC1 is connected to the gate of MOS transistor PM2. The drain of MOS transistor PM2 is connected to one end of capacitor CC2. The other end of capacitor CC2 is connected to the gate of MOS transistor PM1. The functions of capacitors CC1 and CC2 will be described later.

[0044] The latch output section 5 is composed of latch circuit 2 and latch circuit 3. Latch circuit 2 has PMOS transistors 21 and 22, NMOS transistors 23 and 24, and inverters 25 and 26. The source of PMOS transistor 21 is connected to the drain of MOS transistor PM1. The drain of PMOS transistor 21 is connected to the drain of NMOS transistor 23. The source of NMOS transistor 23 is connected to the application terminal of low-potential VSS. The source of PMOS transistor 22 is connected to the drain of MOS transistor PM2. The drain of PMOS transistor 22 is connected to the drain of NMOS transistor 24. The source of NMOS transistor 24 is connected to the application terminal of low-potential VSS.

[0045] The gates of PMOS transistor 21 and NMOS transistor 23 are connected to node N2, which is connected to the drains of PMOS transistor 22 and NMOS transistor 24. The gates of PMOS transistor 22 and NMOS transistor 24 are connected to node N1, which is connected to the drains of PMOS transistor 21 and NMOS transistor 23. That is, the input terminal of inverter 29A, which is composed of PMOS transistor 21 and NMOS transistor 23, is connected to the output terminal of inverter 29B, which is composed of PMOS transistor 22 and NMOS transistor 24, and the input terminal of the inverter composed of PMOS transistor 22 and NMOS transistor 24 is connected to the output terminal of the inverter composed of PMOS transistor 21 and NMOS transistor 23. Node N1 is connected to the input terminal of inverter 25. Node N2 is connected to the input terminal of inverter 26.

[0046] The latch circuit 2 also includes switches 27 and 28. Switches 27 and 28 are provided for resetting the latch circuit 2. Switch 27 is connected between node N1 and the application terminal of the low-potential VSS. Switch 28 is connected between node N2 and the application terminal of the low-potential VSS.

[0047] The latch circuit 3 includes a NAND gate 31 and a NAND gate 32. One input terminal of the NAND gate 31 is connected to the output terminal of the inverter 25, and the other input terminal is connected to the output terminal of the NAND gate 32. One input terminal of the NAND gate 32 is connected to the output terminal of the inverter 26. The other input terminal of the NAND gate 32 is connected to the output terminal of the NAND gate 31. A data signal DATA is output from the output terminal of the NAND gate 31.

[0048] The read completion signal output circuit 4 comprises a NAND gate 4 and a control circuit 4B. One input terminal of the NAND gate 4A is connected to the output terminal of inverter 25, and the other input terminal is connected to the output terminal of inverter 26. The output of the NAND gate 4A and the clock CLK are input to the control circuit 4B. The read completion signal END is output from the control circuit 4B.

[0049] The clamp transistors NM1 and NM2 are composed of N-channel MOSFETs. The gate of MOS transistor PM1 is connected to the drain of clamp transistor NM1. The source of clamp transistor NM1 is connected to bit line BL1 via bit line selection switch SBL1. The gate of MOS transistor PM2 is connected to the drain of clamp transistor NM2. The source of clamp transistor NM2 is connected to bit line BL2 via bit line selection switch SBL2. A clamp voltage Vclp is applied to the gates of clamp transistors NM1 and NM2.

[0050] Switch SW1 is connected between the gate of MOS transistor PM1 and the terminal to which the power supply voltage VDDM is applied. Switch SW2 is connected between the gate of MOS transistor PM2 and the terminal to which the power supply voltage VDDM is applied. Switch SW3 is connected between the gates of MOS transistor PM1 and MOS transistor PM2. Switch control circuit 1A controls the on / off state of switches SW1 to SW3, bit line selection switches SBL1 and SBL2, bit line short switch SSH, and bit line pull-down switches SPD1 and SPD2.

[0051] Next, an example of read operation in the non-volatile memory device 1 according to the first embodiment of this configuration will be described. Figure 5 is a timing chart showing an example of read operation in the non-volatile memory device 1. In Figure 5 (and Figures 7 and 8), the following waveform examples are shown from top to bottom: clock CLK, gate voltages SAP and SAN of MOS transistors PM1 and PM2 respectively, bit line voltages BLP and BLN of bit lines BL1 and BL2 respectively, data signal DATA, and read completion signal END.

[0052] In Figure 5, just before timing t11, sense amplifier SA1 is in a stopped state, and switches SW1 to SW3 are in the ON state. As a result, the gate voltages SAP and SAN become the power supply voltage VDDM, and MOS transistors PM1 and PM2 are in the OFF state. At this time, switches 27 and 28 are in the ON state. Also, the read completion signal END is at a high level.

[0053] At this time, all bit line selection switches SBL1 and SBL2 are in the off state, all bit line short-circuit switches SSH are in the off state, and all bit line pull-down switches SPD1 and SPD2 are in the on state. Also, the word line WL is not selected. As a result, the bit line voltages BLP and BLN are at a low potential VSS.

[0054] Subsequently, at timing t11, when the clock CLK rises to a high level, the word line WL and bit lines BL1 and BL2 corresponding to the memory section 101 to be read are selected. At this time, the read completion signal END falls to a low level.

[0055] Here, as an example, if memory cell M1 is in a programmed state and memory cell M2 is in an unprogrammed state, a memory cell current Im1 that is larger than the memory cell current Im2 flowing through memory cell M2 begins to flow through memory cell M1. At this time, the parasitic capacitances C1 and C2 of bit lines BL1 and BL2 are charged, and the bit line voltages BLP and BLN begin to rise. Bit lines BL1 and BL2 are short-circuited, but due to the current difference between memory cell currents Im1 and Im2, current flows through the bit line short-circuit switch SSH, and a slight potential difference is created between the bit line voltages BLP and BLN.

[0056] Then, at the falling edge timing t12 of the clock CLK, the bit line voltages BLP and BLN converge to the clamp voltage Vclp minus the Vgs voltage of clamp transistors NM1 and NM2. At this time, the sense amplifier SA10 is activated (readout begins). That is, switches SW1 to SW3 and switches 27 and 28 are switched to the off state.

[0057] Here, because the memory cell current Im1 is greater than Im2, the gate voltage SAP decreases faster than SAN and reaches the decision threshold TH before SAN (timing z). As a result, the MOS transistor PM1 turns on, and the power supply voltage VDDM is applied to the source of the PMOS transistor 21. This turns on the PMOS transistor 21, making node N1 high, and node N2, which is the output of inverter 29B, low. At this time, the PMOS transistor 21 is on and the NMOS transistor 23 is off. Therefore, the output of inverter 25 is latched at a low level and the output of inverter 26 is latched at a high level. As a result, the data signal DATA becomes high level (readout of data "1").

[0058] As a result, the read completion signal END rises to a high level, indicating that the read is complete. Then, the sense amplifier SA10 is stopped, switches SW1 to SW3 are turned on, and the gate voltages SAP and SAN become the power supply voltage VDDM. Switches 27 and 28 are also turned on, and latch circuit 2 is reset. Latch circuit 3 maintains the level of the data signal DATA regardless of the reset of latch circuit 2. Also, the selection of the word line WL and bit lines BL1 and BL2 is deselected. At this time, the bit line pull-down switches SPD1 and SPD2 are switched on, and the bit line voltages BL1 and BL2 become the low potential VSS.

[0059] Thus, in this embodiment, data is read out when the gate voltage SAP or SAN with a larger memory cell current falls below the determination threshold TH first, making it less susceptible to the on-resistance (current capability) of the MOS transistors PM1 and PM2. Therefore, even if the absolute value of the memory cell current changes when the product design of the non-volatile memory device 1 is modified, the design of the MOS transistors PM1 and PM2 is less likely to fail. In other words, the degree of design freedom can be improved. Furthermore, by using clamp transistors NM1 and NM2, the drain-source voltage of the memory cells M1 and M2 is limited, and impedance isolation is performed, which accelerates the decrease of the gate voltages SAP and SAN during reading.

[0060] <Second Embodiment> Figure 6 shows the configuration of the non-volatile memory device 1X according to the second embodiment of this disclosure. The difference in configuration between the non-volatile memory device 1X according to this embodiment and the first embodiment (Figure 4) is the configuration of the sense amplifier SA2.

[0061] Specifically, the sense amplifier SA2 differs from the sense amplifier SA1 according to the first embodiment in that it has an idling current generation unit 6. The idling current generation unit 6 includes a constant current source 61 and a current mirror 62. The current mirror 62 includes an input transistor 62A and output transistors 62B and 62C. The input transistor 62A and the output transistors 62B and 62C are composed of N-channel MOSFETs.

[0062] The drain of input transistor 62A is connected to constant current source 61. The gate and drain of input transistor 62A are short-circuited. The source of input transistor 62A is connected to the application terminal of low-potential VSS.

[0063] The gate of the output transistor 62B is connected to the gate of the input transistor 62A. The drain of the output transistor 62B is connected to the source of the clamp transistor NM1. The source of the output transistor 62B is connected to the application terminal of the low-potential VSS. The constant current generated by the constant current source 61 is mirrored, and an idling current Iid1 is generated flowing from the source of the clamp transistor NM1 through the output transistor 62B.

[0064] The gate of the output transistor 62C is connected to the gate of the input transistor 62A. The drain of the output transistor 62C is connected to the source of the clamp transistor NM2. The source of the output transistor 62C is connected to the application terminal of the low-potential VSS. The constant current generated by the constant current source 61 is mirrored, and an idling current Iid2 is generated flowing from the source of the clamp transistor NM2 through the output transistor 62C.

[0065] Next, an example of read operation in the non-volatile memory device 1X according to the second embodiment of this configuration will be described. Figure 7 is a timing chart showing an example of read operation in the non-volatile memory device 1X.

[0066] In Figure 7, just before timing t21, sense amplifier SA2 is in a stopped state, and switches SW1 to SW3 are in the ON state. As a result, the gate voltages SAP and SAN become the power supply voltage VDDM, and MOS transistors PM1 and PM2 are in the OFF state. At this time, switches 27 and 28 are in the ON state, and the read completion signal END is at a low level.

[0067] At this time, all bit line selection switches SBL1 and SBL2 are ON, all bit line short-circuit switches SSH are ON, and all bit line pull-down switches SPD1 and SPD2 are OFF. In this embodiment, the bit line pull-down switches SPD1 and SPD2 do not participate in the operation of the sense amplifier SA2. Also, at this time, the word line WL is not selected. As a result, all bit lines BL1 and BL2 are short-circuited and at the same potential, and the potential of Vgs is set to correspond to the clamp voltage Vlp and the idling currents Iid1 and Iid2 in the clamp transistors NM1 and NM2 (Iid1 = Iid2). At this time, the parasitic capacitances C1 and C2 are charged.

[0068] Subsequently, at timing t21, when the clock CLK rises to a high level, the word line WL and bit lines BL1 and BL2 corresponding to the memory section 101 to be read are selected. That is, the bit line selection switches SBL1 and SBL2 corresponding to the bit lines BL1 and BL2 other than the bit line to be read are switched to the off state. In addition, all bit line short-circuit switches SSH are switched to the off state.

[0069] Here, as an example, if memory cell M1 is in a programmed state and memory cell M2 is in an unprogrammed state, a memory cell current Im1, which is larger than the memory cell current Im2 flowing through memory cell M2, begins to flow through memory cell M1. At this time, a current equal to the sum of the idling current Iid1 and the memory cell current Im1 flows through the clamp transistor NM1, so the Vgs of the clamp transistor NM1 increases, and the bit line voltage BLP of the bit line BL1 decreases.

[0070] Subsequently, at timing t22, when the clock CLK falls to a low level, the sense amplifier SA2 is activated (readout begins). At this time, switches SW1 to SW3 and switches 27 and 28 are switched to the off state.

[0071] A current consisting of the idling current Iid1 plus the memory cell current Im1 flows through clamp transistor NM1, and a current consisting of the idling current Iid2 plus the memory cell current Im2 flows through clamp transistor NM2. Therefore, the gate voltages SAP and SAN decrease according to the relative magnitudes of the memory cell currents Im1 and Iim2. Here, since the memory cell current Im1 is greater than Im2, the gate voltage SAP decreases faster than SAN and reaches the judgment threshold TH before SAN (timing t23). As a result, MOS transistor PM1 turns on, latching the output of inverter 25 at a low level and the output of inverter 26 at a high level. Consequently, the data signal DATA becomes high level (readout of data "1").

[0072] As a result, the read completion signal END rises to a high level, indicating that the read is complete. Then, the sense amplifier SA2 is stopped, switches SW1~SW3 are turned ON, and the gate voltages SAP and SAN become the power supply voltage VDDM. Switches 27 and 28 are also turned ON, and latch circuit 2 is reset. Latch circuit 3 maintains the level of the data signal DATA regardless of the reset of latch circuit 2. Also, the selection of the word line WL and bit lines BL1 and BL2 is deselected. At this time, the bit line pull-down switches SPD1 and SPD2 corresponding to the bit lines BL1 and BL2 that are not being read are switched ON (i.e., all bit line pull-down switches SPD1 and SPD2 are ON), and all bit line short-circuit switches SSH are switched ON. As a result, all bit lines BL1 and BL2 are at the same potential, and the bit line voltages BLP and BLN rise due to charging. Then, at the timing 23 when the clock CLK rises, the bit line voltages BLP and BLN reach the potential set by the idling currents Iid1 and Iid2, and the word line WL and bit lines BL1 and BL2 corresponding to the memory section 101 to be read are selected again.

[0073] In this embodiment, by using an idling current when the sense amplifier SA2 is started, the decrease in gate voltages SAP and SAN is accelerated, reaching the judgment threshold TH. Furthermore, the period required to converge the bit lines BL1 and BL2 to the potential set by the idling current after the readout is completed is shortened, thereby reducing the cycle time.

[0074] <Third Embodiment> In the third embodiment of this disclosure, the non-volatile memory device 1X is configured similarly to that of the second embodiment. The read operation in the third embodiment differs from that of the second embodiment. Figure 8 is a timing chart showing an example of the read operation in the third embodiment.

[0075] In contrast to the second embodiment, in Figure 8, at the timing t31 when the clock CLK rises, the word line WL and bit lines BL1 and BL2 corresponding to the memory unit 101 to be read are selected, and the sense amplifier SA2 is activated. As a result, the gate voltages SAP and SAN due to the memory cell current and idling current begin to decrease from timing t31.

[0076] When either gate voltage SAP or SAN falls below the determination threshold TH first (SAP in the example in Figure 8 (timing t32)), data is read, and data reading is complete. Then, all bit lines BL1 and BL2 are short-circuited and converge to the potential set by the idling current. At the timing t33 ​​when the clock CLK rises, the word line WL and bit lines BL1 and BL2 corresponding to the memory section 101 to be read are selected again, and the sense amplifier SA2 is activated. According to this embodiment, the cycle time can be shortened even further than in the second embodiment.

[0077] <Regarding capacitors CC1 and CC2> Here, we will explain capacitors CC1 and CC2. Figure 9 is a diagram showing part of the configuration in Figure 4 or Figure 6, used to explain capacitors CC1 and CC2. In Figure 9, switches SW1 to SW3 and switches 27 and 28 are collectively shown as "switch SW". Here, we will compare and explain the case in Figure 9 with and without capacitors CC1 and CC2 (dashed lines).

[0078] Figure 10 shows an example waveform illustrating the read operation without capacitors CC1 and CC2. In Figure 10 and Figure 11 (described later), the top row shows, in order, voltage V1 (=gate voltage of MOS transistor PM1), voltage V2 (=gate voltage of MOS transistor PM2), voltage V3 (=drain voltage of MOS transistor PM1), voltage V4 (=drain voltage of MOS transistor PM2), read completion signal END, and the state of switch SW.

[0079] At timing ta, the switch SW is switched from the ON state to the OFF state (sense amplifier activation). When the switch SW is OFF, the nodes for voltages V1 and V2 both have impedances with almost the same capacitance component. Therefore, if the memory cell current Im1 is greater than Im2, the voltage V1 decreases faster than the voltage V2. As a result, PM1 is turned on before MOS transistor PM2. The nodes for voltages V3 and V4 also have impedances with almost the same capacitance component, so because MOS transistor PM1 is turned on first, the node for voltage V3 is charged first, and voltage V3 rises first. At that time, the gate-drain parasitic capacitance Cgd1 of MOS transistor PM1 pushes up voltage V1 due to the rise of voltage V3. As a result, voltages V1 and V2 may be reversed (timing tb). If the potential difference that has been reversed cannot be reversed again and voltages V1 and V2 continue to decrease, the relationship between voltages V3 and V4 will be reversed from what it should be (timing tc). In this case, a readout error will occur. Furthermore, after the read completion signal END rises at timing tc, the switch SW is switched from the off state to the on state at timing td (stopping the sense amplifier). At this time, voltages V3 and V4 remain as the gate-source voltages Vgs21 and Vgs22 of the MOS transistors PM1 and PM2.

[0080] On the other hand, Figure 11 shows an example waveform illustrating the read operation when capacitors CC1 and CC2 are provided, and shows voltages V1 to V4. When the switch SW is turned off at timing ta, voltages V1 and V2 decrease. However, if V1 decreases faster than voltage V2, causing the MOS transistor PM1 to turn on first, voltage V3 rises, and voltage V1 is raised by the gate-drain parasitic capacitance Cgd1. However, here, capacitor CC1 also raises voltage V2. Therefore, it is possible to avoid the reversal of voltage V1 and V2, and the occurrence of read errors can be suppressed. Similarly, the reversal of voltages V1 and V2 can also be prevented by capacitor CC2.

[0081] <Fourth Embodiment> Figure 12 shows the configuration of the non-volatile memory device 1Y according to the fourth embodiment of this disclosure. The difference in configuration from the first embodiment (Figure 4) of the non-volatile memory device 1X according to this embodiment is that the configuration relating to the bit line BL2 is not provided, and a reference current source 7 connected to the gate of the MOS transistor PM2 is provided. The reference current source 7 is included in the sense amplifier SA3.

[0082] In this configuration, when the sense amplifier SA3 is started up, the reference current source 7 is activated, and the gate voltages SAP and SAN decrease according to the relative magnitudes of the memory cell current Im1 and the reference current Iref from the reference current source 7, allowing data to be read.

[0083] Furthermore, when applying a reference current source to the configuration of the second embodiment (Figure 6), the reference current Iref should be the current obtained by adding the idling current to the reference current value to be compared with the memory cell current Im1.

[0084] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0085] For example, when the MOS transistors PM1 and PM2 in this disclosure are configured using N-channel MOSFETs, the sources of the respective MOS transistors PM1 and PM2 are connected to the application terminals of the low-potential VSS.

[0086] <Note> As described above, the sense amplifier (SA1) according to one aspect of this disclosure is A first MOS transistor (PM1) is configured as a MOSFET, with its source connected to the power supply voltage (VDDM) or low potential (VSS) application terminal, and its gate connected to the first bit line (BL1) to which the first memory cell (M1) is connected. A second MOS transistor (PM2) is configured as a MOSFET, with its source connected to the power supply voltage or the low potential application terminal, and its gate connected to the second bit line (BL2) or reference current source (7) to which the second memory cell (M2) is connected, A first switch (SW1) configured to switch between conduction and interruption between the gate and source of the first MOS transistor, A second switch (SW2) is configured to switch between conduction and interruption between the gate and source of the second MOS transistor, A latch output unit (5) is connected to the drain of the first MOS transistor and the drain of the second MOS transistor and is configured to enable latch output of data, The configuration includes the following (first configuration).

[0087] Furthermore, in the first configuration described above, the latch output section includes a first latch circuit (2) configured to be resettable, (3) A configuration may also be provided which includes a second latch circuit that is capable of outputting the data based on the output of the first latch circuit and is configured to be capable of latching the data regardless of the reset of the first latch circuit (second configuration).

[0088] Furthermore, in the second configuration described above, the first latch circuit is A first inverter (29A) connected to the drain of the first MOS transistor, A second inverter (29B) is connected to the drain of the second MOS transistor, its output terminal is connected to the input terminal of the first inverter, and its input terminal is connected to the output terminal of the first inverter, A first reset switch (27) configured to reset the output of the first inverter, The system may also have a configuration that includes a second reset switch (28) configured to reset the output of the second inverter (third configuration).

[0089] Furthermore, in any of the above configurations 1 to 3, a first capacitor (CC1) is connected between the gate of the first MOS transistor and the drain of the second MOS transistor, The configuration may also include a second capacitor (CC2) connected between the gate of the second MOS transistor and the drain of the first MOS transistor (fourth configuration).

[0090] Furthermore, in any of the above configurations 1 to 4, a first bit line selection switch (SBL1) is connected between the gate of the first MOS transistor and the first bit line, The system includes a first bit line pull-down switch (SPD1) connected between the first bit line and the low-potential application terminal, In a configuration where the first bit line is at a low potential by turning on the first bit line pull-down switch, the first bit line is charged by switching the first bit line selection switch to the ON position, and then the sense amplifier is activated to start reading (fifth configuration).

[0091] Furthermore, in the fifth configuration described above, a first clamp transistor (NM1) may be provided, which is connected between the gate of the first MOS transistor and the first bit line selection switch, and configured to apply a clamp voltage (Vclp) to the gate (sixth configuration).

[0092] Furthermore, in the fifth or sixth configuration described above, a second bit line selection switch (SBL2) is connected between the gate of the second MOS transistor and the second bit line, The system includes a second bit line pull-down switch (SPD2) connected between the second bit line and a low-potential application terminal, The second bit line may be charged by switching the second bit line selection switch to the ON position while the second bit line is at the low potential by turning the second bit line pull-down switch ON, and then the sense amplifier may be started to begin reading (seventh configuration).

[0093] Furthermore, in the seventh configuration described above, a bit line short switch (SSH) is provided connected between the first bit line and the second bit line. The bit line short-circuit switch may be turned ON when the first bit line and the second bit line are being charged (eighth configuration).

[0094] Furthermore, in any of the above configurations 1 to 4, a first bit line selection switch is connected between the gate of the first MOS transistor and the first bit line, A first clamp transistor is connected between the gate of the first MOS transistor and the first bit line selection switch, and is configured to apply a clamp voltage to the gate, The system includes an idling current generation unit (6) configured to generate a first idling current (Iid1) flowing out from the source of the first clamp transistor, With all of the multiple first bit line selection switches corresponding to the multiple first bit lines turned ON, the first bit lines are brought to a potential set by the first idling current, and then, at a predetermined timing, the first memory cell to be read is selected, while the first bit line selection switches corresponding to the first bit lines other than the first bit line corresponding to the first memory cell to be read are turned OFF (9th configuration).

[0095] Furthermore, in the ninth configuration described above, the sense amplifier may be activated at the predetermined timing (the tenth configuration).

[0096] Furthermore, in the ninth or tenth configuration described above, a second bit line selection switch is connected between the gate of the second MOS transistor and the second bit line, The system comprises a second clamp transistor (NM2) connected between the gate of the second MOS transistor and the second bit line selection switch, configured such that the clamp voltage is applied to the gate, The idling current generation unit is configured to generate a second idling current (Iid2) that flows out from the source of the second clamp transistor. With all of the multiple second bit line selection switches corresponding to the multiple second bit lines turned ON, the second bit lines are brought to a potential set by the second idling current, and then, at the predetermined timing, the second memory cell to be read is selected, while the second bit line selection switches corresponding to the second bit lines other than the second bit line corresponding to the second memory cell to be read are switched OFF (11th configuration).

[0097] Furthermore, in the 11th configuration described above, a bit line short-circuit switch is provided connected between the first bit line and the second bit line. The bit line short-circuit switch may be turned ON when the potentials of the first bit line and the second bit line are converged (12th configuration).

[0098] Furthermore, one aspect of this disclosure is a non-volatile memory device (1) comprising a sense amplifier having any of the first to twelfth configurations described above, the first bit line, and the first memory cell. [Industrial applicability]

[0099] This disclosure can be used, for example, in semiconductor devices for various applications. [Explanation of symbols]

[0100] 1. Non-volatile memory device 1A Switch Control Circuit 1B Program Circuit 1X,1Y Non-volatile memory device 2. Latch Circuit 3. Latch Circuit 4. Read completion signal output circuit 4A NAND circuit 4B Control Circuit 5. Latch output section 6. Idling current generation unit 7 Reference current source 10 Non-volatile memory devices 10A Switch Control Circuit 10B Programmable Circuit 11. Read completion signal output circuit 11A,11B NOR circuit 11C Inverter 21,22 PMOS transistors 23,24 NMOS transistors 25, 26 Inverter 27, 28 Switches 29A, 29B Inverter 31,32 NAND circuits 61 Constant current source 62 Current Mirror 62A Input Transistor 62B, 62C output transistors 101 Memory section BL1, BL2 bit lines BLP, BLN bitline voltage C1,C2 parasitic capacitance CC1, CC2 Capacitors Cgd1, Cgd2 Gate-Drain Parasitic Capacity IV11, IV12 Inverter NM1, NM2 clamp transistors NM11, NM12 clamp transistors NM13, NM14 NMOS transistors PM1, PM2 MOS transistors PM11, PM12 MOS transistors SA1, SA2, SA3 Sense Amplifier SA10 Sense Amplifier SBL1, SBL2 bit line selection switch SPD1, SPD2 Bit Line Pull-Down Switch SSH bit line short switch SW Switch SW1~SW3 Switches SW11~SW14 Switches

Claims

1. A first MOS transistor is configured to be made of MOSFETs, with its source connected to a power supply voltage or a low potential application terminal, and its gate connected to a first bit line to which a first memory cell is connected. A second MOS transistor, which is composed of a MOSFET, has its source connected to the power supply voltage or the low potential application terminal, and its gate is configured to be connectable to a second bit line or reference current source to which a second memory cell is connected, A first switch configured to switch between conduction and interruption between the gate and source of the first MOS transistor, A second switch configured to switch between conduction and interruption between the gate and source of the second MOS transistor, A latch output unit connected to the drain of the first MOS transistor and the drain of the second MOS transistor, configured to enable latch output of data, A sense amplifier equipped with this feature.

2. The latch output unit is, A first latch circuit configured to be resettable, A sense amplifier according to claim 1, comprising: a second latch circuit capable of outputting the data based on the output of the first latch circuit, and configured to latch and output the data regardless of the reset of the first latch circuit.

3. The first latch circuit is, A first inverter connected to the drain of the first MOS transistor, A second inverter connected to the drain of the second MOS transistor, with its output terminal connected to the input terminal of the first inverter and its input terminal connected to the output terminal of the first inverter; a first reset switch configured to reset the output of the first inverter; The sense amplifier according to claim 2, further comprising a second reset switch configured to reset the output of the second inverter.

4. A first capacitor connected between the gate of the first MOS transistor and the drain of the second MOS transistor, The sense amplifier according to claim 1, further comprising a second capacitor connected between the gate of the second MOS transistor and the drain of the first MOS transistor.

5. A first bit line selection switch is connected between the gate of the first MOS transistor and the first bit line, It includes a first bit line pull-down switch connected between the first bit line and a low-potential application terminal, The sense amplifier according to claim 1, wherein the first bit line is charged by switching the first bit line selection switch to the ON state when the first bit line is at the low potential by turning the first bit line pull-down switch ON, and then reading is started by activating the sense amplifier.

6. The sense amplifier according to claim 5, further comprising a first clamp transistor connected between the gate of the first MOS transistor and the first bit line selection switch, configured to apply a clamp voltage to the gate.

7. A second bit line selection switch is connected between the gate of the second MOS transistor and the second bit line, It includes a second bit line pull-down switch connected between the second bit line and the low-potential application terminal, The sense amplifier according to claim 5, wherein the second bit line is charged by switching the second bit line selection switch to the ON state when the second bit line is at the low potential by turning the second bit line pull-down switch ON, and then reading is started by starting the sense amplifier.

8. A bit line short-circuit switch is provided, connected between the first bit line and the second bit line. The sense amplifier according to claim 7, wherein the bit line short-circuit switch is turned ON when the first bit line and the second bit line are charged.

9. A first bit line selection switch is connected between the gate of the first MOS transistor and the first bit line, A first clamp transistor is connected between the gate of the first MOS transistor and the first bit line selection switch, and is configured such that a clamp voltage is applied to the gate. The system includes an idling current generation unit configured to generate a first idling current flowing out from the source of the first clamp transistor, The sense amplifier according to claim 1, wherein with all of the multiple first bit line selection switches corresponding to the multiple first bit lines turned ON, the first bit lines are brought to a potential set by the first idling current, and then, at a predetermined timing, the first memory cell to be read is selected, while the first bit line selection switches corresponding to the first bit lines other than the first bit line corresponding to the first memory cell to be read are turned OFF.

10. The sense amplifier according to claim 9, which activates the sense amplifier at the predetermined timing.

11. A second bit line selection switch is connected between the gate of the second MOS transistor and the second bit line, The system comprises a second clamp transistor connected between the gate of the second MOS transistor and the second bit line selection switch, configured such that the clamp voltage is applied to the gate, The idling current generation unit is configured to generate a second idling current that flows out from the source of the second clamp transistor. The sense amplifier according to claim 9, wherein with all of the multiple second bit line selection switches corresponding to the multiple second bit lines turned ON, the second bit lines are brought to a potential set by the second idling current, and then, at the predetermined timing, the second memory cell to be read is selected, and the second bit line selection switches corresponding to the second bit lines other than the second bit line corresponding to the second memory cell to be read are turned OFF.

12. A bit line short-circuit switch is provided, connected between the first bit line and the second bit line. The sense amplifier according to claim 11, wherein the bit line short-circuit switch is turned ON when the potentials of the first bit line and the second bit line are converged.

13. A sense amplifier according to any one of claims 1 to 12, The first bit line and, A non-volatile memory device comprising the first memory cell.

Images