Receiving circuit, processing unit, and functional IC

Abstract

To reliably and accurately capture asynchronous signals. [Solution] The receiving circuit (10, 10A, 10B, 10C) includes: a first latch block (1) that generates a first latch signal (SLT1) by latching an input signal (SIN) with a first clock signal (CLK); a second latch block (2) configured to generate a second latch signal (SLT2) by latching an input signal (SIN) at a timing that is out of phase with the second latch signal (SLT1); a third latch block (3) configured to generate a first output signal (S1) by latching the logical OR signal (SOR) of the first latch signal (SLT1) and the second latch signal (SLT2) in accordance with the first clock signal (CLK); and a fourth latch block (4) configured to generate a second output signal (S2) by latching the logical AND signal (SAND) of the first latch signal (SLT1) and the second latch signal (SLT2) in accordance with the first clock signal (CLK).

Description

Technical Field

[0001] The present disclosure relates to a receiving circuit, a processing apparatus using the receiving circuit, and a functional IC including the processing apparatus.

Background Art

[0002] In a semiconductor integrated circuit, signal processing is performed in synchronization with a clock signal. Such a semiconductor integrated circuit may receive an asynchronous input signal. When such an asynchronous input signal is captured using a flip-flop, a metastable state may occur. For example, Patent Document 1 discloses a metastable state removal circuit in which a plurality of D flip-flops are connected in series as a countermeasure against the metastable state (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] When the frequency of the clock signal increases, a metastable state removal circuit in which a plurality of D flip-flops are connected in series may not be able to remove the metastable state, and data capture may become impossible.

[0005] A receiving circuit according to one aspect of the present disclosure includes: a first latch block that generates a first latch signal by latching an input signal at a timing corresponding to a first clock signal; a second latch block configured to generate a second latch signal by latching the input signal at a timing corresponding to the clock signal and with a phase shift relative to the latch timing of the first latch block; an OR block configured to generate a logical OR signal which is the result of the logical OR of the first latch signal and the second latch signal; an AND block configured to generate a logical AND signal which is the result of the logical AND of the first latch signal and the second latch signal; a third latch block configured to generate a first output signal by latching the logical OR signal with the first clock signal; and a fourth latch block configured to generate a second output signal by latching the logical AND signal with the first clock signal. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the overall configuration of the processing unit. [Figure 2] Figure 2 is a schematic diagram showing the general configuration of the receiving circuit. [Figure 3] Figure 3 shows the waveform of the clock signal input to the D flip-flop. [Figure 4] Figure 4 shows the waveforms of each signal during operation when metastable does not occur. [Figure 5] Figure 5 shows the waveforms of each signal during operation in which no metastable occurs, unlike in Figure 4. [Figure 6] Figure 6 shows the waveforms of each signal during the operation in which metastable occurs. [Figure 7] Figure 7 shows the waveforms of each signal when the D flip-flop in the second latch block enters a metastable state. [Figure 8] Figure 8 shows the waveforms of each signal during operation when metastable does not occur. [Figure 9] Figure 9 shows the waveforms of each signal during operation in which no metastable occurs, unlike in Figure 8. [Figure 10]Figure 10 shows the waveforms of each signal during operation when metastable occurs. [Figure 11] Figure 11 shows the waveforms of each signal when the D flip-flop in the second latch block enters a metastable state. [Figure 12] Figure 12 is a schematic diagram of the receiving circuit of the second embodiment. [Figure 13] Figure 13 shows the waveform of the clock signal that drives the D flip-flop used in the receiving circuit shown in Figure 12. [Figure 14] Figure 14 is a schematic diagram of the receiving circuit of the third embodiment. [Figure 15] Figure 15 shows the waveforms of the clock signal and delayed clock signal used in the receiving circuit shown in Figure 14. [Figure 16] Figure 16 is a schematic diagram of the receiving circuit of the fourth embodiment.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are denoted by the same reference numerals, and redundant descriptions relating to the same parts are omitted as a general rule. In this specification, for the sake of simplification of description, symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional parts, circuits, elements, or components corresponding to such symbols or reference numerals may be omitted or abbreviated. For example, the clock signal referred to by "CLK" described later (see Figure 1) may be written as clock signal CLK, or abbreviated as signal CLK or clock CLK, but all of these refer to the same thing.

[0008] Furthermore, some terms used in the description of embodiments of the present invention will be explained. Level refers to the level of electric potential, and for any signal, a high level has a higher potential than a low level. For any signal of interest, when the signal of interest is at a high level, its inverted signal (logical inverted signal) is at a low level, and when the signal of interest is at a low level, its inverted signal (logical inverted signal) is at a high level.

[0009] In any signal, the transition from a low level to a high level is called a rising edge. The rising portion of any signal is also called the rising edge. Similarly, in any signal, the transition from a high level to a low level is called a falling edge. The falling portion of any signal is called the falling edge, and the timing of the falling edge is called the falling timing.

[0010] <First Embodiment> A first embodiment of the present disclosure will be described with reference to the drawings. Figure 1 is a diagram showing the overall configuration of the processing unit 100. The processing unit 100 receives a signal from an external circuit 200 as an input signal SIN. The processing unit 100 includes a receiving circuit 10, a processing circuit 20, and a clock generation circuit 30. The receiving circuit 10 and the processing circuit 20 are configured to operate synchronously based on the clock signal CLK generated by the clock generation circuit 30.

[0011] The processing unit 100 may also be provided as a packaged functional IC (Integrated Circuit). In Figure 1, the functional IC is composed of the processing unit 100, but other components may also be packaged in the same package.

[0012] The input signal SIN supplied from the external circuit 200 to the processing device 100 is an asynchronous signal that is not synchronized with the clock signal CLK. The receiving circuit 10 captures the information included in the input signal SIN, which is an asynchronous signal, as information synchronized with the clock signal CLK. Then, the receiving circuit 10 generates the first output signal S1 and the second output signal S2 synchronized with the clock signal CLK and supplies them to the processing circuit 20.

[0013] Based on the first output signal S1 and the second output signal S2, the processing circuit 20 generates an output signal Sout based on the input signal SIN and outputs the output signal Sout to an external device (not shown).

[0014] The clock generation circuit 30 is a circuit that generates the clock signal CLK. The clock signal CLK is an example of the first clock signal. The clock signal CLK is a rectangular wave signal having a predetermined clock frequency. That is, the signal level of the clock signal CLK periodically switches between the high level and the low level. The clock generation circuit 30 can change the frequency of the clock signal CLK. The clock signal CLK is supplied to the receiving circuit 10 and the processing circuit 20. The receiving circuit 10 and the processing circuit 20 perform signal processing in synchronization with the clock signal CLK.

[0015] Next, the details of the receiving circuit 10 will be described with reference to the drawings. FIG. 2 is a configuration diagram showing the schematic configuration of the receiving circuit 10. As shown in FIG. 2, the receiving circuit 10 includes a first latch block 1, a second latch block 2, a third latch block 3, a fourth latch block 4, an inverter block 5, an OR block 6, and an AND block ⑦.

[0016] In the receiving circuit 10 shown in FIG. 2, the first latch block 1 is composed of, for example, a D flip-flop 11. The second latch block 2 is composed of a D flip-flop 21, the third latch block 3 is composed of a D flip-flop 31, and the fourth latch block 4 is composed of a D flip-flop 41. Note that the D flip-flops 21, 31, and 41 all have the same configuration as the D flip-flop 11.

[0017] Referring to D flip - flop 11 as a representative of D flip - flops 11, 21, 31, and 41, the configuration and operation of the D flip - flop will be described. The D flip - flop 11 has an input terminal (which may also be referred to as the D terminal hereinafter), an output terminal (which may also be referred to as the Q terminal hereinafter), and a clock input terminal.

[0018] A signal having a first logical value or a second logical value is input to the D terminal of the D flip - flop 11, and a signal having a first logical value or a second logical value is output from the Q terminal of the D flip - flop 11. Here, it is assumed that the signal having the first logical value is a low - level signal, and the signal having the second logical value is a high - level signal.

[0019] The D flip - flop 11 is of the positive - edge - trigger type, and latches the logical value of the signal input to the D terminal at the rising timing of the clock signal CLK input to the clock input terminal. Then, the D flip - flop 11 outputs a signal having the latched logical value from the Q terminal. The D flip - flops 21, 31, and 41 have the same configuration as the D flip - flop 11.

[0020] In the receiving circuit 10 shown in FIG. 2, an input signal SIN received from the external circuit 200 is input to the D terminal of the D flip - flop 11 of the first latch block 1. Also, a clock signal CLK is input to the clock terminal of the D flip - flop 11. The D flip - flop 11 latches the logical value of the input signal SIN with the rising edge of the clock signal CLK as a trigger, and outputs the first latch signal SLT1 from the Q terminal.

[0021] The input signal SIN is input to the D terminal of the D flip-flop 21 in the second latch block 2. The clock signal CLK is input to the inverter block 5, and the inverting clock signal CLKB output from the inverter block 5 is input to the clock terminal of the D flip-flop 21. The D flip-flop 21 latches the logic value of the input signal SIN using the rising edge of the inverting clock CLKB as a trigger, and outputs a second latch signal SLT2 with the latched logic value from the Q terminal. Note that the inverting clock signal CLKB is an example of a second clock signal.

[0022] The OR block 6 receives the first latch signal SLT1 and the second latch signal SLT2 as inputs. The OR block 6 then performs a logical OR operation on the first latch signal SLT1 and the second latch signal SLT2. Finally, the OR block 6 outputs the result of the logical OR as the logical OR signal SOR.

[0023] The AND block 7, like the OR block 6, receives the first latch signal SLT1 and the second latch signal SLT2 as inputs. The AND block 7 then performs a logical AND operation on the first latch signal SLT1 and the second latch signal SLT2. Finally, the AND block 7 outputs the result of the logical AND as the logical AND signal SAND.

[0024] The D terminal of the D flip-flop 31 in the third latch block 3 is input with a logical OR signal SOR. The clock terminal of the D flip-flop 31 is input with a clock signal CLK. The D flip-flop 31 latches the logical value of the logical OR signal SOR when triggered by the rising edge of the clock signal CLK, and outputs a first output signal S1 with the latched logical value from the Q terminal.

[0025] A logical AND signal SAND is input to the input terminal of the D flip-flop 41 of the fourth latch block 4. Additionally, a clock signal CLK is input to the clock terminal of the D flip-flop 41. The D flip-flop 41 latches the logical value of the logical AND signal SAND when triggered by the rising edge of the clock signal CLK, and outputs a second output signal S2 containing the latched logical value from the Q terminal.

[0026] The receiving circuit 10 outputs a first output signal S1 and a second output signal S2 to the processing circuit 20. The first output signal S1 is a signal that contains information about the rising edge timing of the input signal SIN, and the second output signal S2 is a signal that contains information about the falling edge timing of the input signal SIN.

[0027] For example, the processing circuit 20 counts the period from the rising edge to the falling edge of the first output signal S1, and based on that information, obtains the length of the high-level period of the input signal SIN. Then, the processing circuit 20 outputs an output signal Sout containing information to control a downstream device (not shown) according to the length of the high-level period of the input signal SIN.

[0028] The processing circuit 20 can be, for example, a circuit that adjusts the output voltage based on the length of the high-level period of the input signal SIN. More specifically, it may be configured to output an output signal Sout that can be controlled to output a higher voltage the longer the high-level period of the input signal SIN is. Furthermore, the output signal Sout is not limited to the above configuration and may be, for example, a drive voltage for driving a downstream device.

[0029] <Operation of the receiving circuit 10> The characteristics of the D flip-flop provided in the receiving circuit 10 will be explained with reference to the drawings. Figure 3 is a waveform diagram of the clock signal CLK input to the D flip-flop.

[0030] In a D flip-flop, the forbidden period Ph is set within the range from the rising edge timing ta1 of the clock signal CLK to the time ta2 before the setup time Tsu, and to the time ta3 after the rising edge timing ta1 has advanced to the hold time Th. In a D flip-flop, if the logic value of the signal input to the D terminal switches during the forbidden period Ph, the signal output from the Q terminal may become unstable, resulting in a so-called metastable state.

[0031] The metastable state converges after a time elapsed, for example, about 10ns, but the signal output from the Q terminal at the time of convergence may be high or low. In other words, when the system is in a metastable state, the output signal from the Q terminal remains unstable until a certain amount of time has elapsed, and even after convergence, an output signal with an incorrect logic value may be output, leading to unstable operation or malfunction of the circuit.

[0032] Therefore, in the functional IC100, which is a synchronization circuit synchronized with the clock signal CLK, the internal signal input to the D terminal of the D flip-flop is designed so that the logic value does not switch during the D flip-flop's forbidden period Ph. Note that the setup time Tsu and hold time Th are predetermined values ​​depending on the configuration of the D flip-flop.

[0033] In the receiving circuit 10, the input signal SIN is a signal from an external circuit 200 outside of the function IC 100. The function IC 100 and the external circuit 200 are often not synchronized circuits. Therefore, the input signal SIN may not be synchronized with the clock signal CLK. In other words, the logic value of the input signal SIN may switch to the forbidden period Ph of the D flip-flop 11 to which the input signal SIN is input.

[0034] The receiving circuit 10 is configured to reliably and accurately detect the rising and falling edges of the input signal SIN, even when the logic value of the input signal SIN switches to the forbidden period Ph of the D flip-flop 11. Note that detecting the timing of the rising and falling edges of the input signal SIN is sometimes referred to as "acquiring the input signal."

[0035] The following describes the operation of the receiving circuit 10 to capture the input signal SIN, with reference to the diagram. First, we will explain how to capture the rising edge of the input signal SIN. Figure 4 shows the waveforms of each signal during operation when metastable does not occur.

[0036] As shown in Figure 4, the input signal SIN rises to a high level at time t1. Time t1 is before the blackout period of the D flip-flop 11 in the first latch block 1. Note that during the period prior to time t1, both the first latch signal SLT1 and the second latch signal SLT2 are assumed to be at a low level.

[0037] At time t11, which is later than time t1, the clock signal CLK rises to a high level. As a result, the D flip-flop 11 latches a high-level logic value. At time t12, which is delayed from time t11, the first latch signal SLT1 rises to a high level. Note that time t12 can be, for example, after the hold time Th of the D flip-flop 11 has elapsed.

[0038] Furthermore, at time t11, the inverting clock signal CLKB is on its falling edge, and the logic value (low level in this case) latched by the D flip-flop 21 does not change. Therefore, the second latch signal SLT2 remains at a low level.

[0039] At time t12, OR block 6 receives a high-level first latch signal SLT1 and a low-level second latch signal SLT2. As a result, at time t12, the logical OR signal SOR rises to a high level.

[0040] Furthermore, at time t12, AND block 7 receives a high-level first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical AND signal SAND remains at a low level at time t12.

[0041] At time t13, which is later than time t12, the inverting clock signal CLKB rises to a high level. As a result, the D flip-flop 21 latches a high logic value. At time t14, which is delayed from time t13, the second latch signal SLT2 rises to a high level.

[0042] At time t14, the second latch signal SLT2, which is input to OR block 6 and AND block 7, rises to a high level.

[0043] At time t14, OR block 6 receives a high-level first latch signal SLT1 and a high-level second latch signal SLT2. As a result, the logical OR signal SOR remains at a high level at time t14.

[0044] At time t14, AND block 7 receives a high-level first latch signal SLT1 and a high-level second latch signal SLT2. As a result, at time t14, the logical AND signal SAND rises to a high level.

[0045] At time t15, which is later than time t14, the logical OR signal SOR is at a high level, and the D flip-flop 31 latches the high-level logic value. Then, at time t16, which is delayed from time t15, the first output signal S1 output from the D flip-flop 31 rises to a high level.

[0046] Furthermore, at time t15, the logical AND signal SAND is at a high level. As a result, the D flip-flop 41 latches the high-level logic value. Then, at time t16, which is delayed from time t15, the second output signal S2 output from the D flip-flop 41 rises to a high level.

[0047] The first output signal S1 and the second output signal S2 are input to the processing circuit 20. As will be described in detail later, the processing circuit 20 determines the rising edge timing of the input signal SIN based on the first output signal S1, and determines the falling edge timing of the input signal SIN based on the second output signal S2.

[0048] Next, we will describe another example of operation in which metastable does not occur. Figure 5 shows the waveforms of each signal during operation in which metastable does not occur, different from Figure 4.

[0049] As shown in Figure 5, the input signal SIN is assumed to rise to a high level at time t2, which is later than time t12. Note that time t2 is between time t11 and time t13, and is outside the blackout period for D flip-flop 11 in the first latch block 1 and D flip-flop 21 in the second latch block 2. Therefore, the outputs of D flip-flop 11 and D flip-flop 21 do not enter a metastable state.

[0050] The input signal SIN rises to a high level at time t2. Later, at time t13, the inverting clock signal CLKB rises to a high level. As a result, the D flip-flop 21 latches a high-level logic value. Then, at time t14, delayed from time t13, the second latch signal SLT2 output from the D flip-flop 21 rises to a high level.

[0051] Furthermore, at time t13, the clock signal CLK is on its falling edge, and the logic value (low level in this case) latched by the D flip-flop 11 does not change. Therefore, the first latch signal SLT1 remains at a low level.

[0052] At time t14, OR block 6 receives a low-level first latch signal SLT1 and a high-level second latch signal SLT2. As a result, at time t14, the logical OR signal SOR rises to a high level.

[0053] Furthermore, at time t14, AND block 7 receives a low-level first latch signal SLT1 and a high-level second latch signal SLT2. As a result, the logical AND signal SAND remains at a low level at time t14.

[0054] At time t15, which is later than time t14, the logical OR signal SOR is at a high level. As a result, the D flip-flop 31 latches the high-level logic value. Then, at time t16, which is delayed from time t15, the first output signal S1 output from the D flip-flop 31 rises to a high level.

[0055] Furthermore, at time t15, the logical AND signal SAND is at a low level. As a result, the logic value latched by the D flip-flop 41 does not change. Therefore, the second output signal S2 output from the D flip-flop 41 is maintained at a low level.

[0056] At time t15, the clock signal CLK rises to a high level. As a result, the D flip-flop 11 latches a high-level logic value. Then, at time t16, which is delayed from time t15, the first latch signal SLT1 output from the D flip-flop 11 rises to a high level. Therefore, at time t16, which is later than time t15, the logical AND signal SAND rises to a high level.

[0057] At time t17, which is later than time t16, the clock signal CLK rises to a high level. At this time, the first output signal S1 is maintained at a high level.

[0058] Furthermore, at time t17, the logical AND signal SAND is at a high level. As a result, the D flip-flop 41 latches the high-level logic value. Then, at time t18, which is delayed from time t17, the second output signal S2 output from the D flip-flop 41 rises to a high level.

[0059] The first output signal S1 and the second output signal S2 are then input to the processing circuit 20.

[0060] An example of when metastable occurs is described. Figure 6 shows the waveforms of each signal during an operation in which metastable occurs. As shown in Figure 6, the input signal SIN rises to a high level at time t3, which is included in the forbidden period that includes time t11. The first latch signal SLT1 output from the D flip-flop 11 enters a metastable state. Note that in Figure 6, the first latch signal SLT1 is oscillating, but is not limited to this. Since the output signal in a metastable state cannot be determined to be either high or low, the logical value of the output signal in a metastable state is considered undefined. In other words, undefined is a state between high and low levels.

[0061] In OR block 6 and AND block 7, a high level is determined when the input signal is above a predetermined threshold. Therefore, when an undefined signal is input to OR block 6 and AND block 7, if the input signal is above the threshold, it becomes a high-level input, and if it is below the threshold, it becomes a low-level input, and the logical OR signal SOR and logical AND signal SAND may become undefined. When the logical OR signal SOR and logical AND signal SAND are undefined, they alternate between high and low levels in a short period of time (see Figure 6, etc.).

[0062] At time t3, the first latch signal SLT1, which is input to OR block 6 and AND block 7, is in a metastable state and is undefined. The metastable state of the first latch signal SLT1 may persist until the rising edge timing of the next clock signal CLK, i.e., time t15. Here, we will describe the case where it persists until time t15.

[0063] Furthermore, at time t3, the inverting clock signal CLKB is on its falling edge and is outside the forbidden period of the D flip-flop 21. Therefore, the output of the D flip-flop 21 does not enter a metastable state. In other words, the second latch signal SLT2 is maintained at a low level. At time t11, the second latch signal SLT2 input to the OR block 6 and AND block 7 is at a low level.

[0064] At time t3, OR block 6 receives an undefined first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical OR signal SOR is undefined at time t3. OR block 6 outputs an undefined logical OR signal SOR until time t14.

[0065] Furthermore, at time t3, AND block 7 receives an undefined first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical AND signal SAND is kept at a low level at time t3.

[0066] At time t13, which is later than time t11, the inverting clock signal CLKB rises to a high level. As a result, the D flip-flop 21 latches a high-level logic value. Then, at time t14, which is delayed from time t13, the second latch signal SLT2 output from the D flip-flop 21 rises to a high level.

[0067] At time t14, OR block 6 receives an undefined first latch signal SLT1 and a high-level second latch signal SLT2. As a result, the logical OR signal SOR rises to a high level.

[0068] Furthermore, at time t14, AND block 7 receives an undefined first latch signal SLT1 and a high-level second latch signal SLT2. As a result, the logical AND signal SAND becomes undefined.

[0069] At time t15, the logical OR signal SOR is at a high level, and the D flip-flop 31 latches the high-level logic value. Then, at time t16, which is delayed from time t15, the first output signal S1 output from the D flip-flop 31 rises to a high level.

[0070] On the other hand, at time t15, the logical AND signal SAND is undefined. Therefore, at time t15, the second output signal S2, which is output when the D flip-flop 41 latches the logical value of the logical AND signal SAND, is undefined, or in other words, in a metastable state.

[0071] The first output signal S1 and the second output signal S2 are then input to the processing circuit 20. At time t16, the second output signal S2 is undefined, but the first output signal S1 rises to a high level.

[0072] In other words, regardless of whether the input signal SIN rises to a high level at time t1 before time t11, time t2 after time t12, or time t3 which falls within the forbidden period near time t11, the first output signal S1 will rise to a high level at time t16.

[0073] In the receiving circuit 10, if the input signal SIN rises between time t10, which is the falling edge timing of the clock signal CLK immediately before time t11, and time t13, which is the falling edge timing of the clock signal CLK immediately after time t11, the first output signal S1 rises to a high level at time t16. In other words, if the phase difference of the rising edge timing of the input signal SIN is within one period of the clock signal CLK, the rising edge timing when synchronized with the clock signal CLK can be set to the same time t16.

[0074] Furthermore, even if the D flip-flop 11 enters a metastable state, the receiving circuit 10 can output a first output signal S1 that rises to a high level at the same timing (time t16) as when it does not enter a metastable state.

[0075] Note that the second output signal S2 may remain in a metastable state until time t15. As described above, the processing circuit 20 detects the rising edge timing of the input signal SIN based on the first output signal S1, so even if the second output signal S2 is in a metastable state, the rising edge timing of the input signal SIN can be accurately detected. In other words, the first output signal S1 is used to detect the rising edge timing of SIN.

[0076] Next, we will explain the case where the D flip-flop 21 of the second latch block 2 enters a metastable state. Figure 7 shows the waveforms of each signal when the D flip-flop 21 of the second latch block 2 enters a metastable state.

[0077] As shown in Figure 7, the input signal SIN rises to a high level at time t3b, which is included in the forbidden period that includes time t13. The second latch signal SLT2 output from the D flip-flop 21 enters a metastable state. At time t3b, the second latch signal SLT2 input to OR block 6 and AND block 7 is undefined. Note that the second latch signal SLT2 may continue until time t110, which is the rising edge timing of the inverting clock signal CLKB. Here, we will describe the case where the second latch signal SLT2 continues until time t110. Note that the second latch signal SLT2 rises to a high level at a timing delayed from time t110.

[0078] At time t13, the clock signal CLK is on its falling edge and is outside the forbidden period of the D flip-flop 11. Therefore, the output of the D flip-flop 11 does not enter a metastable state. That is, the first latch signal SLT1 output from the D flip-flop 11 is maintained at a low level. At time t3b, the first latch signal SLT1 input to the OR block 6 and AND block 7 is at a low level.

[0079] At time t3b, OR block 6 receives a low-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, at time t13, the logical OR signal SOR is undefined. OR block 6 outputs the undefined logical OR signal SOR until time t15.

[0080] Furthermore, at time t3b, AND block 7 receives a low-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical AND signal SAND is kept at a low level.

[0081] At time t15, which is later than time t13, the clock signal CLK rises to a high level. As a result, the D flip-flop 11 latches a high-level logic value. Then, at time t16, which is delayed from time t15, the first latch signal SLT1 output from the D flip-flop 11 rises to a high level.

[0082] At time t15, OR block 6 receives a low-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical OR signal SOR is undefined at time t15. Therefore, the first output signal S1, which is output when the D flip-flop 31 latches the logical value of the logical OR signal SOR, is in a metastable state, i.e., undefined. This metastable state may persist until time t17, which is the rising edge timing of the next clock signal CLK. The case where the first output signal S1 remains metastable until time t17 will be explained below.

[0083] Furthermore, at time t15, the AND block 7 receives a low-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical AND signal SAND is low level. Therefore, at time t15, the logical AND signal SAND is low level. Consequently, the D flip-flop 41 latches the logical value of the logical AND signal SAND, and the output first output signal S1 is low level.

[0084] At time t17, which is later than time t16, the logical OR signal SOR is maintained at a high level. As a result, the D flip-flop 31 latches the high-level logic value. Then, at time t18, which is delayed from time t17, the first output signal S1 output from the D flip-flop 31 rises to a high level.

[0085] Furthermore, at a time delayed from t110, the second latch signal SLT2 rises to a high level, and at the same time, the logical AND signal SAND also rises to a high level. As a result, at time t17, the logical AND signal SAND remains at a high level. This causes the D flip-flop 41 to latch a high-level logic value. Then, at time t18, delayed from time t17, the second output signal S2 output from the D flip-flop 41 rises to a high level.

[0086] The first output signal S1 and the second output signal S2 are input to the processing circuit 20. At time t18, the first output signal S1 rises to a high level.

[0087] As described above, in the receiving circuit 10 according to this embodiment, the D flip-flop 11 of the first latch block 1 and the D flip-flop 21 of the second latch block 2 latch the logic value of the signal at the Q terminal by triggering the rising edge of the clock signal CLK and the inverted clock signal CLKB, which are out of phase by half a wavelength. Therefore, metastable conditions do not occur simultaneously in both the D flip-flop 11 and the D flip-flop 21 in the receiving circuit 10. Furthermore, when receiving the asynchronous signal SIN, even if either the first latch signal SLT1 or the second latch signal SLT2 becomes metastable, the rising edge timing of the input signal SIN can be accurately detected based on the first output signal S1.

[0088] Next, we will explain the case where the input signal SIN falls to a low level. Figure 8 shows the waveforms of each signal during operation when metastable does not occur.

[0089] As shown in Figure 8, the input signal SIN falls to a low level at time t4. Time t4 is before the blackout period, which includes time t21 of the D flip-flop 11 in the first latch block 1. It is assumed that both the first latch signal SLT1 and the second latch signal SLT2 are at a high level during the period prior to time t4.

[0090] At time t21, which is later than time t4, the clock signal CLK rises to a high level. As a result, the D flip-flop 11 latches a low-level logic value. Then, at time t22, which is delayed from time t21, the first latch signal SLT1 output from the D flip-flop 11 falls to a low level.

[0091] Furthermore, at time t21, the inverting clock signal CLKB is on its falling edge, and the logic value (high level in this case) latched by the D flip-flop 21 does not change. Therefore, the second latch signal SLT2 output from the D flip-flop 21 remains at a high level.

[0092] At time t22, OR block 6 receives a low-level first latch signal SLT1 and a high-level second latch signal SLT2. As a result, the logical OR signal SOR remains at a high level at time t22.

[0093] Furthermore, at time t22, AND block 7 receives a low-level first latch signal SLT1 and a high-level second latch signal SLT2. As a result, at time t22, the logical AND signal SAND falls to a low level.

[0094] At time t23, which is later than time t22, the inverting clock signal CLKB rises to a high level. As a result, the D flip-flop 21 latches a low-level logic value. Then, at time t24, which is delayed from time t23, the second latch signal SLT2 output from the D flip-flop 21 falls to a low level.

[0095] At time t24, OR block 6 receives a low-level first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical OR signal SOR falls to a low level at time t24. Also at time t24, AND block 7 receives a low-level first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical AND signal SAND remains at a low level at time t24.

[0096] At time t25, which is later than time t24, the clock signal CLK rises to a high level. At time t25, the logical OR signal SOR is at a low level, and the D flip-flop 31 latches the low-level logic value. As a result, at time t26, which is delayed from time t15, the first output signal S1 output from the D flip-flop 11 falls to a low level.

[0097] Furthermore, at time t25, the logical AND signal SAND is at a low level, and the D flip-flop 41 latches the low-level logic value. As a result, at time t26, which is delayed from time t25, the second output signal S2 output from the D flip-flop 41 falls to a low level.

[0098] The first output signal S1 and the second output signal S2 are then input to the processing circuit 20.

[0099] Next, we will describe another example where metastable does not occur. Figure 9 shows the waveforms of each signal during operation in which metastable does not occur, unlike in Figure 8.

[0100] As shown in Figure 9, the input signal SIN falls to a low level at time t5, which is later than time t21. Note that time t5 is outside the blackout period for the D flip-flop 11 of the first latch block 1 and the D flip-flop 21 of the second latch block 2. Therefore, the outputs of the D flip-flops 11 and 21 do not enter a metastable state.

[0101] The input signal SIN falls to a low level at time t5. At time t23, which is later than time t5, the inverting clock signal CLKB rises to a high level. As a result, the D flip-flop 21 latches a low-level logic value. Then, at time t24, which is delayed from time t23, the second latch signal SLT2 output from the D flip-flop 21 falls to a low level.

[0102] Furthermore, at time t23, the clock signal CLK is on its falling edge, and the logic value (low level in this case) latched by the D flip-flop 11 does not change. Therefore, the first latch signal SLT1 remains at a high level.

[0103] At time t24, OR block 6 receives a high-level first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical OR signal SOR remains at a high level at time t24.

[0104] Furthermore, at time t24, AND block 7 receives a high-level first latch signal SLT1 and a low-level second latch signal SLT2. As a result, at time t24, the logical AND signal SAND falls to a low level.

[0105] At time t25, which is later than time t24, the clock signal CLK rises to a high level. At time t25, the logical AND signal SAND is at a low level, and the D flip-flop 41 latches the low-level logic value. As a result, at time t26, which is delayed from time t25, the second output signal S2 output from the D flip-flop 41 falls to a low level.

[0106] At time t25, the D flip-flop 11 latches a low-level logic value. As a result, at time t26, which is delayed from time t25, the first latch signal SLT1 falls to a low level. Also at time t26, the OR block 6 receives the low-level first latch signal SLT1 and the low-level second latch signal SLT2 as inputs. As a result, at time t26, the logical OR signal SOR falls to a low level. Since time t26 is after time t25, which is the rising edge timing of the clock signal CLK, at time t25, the D flip-flop 31 latches a high-level logic value. Therefore, the first output signal S1 remains high level even after time t26.

[0107] Then, at time t27, which is later than time t26, the clock signal CLK rises to a high level. At this time, the second output signal S2 output from the D flip-flop 31 is maintained at a low level.

[0108] Furthermore, at time t27, a low-level logical OR signal SOR is input to the D flip-flop 31. As a result, the D flip-flop 31 latches a low-level logic value. Then, at time t28, which is delayed from time t27, the first output signal S1 output from the D flip-flop 31 falls to a low level.

[0109] The first output signal S1 and the second output signal S2 are then input to the processing circuit 20.

[0110] Let's look at an example of when metastable occurs. Figure 10 shows the waveforms of each signal during operation when metastable occurs.

[0111] As shown in Figure 10, the input signal SIN falls to a low level at time t6 within the blackout period which includes time t21. Note that at time t21, the inverting clock signal CLKB is falling, and at time t6, it is outside the blackout period for the inverting clock CLKB in the D flip-flop 21 of the second latch block 2. Therefore, the output of the D flip-flop 21 does not enter a metastable state.

[0112] Time t6 falls within the blackout period of the D flip-flop 11, which includes time t21. The input signal SIN falls to a low level within this blackout period. Therefore, the first latch signal SLT1 output from the D flip-flop 11 is in a metastable state and is undefined. The metastable state of the first latch signal SLT1 may persist until the rising edge timing of the next clock signal CLK, i.e., time t25. Here, we will describe the case where it persists until time t25.

[0113] Furthermore, at time t6, the inverting clock signal CLKB is on its falling edge, and the logic value (high level in this case) latched by the D flip-flop 21 does not change. Therefore, the second latch signal SLT2 output from the D flip-flop 21 remains at a high level.

[0114] At time t6, OR block 6 receives an undefined first latch signal SLT1 and a high-level second latch signal SLT2. As a result, the logical OR signal SOR is high at time t6. OR block 6 outputs the high-level logical OR signal SOR until time t24.

[0115] Furthermore, at time t21, the AND block 7 receives an undefined first latch signal SLT1 and a high-level second latch signal SLT2. In other words, at time t21, the logical AND signal SAND is undefined. Therefore, at time t21, the D flip-flop 41 latches the logical value of the logical AND signal SAND, and the second output signal S2 output from the D flip-flop 41 becomes metastable, i.e., undefined. This metastable state persists until time t25, which is the rising edge timing of the next clock signal CLK.

[0116] At time t23, which is later than time t21, the inverting clock signal CLKB rises to a high level. As a result, the D flip-flop 21 latches a low-level logic value. Then, at time t24, which is delayed from time t23, the second latch signal SLT2 output from the D flip-flop 21 falls to a low level.

[0117] At time t24, OR block 6 receives an undefined first latch signal SLT1 and a low-level second latch signal SLT2. As a result, the logical OR signal SOR becomes undefined.

[0118] Furthermore, at time t24, AND block 7 receives an undefined first latch signal SLT1 and a low-level second latch signal SLT2. Therefore, at time t24, the logical AND signal SAND switches from undefined to low level.

[0119] At time t25, the logical AND signal SAND is at a low level, and the D flip-flop 41 latches the low-level logic value. Then, at time t26, which is delayed from time t25, the second output signal S2 output from the D flip-flop 41 falls to a low level.

[0120] On the other hand, at time t25, the logical OR signal SOR is undefined. Therefore, at time t15, the first output signal S1, which is output when the D flip-flop 31 latches the logical value of the logical AND signal SAND, is undefined, or in other words, in a metastable state.

[0121] The first output signal S1 and the second output signal S2 are then input to the processing circuit 20. At time t26, the first output signal S1 is undefined, but the second output signal S2 falls to a low level.

[0122] In other words, regardless of whether the input signal SIN falls to a low level at time t4 before time t21, time t5 after time t22, or time t6 which falls within the forbidden period near time t21, the second output signal S2 will fall to a low level at time t26.

[0123] In the receiving circuit 10, if the input signal SIN falls between time t20, which is the falling edge timing of the clock signal CLK immediately before time t21, and time t23, which is the falling edge timing of the clock signal CLK immediately after time t21, the second output signal S2 falls to a low level at time t26. In other words, if the phase difference of the rising edge timing of the input signal SIN is within one period of the clock signal CLK, the falling edge timing can be the same as time t26 when synchronized with the clock signal CLK.

[0124] Furthermore, even if the first latch signal SLT1 output from the D flip-flop 11 enters a metastable state, the receiving circuit 10 can output a second output signal S2 that falls to a low level at the same timing (time t26) as when it does not enter a metastable state.

[0125] Furthermore, the first output signal S1 may remain in a metastable state even after time t24. As described above, the receiving circuit 10 is configured to detect the falling edge timing of the input signal SIN based on the second output signal S2, so even if the metastable state of the first output signal S1 continues, the falling edge timing of the input signal SIN can be accurately detected.

[0126] Furthermore, when the input signal SIN rises between time t10 and time t13, the processing circuit 20 acquires time t16 as the rising edge timing. Also, when the input signal SIN falls between time t20 and time t23, the processing circuit 20 acquires time t26 as the falling edge timing.

[0127] At this time, the processing circuit 20 can determine that the period from time t16 to time t26 is a period in which the input signal SIN is at a high level. In other words, it determines that the period from time t16 to time t26 is the time in which the input signal SIN is at a high level. As a result, even if the high-level period of the input signal SIN is shifted by one cycle of the clock signal CLK, if the length of the high-level period is the same for the input signals SIN, the high-level period of the input signal SIN can be obtained as having the same length. This suppresses the change in the information obtained depending on the timing of acquisition when acquiring an input signal SIN that is not synchronized with the clock signal CLK. This makes it possible to improve the accuracy of the output signal Sout output from the processing circuit 20.

[0128] Alternatively, the processing circuit 20 may estimate time t11 from time t16 to determine the rising edge timing, and estimate time t21 from time t26 to determine the falling edge timing.

[0129] In the receiving circuit 10 according to this embodiment, the trigger timing of the first latch block 1, that is, the rising edge timing of the clock signal CLK, and the trigger timing of the second latch block 2, that is, the rising edge timing of the inverted clock signal CLKB, are sufficiently far apart in time. Therefore, even if one of the input signals SIN enters a metastable state when it rises or falls at a certain time, both will not enter a metastable state. Thus, in the receiving circuit 10 of this embodiment, even when the second latch block 2 enters a metastable state, the rising and falling edge timings of the input signal SIN, which is asynchronous with respect to the clock signal CLK, can be acquired with high accuracy.

[0130] Next, we will explain the case where the D flip-flop 21 of the second latch block 2 enters a metastable state. Figure 11 shows the waveforms of each signal when the D flip-flop 21 of the second latch block 2 enters a metastable state.

[0131] As shown in Figure 11, the input signal SIN falls to a low level at time t6b, which is included in the forbidden period that includes time t23. The second latch signal SLT2 output from the D flip-flop 21 enters a metastable state. At time t6b, the second latch signal SLT2 is undefined.

[0132] At time t6b, the clock signal CLK is on its falling edge, and time t6b is outside the forbidden period for the D flip-flop 11. Therefore, the output of the D flip-flop 11 does not enter a metastable state. In other words, the first latch signal SLT1 output from the D flip-flop 11 is maintained at a high level.

[0133] At time t6b, OR block 6 receives a high-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical OR signal SOR is high at time t6b. Also at time t6b, AND block 7 receives a high-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical AND signal SAND is undefined at time t6b.

[0134] At time t25, which is later than time t23, the clock signal CLK rises to a high level. As a result, the D flip-flop 11 latches a low-level logic value. Then, at time t26, which is delayed from time t25, the first latch signal SLT1 output from the D flip-flop 11 falls to a low level.

[0135] At time t26, OR block 6 receives a low-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical OR signal SOR changes from a high level to undefined. Also at time t26, AND block 7 receives a low-level first latch signal SLT1 and an undefined second latch signal SLT2. As a result, the logical AND signal SAND falls to a low level. Furthermore, since the logical OR signal SOR becomes undefined, the first output signal S1 enters a metastable state from time t23 onward.

[0136] At time t210, which is later than time t25, the inverting clock signal CLKB rises to a high level. At this time, the input signal SIN is at a low level, and the D flip-flop 11 latches the low-level logic value. Then, at time t26, which is delayed from time t25, the first latch signal SLT1 output from the D flip-flop 21 falls to a low level.

[0137] At time t27, which is later than time t210, the clock signal CLK rises to a high level. At this time, the logical AND signal SAND is maintained at a low level. As a result, the D flip-flop 41 latches the low-level logic value. Then, at time t28, which is delayed from time t27, the second output signal S2 output from the D flip-flop 41 falls to a low level.

[0138] As described above, in the receiving circuit 10 according to this embodiment, the D flip-flop 11 of the first latch block 1 and the D flip-flop 21 of the second latch block 2 latch logic values ​​triggered by the rising edge of the clock signal CLK and the inverted clock signal CLKB, which are out of phase by half a wavelength. Therefore, metastable conditions do not occur simultaneously in both the D flip-flop 11 and the D flip-flop 21. As a result, when acquiring the asynchronous signal SIN, even if either the first latch signal SLT1 or the second latch signal SLT2 becomes metastable, the falling edge timing of the input signal SIN can be accurately detected based on the first output signal S1.

[0139] The processing circuit 20 captures the rising edge timing of the input signal SIN based on the rising edge timing of the first output signal S1. In other words, when capturing the rising edge timing, it is based on the timing when the logical OR signal SOR, which is formed by the logical OR of the first latch signal SLT1 and the second latch signal SLT2, rises to a high level. Therefore, if at least one of the first latch signal SLT1 and the second latch signal SLT2 is at a high level, the logical OR signal SOR will rise to a high level even if the other is at a low level, or even undefined, and thus the rising edge timing of the input signal SIN can be captured.

[0140] Therefore, in the receiving circuit 10, if the frequency of the clock signal CLK is increased, for example, the metastable state may not converge by the next trigger timing. In other words, one of the first latch signal SLT1 and the second latch signal SLT2 may remain in a metastable state. Even in such a case, the other signal will not become metastable.

[0141] Therefore, by using the receiving circuit 10, even if one of the first latch signal SLT1 and the second latch signal SLT2 remains in a metastable state, the rising edge timing of the input signal SIN can be reliably and accurately captured. The clock signal CLK and the inverting clock signal CLKB are set so that the forbidden period Ph of the D flip-flop 11 and the forbidden period Ph of the D flip-flop 21 do not overlap. In other words, it is possible to increase the frequency of the clock signal CLK and the inverting clock signal CLKB while ensuring that the forbidden period Ph of the D flip-flop 11 and the forbidden period Ph of the D flip-flop 21 do not overlap.

[0142] Furthermore, the processing circuit 20 captures the falling edge timing of the input signal SIN based on the falling edge timing of the second output signal S2. In other words, when capturing the falling edge timing, it is based on the timing when the logical AND signal SAND, which is formed by the logical AND of the first latch signal SLT1 and the second latch signal SLT2, falls to a low level. Therefore, if at least one of the first latch signal SLT1 and the second latch signal SLT2 is at a low level, the logical AND signal SAND falls to a low level even if the other is at a high level, or even undefined, so the falling edge timing of the input signal SIN can be captured.

[0143] Therefore, by using the receiving circuit 10, even if one of the first latch signal SLT1 and the second latch signal SLT2 remains in a metastable state, the falling edge timing of the input signal SIN can be reliably and accurately captured.

[0144] <Second Embodiment> Figure 12 is a schematic diagram of the receiving circuit 10A of the second embodiment. Figure 13 is a waveform diagram of the clock signal CLKC that drives the D flip-flop used in the receiving circuit 10A shown in Figure 12. As shown in Figure 12, the receiving circuit 10A of the second embodiment differs from the receiving circuit 10 in that the first latch block 1A, second latch block 2A, third latch block 3A, and fourth latch block 4A are different from the first latch block 1, second latch block 2, third latch block 3, and fourth latch block 4 of the receiving circuit 10. In other respects of the receiving circuit 10A, it has the same configuration as the receiving circuit 10, and the same reference numerals are used for substantially the same parts, and a detailed explanation of the same parts is omitted.

[0145] The first latch block 1A, second latch block 2A, third latch block 3A, and fourth latch block 4A of the receiving circuit 10A shown in Figure 12 each have D flip-flops 12, 22, 32, and 42, respectively. All of the D flip-flops 12, 22, 32, and 42 are negative-triggered flip-flops. That is, as shown in Figure 13, the D flip-flops 12, 22, 32, and 42 are triggered by the falling edge of the input clock signal CLKC and latch the logic value of the signal input to the D terminal. Then, until the falling edge of the next clock signal is input, they output an output signal with the latched logic value from the Q terminal.

[0146] Even in a receiving circuit 10A using a first latch block 1A, a second latch block 2A, a third latch block 3A, and a fourth latch block 4A, each having D flip-flops 12, 22, 32, and 42, it is possible to accurately capture an asynchronous input signal SIN in synchronization with the clock signal CLK, similar to receiving circuit 10.

[0147] <Third Embodiment> Figure 14 is a schematic diagram of the receiving circuit 10B of the third embodiment. Figure 15 is a waveform diagram of the clock signal CLK and the delayed clock signal CLKD used in the receiving circuit 10B shown in Figure 14. As shown in Figure 14, the receiving circuit 10B of the third embodiment differs from the receiving circuit 10 in that it uses a buffer block 8 instead of an inverter block 5. In all other respects of the receiving circuit 10B, it has the same configuration as the receiving circuit 10, and the same parts are denoted by the same reference numerals, and detailed explanations of the same parts are omitted.

[0148] As described above, the receiver circuit 10B can operate if the prohibition period of the D flip-flop 11 and the prohibition period of the D flip-flop 21 do not overlap. Therefore, the receiver circuit 10B generates a delayed clock signal CLKD by delaying the clock signal CLK in the buffer block 8. The D flip-flop 11 in the first latch block 1 is triggered by the rising edge of the clock signal CLK, and the D flip-flop 21 in the second latch block 2 is triggered by the rising edge of the delayed clock signal CLKD.

[0149] As shown in Figure 15, the buffer block 8 generates a delayed clock signal CLKD so that the forbidden period Ph1 of the D flip-flop 11 and the forbidden period Ph2 of the D flip-flop 21 do not overlap. In this way, even if one of the D flip-flops 11 or 21 enters a metastable state, the other will not. Therefore, the receiving circuit 10B can reliably and accurately acquire the rising edge timing to high level and the falling edge timing to low level of the asynchronous input signal SIN, even if one of the D flip-flops 11 or 21 enters a metastable state.

[0150] The delayed clock signal CLKD, delayed by buffer block 8, should be such that the forbidden period Ph2 of D flip-flop 21, including the rising edge timing, does not overlap with the forbidden period Ph1 of D flip-flop 11. Such a delay time Td can be, for example, 1 ns or more, but is not limited to this. Note that a configuration with a half-period shift can be handled by an inverter block. Therefore, the delay time Td by buffer block 8 may be less than half a period of the clock signal CLK. Note that the delay time Td is just an example, and a wide range of times can be adopted where the forbidden periods Ph1 and Ph2 do not overlap.

[0151] <Fourth Embodiment> Figure 16 is a schematic diagram of the receiving circuit 10C of the fourth embodiment. As shown in Figure 16, the receiving circuit 10C of the fourth embodiment differs from the receiving circuit 10 in that it uses a second latch block 2A instead of the second latch block 2 and omits the inverter block 5. In all other respects of the receiving circuit 10C, it has the same configuration as the receiving circuit 10, and the same parts are denoted by the same reference numerals, and detailed explanations of the same parts are omitted.

[0152] As shown in Figure 16, in the receiving circuit 10C, the first latch block 1, which receives the input signal SIN, has a positively triggered D flip-flop 11, and the second latch block 2A has a negatively triggered D flip-flop 22. In other words, the same clock signal CLK is input to the clock terminal of the D flip-flop 11 and the clock terminal of the D flip-flop 22.

[0153] The D flip-flop 11 is triggered by the rising edge of the clock signal CLK, and the D flip-flop 21 is triggered by the falling edge of the clock signal CLK. Therefore, the trigger timing of the D flip-flop 11 and the trigger timing of the D flip-flop 21 are out of phase by half a period of the clock signal CLK. As a result, even if one of the D flip-flops, 11 or 21, becomes metastable due to the rising edge timing of the input signal SIN, the other will not become metastable.

[0154] In other words, in the receiving circuit 10C, the first latch signal SLT1 and the second latch signal SLT2 operate in the same state as in the receiving circuit 10. Therefore, even when using the receiving circuit 10C, the rising and falling timings of the asynchronous input signal SIN can be reliably and accurately captured.

[0155] <Other> The embodiments described above should be considered illustrative and not restrictive in all respects, and the technical scope of the present invention is indicated by the claims rather than by the description of the embodiments described above, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0156] <Note> The various embodiments described above will be summarized below.

[0157] The receiving circuit described above (10, 10A, 10B, 10C) includes a first latch block (1, 1A) that generates a first latch signal (SLT1) by latching the input signal (SIN) at a timing corresponding to the clock signal (CLK), A second latch block (2, 2A) is configured to generate a second latch signal (SLT2) that latches the input signal (SIN) at a timing corresponding to the clock signal (CLK) and at a timing that is phase-shifted with respect to the latch timing of the first latch block (1). An OR block (6) is configured to generate a logical OR signal (SOR), which is the result of the logical OR of a first latch signal (SLT1) and a second latch signal (SLT2), An AND block (7) is configured to generate a logical AND signal (SAND), which is the result of the logical AND of a first latch signal (SLT1) and a second latch signal (SLT2), A third latch block (3, 3A) is configured to generate a first output signal (S1) by latching a logical OR signal (SOR) at a timing corresponding to the clock signal (CLK), The configuration (first configuration) includes a fourth latch block (4, 4A) configured to generate a second output signal (S2) by latching a logical AND signal (SAND) at a timing corresponding to the clock signal (CLK).

[0158] In the receiving circuit (10, 10A, 10B) of the first configuration described above, the first latch block (1, 1A), the second latch block (2, 2A), the third latch block (3, 3A), and the fourth latch block (4, 4A) are all composed of either positive triggers (11, 21, 31, 41) or negative triggers (12, 22, 32, 42) (second configuration).

[0159] In the receiving circuit (10C) of the first configuration described above, the first latch block (1) and the second latch block (2) are configured such that one is a positive trigger (11, 21) and the other is a negative trigger (12, 22). The third latch block (3) and the fourth latch block (4) are both composed of positive triggers (31, 41) or negative triggers (32, 42) (third configuration).

[0160] In the receiving circuits (10, 10A, 10B) of the first or second configuration described above, the second latch block (2, 2A) is configured to receive a second clock signal (CLKB, CLKD) which is generated based on the first clock signal (CLK) and is out of phase with respect to the first clock signal (CLK) (fourth configuration).

[0161] In the receiving circuit (10, 10A) of the fourth configuration described above, the second clock signal (CLKB) is composed of an inverted clock signal (CLKB), which is the inverted signal of the clock signal (CLK) (fifth configuration).

[0162] In the receiving circuit (10B) of the fourth configuration described above, the second clock signal (CLKC) is configured to be out of phase with respect to the clock signal (CLK) by 1 ns or more (sixth configuration).

[0163] In the receiving circuit (10, 10A, 10B, 10C) of any of the above configurations 1 to 6, the rising edge timing of the first output signal (S1) sets the rising edge timing of the input signal (SIN), and the falling edge timing of the second output signal (S2) sets the falling edge timing of the input signal (SIN) (configuration 7).

[0164] In the receiving circuits (10, 10A, 10B, 10C) of any of the above configurations 1 to 7, the first latch block (1, 1A), the second latch block (2, 2A), the third latch block (3, 3A), and the fourth latch block (4, 4A) are configured to include D flip-flops (11, 12, 21, 22, 31, 32, 41, 42) (configuration 8).

[0165] The processing device (100) described above comprises a receiving circuit (10, 10A, 10B, 10C) having any of the first to eight configurations described above, The configuration (the ninth configuration) includes a processing circuit (20) configured to receive a first output signal (S1) and a second output signal (S2) from a receiving circuit (10).

[0166] The functional IC (100) described above has a configuration that includes the processing unit (100) of the ninth configuration described above (the tenth configuration). [Explanation of Symbols]

[0167] 100 Function ICs 10, 10A, 10B, 10C receiving circuit 20 Processing Circuits 30 Clock generation circuit 200 External circuit 1, 1A First latch block 2, 2A Second latch block 3, 3A Third latch block 4, 4A Fourth latch block 11, 21, 31, 41, 12, 22, 32, 42 D flip-flops 5 Inverter Block 6 OR Blocks 7 AND block 8 buffer blocks SIN input signal S1 First output signal S2 Second output signal SAND logical AND signal SOR OR signal CLK clock signal CLKB inverted clock signal CLKC clock signal CLKD delayed clock signal Ph ban period Ph1 ban period Ph2 ban period SLT1 First latch signal SLT2 Second latch signal Sout output signal Th hold time Tsu Setup Time ta1 Rise timing

Claims

1. A first latch block generates a first latch signal by latching an input signal at a timing corresponding to a first clock signal, A second latch block is configured to generate a second latch signal by latching the input signal at a timing corresponding to the first clock signal and at a timing that is out of phase with respect to the latch timing of the first latch block, An OR block configured to generate a logical OR signal which is the result of the logical OR of the first latch signal and the second latch signal, An AND block configured to generate a logical AND signal which is the result of the logical AND of the first latch signal and the second latch signal, A third latch block configured to latch the logical OR signal with the first clock signal to generate a first output signal, A receiving circuit having a fourth latch block configured to latch the aforementioned AND signal with the first clock signal to generate a second output signal.

2. The receiving circuit according to claim 1, wherein the second latch block is configured to receive a second clock signal that is generated based on the first clock signal and is out of phase with respect to the first clock signal.

3. The receiving circuit according to claim 2, wherein the second clock signal is an inverted clock signal which is an inverted signal of the first clock signal.

4. The receiving circuit according to claim 1, wherein the rising edge timing of the first output signal sets the rising edge timing of the input signal, and the falling edge timing of the second output signal sets the falling edge timing of the input signal.

5. The receiving circuit according to claim 1, wherein the first latch block, the second latch block, the third latch block, and the fourth latch block are all configured to be either positive triggers or negative triggers.

6. The first latch block and the second latch block are configured with one being a positive trigger and the other a negative trigger. The receiving circuit according to claim 1, wherein both the third latch block and the fourth latch block are configured to be positive triggers or negative triggers.

7. The receiving circuit according to claim 2, wherein the second clock signal is configured to be out of phase with respect to the first clock signal.

8. The receiving circuit according to claim 1, wherein the first latch block, the second latch block, the third latch block, and the fourth latch block are configured to include a D flip-flop.

9. A receiving circuit having the configuration described in any one of claims 1 to 8, A processing device having a processing circuit configured to receive the first output signal and the second output signal from the receiving circuit.

10. A functional IC with a configuration including the processing device shown in claim 9.

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