Digital circuit devices, processing units, and functional ICs

Abstract

Reduce the time required for the test. [Solution] The digital circuit device (100) has a plurality of processing blocks (20_1, 20_2, 20_3, ..., 20_N) to which the same test data (DST) is supplied simultaneously, an AND block (1) configured to generate logical AND data (DAND) of output data (Mc_1, Mc_2, Mc_3, ..., Mc_N), an OR block (2) configured to generate logical OR data (DOR) of output data (Mc_1, Mc_2, Mc_3, ..., Mc_N), and logic circuits (3, 4) configured to generate final output data (DOUT) corresponding to at least one of the logical AND data (DAND) and logical OR data (DOR) using output data (Mc_1) as selected data. The configuration outputs the final output data (DOUT) and the selected data (Mc_1).

Description

Technical Field

[0001] The present disclosure relates to a digital circuit device, a processing device using the digital circuit device, and a functional IC including the processing device.

Background Art

[0002] A scan test is used to detect abnormalities such as defects and failures in a semiconductor integrated circuit including a selection circuit. The scan test supplies test pattern data to the selection circuit and determines the presence or absence of an abnormality in the selection circuit by comparing the output data output from the selection circuit with expected data (see, for example, Patent Document 1).

[0003] In a semiconductor integrated circuit, there may be a plurality of selection circuits having the same circuit configuration. In such a configuration, test pattern data is supplied to each selection circuit to perform a scan test on each selection circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] As described above, in the case of a configuration in which scan tests are sequentially performed on a plurality of selection circuits, the time required for the scan test increases according to the number of selection circuits. In recent years, the number of selection circuits in a semiconductor integrated circuit has been increasing, and there is an increasing demand for shortening the time required for the scan test.

[0006] A digital circuit device according to one aspect of the present disclosure includes: a plurality of processing blocks having the same configuration configured to simultaneously supply the same test data; an AND block configured to generate logical AND data corresponding to the logical AND of the output data of each of the plurality of processing blocks; an OR block configured to generate logical OR data corresponding to the logical OR of the output data of each of the plurality of processing blocks; and a logic circuit configured to receive the logical AND data and the logical OR data as input and to generate final output data corresponding to at least one of the logical AND data and the logical OR data using the output data output from any of the plurality of processing blocks as selected data. The selected data is output together with the final output data. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows the overall configuration of the processing unit. [Figure 2] Figure 2 is a schematic diagram showing the state of the flip-flops when a scan test is performed. [Figure 3] Figure 3 shows waveform diagrams of test data and intermediate output data. [Figure 4] Figure 4 shows the configuration of a functional IC. [Figure 5] Figure 5 shows the data for each processing block when there are no abnormalities in any of the processing blocks. [Figure 6] Figure 6 shows the data when there is an abnormality in part of the processing block. [Figure 7] Figure 7 shows the data when there is an abnormality in the processing block that outputs the intermediate output data used as selected data. [Figure 8] Figure 8 is a diagram showing the configuration of a logic circuit used in a modified digital circuit device.

[0008] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are denoted by the same reference numerals, and redundant descriptions relating to the same parts are omitted as a general rule. In this specification, for the sake of simplification of description, symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional parts, circuits, elements, or components corresponding to such symbols or reference numerals may be omitted or abbreviated. For example, the clock signal referred to by "CLK" described later (see Figure 1) may be written as clock signal CLK, or abbreviated as signal CLK or clock CLK, but all of these refer to the same thing.

[0009] Furthermore, some terms used in the description of embodiments of the present invention will be explained. Level refers to the level of electric potential, and for any signal, a high level has a higher potential than a low level. For any signal of interest, when the signal of interest is at a high level, its inverted signal (logical inverted signal) is at a low level, and when the signal of interest is at a low level, its inverted signal (logical inverted signal) is at a high level.

[0010] In any signal, the transition from a low level to a high level is called the rising edge. The rising portion of any signal is called the rising edge, and the timing of the rising edge is called the rising timing. Similarly, in any signal, the transition from a high level to a low level is called the falling edge. The falling portion of any signal is called the falling edge, and the timing of the falling edge is called the falling timing.

[0011] In this specification, a MOS (Metal Oxide Semiconductor) field-effect transistor refers to a transistor whose gate structure consists of at least three layers: a conductor or a semiconductor such as polysilicon with low resistance; an insulating layer; and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field-effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0012] The configuration of this disclosure will be described with reference to the drawings. Figure 1 is a diagram showing the overall configuration of the processing unit 600. The processing unit 600 is, for example, a multiphase DC / DC converter and constitutes part of the power supply circuit. The processing unit 600 has a digital circuit device 100, a control device 200, a test judgment device 300, and a plurality (in this case, N) of output units 400. In the following description, when it is necessary to distinguish between a configuration having multiple identical components, the reference numerals will be used to indicate this. For example, in the case of multiple output units 400, they may be referred to as output unit 400, or each output unit may be referred to as output unit 400_1, output unit 400_2, etc.

[0013] The processing unit 600 may also be provided as a functional IC (Integrated Circuit) 500 that packages the digital circuit device 100, the control device 200, and the test judgment device 300. Furthermore, the functional IC 500 may be configured, for example, by packaging some or all of the multiple output units 400 in the same package.

[0014] In the processing unit 600, the control signal Cnt from the control device 200 is input to a plurality of processing blocks 20, which will be described later, arranged in the digital circuit device 100. Each of the plurality of processing blocks 20 then outputs a drive signal Sp to a corresponding plurality of (in this case, N) output units 400, operating the output units 400. As a result, each of the output units 400 outputs a current I based on the drive signal Sp. The processing unit 600 outputs an output current IOUT, which is the sum of the currents I, to the outside.

[0015] The output unit 400 combines, for example, a bridge circuit (not shown) with MOS transistors connected in series, and a driver circuit (not shown) that operates the bridge circuit. The output units 400_1, 400_2, 400_3, ..., 400_N receive drive signals Sp_1, Sp_2, Sp_3, ..., Sp_N from processing blocks 20_1, 20_2, 20_3, ..., 20_N, respectively.

[0016] The output units 400 are configured to be driven by PWM (Pulse Width Modulation) control, and the drive signal Sp is a PWM signal used to set the on-duty cycle of each output unit 400. The driver circuit of the output unit 400 controls the ON or OFF state of the bridge circuit based on the drive signal Sp and outputs a current I. The processing unit 600 adjusts the output current IOUT by adjusting the number of output units 400 to be operated, adjusting the current I output from the output units 400, etc.

[0017] In the processing unit 600, a scan test is performed to confirm that there are no abnormalities in the digital circuit device 100. The test determination device 300 determines whether or not there are abnormalities in the digital circuit device 100 when the scan test is performed. Details of the test determination device 300 will be described later.

[0018] The control device 200 outputs a control signal Cnt to the digital circuit device 100. The control signal Cnt outputs control signals Cnt_1, Cnt_2, Cnt_3, ..., Cnt_N to each processing block 20_1, 20_2, 20_3, ..., 20_N of the digital circuit device 100, respectively. The control device 200 also operates as a device that outputs test data DST in order to perform a scan test of the digital circuit device 100. In this embodiment, the control device 200 is configured to output test data DST, but a separate circuit device that supplies test data DST to the digital circuit device 100 may also be provided. Details of the test data DST will be described later.

[0019] <Digital circuit device 100> As shown in FIG. 1, the digital circuit device 100 includes a selection circuit 10, a plurality (n) of processing blocks 20, and a clock generation circuit 30. The clock generation circuit 30 is a circuit that generates a clock signal CLK. The clock signal CLK is a rectangular wave signal having a predetermined clock frequency. That is, the clock signal CLK periodically switches between a high level and a low level in terms of signal level.

[0020] The clock generation circuit 30 can change the frequency of the clock signal CLK. The clock signal CLK is supplied to each processing block 20 and the selection circuit 10. That is, in the selection circuit 10 and the plurality of processing blocks 20, processing is executed in synchronization with the clock signal CLK. Note that the processing blocks 20_1, 20_2, 20_3, ···, 20_N have the same circuit configuration.

[0021] The scan test checks whether the flip - flops included in each processing block 20 are operating correctly. FIG. 2 is a schematic diagram showing the state of the flip - flops when the scan test is performed.

[0022] As shown in FIG. 2, it is assumed that the processing block 20 includes four flip - flops 21, 22, 23, and 24. The flip - flops 21, 22, 23, and 24 are D - type flip - flops and have an input terminal (hereinafter, may be referred to as a D terminal), an output terminal (hereinafter, may be referred to as a Q terminal), and a clock input terminal.

[0023] In the processing block 20, when operating to output the above - described drive signal Sp (hereinafter, referred to as normal operation), each of the flip - flops 21, 22, 23, and 24 performs the given processing respectively. On the other hand, in the digital circuit device 100, when operating to perform a scan test (hereinafter, referred to as test operation), as shown in FIG. 2, the flip - flops 21, 22, 23, and 24 are cascade - connected.

[0024] In other words, as shown in Figure 2, in processing block 20, the Q terminal of flip-flop 21 is connected to the D terminal of flip-flop 22. Similarly, the Q terminal of flip-flop 22 is connected to the D terminal of flip-flop 23, and the Q terminal of flip-flop 23 is connected to the D terminal of flip-flop 24. The clock signal CLK from the clock generation circuit 30 is input to the clock terminals of flip-flops 21, 22, 23, and 24. Test data DST is input to the D terminal of flip-flop 21. Furthermore, intermediate output data Mc is output from the Q terminal of flip-flop 24.

[0025] The test data DST is a signal generated by the control unit 200, and it is a signal that takes either a high or low level. In the following explanation, the logical value of the high level of test data DST is "1", and the logical value of the low level is "0".

[0026] Then, in the state shown in Figure 2, flip-flop 21, triggered by the rising edge of the clock signal CLK from a low level to a high level, holds the logical value of the test data DST. It then outputs the data containing the held logical value from the Q terminal. Similarly, flip-flops 22, 23, and 24, triggered by the rising edge of the clock signal CLK from a low level to a high level, hold the logical value of the data output from the Q terminal of the preceding flip-flop. They then output the data containing the held logical value from the Q terminal.

[0027] Here, we will explain the test data. Figure 3 is a waveform diagram showing the test data and intermediate output data Mc. As shown in Figure 3, the control device 200 generates test data DST synchronized with the clock signal CLK. In other words, the test data DST is a serial signal, and a theoretical value is given for each period of the clock signal CLK. In the example shown in Figure 3, the test data DST is data that alternates between logical values ​​"1" and "0", and the logical value switches between "1" and "0" for each period of the clock signal CLK.

[0028] When test data DST is input, flip-flop 21 first latches the theoretical value of the first bit of the test data DST. In Figure 3, the theoretical value of the first bit is "1", so "1" is latched. Note that the output of the data with the latched theoretical value from the Q terminal of flip-flop 21 is delayed from the rising edge timing of the clock signal CLK. Therefore, flip-flop 22 latches the theoretical value of the first bit of the test data DST at the rising edge timing of the next clock signal CLK.

[0029] Similarly, flip-flop 23 latches the theoretical value of the first bit of test data DST at the rising edge of the next clock signal CLK following the timing when flip-flop 22 latched the theoretical value. Similarly, it latches the theoretical value of the first bit of test data DST again at the rising edge of the next clock signal CLK and outputs intermediate output data Mc with the latched theoretical value.

[0030] In processing block 20, the theoretical values ​​of bits 2 through 8 are similarly transmitted by being latched with sequential delays, and intermediate output data Mc is output with a time delay determined by the number of bits. In other words, in processing block 20, if there are no defects in flip-flops 21, 22, 23, and 24, intermediate output data with the same value as the test data DST is output, but with a delay of several clock cycles.

[0031] Furthermore, if there is a malfunction in any of the flip-flops 21, 22, 23, or 24, the output of that flip-flop may be inverted or become undefined. In such cases, the intermediate output data Mc will be different from the test data DST. For example, if there is an abnormality in the processing block 20, the intermediate output data Mc may exhibit abnormalities such as only certain bits being inverted, all bits being inverted, or all bits becoming "0" or "1". As will be described in more detail later, the test judgment device 300 determines whether or not there is an abnormality in the digital circuit device 100 based on the abnormality in the intermediate output data Mc.

[0032] Although the explanation assumes that processing block 20 contains four flip-flops, the number of flip-flops is not limited to four. Furthermore, the configuration does not have to cascade all the flip-flops in processing block 20; some of the flip-flops may be cascaded. Alternatively, a configuration may be formed in which multiple cascaded flip-flops are connected, and a scan test is performed for each set. By forming sets and performing scan tests, for example, it is possible to perform scan tests on flip-flops that are not currently used in the processing block 20, and to perform scan tests on flip-flops while processing block 20 continues to operate.

[0033] The test data DST is determined based on the configuration of the digital circuit device 100, which includes the processing block 20. While a detailed explanation is omitted, the test results may vary depending on the configuration of the test data DST. The control device 200 may be configured to generate the optimal test data DST using a separately provided algorithm, or it may always use test data DST that provides a certain degree of accuracy.

[0034] <Selection Circuit 10> Next, the selection circuit 10 will be explained. Figure 4 shows the configuration of the functional IC 500. The selection circuit 10 processes the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N output from processing blocks 20_1, 20_2, 20_3, ..., 20_N, and outputs the final output data DOUT.

[0035] As shown in Figure 4, the selection circuit 10 includes an AND block 1, an OR block 2, and a logic circuit 3. The AND block 1 receives intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N from processing blocks 20_1, 20_2, 20_3, ..., 20_N as input. The AND block 1 then performs a logical AND operation on the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N. The AND block 1 then outputs the result of the logical AND as logical AND data DAND.

[0036] OR block 2 receives the same intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N from processing blocks 20_1, 20_2, 20_3, ..., 20_N as AND block 1. OR block 2 then performs a logical OR operation on the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N. Finally, OR block 2 outputs the result of the logical OR as the logical OR data DOR.

[0037] Furthermore, as shown in Figure 4, logic circuit 3 is a circuit that selects one data from the input data and outputs it. In this case, logic circuit 3 has a multiplexer 3A.

[0038] The logic circuit 3 has three input terminals 31, 32, and 33 and one output terminal 34. Input terminal 31 receives the logical AND data DAND. Input terminal 32 receives the logical OR data DOR. Input terminal 33 receives the intermediate output data Mc_1 of processing block 20_1. In other words, the intermediate output data Mc_1 of processing block 20_1 acts as selection data to select either input terminal 31 or input terminal 32. The final output data DOUT is output from output terminal 34. In this embodiment, the intermediate output data Mc_1 of processing block 20_1 is used as selection data, but intermediate output data from other processing blocks may be used.

[0039] As described above, the intermediate output data Mc_1 is a data that can take the value of "0" or "1". When the intermediate output data Mc_1 input to input terminal 33 of logic circuit 3 is "1", input terminal 31 is selected. As a result, the value of the logical AND data DAND is output from output terminal 34 as the final output data DOUT. When the intermediate output data Mc_1 is "0", input terminal 32 is selected. As a result, the value of the logical OR data DOR is output from output terminal 34 as the final output data DOUT. The selection of input terminals 31 and 32 is determined by the value of the intermediate output data Mc_1. Therefore, the switching occurs at a minimum of one cycle of the clock signal CLK.

[0040] The digital circuit device 100 then outputs intermediate output data Mc_1 and final output data DOUT to the test judgment device 300. The processing device 600, which has the digital circuit device 100, has the configuration described above.

[0041] As mentioned above, the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N have the same number of bits as the test data DST. Therefore, the logical AND data DAND and logical OR data DOR, determined based on the intermediate output data Mc_1, are selected using the values ​​of each bit in the intermediate output data Mc_1. Consequently, the final output data DOUT also has the same number of bits as the test data DST.

[0042] <Decision Process> Next, the process by which the test judgment device 300 determines whether or not there is an abnormality in the digital circuit device 100 will be explained with reference to the drawings. First, the case where there is no abnormality will be explained.

[0043] Figure 5 shows the data when there are no abnormalities in any processing block. The test data DST is 8 bits of data. Here, it is assumed to be data with alternating "1"s and "0"s. In other words, as shown in Figure 5, the test data DST is "10101010".

[0044] The test determination device 300 has expected value data DEX corresponding to the test data DST. As shown in Figure 5, when the digital circuit device 100 has the configuration described above, the expected value data DEX is 8-bit data with the same value as the test data DST. However, the expected value data DEX may be different from the test data DST depending on the configuration of the processing block 20, etc. Therefore, the test determination device 300 may be configured to generate the expected value data DEX based on the test data DST. In other words, the expected value data DEX is data generated according to the test data. Alternatively, the control device 200 may generate the expected value data DEX together with the test data DST and supply it to the test determination device 300. The expected value data DEX is the same value as the test data DST when there is no abnormality in the flip-flop.

[0045] In other words, as shown in Figure 5, the expected value data DEX will be "10101010". As mentioned above, if there are no abnormalities in processing blocks 20_1, 20_2, 20_3, ..., 20_N, the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N will be "10101010".

[0046] When the value of test data DST is "1", the values ​​of intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N are all "1", and the value of logical AND data DAND is also "1", and the value of logical OR data DOR is also "1". Then, the value of Mc_1, "1", is input to input terminal 33 of logic circuit 3. Therefore, the value of logical AND data DAND, "1", is selected and output as the final output data DOUT.

[0047] Furthermore, if the value of the test data DST is "1", the value of the expected value data DEX is "1", and the values ​​of the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N are all "1". Therefore, the values ​​of the logical AND data DAND and the logical OR data DOR are also "1". Then, the value of Mc_1, "1", is input to the input terminal 33 of the logic circuit 3. Therefore, the value of the logical AND data DAND, "1", is selected and output as the final output data DOUT. In other words, the final output data DOUT is the same data as the expected value data DEX.

[0048] Furthermore, if the value of the test data DST is "0", the value of the expected value data DEX is "0", and the values ​​of the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N are all "0". Therefore, the values ​​of the logical AND data DAND and the logical OR data DOR are "0". Then, the value of Mc_1, "0", is input to the input terminal 33 of the logic circuit 3. Therefore, the value of the logical OR data DOR, "0", is selected and output as the final output data DOUT. In other words, the final output data DOUT is the same data as the expected value data DEX.

[0049] Based on the above, if there are no abnormalities in all processing blocks 20_1, 20_2, 20_3, ..., 20_N, the final output data DOUT will be "10101010", which matches the expected value data DEX.

[0050] Next, we will explain the case where an abnormality occurs in at least one of the processing blocks 20_1, 20_2, 20_3, ..., 20_N. We will explain this separately for cases where an abnormality occurs in processing block 20_1 and cases where an abnormality occurs in processing blocks other than 20_1, such as 20_2, 20_3, ..., 20_N. Note that abnormalities that occur in the values ​​of intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N due to an abnormality in processing blocks 20_1, 20_2, 20_3, ..., 20_N are referred to as errors, and are shown with an underline in the diagram.

[0051] First, let's explain the case where there is an abnormality other than in processing block 20_1. When the value of test data DST is "1", the value of intermediate output data Mc_1 is "1". Also, at least one value of intermediate output data Mc_2, Mc_3, ..., Mc_N will be "0". Therefore, the value of logical AND data DAND will be "0", and the logical OR data DOR will be "1". Then, the value of Mc_1, "1", is input to input terminal 33 of logic circuit 3. Therefore, the value of logical AND data DAND, "0", is selected and output as the final output data DOUT.

[0052] Furthermore, when the value of test data DST is "0", the value of intermediate output data Mc_1 becomes "0". Also, at least one of the intermediate output data Mc_2, Mc_3, ..., Mc_N will be "1". Therefore, the value of the logical AND data DAND becomes "0", and the logical OR data DOR becomes "1". Then, the value of Mc_1, "0", is input to the input terminal 33 of logic circuit 3. Therefore, the value of the logical OR data DOR, "1", is selected and output as the final output data DOUT.

[0053] In other words, if at least one of the intermediate output data Mc_2, Mc_3, ..., Mc_N, other than the intermediate output data Mc_1 used as the selection data, contains an error, the final output data DOUT will be different from the test data DST, i.e., the expected value data DEX.

[0054] The test judgment device 300 determines that there is an abnormality in one of the processing blocks 20_1, 20_2, 20_3, ..., 20_N, that is, there is an abnormality in the digital circuit device 100, if the final output data DOUT and the expected value data DEX are different.

[0055] For example, let's explain using the case where there is an abnormality in processing block 20_3, referring to the diagram. Figure 6 shows the data when there is an abnormality in a part of the processing block. As shown in Figure 6, the test data DST is the same as in Figure 5, i.e., "10101010". Then, let's explain assuming that the 4th and 5th bits are inverted due to the abnormality in processing block 20_3. In other words, the intermediate output data Mc_3 output from processing block 20_3 is assumed to be "10110010".

[0056] In processing blocks other than processing block 20_3, there are no abnormalities, so the intermediate output data in all of them will be the same as the test data DST, "10101010". As mentioned above, the value of the fourth bit of the intermediate output data Mc_1 used as selection data is "0", so input terminal 32 is selected in logic circuit 3, and the value of the logical OR data DOR is output as the final output data DOUT. Since the value of the fourth bit of processing block 20_3 is "1", the logical OR data DOR is "1", and the value of the fourth bit of the final output data DOUT is "1".

[0057] Furthermore, since the value of the 5th bit of the intermediate output data Mc_1, which is used as selection data, is "1", the input terminal 31 is selected in logic circuit 3, and the value of the logical AND data DAND is output as the final output data DOUT. Since the value of the 5th bit of processing block 20_3 is "0", the logical AND data DAND is "0", and the value of the 5th bit of the final output data DOUT is "0".

[0058] The values ​​of all bits except the 4th and 5th bits of the intermediate output data Mc_3 are correct, and the values ​​of all bits except the 4th and 5th bits of the final output data DOUT are the same as the values ​​of the same bits in the test data DST. In other words, if there is an abnormality in processing block 20_3 and the intermediate output data Mc_3 as described above is output, the final output data DOUT will be "10110010". The expected value data DEX is the same as the test data DST, i.e., "10101010". The test judgment device 300 compares these two data and determines that there is an abnormality in the digital circuit device 100 because the data are different. Note that the above example uses the case where there is an abnormality in processing block 20_3, but it is not limited to this, and an abnormality can be determined in the same way when there is an abnormality in processing blocks other than processing blocks 20_1 and 20_3.

[0059] Next, we will explain the case where only processing block 20_1 has an abnormality. When the value of test data DST is "1", the value of intermediate output data Mc_1 becomes "0". Also, the values ​​of intermediate output data Mc_2, Mc_3, ..., Mc_N become "1". Therefore, the value of logical AND data DAND becomes "0", and the logical OR data DOR becomes "1". Then, the value of Mc_1, "0", is input to input terminal 33 of logic circuit 3. Therefore, the value of the logical OR data DOR, "1", is selected and output as the final output data DOUT.

[0060] Furthermore, when the value of test data DST is "0", the value of intermediate output data Mc_1 becomes "1". Also, the values ​​of intermediate output data Mc_2, Mc_3, ..., Mc_N become "0". Therefore, the value of logical AND data DAND becomes "0", and the logical OR data DOR becomes "1". Then, the value of Mc_1, "1", is input to input terminal 33 of logic circuit 3. Therefore, the value of logical AND data DAND, "0", is selected and output as the final output data DOUT.

[0061] In other words, if only the intermediate output data Mc_1, which is used as the selected data, contains errors, the final output data DOUT will be the same as the test data DST, i.e., the expected value data DEX.

[0062] As described above, if an anomaly occurs only in processing block 20_1, comparing the final output data DOUT with the expected value data DEX alone is insufficient to detect the anomaly. Therefore, the test judgment device 300 is configured to perform a comparison between the final output data DOUT and the expected value data DEX, as well as a comparison between the intermediate output data Mc_1, which is used as selected data, and the expected value data DEX.

[0063] Next, we will explain the case where only processing block 20_1 is abnormal, referring to the diagram. Figure 7 shows the data when there is an abnormality in the processing block that outputs the intermediate output data used as selection data. As shown in Figure 7, the test data DST is the same as in Figure 5, i.e., "10101010". Then, we will explain assuming that the fourth and fifth bits are inverted due to the abnormality in processing block 20_1. In other words, the intermediate output data Mc_1 output from processing block 20_1 is assumed to be "10110010".

[0064] In processing blocks other than processing block 20_1, there are no abnormalities, so the intermediate output data in all of them will be the same as the test data DST, "10101010". As mentioned above, the value of the fourth bit of the intermediate output data Mc_1 used as selection data is "1", so input terminal 31 is selected in logic circuit 3, and the value of the logical AND data DAND is output as the final output data DOUT. Since the value of the fourth bit in processing blocks other than processing block 20_1 is "0", the logical AND data DAND is "0", and the value of the fourth bit of the final output data DOUT is "0".

[0065] Furthermore, since the value of the 5th bit of the intermediate output data Mc_1, which is used as selection data, is "0", the input terminal 32 is selected in logic circuit 3, and the value of the logical AND data DAND is output as the final output data DOUT. Since the value of the 5th bit of all processing blocks except 20_1 is "1", the logical OR data DOR is "1", and the value of the 5th bit of the final output data DOUT is "1".

[0066] The values ​​of all bits except the 4th and 5th bits of the intermediate output data Mc_1 are correct, and the values ​​of all bits except the 4th and 5th bits of the final output data DOUT are the same as the values ​​of the corresponding bits in the test data DST. In other words, if there is an error in processing block 20_1 and the intermediate output data Mc_1 as described above is output, the final output data DOUT will be "10101010", which is the same data as the expected value data DEX.

[0067] To prepare for such situations, the test determination device 300 compares the intermediate output data Mc_1, which is used as the selected data, with the expected value data DEX. The test determination device 300 then determines that there is an abnormality in the digital circuit device 100 because the intermediate output data Mc_1 and the expected value data DEX are different.

[0068] In other words, the test determination device 300 determines whether or not there is an abnormality in the digital circuit device 100 based on the comparison result of the final output data DOUT and the expected value data DEX, and the comparison result of the intermediate output data (here, Mc_1) used as selection data. By having the test determination device 300 determine the abnormality of the digital circuit device 100 based on the final output data DOUT and the intermediate output data used as selection data, an abnormality in the digital circuit device 100 can be accurately determined.

[0069] Furthermore, according to the digital circuit device 100 of this embodiment, when performing a test operation, the same test data DST is supplied to each processing block 20_1, 20_2, 20_3, ..., 20_N at the same timing. Then, each processing block 20_1, 20_2, 20_3, ..., 20_N outputs intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N at the same timing. In other words, a scan test is performed simultaneously in all processing blocks 20_1, 20_2, 20_3, ..., 20_N. By using the digital circuit device 100 and the test determination device 300, if the time required for a test scan in one processing block 20 is Tprs, then it is possible to determine whether or not there is an abnormality in any of the processing blocks 20_1, 20_2, 20_3, ..., 20_N in time Tprs.

[0070] On the other hand, if sequential scan tests are performed for each processing block 20_1, 20_2, 20_3, ..., 20_N, it will take Tprs × N time to complete all scan tests. In other words, by using the digital circuit device 100 according to this embodiment, the time required for the test scan of the digital circuit device 100 can be shortened.

[0071] <Variation> Modified examples of the digital circuit device shown in this disclosure will be described with reference to the drawings. Figure 8 is a diagram of the configuration of the logic circuit 4 used in the modified digital circuit device 100. The modified digital circuit device 100 has logic circuit 4 instead of logic circuit 3. In all other respects, it has the same configuration as described above. Therefore, a detailed explanation of the same configuration will be omitted.

[0072] As shown in Figure 8, the logic circuit 4 has a first AND circuit 41, a second AND circuit 42, and an OR circuit 43. The first AND circuit 41 receives the intermediate output data Mc_1 and the logical AND data DAND, which is the output of AND block 1, as selected data. The second AND circuit 42 receives the inverted value of the intermediate output data Mc_1 as selected data, as well as the logical OR data DOR, which is the output of OR block 2. The OR circuit 43 receives the first output D1 from the first AND circuit 41 and the second output D2 from the second AND circuit. The output of the OR circuit 43 is the final output data DOUT.

[0073] Let's explain the case where there is no abnormality in the digital circuit device 100. When the value of the test data DST is "1", the values ​​of the intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N are all "1", the value of the logical AND data DAND is also "1", and the value of the logical OR data DOR is also "1". Then, the value of the intermediate output data Mc_1, i.e., "1", and the value of the logical AND data DAND, which is "1", are input to the first AND circuit 41. Therefore, the value of the first output D1 output from the first AND circuit 41 is "1".

[0074] Furthermore, the second AND gate 42 receives the inverted data of the intermediate output data Mc_1, i.e., "0", and the value of the logical OR data DOR, which is "1". Therefore, the value of the second output D2 output from the second AND gate 42 is "0". Then, the OR gate 43 receives the value of the first output D1, which is "1", and the value of the second output D2, which is "0". Therefore, the value of the final output data, which is the output of the OR gate 43, is "1".

[0075] When the value of test data DST is "0", the values ​​of intermediate output data Mc_1, Mc_2, Mc_3, ..., Mc_N are all "0", and the value of logical AND data DAND is also "0", and the value of logical OR data DOR is also "0". When intermediate output data Mc_1 is "0", the value of intermediate output data Mc_1, i.e. "0", and the value of logical AND data DAND, which is "0", are input to the first AND circuit 41. Therefore, the value of the first output D1 output from the first AND circuit 41 is "0".

[0076] Furthermore, the second AND gate 42 receives the inverted data of the intermediate output data Mc_1, i.e., "1", and the value of the logical OR data DOR, which is "0". Therefore, the value of the second output D2 output from the second AND gate 42 is "0". Then, the OR gate 43 receives the value of the first output D1, which is "0", and the value of the second output D2, which is "0". Therefore, the value of the final output data, which is the output of the OR gate 43, is "0".

[0077] As shown above, logic circuit 4 performs the same operation as logic circuit 3. Therefore, each output data is the same as the data obtained when using logic circuit 3 (see Figure 5).

[0078] Next, we will explain the case where an abnormality occurs in at least one of the processing blocks 20_1, 20_2, 20_3, ..., 20_N. We will explain this separately for the case where an abnormality occurs in processing block 20_1 and the case where an abnormality occurs in processing blocks other than processing block 20_1, such as 20_2, 20_3, ..., 20_N.

[0079] First, let's explain the case where there is an abnormality other than in processing block 20_1. When the value of test data DST is "1", the value of intermediate output data Mc_1 will also be "1". In addition, at least one value among the intermediate output data Mc_2, Mc_3, ..., Mc_N will be "0". Therefore, the value of the logical AND data DAND will be "0", and the logical OR data DOR will be "1".

[0080] Then, the first AND gate 41 of logic circuit 4 receives the value of the selected intermediate output data Mc_1, which is "1", and the value of the logical AND data DAND, which is "0". Therefore, the value of the first output D1 becomes "0".

[0081] Furthermore, the second AND gate 42 receives the inverted data of the intermediate output data Mc_1, i.e., "0", and the value of the logical OR data DOR, which is "1". Therefore, the value of the second output D2 output from the second AND gate 42 is "0". Then, the OR gate 43 receives the value of the first output D1, which is "1", and the value of the second output D2, which is "0". Therefore, the value of the final output data, which is the output of the OR gate 43, is "1".

[0082] Furthermore, when the value of test data DST is "0", the value of intermediate output data Mc_1 will also be "0". In addition, at least one value among the intermediate output data Mc_2, Mc_3, ..., Mc_N will be "1". Therefore, the value of the logical AND data DAND will be "0", and the logical OR data DOR will be "1".

[0083] Then, the first AND gate 41 of logic circuit 4 receives the value of the selected intermediate output data Mc_1, which is "0", and the value of the logical AND data DAND, which is "0". Therefore, the value of the first output D1 becomes "0".

[0084] Furthermore, the second AND gate 42 receives the inverted data of the intermediate output data Mc_1, i.e., "1", and the value of the logical OR data DOR, which is "1". Therefore, the value of the second output D2 output from the second AND gate 42 is "1". Then, the OR gate 43 receives the value of the first output D1, which is "0", and the value of the second output D2, which is "1". Therefore, the value of the final output data, which is the output of the OR gate 43, is "1".

[0085] In other words, if at least one of the intermediate output data Mc_2, Mc_3, ..., Mc_N, other than the intermediate output data Mc_1 used as the selection data, contains an error, the final output data DOUT will be different from the test data DST, i.e., the expected value data DEX.

[0086] As shown above, logic circuit 4 performs the same operation as logic circuit 3. Therefore, if there is an abnormality in at least one of the processing blocks 20_2, 20_3, ..., 20_N other than processing block 20_1, the data output will be the same as the data output when using logic circuit 3 (see Figure 6).

[0087] The example above uses the case where there is an abnormality in processing block 20_3, but it is not limited to this case. The same method can be used to determine whether or not there is an abnormality in processing blocks other than processing blocks 20_1 and 20_3.

[0088] Next, we will explain the case where there is an abnormality only in processing block 20_1. When the value of test data DST is "1", the value of intermediate output data Mc_1 becomes "0". Also, the values ​​of intermediate output data Mc_2, Mc_3, ..., Mc_N become "1". Therefore, the value of logical AND data DAND becomes "0", and the value of logical OR data DOR becomes "1". At this time, the first AND circuit 41 receives the value of intermediate output data Mc_1, which is "0", and the value of logical AND data DAND, which is "0", and the value of the first output D1 is "0".

[0089] Furthermore, the second AND gate 42 receives the inverted value of the intermediate output data Mc_1, which is "1," and the OR value of the logical OR data DOR, which is also "1," resulting in the value of the second output D2 being "1." Then, the OR gate 43 receives the value of the first output D1, which is "0," and the value of the second output, which is "1," resulting in the value of the final output data DOUT being "1." The final output data DOUT is the same as the expected value data DEX.

[0090] When the value of test data DST is "0", the value of intermediate output data Mc_1 becomes "1". Also, the values ​​of intermediate output data Mc_2, Mc_3, ..., Mc_N become "0". Therefore, the value of logical AND data DAND becomes "0", and the value of logical OR data DOR becomes "1". At this time, the first AND circuit 41 receives the value of intermediate output data Mc_1, which is "1", and the value of logical AND data DAND, which is "0", and the value of the first output D1 is "0".

[0091] Furthermore, the second AND gate 42 receives the inverted value of the intermediate output data Mc_1, which is "0", and the OR value of the logical OR data DOR, which is "1", so the value of the second output D2 is "0". Then, the OR gate 43 receives the value of the first output D1, which is "0", and the value of the second output, which is "0", so the value of the final output data DOUT is "0". The final output data DOUT is the same as the expected value data DEX.

[0092] As shown above, logic circuit 4 performs the same operations as logic circuit 3. Therefore, when there is an abnormality only in processing block 20_1, the data output will be the same as the data output when using logic circuit 3 (see Figure 7).

[0093] Thus, if there is an abnormality in the intermediate output data Mc_1 used as selection data, an error may not occur in the final output data DOUT, which is the output of logic circuit 4. Therefore, the processing unit 600 is configured to perform a comparison between the intermediate output data (in this case, Mc_1) used as selection data and the expected value data DEX, similar to the case where logic circuit 3 is used.

[0094] In other words, the test judgment device 300 can accurately determine whether or not there is an abnormality in any of the processing blocks 20_1, 20_2, 20_3, ..., 20_N of the digital circuit device 100 by comparing the intermediate output data Mc_1 with the expected value data DEX and the final output data DOUT with the expected value data DEX, respectively.

[0095] In the embodiments described above, scan testing is used as the testing method for the processing blocks, but this is not the only method. A wide range of testing methods can be employed that allow simultaneous testing of multiple processing blocks and perform pass / fail judgments based on the output data.

[0096] <Other> The embodiments described above should be considered illustrative and not restrictive in all respects, and the technical scope of the present invention is indicated by the claims rather than by the description of the embodiments described above, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0097] <Note> The various embodiments described above will be summarized below.

[0098] The digital circuit device (100) described above comprises multiple processing blocks (20_1, 20_2, 20_3, ..., 20_N) having the same configuration and configured to be supplied with the same test data (DST) simultaneously. AND block (1) is configured to generate logical AND data (DAND) corresponding to the logical AND of the output data (Mc_1, Mc_2, Mc_3, ..., Mc_N) of multiple processing blocks (20_1, 20_2, 20_3, ..., 20_N), An OR block (2) is configured to generate logical OR data (DOR) corresponding to the logical OR of the output data (Mc_1, Mc_2, Mc_3, ..., Mc_N) of multiple processing blocks (20_1, 20_2, 20_3, ..., 20_N), The system includes logic circuits (3, 4) that receive logical AND data (DAND) and logical OR data (DOR) as inputs, and use output data (Mc_1) output from one of several processing blocks (20_1, 20_2, 20_3, ..., 20_N) as selected data to generate final output data (DOUT) corresponding to at least one of the logical AND data (DAND) and logical OR data (DOR), This configuration (the first configuration) outputs the selected data (Mc_1) along with the final output data (DOUT).

[0099] In the digital circuit device (100) with the first configuration described above, the logic circuit (3) has a configuration that includes a multiplexer (3A), The multiplexer (3A) is configured (second configuration) to output either a logical AND (DAND) or logical OR (DOR) data as the final output data (DOUT) based on the logical value of the selected data (Mc_1).

[0100] In the digital circuit device (100) with the first configuration described above, the logic circuit (4) includes a first AND circuit (41) that generates a first output (D1) corresponding to the logical AND of selected data (Mc_1) and logical AND data (DAND), A second AND circuit (42) generates a second output (D2) corresponding to the logical AND of the inverted data of the selected data (Mc_1) and the logical OR data (DOR), This configuration (third configuration) includes an OR circuit (43) that generates final output data (DOUT) corresponding to the logical OR of the first output (D1) and the second output (D2).

[0101] The processing device (600) described above comprises a digital circuit device (100) having any of the first to third configurations described above, The configuration (fourth configuration) includes a test determination device (300) configured to compare the final output data (DOUT) and selected data (Mc_1) output from the logic circuits (3, 4) with the expected value data (DEX) generated according to the test data (DST) to determine whether or not there is an abnormality in the digital circuit device (100).

[0102] In the processing unit (600) of the fourth configuration described above, the test determination device (300) is configured to determine that no abnormality has occurred in the digital circuit device (100) when both the final output data (DOUT) and the selected data (Mc_1) match the expected value data (DEX) (fifth configuration).

[0103] The functional IC (500) described above is a packaged configuration (sixth configuration) that includes at least a part of the processing unit (600) of the fourth or fifth configuration described above. [Explanation of Symbols]

[0104] 100 Digital Circuitry Devices 200 Control device 300 Test Judgment Devices Output section for 400_1, 400_2, 400_3, ..., 400_N 500 Function ICs 600 Processing Unit 10 Selection Circuit 1 AND block 2 OR Blocks 3. Logic Circuits 20_1, 20_2, 20_3, ..., 20_N processing blocks 21, 22, 23, 24 Flip-flops 3A Multiplexer 31 Input terminals 31, 32, 33 Input terminals 4. Logic Circuits 41. First AND gate 42 2nd AND circuit 43 OR circuits 30 Clock generation circuit CLK clock signal D1 First Output D2 2nd output Sp_1, Sp_2, Sp_3, ..., Sp_N drive signals Cnt_1, Cnt_2, Cnt_3, ..., Cnt_N control signals Mc_1, Mc_2, Mc_3, ..., Mc_N Intermediate output data DAND logical AND data DST Test Data DEX Expected Value Data DOR (Logical OR) Data DOUT Final Output Data DST Test Data IOUT Output Current

Claims

1. Multiple processing blocks having the same configuration, configured to simultaneously supply the same test data, An AND block configured to generate logical AND data corresponding to the logical AND of the output data of each of the multiple processing blocks, An OR block configured to generate logical OR data corresponding to the logical OR of the output data of each of the multiple processing blocks, The system includes a logic circuit that receives the aforementioned AND data and OR data as input and generates a final output data corresponding to at least one of the AND data and OR data using output data output from any of the plurality of processing blocks as selected data, A digital circuit device configured such that the selected data is output along with the final output data.

2. The logic circuit has a configuration that includes a multiplexer. The digital circuit device according to claim 1, wherein the multiplexer is configured to output the logical AND data or the logical OR data based on the logical value of the selected data.

3. The aforementioned logic circuit is A first AND circuit that generates a first output corresponding to the logical AND of the selected data and the logical AND data, A second AND circuit generates a second output corresponding to the logical AND of the inverted data of the selected data and the logical OR data, The digital circuit device according to claim 1, comprising an OR circuit that generates final output data corresponding to the logical OR of the first output and the second output.

4. A digital circuit device according to any one of claims 1 to 3, A processing device having a test determination device configured to compare the final output data and the selected data output from the logic circuit with expected value data generated according to the test data, and to determine whether or not there is an abnormality in the digital circuit device.

5. The processing apparatus according to claim 4, wherein the test determination device determines that no abnormality has occurred in the digital circuit device when both the final output data and the selected data match the expected value data.

6. A functional IC comprising at least a part of the processing apparatus described in claim 4, packaged together.

7. A functional IC comprising at least a part of the processing apparatus described in claim 5, packaged together.

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