Manufacturing method for silicon carbide semiconductor devices

Abstract

To provide a silicon carbide semiconductor device in which the occurrence of defects is suppressed. [Solution] A method for manufacturing a silicon carbide semiconductor device comprises the steps of: preparing a silicon carbide wafer; fixing the silicon carbide wafer to a substrate; and grinding the silicon carbide substrate on a second main surface while the silicon carbide wafer is fixed to the substrate. The silicon carbide wafer includes a silicon carbide substrate and a surface element structure. The surface element structure has a third main surface. The third main surface is composed of an edge region and a planar region. The substrate is more flexible than the silicon carbide substrate. In the step of fixing the silicon carbide wafer to the substrate, the substrate covers the entire planar region and at least a part of the edge region.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2014-139972 (Patent Document 1) describes a method for manufacturing a silicon carbide semiconductor device. The method for manufacturing the silicon carbide semiconductor device includes a step of fixing a silicon carbide wafer to a substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to provide a method for manufacturing a silicon carbide semiconductor device in which the occurrence of defects is suppressed.

Means for Solving the Problems

[0006] According to this disclosure, it is possible to provide a silicon carbide semiconductor device in which the occurrence of defects is suppressed. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment. [Figure 2] Figure 2 is a schematic plan view of the silicon carbide semiconductor device according to this embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment. [Figure 4] Figure 4 is a schematic flowchart showing the manufacturing method for preparing the silicon carbide wafer according to this embodiment. [Figure 5]Figure 5 is a schematic perspective view showing the configuration of the silicon carbide substrate according to this embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view showing the configuration of the silicon carbide substrate according to this embodiment. [Figure 7] Figure 7 is a schematic cross-sectional diagram showing the process of forming a silicon carbide epitaxial layer. [Figure 8] Figure 8 is a schematic cross-sectional view showing the process of forming the body region. [Figure 9] Figure 9 is a schematic cross-sectional view showing the process of forming the source region. [Figure 10] Figure 10 is a schematic cross-sectional view showing the process of forming trenches on the fourth main surface of the silicon carbide epitaxial layer. [Figure 11] Figure 11 is a schematic cross-sectional view showing the process of forming the gate insulating film. [Figure 12] Figure 12 is a schematic cross-sectional view showing the process of forming the gate electrode and interlayer insulating film. [Figure 13] Figure 13 is a schematic cross-sectional view showing the process of forming a surface protection electrode. [Figure 14] Figure 14 is a schematic flowchart showing the manufacturing method of the silicon carbide semiconductor device according to this embodiment. [Figure 15] Figure 15 is a schematic cross-sectional view showing the process of fixing a silicon carbide wafer to a substrate. [Figure 16] Figure 16 is a schematic cross-sectional view showing the process of grinding a silicon carbide substrate from the second main surface. [Figure 17] Figure 17 is a schematic cross-sectional view showing the process of mounting silicon carbide wafers onto a tray. [Figure 18] Figure 18 is a schematic cross-sectional view showing the process of forming the drain electrode. [Figure 19] Figure 19 is a schematic cross-sectional view showing the process of forming the back surface protective electrode. [Modes for carrying out the invention]

[0008] [Summary of the embodiments of this disclosure] First, an overview of the embodiments of the present disclosure will be described.

[0009] (1) The method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes a step of preparing a silicon carbide wafer, a step of fixing the silicon carbide wafer to a base material, and a step of grinding the silicon carbide substrate from the second main surface in a state where the silicon carbide wafer is fixed to the base material. The silicon carbide wafer includes a silicon carbide substrate and a surface element structure. The surface element structure is formed on the silicon carbide substrate. The silicon carbide substrate has a first main surface, a second main surface, and a first outer peripheral surface. The second main surface is located opposite to the first main surface. The first outer peripheral surface is continuous with the first main surface. The surface element structure is formed on the first main surface. The first main surface is composed of a first chamfered region and a first central region. The first chamfered region is continuous with the first outer peripheral surface. The first central region is surrounded by the first chamfered region. The surface element structure has a third main surface and a second outer peripheral surface. The third main surface is located opposite to the first main surface. The second outer peripheral surface is continuous with the third main surface. The third main surface is composed of an end region and a planar region. The end region faces the first chamfered region. The planar region faces the first central region. The base material is more flexible than the silicon carbide substrate. In the step of fixing the silicon carbide wafer to the base material, the base material covers the entire planar region and at least a part of the end region.

[0010] (2) According to the method for manufacturing a silicon carbide semiconductor device according to (1) above, when viewed from a direction perpendicular to the third main surface, the base material may be disposed inside the second outer peripheral surface.

[0011] (3) According to the method for manufacturing a silicon carbide semiconductor device according to (1) or (2) above, the end region may be within 0.5 mm from the second outer peripheral surface toward the center of the third main surface.

[0012] (4) According to the method for manufacturing a silicon carbide semiconductor device according to any one of (1) to (3) above, the second main surface may include a polished surface.

[0013] (5) In the method for manufacturing a silicon carbide semiconductor device according to any of (1) to (4) above, in the step of grinding the silicon carbide substrate from the second main surface, the silicon carbide substrate may be ground from the second main surface using a grinding wheel. The rotation axis of the grinding wheel may be located outside the central axis of the silicon carbide substrate.

[0014] (6) In the method for manufacturing a silicon carbide semiconductor device according to any of (1) to (5) above, the maximum diameter of the first main surface may be 95 mm or more.

[0015] (7) In the method for manufacturing a silicon carbide semiconductor device according to any of (1) to (6) above, the maximum diameter of the first main surface may be 205 mm or less.

[0016] (8) A method for manufacturing a silicon carbide semiconductor device according to any of (1) to (7) above may further include a step of mounting a silicon carbide wafer fixed to a substrate onto a tray after a step of grinding a silicon carbide substrate from a second main surface.

[0017] (9) A method for manufacturing a silicon carbide semiconductor device according to any of (1) to (8) above may include a step of forming a drain electrode on a second main surface and a step of heating the silicon carbide substrate to remove impurities after the step of grinding the silicon carbide substrate from the second main surface and before the step of forming a drain electrode on the second main surface.

[0018] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below with reference to the drawings. In the following drawings, identical or corresponding parts will be given the same reference numeral, and their descriptions will not be repeated. In the crystallographic descriptions herein, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. In addition, while in crystallography a "-" (bar) is placed above the number for negative exponents, in this specification a negative sign is placed before the number.

[0019] First, the configuration of the silicon carbide semiconductor device 300 according to this embodiment will be described. Figure 1 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device 300 according to this embodiment. As shown in Figure 1, the silicon carbide semiconductor device 300 according to this embodiment includes a silicon carbide wafer 100, a drain electrode 123, and a back surface protection electrode 124.

[0020] The silicon carbide wafer 100 includes a silicon carbide substrate 10 and a surface element structure 20. The silicon carbide substrate 10 has a first main surface 11, a second main surface 12, and a first outer peripheral surface 21. The second main surface 12 is located opposite the first main surface 11. The first outer peripheral surface 21 is continuous with the first main surface 11 and the second main surface 12. The silicon carbide substrate 10 is made of, for example, hexagonal silicon carbide. The polytype of the hexagonal silicon carbide is, for example, 4H. The silicon carbide substrate 10 contains n-type impurities such as nitrogen.

[0021] The first main surface 11 is, for example, the {0001} surface or a surface inclined by an off-angle with respect to the {0001} surface. Specifically, the first main surface 11 may be the (0001) surface or a surface inclined by an off-angle with respect to the (0001) surface, or the (000-1) surface or a surface inclined by an off-angle with respect to the (000-1) surface. The off-angle may be, for example, 5° or less, or 3° or less. The off-direction may be, for example, the <11-20> direction.

[0022] The maximum diameter of the first main surface 11 may be, for example, 95 mm or more, 100 mm or more, 105 mm or more, 145 mm or more, 150 mm or more, or 155 mm or more. The maximum diameter of the first main surface 11 may be, for example, 205 mm or less, 200 mm or less, or 195 mm or less. The thickness of the silicon carbide substrate 10 may be, for example, 350 μm or more and 500 μm or less, or 200 μm or more and 700 μm or less.

[0023] The first main surface 11 is composed of a first central region 11a and a first chamfered region 11b. The first central region 11a is surrounded by the first chamfered region 11b. The first chamfered region 11b is connected to the first central region 11a and the first outer surface 21.

[0024] The second main surface 12 is composed of a second central region 12a and a second chamfered region 12b. The second central region 12a is surrounded by the second chamfered region 12b. The second chamfered region 12b is connected to the second central region 12a and the first outer surface 21.

[0025] The first chamfered region 11b and the second chamfered region 12b are regions where the silicon carbide substrate 10 has been chamfered. The first chamfered region 11b and the second chamfered region 12b are formed by chamfering the silicon carbide substrate 10. The first chamfered region 11b and the second chamfered region 12b may be outwardly convex curved surfaces, or they may be flat surfaces formed by C-chamfering the silicon carbide substrate 10. The first central region 11a and the second central region 12a are flat regions. The first chamfered region 11b is within a distance d1 from the first outer peripheral surface 21 toward the center of the first main surface 11. The second chamfered region 12b is within a distance d1 from the first outer peripheral surface 21 toward the center of the second main surface 12 (see Figure 6). The distance d1 is, for example, 0.5 mm.

[0026] The surface element structure 20 is formed on the silicon carbide substrate 10. Specifically, the surface element structure 20 is formed on the first main surface 11. The surface element structure 20 has a third main surface 13 and a second outer peripheral surface 22. The third main surface 13 is located opposite the first main surface 11. The second outer peripheral surface 22 is connected to the third main surface 13 and the first main surface 11.

[0027] The third main surface 13 is composed of a planar region 13a and an end region 13b. The planar region 13a is surrounded by the end region 13b. The end region 13b is connected to the planar region 13a and the second outer surface 22.

[0028] The planar region 13a is opposite the first central region 11a. The end region 13b is opposite the first chamfered region 11b. From a different perspective, when viewed from a direction perpendicular to the first main surface 11, the planar region 13a overlaps with the first central region 11a, and the end region 13b overlaps with the first chamfered region 11b.

[0029] The end region 13b may be an outwardly convex curved surface or a flat surface. The flat region 13a is a flat region. The end region 13b is within a distance d2 from the second outer surface 22 toward the center 13c of the third main surface 13. The distance d2 may be the same as the distance d1, and may be, for example, 0.1 mm, 0.5 mm, 1.0 mm, or 2.0 mm. From a different perspective, the end region 13b is tangent to the flat region 13a at a virtual boundary line 13d.

[0030] Figure 2 is a schematic plan view of the silicon carbide semiconductor device 300 according to this embodiment. The second outer peripheral surface 22 has an arc-shaped portion 22a and an orientation flat portion 22b. The arc-shaped portion 22a is continuous with the orientation flat portion 22b. As shown in Figure 2, when viewed from a direction perpendicular to the third main surface 13, the orientation flat portion 22b is linear.

[0031] As shown in Figure 2, the planar region 13a is the region that includes the center 13c of the third principal surface 13. The center 13c of the third principal surface 13 is the center of the arc-shaped portion 22a of the third principal surface 13.

[0032] As shown in Figure 1, the drain electrode 123 is formed on the second main surface 12. The drain electrode 123 is made of an alloy containing, for example, nickel and silicon (e.g., NiSi).

[0033] The back surface protective electrode 124 is formed on the drain electrode 123. Specifically, the back surface protective electrode 124 is provided on the side of the drain electrode 123 opposite to the side on which the silicon carbide substrate 10 is located. The back surface protective electrode 124 has a laminated structure in which a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked in that order.

[0034] Figure 3 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device 300 according to this embodiment. The silicon carbide semiconductor device 300 is, for example, a metal oxide semiconductor transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide wafer 100 has a silicon carbide substrate 10, a silicon carbide epitaxial layer 40, a gate electrode 127, a gate insulating film 115, a source electrode 116, a surface protection electrode 119, and an interlayer insulating film 126.

[0035] The surface element structure 20 is composed of a silicon carbide epitaxial layer 40, a gate electrode 127, a gate insulating film 115, a source electrode 116, a surface protection electrode 119, and an interlayer insulating film 126. The surface of the surface protection electrode 119 constitutes the third main surface 13 of the surface element structure 20.

[0036] The silicon carbide epitaxial layer 40 includes a buffer layer 51, a drift layer 52, a body region 113, a source region 114, and a contact region 118.

[0037] (Method for manufacturing silicon carbide wafers) Next, the method for manufacturing the silicon carbide wafer 100 according to this embodiment will be described. Figure 4 is a schematic flowchart showing the method for manufacturing the silicon carbide wafer 100 according to this embodiment. As shown in Figure 4, the method for manufacturing the silicon carbide wafer 100 according to this embodiment mainly comprises a step of preparing a silicon carbide substrate (S11) and a step of forming a surface element structure (S12).

[0038] First, a process (S11) is carried out to prepare the silicon carbide substrate. First, an ingot composed of polytype 4H silicon carbide single crystals is formed, for example, by sublimation. After the ingot is shaped, it is sliced ​​using a multi-wire saw device. This cuts out the silicon carbide substrate 10 from the ingot.

[0039] Figure 5 is a schematic perspective view showing the configuration of the silicon carbide substrate 10 according to this embodiment. Figure 6 is a schematic cross-sectional view showing the configuration of the silicon carbide substrate 10 according to this embodiment. The thickness of the silicon carbide substrate 10 is, for example, 1 mm. The first main surface 11 is, for example, a surface that is set off by 4° or less in the <11-20> direction with respect to the {0001} surface. Specifically, the first main surface 11 may be, for example, a surface set off by an angle of about 4° or less with respect to the (0001) surface, or a surface set off by an angle of about 4° or less with respect to the (000-1) surface.

[0040] A first chamfered region 11b and a second chamfered region 12b are formed by chamfering the silicon carbide substrate 10 cut from the ingot. As shown in Figure 6, the first chamfered region 11b is within a distance d1 from the first outer surface 21 toward the center of the first main surface 11. From a different perspective, the first chamfered region 11b is tangent to the first central region 11a at a virtual boundary line 11d. The second chamfered region 12b is within a distance d1 from the first outer surface 21 toward the center 11c of the second main surface 12. The distance d1 may be, for example, 0.1 mm, 0.5 mm, 1.0 mm, or 2.0 mm.

[0041] An orientation flat portion (not shown) may be formed by processing the first outer peripheral surface 21 of the silicon carbide substrate 10 cut from the ingot.

[0042] Next, a process (S12) for forming the surface element structure 20 is carried out. Figure 7 is a schematic cross-sectional view showing the process for forming the silicon carbide epitaxial layer 40. Specifically, a mixed gas containing silane, propane, ammonia, and hydrogen is introduced into a film deposition apparatus (not shown), and the mixed gas is thermally decomposed on the silicon carbide substrate 10. As a result, the silicon carbide epitaxial layer 40 is formed on the silicon carbide substrate 10. The silicon carbide epitaxial layer 40 has a fourth main surface 14. The fourth main surface 14 is the surface located opposite to the surface in contact with the first main surface 11 of the silicon carbide epitaxial layer 40.

[0043] The silicon carbide epitaxial layer 40 may have a buffer layer 51 and a drift layer 52. The buffer layer 51 is in contact with the silicon carbide substrate 10 on the first main surface 11. The drift layer 52 is provided on top of the buffer layer 51. Each of the buffer layer 51 and the drift layer 52 contains n-type impurities, such as nitrogen. The concentration of n-type impurities in the buffer layer 51 may be higher than the concentration of n-type impurities in the drift layer 52.

[0044] Next, a process for forming the body region 113 is carried out. Figure 8 is a schematic cross-sectional view showing the process for forming the body region 113. In the process for forming the body region 113, p-type impurities, such as aluminum, are ion-implanted into the fourth main surface 14 of the silicon carbide epitaxial layer 40. This forms a body region 113 having a p-type conductivity. The portion where the body region 113 was not formed becomes the drift layer 52 and the buffer layer 51. The thickness of the body region 113 is, for example, 0.9 μm. The silicon carbide epitaxial layer 40 includes the buffer layer 51, the drift layer 52, and the body region 113.

[0045] Next, a process to form the source region 114 is carried out. Figure 9 is a schematic cross-sectional view showing the process of forming the source region 114. Specifically, n-type impurities, such as phosphorus, are ion-implanted into the body region 113. This forms a source region 114 having an n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of n-type impurities in the source region 114 is higher than the concentration of p-type impurities in the body region 113.

[0046] Next, a contact region 118 is formed by ion implantation of p-type impurities, such as aluminum, into the source region 114 (see Figure 10). The contact region 118 penetrates the source region 114 and the body region 113 and is formed to be in contact with the drift layer 52. The concentration of p-type impurities in the contact region 118 is higher than the concentration of n-type impurities in the source region 114.

[0047] Next, activation annealing is performed to activate the ion-implanted impurities. The activation annealing temperature is, for example, between 1500°C and 1900°C. The activation annealing time is, for example, about 30 minutes. The activation annealing atmosphere is, for example, an argon atmosphere.

[0048] Next, a step is performed to form trenches 56 on the fourth main surface 14 of the silicon carbide epitaxial layer 40. Figure 10 is a schematic cross-sectional view showing the step of forming trenches 56 on the fourth main surface 14 of the silicon carbide epitaxial layer 40. A mask 117 having an opening is formed on the fourth main surface 14, which consists of a source region 114 and a contact region 118. Using the mask 117, the source region 114, the body region 113, and a part of the drift layer 52 are removed by etching. As an etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF6 or a mixed gas of SF6 and O2 as the reaction gas is used. By etching, recesses are formed on the fourth main surface 14.

[0049] Next, thermal etching is performed in the recesses. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with the mask 117 formed on the fourth main surface 14. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, Cl2, BCl3, SF6, or CF4. For example, a mixed gas of chlorine gas and oxygen gas is used as the reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 700°C to 1000°C. The reaction gas may also contain a carrier gas in addition to the chlorine gas and oxygen gas mentioned above. As the carrier gas, for example, nitrogen gas, argon gas, or helium gas can be used.

[0050] As shown in Figure 10, a trench 56 is formed on the fourth main surface 14 by thermal etching. The trench 56 is defined by a side wall surface 53 and a bottom wall surface 54. The side wall surface 53 consists of a source region 114, a body region 113, and a drift layer 52. The bottom wall surface 54 consists of the drift layer 52. Next, the mask 117 is removed from the fourth main surface 14.

[0051] Next, a step of forming the gate insulating film 115 is carried out. Figure 11 is a schematic cross-sectional view showing the step of forming the gate insulating film 115. Specifically, the silicon carbide epitaxial layer 40, on which trenches 56 are formed on the fourth main surface 14, is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms a gate insulating film 115 that is in contact with the drift layer 52 at the bottom wall surface 54, in contact with the drift layer 52, the body region 113, and the source region 114 at the side wall surface 53, and in contact with the source region 114 and the contact region 118 at the fourth main surface 14.

[0052] Next, the process of forming the gate electrode 127 is carried out. Figure 12 is a schematic cross-sectional view showing the process of forming the gate electrode 127 and the interlayer insulating film 126. The gate electrode 127 is formed inside the trench 56 so as to be in contact with the gate insulating film 115. The gate electrode 127 is positioned inside the trench 56 and is formed on the gate insulating film 115 so as to face the side wall surface 53 and the bottom wall surface 54 of the trench 56, respectively. The gate electrode 127 is formed, for example, by the LPCVD (Low Pressure Chemical Vapor Deposition) method.

[0053] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed, for example, by chemical vapor deposition. The interlayer insulating film 126 is made of a material containing, for example, silicon dioxide. Next, parts of the interlayer insulating film 126 and the gate insulating film 115 are etched so that openings are formed on the source region 114 and the contact region 118. This exposes the contact region 118 and the source region 114 from the gate insulating film 115.

[0054] Next, a process is carried out to form the source electrode 116. The source electrode 116 is formed to be in contact with the source region 114 and the contact region 118, respectively (see Figure 13). The source electrode 116 is formed, for example, by a sputtering method. The source electrode 116 is composed of a material including, for example, Ti (titanium), Al (aluminum), and Si (silicon).

[0055] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with the source region 114 and the contact region 118 is held at a temperature of, for example, 900°C to 1100°C for about 5 minutes. This causes at least a portion of the source electrode 116 to silicide. As a result, the source electrode 116 forms an ohmic bond with the source region 114. The source electrode 116 may also form an ohmic bond with the contact region 118.

[0056] Next, a surface protection electrode 119 is formed. Figure 13 is a schematic cross-sectional view showing the process of forming the surface protection electrode 119. The surface protection electrode 119 is electrically connected to the source electrode 116. The surface protection electrode 119 is formed to cover the source electrode 116 and the interlayer insulating film 126. The surface of the surface protection electrode 119 constitutes the third main surface 13.

[0057] In this way, a surface element structure 20 is formed on the first main surface 11 of the silicon carbide substrate 10. That is, the silicon carbide wafer 100 shown in Figure 13 can be prepared.

[0058] (Manufacturing method for silicon carbide semiconductor devices) Next, a method for manufacturing the silicon carbide semiconductor device 300 according to this embodiment will be described. Figure 14 is a schematic flowchart showing the method for manufacturing the silicon carbide semiconductor device 300 according to this embodiment. As shown in Figure 14, the method for manufacturing the silicon carbide semiconductor device 300 according to this embodiment mainly comprises the steps of preparing a silicon carbide wafer (S10), fixing the silicon carbide wafer to a substrate (S20), grinding the silicon carbide substrate from the second main surface (S30), dry etching (S40), mounting the silicon carbide wafer on a tray (S50), removing impurities (S60), sputter etching (S70), forming a drain electrode (S80), forming a back surface protective electrode (S90), removing the silicon carbide wafer from the tray (S100), and removing the substrate from the silicon carbide wafer (S110).

[0059] First, a step (S10) for preparing the silicon carbide wafer is carried out. The step (S10) for preparing the silicon carbide wafer includes the step (S11) for preparing the silicon carbide substrate mentioned above and the step (S12) for forming the surface element structure. In this way, the silicon carbide wafer 100 shown in Figure 13 is prepared.

[0060] Next, a step (S20) is performed to fix the silicon carbide wafer to the substrate. Figure 15 is a schematic cross-sectional view showing the step of fixing the silicon carbide wafer 100 to the substrate 90. Specifically, the silicon carbide wafer 100 is fixed to the substrate 90 by attaching the substrate 90 to the third main surface 13. The substrate 90 is more flexible than the silicon carbide substrate 10. In other words, the substrate 90 is more flexible than the silicon carbide substrate 10.

[0061] The base material 90 is, for example, an adhesive tape made of an organic compound. As shown in Figure 15, the base material 90 includes, for example, a base portion 92 and an adhesive portion 91 connected to the base portion 92. Various materials can be used for the base portion 92 and the adhesive portion 91. For example, the base portion 92 may be an organic compound such as polyester or polyolefin, and the adhesive portion 91 may be an acrylic adhesive with adhesive properties.

[0062] The adhesive portion 91 may be made of a material whose adhesive strength decreases when irradiated with energy rays such as ultraviolet rays. Examples of materials whose adhesive strength decreases when irradiated with energy rays such as ultraviolet rays include ultraviolet-curable resins. The adhesive portion 91 may also be made of a material whose adhesive strength decreases when heated. Examples of materials whose adhesive strength decreases when heated include thermosetting resins.

[0063] In this embodiment, the substrate 90 is in contact with the surface protective electrode 119 of the surface element structure 20, but the substrate 90 may also be in contact with an insulating film such as the interlayer insulating film 126 of the surface element structure 20.

[0064] In this embodiment, adhesive tape was used as an example of the base material 90, but the base material 90 may be composed of a material in which one side is adhesive and the other side is not adhesive. Furthermore, the base material 90 may be removable from the silicon carbide substrate 10 without the use of solvents.

[0065] As shown in Figure 15, in the step of fixing the silicon carbide wafer to the substrate (S20), the substrate 90 covers the entire planar region 13a. In addition, the substrate 90 covers at least a portion of the edge region 13b. From a different perspective, when viewed from a direction perpendicular to the third main surface 13, the entire planar region 13a overlaps with the substrate 90, and at least a portion of the edge region 13b overlaps with the substrate 90. In other words, when viewed from a direction perpendicular to the third main surface 13, the substrate 90 is positioned inside the first outer peripheral surface 21 and the second outer peripheral surface 22.

[0066] When viewed from a direction perpendicular to the third main surface 13, the base material 90 only needs to overlap a part of the end region 13b, and the base material 90 may be in direct contact with the end region 13b along the shape of its surface, or it may be spaced apart from the end region 13b.

[0067] When fixing the silicon carbide wafer 100 to the substrate 90, the amount of displacement of the silicon carbide wafer 100 can be detected by adjusting the alignment of the silicon carbide wafer 100. By taking this amount of displacement into consideration, the silicon carbide wafer can be fixed to the substrate 90 with high precision.

[0068] Next, with the silicon carbide wafer fixed to the substrate, a step (S30) is performed in which the silicon carbide substrate is ground from the second main surface. Figure 16 is a schematic cross-sectional view showing the step of grinding the silicon carbide substrate 10 from the second main surface 12. Specifically, with the silicon carbide substrate 10 and the surface element structure 20 fixed to the substrate 90, the silicon carbide substrate 10 is ground from the second main surface 12 using a grinding wheel 93.

[0069] The grinding wheel 93 is mounted, for example, on a grinding machine (not shown). The grinding wheel 93 is positioned on the second main surface 12. By pressing the grinding wheel 93, which is rotating around the rotation axis B, against the second main surface 12 along the thickness direction of the silicon carbide substrate 10, the silicon carbide substrate 10 can be thinned to a desired thickness.

[0070] In this way, the silicon carbide crystals of the silicon carbide substrate 10 on the second main surface 12 are removed. After the silicon carbide substrate 10 is ground, a processed altered layer with a disordered crystalline state is formed on the second main surface 12 of the silicon carbide substrate 10. Thus, the second main surface 12 includes a polished surface ground by the grinding wheel 93. The polished surface corresponds to the second central region 12a.

[0071] The area of ​​the surface that grinds the second main surface 12 is more than half the area of ​​the second main surface 12. As shown in Figure 16, the rotation axis B of the grinding wheel 93 is located outside the central axis A of the silicon carbide substrate 10.

[0072] Here, if the base material 90 is inside the planar region 13a (when viewed from a direction perpendicular to the third main surface 13, the base material 90 is inside the boundary line 13d), then a large pressure is applied to the planar region 13a in contact with the edge of the base material 90. As a result, there is a risk of defects occurring in the planar region 13a in contact with the edge of the base material 90.

[0073] In the manufacturing method of the silicon carbide semiconductor device 300 according to this embodiment, the substrate 90 is positioned such that, when viewed from a direction perpendicular to the third main surface 13, the edge of the substrate 90 overlaps with the edge region 13b, so as to cover at least a portion of the edge region 13b. Therefore, large pressure is not generated in the planar region 13a, and the occurrence of defects is suppressed.

[0074] Next, a dry etching process (S40) is performed. With the silicon carbide wafer 100 fixed to the substrate 90, the processed altered layer made of silicon carbide formed on the second main surface 12 of the silicon carbide substrate 10 is removed by dry etching. The processed altered layer can be removed from the silicon carbide substrate 10 by reactive ion etching using SF6 as the reaction gas. Dry etching is performed using an etching apparatus.

[0075] Next, a step (S50) is performed in which the silicon carbide wafer fixed to the substrate 90 is placed on a tray. Figure 17 is a schematic cross-sectional view showing the step of placing the silicon carbide wafer 100 on the tray 30. With the silicon carbide wafer 100 fixed to the substrate 90, the silicon carbide substrate 10 is placed on the tray 30. The step (S50) of placing the silicon carbide wafer fixed to the substrate 90 on the tray may be performed after the step (S30) of grinding the silicon carbide substrate from the second main surface, or after the dry etching step (S40).

[0076] The tray 30 has a mounting surface 31 and an inner circumferential surface 32 connected to the mounting surface 31. The substrate 90 and the silicon carbide wafer 100 are placed on the mounting surface 31 so that the substrate 90 is in contact with the mounting surface 31. When the silicon carbide wafer 100 is mounted on the tray 30, the first outer circumferential surface 21, the second outer circumferential surface 22, and the end of the substrate 90 face each other on the inner circumferential surface 32. In other words, when viewed from a direction perpendicular to the second main surface 12, the first outer circumferential surface 21, the second outer circumferential surface 22, and the substrate 90 are arranged so as to be surrounded by the inner circumferential surface 32.

[0077] As described above, the substrate 90 is positioned inside the first outer surface 21 and the second outer surface 22. Therefore, the edges of the substrate 90 do not come into contact with the inner surface 32 of the tray 30. In other words, adhesion of the substrate 90 to the tray 30 is prevented, and displacement of the silicon carbide wafer 100 is suppressed. With the silicon carbide wafer 100 mounted on the tray 30, the silicon carbide wafer 100 is transported to the next process.

[0078] Next, a step (S60) is performed in which the silicon carbide substrate 10 is heated to remove impurities. With the silicon carbide wafer 100 mounted on the tray 30, the silicon carbide substrate 10 is heated to 100°C or higher using, for example, a heater. In this way, impurities such as water vapor contained in the base material 90 can be removed. The silicon carbide substrate 10 fixed to the base material 90 may be heated to 120°C to 200°C or to 140°C to 180°C.

[0079] Next, a sputter etching process (S70) is performed. Specifically, with the silicon carbide wafer 100 fixed to the substrate 90, the silicon carbide substrate 10 fixed to the substrate 90 is sputter-etched, for example, under an argon atmosphere, to remove the SF6 reaction gas adhering to the second main surface 12 of the silicon carbide substrate 10.

[0080] Next, a step (S80) is performed to form a drain electrode on the second main surface. Figure 18 is a schematic cross-sectional view showing the process of forming the drain electrode 123. With the silicon carbide wafer 100 fixed to the substrate 90, the drain electrode 123 is formed so as to be in contact with the second main surface 12. The drain electrode 123 is formed by annealing a metal layer formed by the sputtering method.

[0081] Next, the process of forming the back surface protective electrode (S90) is carried out. Figure 19 is a schematic cross-sectional view showing the process of forming the back surface protective electrode 124. With the silicon carbide wafer 100 fixed to the substrate 90, the back surface protective electrode 124 is formed on the drain electrode 123. The back surface protective electrode 124 may be formed by sputtering.

[0082] During the process from the impurity removal step (S60) to the back surface protection electrode formation step (S90), the silicon carbide wafer 100 is mounted on the tray 30. With the silicon carbide wafer 100 mounted on the tray 30, the process from the impurity removal step (S60) to the back surface protection electrode formation step (S90) is carried out using a single sputtering apparatus. During the process from the impurity removal step (S60) to the back surface protection electrode formation step (S90), the silicon carbide substrate 10 fixed to the base material 90 may be held in a vacuum. Here, the oxygen partial pressure in the vacuum is 1 × 10⁻⁶. -4 It may be under an atmosphere of Pa or less, 1 × 10 -5 It is also acceptable in an atmosphere below Pa.

[0083] Next, the process of removing the silicon carbide wafer from the tray (S100) is carried out. The substrate 90 and the silicon carbide wafer 100 that were placed on the mounting surface 31 are removed from the tray 30. As mentioned above, the edges of the substrate 90 are not in contact with the inner circumferential surface 32 of the tray 30. In other words, since the substrate 90 is not adhering to the tray 30, displacement of the silicon carbide wafer 100 is suppressed.

[0084] Next, a step (S110) is performed to remove the substrate from the silicon carbide wafer. The substrate 90, which was fixed to the third main surface 13, is removed from the silicon carbide wafer 100. In this way, the silicon carbide semiconductor device 300 according to this embodiment shown in Figure 1 is manufactured.

[0085] Furthermore, after the step of removing the substrate from the silicon carbide wafer (S110), a new substrate (not shown) may be fixed to the back surface protective electrode 124. The new substrate may be larger than the second main surface 12 and the third main surface 13.

[0086] Next, a silicon carbide wafer dicing step may be performed. In the silicon carbide wafer dicing step, multiple silicon carbide semiconductor devices 300 can be obtained by cutting the silicon carbide wafer 100, the drain electrode 123, and the back surface protective electrode 124 in the thickness direction of the silicon carbide substrate 10. Laser dicing or scribing may be used to cut the silicon carbide wafer 100, the drain electrode 123, and the back surface protective electrode 124.

[0087] Next, the effects and advantages of the manufacturing method of the silicon carbide semiconductor device 300 according to this embodiment will be described.

[0088] When grinding the silicon carbide substrate 10 from the second main surface 12 while the silicon carbide wafer 100 is fixed to the substrate 90, if the edge of the substrate 90 is in contact with the planar region 13a, a large amount of pressure is applied to the area where the edge of the substrate 90 is in contact. As a result, there is a risk of chipping occurring in the planar region 13a where the edge of the substrate 90 is in contact.

[0089] A method for manufacturing a silicon carbide semiconductor device 300 according to this disclosure comprises the steps of: preparing a silicon carbide wafer 100 (S10); fixing the silicon carbide wafer 100 to a substrate 90 (S20); and grinding the silicon carbide substrate 10 from the second main surface 12 while the silicon carbide wafer 100 is fixed to the substrate 90 (S30). The silicon carbide wafer 100 includes a silicon carbide substrate 10 and a surface element structure 20. The surface element structure 20 is formed on the silicon carbide substrate 10. The silicon carbide substrate 10 has a first main surface 11, a second main surface 12, and a first outer peripheral surface 21. The second main surface 12 is located opposite the first main surface 11. The first outer peripheral surface 21 is connected to the first main surface 11. The surface element structure 20 is formed on the first main surface 11. The first main surface 11 is composed of a first chamfered region 11b and a first central region 11a. The first chamfered region 11b is connected to the first outer peripheral surface 21. The first central region 11a is surrounded by the first chamfered region 11b. The surface element structure 20 has a third main surface 13 and a second outer peripheral surface 22. The third main surface 13 is located opposite the first main surface 11. The second outer peripheral surface 22 is connected to the third main surface 13. The third main surface 13 is composed of an end region 13b and a planar region 13a. The end region 13b is opposite to the first chamfered region 11b. The planar region 13a is opposite to the first central region 11a. The substrate 90 is more flexible than the silicon carbide substrate 10. In the step of fixing the silicon carbide wafer 100 to the substrate 90 (S20), the substrate 90 covers the entire planar region 13a and at least a portion of the edge region 13b. In this way, when viewed from a direction perpendicular to the third main surface 13, the edge of the substrate 90 is positioned to overlap the edge region 13b. Therefore, large pressure is not generated in the planar region 13a, and the occurrence of defects is suppressed.

[0090] According to the manufacturing method of the silicon carbide semiconductor device 300 described herein, the substrate 90 may be positioned inside the second outer peripheral surface 22 when viewed from a direction perpendicular to the third main surface 13. In this way, when the silicon carbide wafer 100 is mounted on the tray 30, contact between the substrate 90 and the tray is suppressed.

[0091] The method for manufacturing the silicon carbide semiconductor device 300 according to this disclosure may include a step of forming a drain electrode 123 on the second main surface 12 (S90), and a step of heating the silicon carbide substrate 10 to remove impurities (S60) after the step of grinding the silicon carbide substrate 10 from the second main surface 12 (S30) and before the step of forming the drain electrode 123 on the second main surface 12 (S90). In this way, impurities such as water vapor contained in the substrate 90 can be removed.

[0092] The embodiments and examples disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than the foregoing description and is intended to include all modifications within the meaning and scope of the claims. [Explanation of Symbols]

[0093] 10 Silicon carbide substrate 11. First Main Surface 11a 1st central area 11b First chamfered area 11c center 11d border 12 Second Main Surface 12a 2nd central area 12b Second chamfered area 13 Third Main Surface 13a Plane area 13b End area 13c center 13d border 14. Fourth Main Surface 20 Surface element structure 21 First outer surface 22 Second outer peripheral surface 22a Arc-shaped portion 22b Orientation Flat Section 30 Drip tray 31 Mounting surface 32 Inner surface 40 Silicon carbide epitaxial layer 51 Buffer Layer 52 Drift Layers 53 Side wall 54 Bottom wall 56 Trench 90 Base material 91 Adhesive part 92 Base section 93 Sharpening Stone 100 silicon carbide wafers 113 Body Region 114 Source Area 115 Gate Insulator 116 Source electrodes 117 masks 118 Contact Area 119 Surface protection electrode 123 Drain electrode 124 Backside protective electrode 126 Interlayer insulating film 127 Gate 300 Silicon Carbide Semiconductor Devices A center axis B Rotation axis d1 distance d2 distance

Claims

1. The process includes a step of preparing a silicon carbide wafer, which includes a silicon carbide substrate and a surface element structure formed on the silicon carbide substrate. The silicon carbide substrate has a first main surface, a second main surface located opposite the first main surface, and a first outer peripheral surface connected to the first main surface. The surface element structure is formed on the first main surface, The first main surface is composed of a first chamfered region connected to the first outer surface and a first central region surrounded by the first chamfered region. The surface element structure has a third main surface located opposite the first main surface and a second outer peripheral surface connected to the third main surface. The third main surface is composed of an end region facing the first chamfered region and a planar region facing the first central region, and further, A step of fixing the silicon carbide wafer to a substrate that is more flexible than the silicon carbide substrate, The process includes grinding the silicon carbide substrate from the second main surface while the silicon carbide wafer is fixed to the substrate, In the step of fixing the silicon carbide wafer to the substrate, A method for manufacturing a silicon carbide semiconductor device, wherein the substrate covers the entire planar region and covers at least a portion of the edge region.

2. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein, when viewed from a direction perpendicular to the third main surface, the substrate is arranged inside the second outer peripheral surface.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the end region is within 0.5 mm from the second outer surface toward the center of the third main surface.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the second main surface includes a polished surface.

5. In the process, the silicon carbide substrate is laid from the second main surface, The silicon carbide substrate is ground from the second main surface using a grinding wheel. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the rotation axis of the grinding wheel is positioned outside the central axis of the silicon carbide substrate.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the maximum diameter of the first main surface is 95 mm or more.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the maximum diameter of the first main surface is 205 mm or less.

8. A method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising the step of grinding the silicon carbide substrate from the second main surface, and then mounting the silicon carbide wafer fixed to the substrate onto a receiving tray.

9. The step of forming a drain electrode on the second main surface, A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 8, comprising the step of heating the silicon carbide substrate to remove impurities after the step of grinding the silicon carbide substrate from the second main surface and before the step of forming the drain electrode on the second main surface.

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