Arithmetic processing unit, arithmetic processing system, arithmetic processing method, arithmetic processing program, information processing unit, information processing method, and information processing program

Abstract

A processing unit is configured to connect processing cores equipped with systolic arrays, and then accurately perform super-resolution processing for each segmented image. [Solution] The system includes multiple computing cores, each containing multiple computing units that perform calculations on segmented images obtained by dividing an image according to a trained model, and a storage unit that stores multiple trained models trained using training datasets with different features. The system reads the segmented images from the storage unit (step S201), selects a trained model for each of the multiple computing cores according to the features of the segmented images to be calculated by each of the multiple computing cores (S202), and causes each of the multiple computing cores to perform calculations on the segmented images according to the selected trained model (S203).

Description

Technical Field

[0001] The present invention relates to an arithmetic processing device, an arithmetic processing system, an arithmetic processing method, an arithmetic processing program, an information processing device, an information processing method, and an information processing program.

Background Art

[0002] Super-resolution technology for generating a high-resolution image from a low-resolution image is known. Such super-resolution processing is also utilized in the field of gaming machines. There has been a consideration to execute super-resolution processing that was conventionally performed by calculation algorithms such as bilinear and bicubic using inference processing. Inference processing is a process executed using a learned model of machine learning including a network structure and weights. In the following description, super-resolution processing using inference processing is also referred to as super-resolution processing using AI or simply super-resolution processing. Convolution processing is an important process in super-resolution processing. A processor having a characteristic configuration for performing convolution processing is disclosed in Patent Document 1. The processor disclosed in Patent Document 1 includes a plurality of processing cores each having a plurality of processing elements arranged in a matrix called a systolic array. The processor of Patent Document 1 inputs information of low-resolution data to be subjected to super-resolution processing and weight data based on a learned model to each processing core and performs convolution processing. More specifically, input data is supplied in the row direction of the systolic array, weight data is supplied in the column direction of the systolic array, and convolution processing is performed by sequentially multiplying and accumulating the input data and the weight data by the processing elements based on the network structure based on the learned model.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] By linking together numerous processing cores that have systolic arrays as described in Reference 1, and having each processing core process the divided low-resolution data, it is expected that super-resolution processing, including convolution, can be accelerated. However, in conventional super-resolution processing using multiple processing cores, each processing core performs super-resolution processing, including convolution, using the same pre-trained model, regardless of the features of the segmented images input to each processing core. Therefore, it was not possible to perform convolution processing accurately using a pre-trained model optimized for the features of the segmented images. One aspect of the present invention is to enable accurate convolution processing for each segmented image in a computing device that connects processing cores equipped with a systolic array, such as the one disclosed in Patent Document 1. [Means for solving the problem]

[0005] The information processing system of the present invention comprises, in one aspect, a plurality of processing cores including a plurality of processing units that perform operations according to a trained model on segmented images obtained by dividing an image; a storage unit that stores a plurality of trained models trained using training datasets with different characteristics; and a selection unit that selects a trained model for each of the plurality of processing cores according to the characteristics of the segmented images on which the operations are performed, and controls the plurality of processing cores according to the selected trained model to perform the operations on each segmented image. [Effects of the Invention]

[0006] According to the present invention, one aspect is that a computing device with interconnected processing cores can perform convolution processing with high accuracy for each segmented image. [Brief explanation of the drawing]

[0007] [Figure 1] This diagram shows a conventional processing unit that performs super-resolution processing. [Figure 2] This figure illustrates the super-resolution processing using the processing unit shown in Figure 1. [Figure 3] This figure shows the arithmetic processing unit of Figure 2 in more detail. [Figure 4] Figure 2 illustrates a conventional super-resolution processing method using the processing unit shown in Figure 2. [Figure 5] This diagram illustrates the arithmetic processing performed by the arithmetic processing unit in Figure 3. [Figure 6] This is a functional block diagram showing an example of the arithmetic processing system of the first embodiment. [Figure 7] This figure shows model information, which associates a trained model with a model identifier. [Figure 8] This figure shows segmented image information, which associates segmented images with model identifiers. [Figure 9] This flowchart shows an example of the processing performed by the information processing device of the first embodiment. [Figure 10] This is a flowchart showing an example of the processing performed by the arithmetic processing unit of the first embodiment. [Figure 11] This figure illustrates the super-resolution processing of the second embodiment. [Figure 12] This figure illustrates the super-resolution processing of the second embodiment. [Figure 13] This figure shows the segmented layer information, which associates segmented layers with model identifiers. [Figure 14] This is a functional block diagram showing an example of the arithmetic processing system of the second embodiment. [Figure 15] This figure illustrates the super-resolution processing of the third embodiment. [Figure 16] This figure shows the segmented layer information, which associates low-resolution segmented layers with the characteristics of low-resolution segmented layers. [Figure 17] This figure shows segmented image information associated with a pre-trained model suitable for segmented images. [Figure 18] This figure shows model information, which associates a trained model with a model identifier. [Figure 19] It is a functional block diagram showing an example of an arithmetic processing system according to the third embodiment. [Figure 20] It is a diagram showing a schematic configuration of a gaming machine. [Figure 21] It is a diagram showing the configuration of an effect control device. [Figure 22] It is a block diagram showing an example of a computer device.

Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments, and can be implemented with appropriate modifications within the scope of the object of the present invention. The arithmetic processing device of the present embodiment is an arithmetic processing device including an arithmetic core having a systolic array by a plurality of arithmetic cores. The systolic array is configured to efficiently execute convolution processing. Hereinafter, super-resolution processing including convolution processing using the systolic array will be described as an example, but the arithmetic processing device of the present embodiment can be applied to general convolution processing.

[0009] FIG. 1 is a configuration diagram showing an arithmetic processing system that executes super-resolution processing. The arithmetic processing system 100 includes an information processing device 101, a storage device 102, and an arithmetic processing device 103. The information processing device 101 generates an image to be subjected to super-resolution processing including convolution processing. Then, the information processing device 101 writes the generated image into the storage device 102. Note that generating an image means drawing an image by overlapping layers each including an object such as a character, a symbol, a character, or a background. In the following description, when characters, symbols, and characters are not particularly distinguished, these are also referred to as objects. The background is distinguished from objects such as characters, symbols, and characters.

[0010] The storage device 102 is connected to the information processing device 101 and stores images generated by the information processing device 101. The storage device 102 is also connected to the arithmetic processing device 103 and outputs images to the arithmetic processing device 103 in response to requests from the arithmetic processing device 103. The arithmetic processing unit 103 requests data from the storage device 102 and divides the low-resolution image input from the storage device 102 to generate segmented images. The arithmetic processing unit 103 increases the resolution of the segmented images through super-resolution processing to generate high-resolution segmented images. Then, the arithmetic processing unit 103 combines the high-resolution segmented images to generate a high-resolution image.

[0011] Figure 2 shows a processing unit that performs super-resolution processing. The arithmetic processing unit 103 shown in Figure 2 comprises a control circuit 10, an arithmetic core 20, an arithmetic core 30, an arithmetic core 40, and an arithmetic core 50. In the following description, when arithmetic cores 20, 30, 40, and 50 are not distinguished, they will simply be referred to as arithmetic cores. Although they are denoted by different symbols, all of these arithmetic cores can have the same configuration.

[0012] Figure 3 is a diagram that shows the arithmetic processing unit of Figure 2 in more detail. The arithmetic processing unit 103 comprises a control circuit 10 and four arithmetic cores: 20, 30, 40, and 50. For the sake of simplicity, the arithmetic processing unit 103 is assumed to contain four arithmetic cores. Furthermore, each arithmetic core contains nine arithmetic units in the systolic array SA described later, arranged in a 3x3 grid. However, the number of arithmetic cores in the arithmetic processing unit 103 and the number of arithmetic units in the systolic array SA may be set to any number as appropriate, depending on the type and size of the data being handled.

[0013] The arithmetic core 20 includes a weight memory 21, a data memory 22, an address generator 23, a weight output unit 24, a data output unit 25, a plurality of arithmetic units 26 that construct a systolic array SA, an output memory 27, and an arithmetic result output unit 28. The arithmetic core 30 includes a weight memory 31, a data memory 32, an address generator 33, a weight output unit 34, a data output unit 35, a plurality of arithmetic units 36 that construct a systolic array SA, an output memory 37, and an arithmetic result output unit 38. The arithmetic core 40 includes a weight memory 41, a data memory 42, an address generator 43, a weight output unit 44, a data output unit 45, a plurality of arithmetic units 46 that construct a systolic array SA, an output memory 47, and an arithmetic result output unit 48. The arithmetic core 50 includes a weight memory 51, a data memory 52, an address generator 53, a weight output unit 54, a data output unit 55, a plurality of arithmetic units 56 that construct a systolic array SA, an output memory 57, and an arithmetic result output unit 58. In each computing core, the systolic array SA has, for example, computing units arranged in a matrix.

[0014] In the following explanation, when weight memories 21, 31, 41, and 51 are not distinguished, they will simply be referred to as weight memory WM. Similarly, when data memories 22, 32, 42, and 52 are not distinguished, they will simply be referred to as data memory DM. Address generators 23, 33, 43, and 53 are not distinguished, they will simply be referred to as address generator AG. Weight output units 24, 34, 44, and 54 are not distinguished, they will simply be referred to as weight output unit WO. Data output units 25, 35, 45, and 55 are not distinguished, they will simply be referred to as data output unit DO. Arithmetic units 26, 36, 46, and 56 are not distinguished, they will simply be referred to as arithmetic unit PE. Output memories 27, 37, 47, and 57 are not distinguished, they will simply be referred to as output memory OM. Arithmetic result output units 28, 38, 48, and 58 are not distinguished, they will simply be referred to as arithmetic result output unit OO. In the diagrams from Figure 3 onward, the weight memory is denoted as WM, and the data memory as DM. The address generator is denoted as AG, and the weight output unit as WO. The output memory is denoted as OM, the arithmetic unit as PE, and the arithmetic result output unit as OO.

[0015] The super-resolution processing using the arithmetic processing unit 103 shown in Figures 2 and 3 will be explained using conventional super-resolution processing. In conventional super-resolution processing, the same trained model is applied to each arithmetic core. In each embodiment of this embodiment, as described later, the trained model applied to the arithmetic core is different depending on the characteristics of the low-resolution image input to the arithmetic core. This enables more optimized super-resolution processing. The configuration of the arithmetic processing unit 103 remains unchanged from the conventional technology and embodiments described below, and different processing is achieved by the control circuit 10's control of the address generator AG of each arithmetic core.

[0016] Figure 4 illustrates a conventional super-resolution processing method using the processing unit shown in Figure 2. The conventional technique shown in Figure 4 simply divides the generated low-resolution image described above, inputs the divided images into each computing core, performs super-resolution processing based on the same trained model, and then synthesizes them to obtain a high-resolution image. The first embodiment, which will be explained from Figure 6 onwards, will also be explained using Figure 4. In the first embodiment, the images input to each computing core are the same as in Figure 4, but different trained models are applied to each computing core.

[0017] The arithmetic processing unit 103 takes the low-resolution image p0 in Figure 4(a) as an input image and performs inference processing to generate the high-resolution image P0 in Figure 4(d). More specifically, the control circuit 10 divides the low-resolution image p0 input to the arithmetic processing unit 103 to generate the low-resolution divided images p1 to p4 shown in Figure 4(b). The control circuit 10 then inputs the generated segmented images p1 to p4 to the processing cores 20, 30, 40, and 50, respectively. The processing cores 20, 30, 40, and 50 each perform super-resolution processing, including convolution, on the input segmented images p1 to p4 to generate high-resolution segmented images P1 to P4 as shown in Figure 4(c). The control circuit 10 further combines the segmented images P1 to P4 to generate a high-resolution image P0 as shown in Figure 4(d). In the following explanation, when no particular distinction is made between the divided images p1 to p4, they will also be referred to as low-resolution divided images. Similarly, when no particular distinction is made between the divided images P1 to P4, they will also be referred to as high-resolution divided images.

[0018] The number of divisions in a low-resolution image can correspond to the number of processing cores in the processing unit 103. In other words, in super-resolution processing, multiple processing cores are used in coordination depending on the size of the low-resolution input image (input data). By increasing the resolution of each divided image with the corresponding processing core, super-resolution processing can be performed efficiently. The more processing units that constitute the systolic array included in the processing core (described later) the processing core can handle, the larger the size of the divided images that the processing core can convolve. Therefore, the more processing units a processing core has, the fewer divisions the low-resolution image can be. This is also true in each of the embodiments described later.

[0019] Figure 5 is a diagram illustrating the arithmetic processing performed by the arithmetic processing unit shown in Figure 3. As shown in Figure 5, the arithmetic unit PE performs a sum-of-products operation between the input data Dxx written to the data memory DM and the weights Wxx written to the weight memory WM, and stores the calculation result in the output memory OM. As an example, in the frontmost processing core 20, D11*W11+D12*W12+D13*W13, D11*W21+D12*W22+D13*W23, D11*W31+D12*W32+D13*W33 D21*W11+D22*W12+D23*W13, D21*W21+D22*W22+D23*W23, D21*W31+D22*W32+D23*W33 D31*W11+D32*W12+D33*W13, D31*W21+D32*W22+D33*W23, D31*W31+D32*W32+D33*W33 This is written to output memory 27. The output memory 27 outputs the calculation result to the calculation result output unit 28 according to the output address. When the calculation result is input from the output memory 27, the calculation result output unit 28 outputs the calculation result to the data memory 22, the write destination, according to the write address.

[0020] In the subsequent processing core 30, D41*W11+D42*W12+D43*W13, D41*W21+D42*W22+D43*W23, D41*W31+D42*W32+D43*W33 D51*W11+D52*W12+D53*W13, D51*W21+D52*W22+D53*W23, D51*W31+D52*W32+D53*W33 D61*W11+D62*W12+D63*W13, D61*W21+D62*W22+D63*W23, D61*W31+D62*W32+D63*W33 This is written to output memory 37. The output memory 37 outputs the calculation result to the calculation result output unit 38 according to the output address. When the calculation result is input from the output memory 37, the calculation result output unit 38 outputs the calculation result to the data memory 32, the write destination, according to the write address. Each arithmetic core's arithmetic unit may, if necessary, perform addition operations that add a value called a bias term in addition to the sum-of-products operation.

[0021] In the conventional example, the weights input to each processing core are the same. Furthermore, the input data to each of the processing cores 20 through 50 corresponds to the values ​​of the divided images p1 through p4, respectively. Each processing core repeats the above process to perform a convolution operation and generates high-resolution segmented images P1 to P4 shown in Figure 4(c). Furthermore, the control circuit 10 combines the segmented images P1 to P4 to generate a high-resolution image P0 shown in Figure 4(d), which is a higher-resolution version of the image p0 shown in Figure 4(a).

[0022] In the explanation for Figure 4, the same pre-trained model is applied to each computing core. In this case, it is not possible to perform super-resolution processing accurately using a pre-trained model optimized for the features of the segmented images. In the embodiments described below, the processing unit 103 of the arithmetic processing system 100 having the configuration shown in Figures 1 to 3 uses different trained models applied to each processing core, and performs super-resolution processing with high accuracy using trained models optimized for the features of the segmented images.

[0023] [First Embodiment] In the first embodiment, as described in Figure 4, super-resolution processing is performed on the divided images obtained by simply dividing the layered low-resolution image. However, in the information processing system 100 of Figure 1, the information processing device 101 pre-associates an identifier of a trained model used for super-resolution processing with each segmented image and stores it in the storage device 102. The information processing device 101 may determine the trained model to be used in the super-resolution processing of each segmented image by, for example, using the scene analysis disclosed in International Publication 2021 / 193648 or the "image comparison (image quality comparison as an image processing result using a trained model)" disclosed in International Publication 2021 / 095256. The information processing device 101 may also determine the trained model to be used in the super-resolution processing of each segmented image by performing inference processing using the trained model for determining the features of the segmented image.

[0024] The storage device 102 stores the identifier of the trained model determined by the information processing device 101 in association with the segmented image. The storage device 102 stores the segmented images p1 to p4 (Figure 4) generated by the information processing device 101 in association with the identifier of the trained model used in the super-resolution processing of the segmented images p1 to p4. In the first embodiment, the arithmetic processing unit 103 reads a segmented image from the storage device 102 and refers to the identifier of the trained model associated with the read segmented image. The arithmetic processing unit 103 uses the trained model corresponding to the trained model identifier to perform super-resolution processing on the segmented image and generate a high-resolution segmented image. The arithmetic processing unit 103 then combines the generated high-resolution segmented images to generate a high-resolution image.

[0025] More specifically, the control circuit 10 of the processing unit 103 reads out the segmented images p1 to p4 and the identifiers of the trained models associated with the segmented images p1 to p4 from the storage device 102. The control circuit 10 then outputs the divided image p1 to the processing core 20. The control circuit 10 then outputs the divided image p2 to the processing core 30. The control circuit 10 then outputs the divided image p3 to the processing core 40. The control circuit 10 then outputs the divided image p4 to the processing core 50. The control circuit 10 refers to the identifier of the trained model associated with the segmented image p1 and outputs the weights to the computing core 20 according to the corresponding trained model. The control circuit 10 refers to the identifier of the trained model associated with the segmented image p2 and outputs the weights to the computational core 30 according to the corresponding trained model. The control circuit 10 refers to the identifier of the trained model associated with the segmented image p3 and outputs the weights to the computing core 40 according to the corresponding trained model. The control circuit 10 refers to the identifier of the trained model associated with the segmented image p4 and outputs the weights to the computing core 50 according to the corresponding trained model. Computation cores 20 to 50 perform super-resolution processing on the divided images p1 to p4, including convolution, pooling, and activation function processing, respectively, thereby generating high-resolution divided images P1 to P4 as shown in Figure 4(c). Next, the control circuit 10 combines the divided images P1 to P4 to generate a high-resolution image P0, which is the same image p0 shown in Figure 4(d). With the above configuration, the arithmetic processing unit 103 improves the accuracy of super-resolution processing performed by the arithmetic processing unit 103 using the arithmetic core.

[0026] Referring to Figures 3 and 4, the processing of the control circuit 10 and the arithmetic core 20 in the first embodiment will be explained. Since the arithmetic cores 30 to 50 have the same configuration and perform the same processing as the arithmetic core 20, their explanation will be omitted. The control circuit 10 stores the weights to be used in the convolution process in the weight memory 21 of the computing core 20, according to the trained model corresponding to the identifier of the trained model associated with the segmented image p1. Furthermore, the control circuit 10 stores the input data corresponding to the low-resolution segmented image p1 shown in Figure 4(b), which is read from the storage device 102, in the data memory 22. The control circuit 10 creates address generation information (control information) according to the learned model and outputs it to the address generator 23 of the arithmetic core 20. The address generator 23 generates various addresses from the input address generation information and inputs the generated addresses to the weight output unit 24, the data output unit 25, and the calculation result output unit 28, respectively.

[0027] The weight output unit 24 receives the weight address indicating the output order of the weights. The data output unit 25 receives the data address indicating the output order of the input data. The calculation result output unit 28 receives the write address indicating the data memory to which the calculation result will be written. Furthermore, the output memory 27 receives output addresses indicating the output order of the calculation results via the data output unit 25. The weight output unit 24 outputs the weights according to the weight addresses. The data output unit 25 outputs the input data according to the data address. As a result, each arithmetic unit 26 in the arithmetic core 20 performs a sum-of-products operation on the input data and weights, and stores the calculation result in the output memory 27. Each arithmetic unit 26 of the arithmetic core 20 may, if necessary, perform an addition operation in addition to the sum-of-products operation by adding a value called a bias term.

[0028] Furthermore, between the arithmetic units that construct the systolic array and the output memory, there are processing blocks (not shown) that perform pooling and activation function processing. The control circuit 10 then issues instructions to the processing blocks according to the learned model, performing pooling and activation function processing on the processing results from each arithmetic unit, and stores the results as calculation results in the output memory 27. The output memory 27 outputs the calculation result to the calculation result output unit 28 according to the output address. When the calculation result is input from the output memory 27, the calculation result output unit 28 outputs the calculation result to the data memory 22, the write destination, according to the write address. The processing core 20 performs the convolution process by repeating the above-described process.

[0029] Then, the control circuit 10 reads the calculation results from data memory 22, data memory 32, data memory 42, and data memory 52 according to the learned model and generates high-resolution segmented images P1 to P4 shown in Figure 4(c). Furthermore, the control circuit 10 combines the divided images P1 to P4 to generate the image P0 shown in Figure 4(d), which is a high-resolution version of the image p0 shown in Figure 4(a). The configuration of the arithmetic processing unit 103 according to the first embodiment involves connecting conventionally known arithmetic cores and applying them to super-resolution processing using inference processing. However, by selecting a pre-trained model to be used by each arithmetic core according to the characteristics of the segmented image input to each arithmetic core, super-resolution processing can be performed with high accuracy.

[0030] Figure 6 is a functional block diagram showing an example of the arithmetic processing system of the first embodiment. Figure 7 shows model information, which associates the trained model with the model identifier. Figure 8 shows segmented image information, which associates segmented images with model identifiers. The calculation system 100 of the first embodiment will be described in more detail with reference to Figures 6 to 8. The information processing device 101 will be described. The information processing device 101 comprises a control unit 60 and a storage unit 70. The control unit 60 includes a division unit 61, a determination unit 62, an association unit 63, and a writing unit 64. The memory unit 70 stores model information 71, image information 72, and segmented image information 73. As shown in Figure 7, the model information 71 stores pre-trained models associated with model identifiers for each type of low-resolution image (object or background). The pre-trained models displayed in the model information 71 corresponding to the model identifier are the optimal pre-trained models for the object or background, respectively. The corresponding image type (object or background) can be identified by the model identifier, and the image type does not necessarily need to be included in the model information 71.

[0031] In the model information 71 of Figure 7, the trained model LA corresponding to the model identifier IA is a trained model that was trained using a training dataset, prepared for super-resolution processing of character images through inference. The trained model LB, corresponding to the model identifier IB, is a trained model prepared for super-resolution processing of image data by inference, and trained using the training dataset. The trained model LC, corresponding to the model identifier IC, is a trained model that has been trained using the training dataset and is prepared for super-resolution processing of background images through inference. The trained model LD corresponding to the model identifier ID is a trained model that has been trained using the training dataset and is prepared for super-resolution processing of character images through inference. In the above, the trained models are classified according to the training dataset used for training; however, they could also be classified according to the image quality obtained by super-resolution processing, and consequently, the load on super-resolution processing. Generally, the larger (longer) the network structure of the pre-trained model used for super-resolution processing, the better the image quality, but the higher the inference processing load naturally becomes. It is preferable to select a pre-trained model according to the type of image and the desired image quality. For example, it is desirable to use a low-resolution (low-load) pre-trained model for backgrounds and a high-resolution (high-load) pre-trained model for objects (text, patterns, characters). You can also assign priorities to objects, such as using the highest quality (highest load) for text, medium-high quality (medium-high load) for patterns, and low-high quality (low-high load) for characters. In the following explanation, for example, the pre-trained model LA for characters may mean a high-resolution (highest load) pre-trained model, the pre-trained model LB for images may mean a medium-high resolution (medium-high load) pre-trained model, and the pre-trained model LD for characters may mean a low-high resolution (low-high load) pre-trained model. The model information 71 is stored as model information 81 in the storage unit 80 of the arithmetic processing unit 103, which will be described later, via the storage device 102.

[0032] Image information 72 stores a low-resolution image that is the target of super-resolution processing. The low-resolution image may be an image generated by the information processing device 101 based on image data, or it may be an image pre-generated by another device. An example of a low-resolution image is image p0 shown in Figure 4(a). The segmented image information 73 shown in Figure 8 stores the segmented image and a model identifier indicating the trained model to be used for that segmented image, in association with each other. Since the model identifier allows for the identification of the learning model to be applied to the segmented image, the type of image that the learning model corresponds to does not necessarily need to be included in the segmented image information 73. The segmented images are low-resolution segmented images generated by the segmentation unit 61 by dividing the image. Examples of low-resolution segmented images are the segmented images p1 to p4 shown in Figure 4(b). In the following explanation, we will refer to the low-resolution segmented images p1 to p4 shown in Figure 4(b), which are stored in segmented image 73. I will omit the explanation, but the same process is performed on the segmented images p5 through p8.

[0033] The splitting unit 61 divides the low-resolution image stored in the image information 72 to generate low-resolution segmented images. For example, the splitting unit 61 divides the low-resolution image p0 shown in Figure 4(a) to generate low-resolution segmented images p1 to p4 shown in Figure 4(b). The decision unit 62 determines the trained model to be used for super-resolution processing of each segmented image from the trained models shown in Figure 7. The determination unit 62, for example, analyzes the segmented images to determine the optimal trained model for super-resolution processing of each segmented image. The determination unit 62 may also determine the trained model to be used for super-resolution processing of each segmented image by utilizing the scene analysis and image comparison described above. Alternatively, the information processing device 101 may determine the trained model to be used for super-resolution processing of each segmented image by performing inference processing using a trained model for determining the features of the segmented images. Specifically, since the segmented image p1 in Figure 4(b) contains many characters, the decision unit 62 decides to use the trained model LA for segmented image p1. Similarly, since the segmented image p2 in Figure 4(b) contains many patterns, the decision unit 62 decides to use the trained model LB for segmented image p2. Furthermore, since the segmented image p3 in Figure 4(b) contains many backgrounds, the decision unit 62 decides to use the trained model LC for segmented image p3. Finally, since the segmented image p4 in Figure 4(b) contains many characters, the decision unit 62 decides to use the trained model LD for segmented image p4. In this case, the decision unit 62 may determine which trained model to use based on the content of the divided images, taking into consideration the processing load and image quality of each trained model as described above.

[0034] The association unit 63 associates a model identifier with the low-resolution segmented image and stores it in the segmented image information 73 (Figure 8) according to the decision of the determination unit 62. Furthermore, the trained model to be used for each segmented image is not determined by the information processing device 101, but rather by the user of the information processing device 101, who may decide on the model based on the content of the segmented image and the processing load and image quality of each trained model, and register it in the segmented image information 73. The information processing device 101 may be equipped with an editing unit that uses an input device such as a keyboard to register the information in the segmented image information 73. The writing unit 64 writes the segmented image information 73 to the storage device 102. The writing unit 64 may also compress the low-resolution segmented images stored in the segmented image information 73 before writing them to the storage device 102. The storage device 102 stores the segmented image information 73 in response to a write request from the information processing device 101. The storage device 102 also outputs the information contained in the segmented image information 73 to the arithmetic processing device 103 in response to a read request from the arithmetic processing device 103.

[0035] The arithmetic processing unit 103 will now be described. The arithmetic processing unit 103 comprises a control unit 10, a storage unit 80, and an arithmetic unit 90. In describing the arithmetic processing unit 103, the process when reading segmented image p1 corresponding to the model identifier IA from the segmented image information 73 in Figure 8 from the storage device 102 will be described as an example. Similar processing is performed when reading other segmented images p2 to p8, so some explanation will be omitted.

[0036] The control unit 10 includes a reading unit 11, a selection unit 12, an output unit 13, and a coupling unit 14. The memory unit 80 stores model information 81 and calculation result information 82. Model information 81 stores the same information as model information 71, as explained in Figure 7. This allows the processing unit 103 to perform super-resolution processing using the trained model determined by the information processing unit 101. Note that model information 81 only needs to contain the information stored in model information 71, and may also store more trained models. The calculation result information 82 stores the calculation results obtained by convolution processing of the input data corresponding to the low-resolution segmented images in the calculation cores 20 to 50. Note that if the calculation results are processed directly by the merging unit 14 after being read by the reading unit 11 (described later), the calculation result information 82 may be omitted.

[0037] The reading unit 11 reads a low-resolution segmented image p1 and the model identifier IA associated with segmented image p1 from the segmented image information 73 stored in the storage device 102. If the low-resolution segmented image stored in the segmented image information 73 is compressed, the reading unit 11 may decompress the low-resolution segmented image. Furthermore, the reading unit 11 reads the calculation results of the convolution process from the calculation unit 90 according to the trained model and stores them in the calculation result information 82. The selection unit 12 refers to the model identifier IA read out by the reading unit 11 and selects a trained model LA to be used for super-resolution processing from the model information 81. The output unit 13 reads the trained model LA selected by the selection unit 12 from the model information 81. Then, the output unit 13 outputs the weights to be used in the convolution process according to the trained model LA to the arithmetic core 20 of the arithmetic unit 90. Furthermore, the output unit 13 outputs the input data corresponding to the segmented image p1 to the arithmetic core 20 of the arithmetic unit 90.

[0038] The coupling unit 14 reads the calculation results from the calculation result information 82 according to the trained model and generates high-resolution segmented images. The high-resolution segmented images are, for example, the segmented images P1 to P4 shown in Figure 4(c). The coupling unit 14 then combines the high-resolution segmented images to generate a high-resolution image. The high-resolution image is, for example, image P0 shown in Figure 4(d), which is generated by combining the segmented images P1 to P4. The arithmetic unit 90 includes arithmetic cores 20 to 50, each of which performs convolution processing according to control from the control unit 10. Each arithmetic core also outputs the calculation result of the super-resolution processing to the control unit 10 according to a request from the control unit 10. As described above, the arithmetic processing system 100 performs super-resolution processing on a low-resolution image to generate a high-resolution image.

[0039] Figure 9 is a flowchart showing an example of processing in the information processing device of the first embodiment. Please refer to Figure 9 for further explanation. In step S101, the information processing device 101 divides the low-resolution image stored in the image information 72 to generate low-resolution divided images. In step S102, the information processing device 101 analyzes the contents of the low-resolution segmented image (objects and background included in the segmented image) and determines the characteristics of the low-resolution segmented image. The information processing device 101 may, for example, determine the characteristics of the segmented image based on the object or background that occupies the most pixels among the contents included in the low-resolution segmented image. The information processing device 101 may, for example, determine the characteristics of the segmented image using the scene analysis described above. Alternatively, the information processing device 101 may, for example, determine the characteristics of the segmented image by performing inference processing using a trained model for determining objects and background included in the low-resolution segmented image. In step S103, the information processing device 101 associates the segmented images with model identifiers according to the characteristics of the segmented images and creates segmented image information 73. In step S104, the information processing device 101 stores the segmented image information 73 in the storage device 102.

[0040] Figure 10 is a flowchart showing an example of the processing of the arithmetic processing unit of the first embodiment. Refer to Figure 10 for further explanation. In step S201, the processing unit 103 reads the divided image from the storage device 102. In step S202, the processing unit 103 selects a trained model to be used for super-resolution processing by referring to the model identifier associated with the read segmented image. The arithmetic processing unit 103 reads the trained model selected in step S202 from the model information 81. Then, in step S203, the arithmetic processing unit 103 performs super-resolution processing according to the trained model read out, as described above. As a result, the arithmetic processing unit 103 performs super-resolution processing with high accuracy using a pre-trained model suitable for each systolic array.

[0041] [Second Example] The arithmetic processing system 100 of the second embodiment has the same configuration as the arithmetic processing system 100 of Figure 1. The second embodiment differs from the first embodiment in that the information processing device 101 generates a divided layer for each layer used in image generation, and the arithmetic processing device 103 applies an appropriate trained model to each divided layer to perform super-resolution processing. Figures 11 and 12 illustrate the super-resolution processing of the second embodiment. Figure 13 shows the segmented layer information, which associates segmented layers with model identifiers. A second embodiment will be outlined with reference to Figures 11 to 13. A low-resolution image is, for example, the low-resolution image p00 shown in Figure 11(a). A low-resolution layer is a layer for compositing low-resolution images, and is, for example, the low-resolution layers p10 to p40 shown in Figure 11(b). The information processing device 101 divides the low-resolution layer to generate low-resolution divided layers. The low-resolution divided layers are, for example, the divided layers p11 to p44 shown in Figure 11(c). The information processing device 101 determines a trained model suitable for super-resolution processing for each segmented layer, associates each segmented layer with the model identifier of the selected trained model, and stores it in segmented layer information 75 (Figure 13). The information processing device 101 stores the segmented layer information 75 in the storage device 102.

[0042] In the segmented layer information shown in Figure 13, the presence of a blank (-) in the model identifier indicates that the process simply increases the number of pixels, rather than performing super-resolution processing using a pre-trained model. For example, the low-resolution segmented layer p21 of the low-resolution character layer p20 shown in Figure 11(c) is a segmented layer that does not contain characters. In this case, the number of transparent pixels (the sheet portion of the layer) should be set to the number of pixels corresponding to super-resolution. The processing unit 103 can generate the high-resolution segmented layer P21 shown in Figure 12(a) by increasing the number of transparent pixels without performing convolution processing by inference using the processing core. Alternatively, the low-resolution segmented layer p41 of the low-resolution background layer p40 shown in Figure 11(c) is a segmented layer where the background pixels have the same color. In this case, the number of pixels of the same color should be set to the number of pixels corresponding to super-resolution. The processing unit 103 can generate the high-resolution segmented layer P41 shown in Figure 12(a) by increasing the number of pixels of the same color without performing convolution processing using the processing core. In cases where there are no objects within the low-resolution segmented layer, or where all backgrounds within the low-resolution segmented layer are the same color, the convolution process by the processing device 103 can be omitted, thereby reducing the processing load.

[0043] Whether or not to set a blank (-) as the model identifier in the subdivision layer information 75 (Figure 13) can be selected as appropriate. If a blank is not set, a model identifier will be set for the subdivision layers even if there are no objects in the low-resolution subdivision layers, or if all the background colors in the low-resolution subdivision layers are the same color, and the convolution process using the computing core will be executed.

[0044] When the information processing device 101 determines a trained model suitable for super-resolution processing of a divided layer, it may use a method for analyzing the divided layer or a method for using a trained model for determining an object or background, as described in the first embodiment, but it is preferable to use information about the types of layers that have been prepared in advance. Specifically, layers are categorized into objects such as text, patterns, and characters, and backgrounds, depending on the type of image they contain. Therefore, by determining a suitable pre-trained model according to the type of layer, the information processing device 101 can select a pre-trained model that can perform super-resolution processing with greater accuracy compared to methods that analyze divided layers or methods that use pre-trained models to determine objects or backgrounds. In this case as well, if a blank (-) is set as the model identifier for the divided layer information 75, it is necessary to determine whether there are any objects or backgrounds in the low-resolution divided layer, or whether all the backgrounds included in the low-resolution divided layer are the same color. Furthermore, if the layers are not categorized into objects or backgrounds, the information processing device 101 may classify the type of each layer through analysis or inference and determine a trained model suitable for the low-resolution divided layer.

[0045] The processing unit 103 reads the low-resolution segmented layer and the model identifier associated with the segmented layer from the segmented layer information 75 (Figure 13) stored in the storage device 102. Then, the processing unit 103 executes a process to generate a high-resolution segmented layer from the low-resolution segmented layer using the same method as the super-resolution processing of segmented images in the first embodiment. Low-resolution segmented layers are, for example, segmented layers p11 to p44 shown in Figure 11(c), and high-resolution segmented layers are, for example, segmented layers P11 to P44 shown in Figure 12(a). The processing unit 103 combines the high-resolution segmented layers to generate a high-resolution layer. The high-resolution layer is, for example, layers P10 to P40 shown in Figure 12(b). The processing unit 103 then superimposes high-resolution layers to generate a high-resolution image. The high-resolution image is, for example, image P11 shown in Figure 12(c).

[0046] Figure 14 is a functional block diagram showing an example of the arithmetic processing system of the second embodiment. The calculation processing system of the second embodiment will be described with reference to Figure 14. The arithmetic processing system 100 of the second embodiment differs from the arithmetic processing system 100 of the first embodiment (Figure 6) only partially; therefore, the differences will be explained primarily, and the common components will be omitted from the explanation. The processing of the information processing device 101 in the second embodiment will be described. The memory unit 70 stores layer information 74 and divided layer information 75 (Figure 13) instead of the image information 72 and divided image information 73 of the first embodiment. Layer information 74 stores information about the layers used to draw the image. Specifically, layer information 74 stores the layer and its type (text, patterns, objects such as characters, background) in association with each other. As shown in Figure 13, the divided layer information 75 stores the divided layer and the model identifier corresponding to the divided layer, associated with the low-resolution layer before division and its type based on the layer information 74. The low-resolution layers are, for example, layers p10 to p40 shown in Figure 11(b). The model identifier is the identifier of the trained model used for super-resolution processing of the divided layer, as determined by the decision unit 62. The divided layers are low-resolution divided layers generated by the dividing unit 61 by dividing the layers stored in the layer information 74, for example, the divided layers p11 to p44 shown in Figure 11(c). Since super-resolution processing is possible for the divided layers as long as the divided layers are associated with model identifiers, the layers before division and their types based on the layer information 74 do not need to be included in the divided layer information 75.

[0047] The decision unit 62 determines, based on the type of low-resolution layer before division, a trained model to be used for super-resolution processing of the low-resolution division layer from the model information 71 shown in Figure 7. In this case, based on the type of low-resolution layer before splitting, the trained model to be used may be determined considering the processing load and image quality for each trained model as described above. The association unit 63 associates the model identifier of the trained model determined by the decision unit 62 with the low-resolution segmented layer and stores it in the segmented layer information 75 (Figure 13). Furthermore, the trained model to be used for each segmented layer may not be determined by the information processing device 101, but rather by the user of the information processing device 101, who may decide and register it in the segmented layer information 75. The information processing device 101 may be equipped with an editing unit that uses an input device such as a keyboard to register the information in the segmented layer information 75. The writing unit 64 stores the divided layer information 75 in the storage device 102.

[0048] The processing of the arithmetic processing unit 103 in the second embodiment will be described. The control unit 10 includes a synthesis unit 15 in addition to the configuration of the first embodiment. The storage unit 80 stores calculation result information 83 instead of calculation result information 82 in the first embodiment. Then, the control unit 10 performs the following processing. The reading unit 11 reads out the low-resolution divided layer and the model identifier associated with the low-resolution divided layer from the divided layer information 75. The selection unit 12 refers to the model identifier read by the reading unit 11 and selects a trained model to be used for super-resolution processing from the model information 81 shown in Figure 14. The output unit 13 reads the trained model selected by the selection unit 12 from the model information 81. Then, the output unit 13 outputs the weights to be used in the convolution process to the computation core of the computation unit 90, according to the trained model. Furthermore, the output unit 13 outputs the input data corresponding to the division layer to the computation core of the computation unit 90, according to the trained model. The calculation unit 90 performs a convolution operation using the input weights and input data.

[0049] The reading unit 11 reads the convolution calculation results from each calculation core of the calculation unit 90 according to the trained model and stores them in the calculation result information 83. As a result, the calculation result information 83 stores the calculation result obtained by convolution processing using the input data corresponding to the low-resolution segmented layer in each calculation core. The coupling unit 14 reads the calculation results from the calculation result information 83 according to the trained model and generates high-resolution segmented layers. The high-resolution segmented layers are, for example, the segmented layers P11 to P44 shown in Figure 12(a). The joining unit 14 then combines the high-resolution segmented layers to generate a high-resolution layer. The high-resolution layer is, for example, the layers P10 to P40 shown in Figure 12(b), which are generated by combining segmented layers P11 to P14, segmented layers P21 to P24, segmented layers P31 to P34, and segmented layers P41 to P44, respectively.

[0050] The compositing unit 15 combines high-resolution layers to generate a high-resolution image. The high-resolution image is, for example, image P11 shown in Figure 12(c), which is generated by superimposing layers P10 to P40. If each pixel of the low-resolution layers p10 to p40 has a set transparency, the compositing unit 15 may also apply the transparency to the corresponding pixels of the high-resolution layers P10 to P40 and perform the compositing process (alpha blending). As described above, in the second embodiment, the arithmetic processing unit 103 selects a trained model suitable for the divided layer and performs super-resolution processing. Therefore, the accuracy of super-resolution processing by the arithmetic processing unit 103 using the arithmetic core can be improved.

[0051] Although the flowchart in Figure 9 describes the processing by the information processing device of the first embodiment, the information processing device 101 of the second embodiment can perform the following processing: in step S101, a low-resolution image is divided into low-resolution layers to generate low-resolution divided layers; in step S102, the type of divided layer is identified; in step S103, the divided layer is associated with a model identifier; and in step S104, the divided layer information 75 is stored in the storage device 102. Furthermore, while the flowchart in Figure 10 illustrates the processing performed by the arithmetic processing unit 103 in the first embodiment, the processing performed by the arithmetic processing unit 103 in the second embodiment includes reading the low-resolution segmented layer in step S201, selecting a trained model corresponding to the low-resolution segmented layer based on the segmented layer information 75 in step S202, and performing super-resolution processing on the low-resolution segmented layer using the trained model in step S203.

[0052] [Third Embodiment] The arithmetic processing system 100 of the third embodiment has the same configuration as the arithmetic processing system 100 of Figure 1. The third embodiment is similar to the first embodiment in that the arithmetic processing unit 103 applies an appropriate trained model to each segmented image to perform super-resolution processing, but the processing by the information processing unit 101 differs from that of the first embodiment. In the third embodiment, the information processing device 101 generates a low-resolution segmented layer for each low-resolution layer used to generate an image, and determines the characteristics of each low-resolution segmented layer (objects and background included in the segmented layer). The information processing device 101 also determines a trained model to be used for super-resolution processing of the low-resolution segmented images in the corresponding region, based on the characteristics of the low-resolution segmented layers that are superimposed at the same position during synthesis. In the arithmetic processing system 100 of the second embodiment described above, super-resolution processing is performed on the entire layer to synthesize a high-resolution layer, thus enabling high-precision high-resolution processing. On the other hand, because the area to be super-resolution processed is large, the processing load on the arithmetic processing unit 103 was large. In contrast, the arithmetic processing system 100 of the third embodiment reduces the load of super-resolution processing by performing super-resolution processing on each segmented image obtained by dividing the image into layers, similar to the first embodiment. Furthermore, it can perform super-resolution processing on the segmented images with high accuracy by using a trained model that is suitable for the characteristics of the segmented layers that make up each segmented image.

[0053] The information processing device 101 generates a low-resolution image by combining low-resolution layers. The information processing device 101 also generates low-resolution segmented images by dividing the low-resolution image. The information processing device 101 associates the identifier of the trained model used in the super-resolution processing, which was determined in the process of determining the trained model, with the low-resolution segmented images. The arithmetic processing unit 103 performs super-resolution processing using a trained model (Figure 8) corresponding to the identifier of the trained model, similar to the first embodiment. Specifically, the arithmetic processing unit 103 performs super-resolution processing on each low-resolution segmented image using the trained model determined by the information processing unit 101. Then, the arithmetic processing unit 103 combines the high-resolution segmented images to generate a high-resolution image.

[0054] In the third embodiment, the arithmetic processing system 100 determines the features of the low-resolution divided image using the features of the low-resolution divided layer obtained from the types of low-resolution layers known in advance. Therefore, compared to the arithmetic processing system 100 of Embodiment 1, which directly analyzes the divided image containing multiple objects or backgrounds to determine the features of the divided image, the accuracy of determining the features of the low-resolution divided image is improved. Accordingly, the arithmetic processing system 100 can select a more suitable trained model for each low-resolution segmented image compared to the arithmetic processing system 100 of the first embodiment. Therefore, the arithmetic processing system of the third embodiment can further improve the accuracy of super-resolution processing compared to the first embodiment. In the following description, configurations and information common to both the first and second embodiments will be omitted as appropriate. Furthermore, configurations and information similar to those in the first and second embodiments will be explained using the drawings used in the descriptions of the first and second embodiments as needed.

[0055] Figure 15 illustrates the super-resolution processing of the third embodiment. Figure 16 shows the segmented layer information, which correlates the characteristics of low-resolution segmented layers with those of low-resolution segmented layers. Figure 17 shows segmented image information associated with the segmented images and the trained model. Figure 18 shows model information, which associates the trained model with the model identifier.

[0056] The calculation processing system of the third embodiment will be described with reference to Figures 15 to 18. The low-resolution image is, for example, the low-resolution image p00 shown in Figures 11(a) and 15(a). The low-resolution layer is a layer for compositing low-resolution images, and is, for example, the low-resolution layers p10 to p40 shown in Figure 11(b). The information processing device 101 of the third embodiment divides a low-resolution layer to generate low-resolution divided layers. The low-resolution divided layers are, for example, the divided layers p11 to p44 shown in Figure 11(c). The information processing device 101 determines the characteristics of each low-resolution segmented layer and stores the segmented layer information 76 (Figure 16) by associating each low-resolution segmented layer with the characteristics of the low-resolution segmented layer. In Figure 16, the transparency of the low-resolution segmented layer indicates that when the type of the low-resolution layer from which the low-resolution segmented layer is derived is "object," the low-resolution segmented layer does not contain any objects. Furthermore, the fact that the characteristics of the low-resolution segmented layer are the same color indicates that when the type of low-resolution layer from which the low-resolution segmented layer originates is "background," the pixels within the low-resolution segmented layer are the same color.

[0057] For example, the divided layer p21 shown in Figure 11(c) is derived from the original layer p20, which contains text, but the divided layer p21 does not contain any text. In other words, the divided layer p21 contains only transparent pixels (the sheet portion of the layer). Therefore, the information processing device 101 determines that the characteristics of the divided layer p21 are transparent. Furthermore, although the original layer p40 in Figure 11(c) is a background, the pixels contained within the divided layer p41 are the same color. Therefore, the information processing device 101 determines that the characteristics of the divided layer p41 are the same color. However, whether or not to set transparency or same color as the features of the divided layer information 76 may be selected as appropriate. If transparency or same color is not set, the features of the divided layer information 76 will store, for example, features corresponding to the type of the original low-resolution layer, even when there are no objects or backgrounds in the low-resolution divided layer, and when all the background colors included in the low-resolution divided layer are the same color. In the following explanation, we will assume that transparency or same color is set as the features of the divided layer information 76.

[0058] When the information processing device 101 determines the characteristics of a low-resolution segmented layer, it may use the methods described above, such as "scene analysis" or "image comparison," as explained using the low-resolution image of the first embodiment. However, it is preferable to use information about the types of low-resolution layers that have been prepared in advance. Specifically, the layers before splitting are classified into objects such as text, patterns, and characters, and backgrounds, depending on the type of image contained in the layer. Therefore, the information processing device 101 can determine the characteristics of the split layers with greater accuracy compared to the scene analysis and pre-trained model methods described above, by determining the characteristics of the low-resolution split layers according to the type of low-resolution layer.

[0059] Even in this case, in order to set transparency or same-color features in the divided layer information 76, it is necessary to determine whether there are no objects or backgrounds in the low-resolution divided layer, or whether all background colors included in the low-resolution divided layer are the same color. Furthermore, if the layers are not classified into objects such as text, patterns, characters, etc., and backgrounds based on the type of image they contain, the information processing device 101 may determine the type of each layer through analysis or inference and then determine the features of the low-resolution divided layer. Determining the type of layer is easier than determining the type of a composite image containing multiple objects or backgrounds, because each layer contains only one type of object or background, and accurate classification is possible. For this reason, the information processing device 101 can perform the processing of the third embodiment even if classification information for the types of layers is not prepared in advance.

[0060] The information processing device 101 further determines the characteristics of the low-resolution segmented image from the characteristics of the low-resolution segmented layer stored in the segmented layer information 76 (Figure 16), and determines a trained model corresponding to the characteristics of the low-resolution segmented image. Specifically, the information processing device 101 determines the characteristics of the low-resolution segmented image from the characteristics of the low-resolution segmented layer in the same region as the low-resolution segmented image. Then, according to the characteristics of the low-resolution segmented image, the information processing device 101 determines a trained model suitable for super-resolution processing of the low-resolution segmented image.

[0061] More specifically, the information processing device 101 refers to the features of the divided layers p11, p21, p31, and p41 shown in Figure 11(c) and determines the features of the divided image p51 shown in Figure 15(b), which is an image formed by superimposing the divided layers p11, p21, p31, and p41. Referring to the segmented layer information 76 (Figure 16), the information processing device 101 determines that the segmented image p51 best reflects the characteristics of the pattern, as segmented layer p11 has the characteristic of a pattern, segmented layers p21 and p31 have the characteristic of transparency, and segmented layer p41 has the characteristic of the same color. Referring to the model information 71 (Figure 7), the information processing device 101 associates the model identifier IB of the trained model LB suitable for the pattern with the segmented image p51, as shown in Figure 17, and stores it in the segmented image information 77.

[0062] The information processing device 101 refers to the features of the divided layers p12, p22, p32, and p42 shown in Figure 11(c) and determines the features of the divided image p52 shown in Figure 15(b), which is an image formed by superimposing the divided layers p12, p22, p32, and p42. Referring to the segmented layer information 76 (Figure 16), the information processing device 101 determines that the segmented image p52 best reflects the characteristics of the pattern, as the features of segmented layer p12 are a pattern, the features of segmented layers p22 and p32 are transparency, and the features of segmented layer p42 are the same color. Then, referring to the model information 71 (Figure 7), the information processing device 101 associates the model identifier IB of the trained model LB suitable for the pattern with the segmented image p52, as shown in Figure 17, and stores it in the segmented image information 77.

[0063] The information processing device 101 refers to the features of the divided layers p13, p23, p33, and p43 shown in Figure 11(c) and determines the features of the divided image p53 shown in Figure 15(b), which is an image formed by superimposing the divided layers p13, p23, p33, and p43. Referring to the divided layer information 76 (Figure 16), the features of divided layer p13 are a pattern, the features of divided layer p23 are characters, the features of divided layer p33 are transparency, and the features of divided layer p43 are background. Therefore, the information processing device 101 analyzes the divided image and determines the features that are most reflected in the divided image p53. In this case, the information processing device 101 may, for example, use the "scene analysis" or "image comparison" described above to determine which feature is most reflected in the divided image p53. In this case, the information processing device 101 determines whether the feature most reflected in the divided image p53 is a pattern, text, or background, based on the features of the divided layers p13, p23, and p43. Therefore, since the information processing device 101 narrows down the types of images included in the divided image p53 before analysis, it can accurately determine which feature is most reflected in the divided image p53.

[0064] Alternatively, the information processing device 101 may determine the feature most reflected in the segmented image p53 by performing inference processing using a trained model for determining objects or backgrounds included in the segmented image. In this case, the information processing device 101 uses a trained model suitable for determining whether the feature most reflected in the segmented image p53 is a pattern, text, or background, based on the features of segmented layers p13, p23, and p43. Therefore, since the information processing device 101 narrows down the types of images included in the segmented image p53 in advance before performing inference, it can accurately determine the feature most reflected in the segmented image p53. If the information processing device 101 determines that the feature most reflected in the segmented image p53 is the background, it refers to the model information 71 (Figure 7), associates the model identifier IC of the trained model LC suitable for the background with the segmented image p53, and stores it in the segmented image information 77 (Figure 17).

[0065] Referring to the divided layer information 76 (Figure 16), the features of divided layer p13 are a pattern, the features of divided layer p23 are characters, the features of divided layer p33 are transparency, and the features of divided layer p43 are background. Therefore, the information processing device 101 analyzes the divided image and determines the features that are most reflected in the divided image p53.

[0066] The information processing device 101 refers to the features of the divided layers p14, p24, p34, and p44 shown in Figure 11(c) and determines the features of the divided image p54 shown in Figure 15(b), which is an image formed by superimposing the divided layers p14, p24, p34, and p44. Referring to the divided layer information 76 (Figure 16), the features of divided layer p14 are patterns, the features of divided layer p24 are characters, the features of divided layer p34 are characters, and the features of divided layer p44 are backgrounds. Therefore, the information processing device 101 analyzes the divided image and determines the features that are most reflected in the divided image p54. In this case, the information processing device 101 may, for example, use the "scene analysis" or "image comparison" described above to determine the feature that is most reflected in the divided image p54. In this case, the information processing device 101 determines from the features of the divided layers p14, p24, p34, and p44 whether the feature that is most reflected in the divided image p54 is text, a pattern, a character, or a background. Therefore, since the information processing device 101 narrows down the types of images included in the divided image p54 in advance before analysis, it can accurately determine the feature that is most reflected in the divided image p54.

[0067] Alternatively, the information processing device 101 may determine the feature most reflected in the segmented image p54 by performing inference processing using a trained model for determining objects or backgrounds included in the segmented image. In this case, the information processing device 101 uses a trained model suitable for determining whether the feature most reflected in the segmented image p54 is text, a pattern, a character, or a background, based on the features of the segmented layers p14, p24, p34, and p44. Therefore, since the information processing device 101 narrows down the types of images included in the segmented image p54 in advance before performing inference, it can accurately determine the feature most reflected in the segmented image p54. If the information processing device 101 determines that the feature most reflected in the segmented image p54 is a character, it refers to the model information 71 (Figure 7), associates the model identifier ID of a trained model LD suitable for the character with the segmented image p54, and stores it in the segmented image information 77 (Figure 17).

[0068] Furthermore, when the information processing device 101 determines an object or background included in a divided image, it may weight the object or background according to the degree to which it attracts the user's attention, and then determine the feature that is most reflected in the divided image. More specifically, the information processing device 101 may, for example, weight characters, letters, patterns, and backgrounds in that order, and then perform analysis and inference to determine the object or background included in the divided image.

[0069] Furthermore, as shown in Figure 18, the information processing device 101 may prepare multiple pre-trained models for use in super-resolution processing and use a pre-trained model appropriate to the characteristics of the low-resolution segmented layer that forms the basis of the low-resolution segmented images. Specifically, the information processing device 101 stores the model information 78 shown in Figure 18. Referring to the segmented layer information 76 (Figure 16), for example, the features of the segmented layers p13, p23, p33, and p43, which are the source of the segmented image p53, include patterns, characters, and backgrounds. In this case, the information processing device 101 determines, for example, that the more reflected features are patterns and backgrounds, and decides to use the trained model LH ​​corresponding to patterns and backgrounds from the model information 78. If the information processing device 101 determines that the more reflected features include characters, it may decide to use the trained model IA that includes characters in a suitable object.

[0070] Since the features of the segmented layers p14, p24, p34, and p44, which form the basis of the segmented image p53, include text, patterns, characters, and backgrounds, the information processing device 101 decides to use, for example, a general-purpose pre-trained IK model. If the low-resolution segmented layer that forms the basis of the low-resolution segmented image has two types of features, the information processing device 101 may determine which trained model to use from among trained models suitable for two types of objects or backgrounds. If the low-resolution segmented layer that forms the basis of the low-resolution segmented image has three types of features, the information processing device 101 may, depending on the degree to which it is likely to attract the user's attention, prioritize in the order of characters, letters, patterns, and backgrounds, and then determine which pre-trained model to use from among the pre-trained models suitable for the top two types of objects or backgrounds.

[0071] Furthermore, if the low-resolution segmented layers that form the basis of the low-resolution segmented images have three types of features, the information processing device 101 may determine which trained model to use from among two types of trained models suitable for objects or backgrounds, depending on the number of segmented layers that contain the same features. Specifically, the information processing device 101, considering the four low-resolution segmented layers, decides to use a pre-trained model LJ suitable for the background and character, taking into account the aforementioned degree of user attention. Alternatively, the information processing device 101 may decide to use a general-purpose pre-trained IK model if there are three types of features in the segmentation layer that forms the basis of the low-resolution segmented image.

[0072] Then, the information processing device 101 stores the segmented image information 77 created as described above in the storage device 102. The arithmetic processing unit 103 reads the low-resolution segmented images and the model identifiers associated with the low-resolution segmented images from the segmented image information 77 stored in the storage device 102. Then, the arithmetic processing unit 103 executes a process to generate high-resolution segmented images from the low-resolution segmented images using a method similar to the super-resolution processing of the low-resolution segmented images in the first embodiment. The low-resolution segmented images are, for example, the segmented layers p51 to p54 shown in Figure 15(b). The high-resolution segmented images are, for example, the segmented images P51 to P54 shown in Figure 15(c). The processing unit 103 selects a trained model to be used for super-resolution processing from the model information 81 by referring to the model identifier associated with the low-resolution segmented image. However, if the information processing unit 101 has determined the trained model using the model information 78 (Figure 18), the processing unit 103 stores the model information 78 as model information 83 and selects a trained model to be used for super-resolution processing from the model information 83. The processing unit 103 combines high-resolution segmented images to generate a high-resolution image. The high-resolution image is, for example, image P11 shown in Figure 15(d).

[0073] Figure 19 is a functional block diagram showing an example of the arithmetic processing system of the third embodiment. Referring to Figure 19, the arithmetic processing system 100 of the third embodiment will be described. In the following description, the differences from the arithmetic processing system 100 of the first embodiment will be explained, and descriptions of similar processes will be omitted as appropriate. The processing of the information processing device 101 in the third embodiment will be described. The storage unit 70 stores layer information 74, divided layer information 76, and divided image information 77 in place of the image information 72 and divided image information 73 of the first embodiment. Layer information 74 stores information about low-resolution layers for rendering low-resolution images. Specifically, layer information 74 stores the low-resolution layer and the type of low-resolution layer (objects such as text, patterns, characters, or backgrounds) in association with each other.

[0074] As shown in Figure 16, the segmented layer information 76 stores the characteristics of the low-resolution segmented layer and the low-resolution segmented layer in association with each other. The divided layer information 76 stores the divided layer and its characteristics, based on the layer information 74, and associated with the low-resolution layer before division and its type. The low-resolution layer is, for example, layer p10 to p40 shown in Figure 11(b). The characteristics of the divided layer are those determined by the determination unit 62. The divided layer is a low-resolution divided layer generated by the division unit 61 by dividing the layer stored in the layer information 74, and is, for example, the divided layers p11 to p44 shown in Figure 11(c). Since super-resolution processing is possible for the divided layers if the divided layers are associated with feature model identifiers, the layers before division and their types do not need to be included in the divided layer information 76.

[0075] The compositing unit 65 combines low-resolution layers to generate a low-resolution image. The low-resolution image is, for example, image p00 shown in Figures 11(a) and 15(a), and is generated by superimposing layers p10 to p40 shown in Figure 11(b). If each pixel of the low-resolution layers p10 to p40 has a set transparency, the compositing unit 65 may apply the transparency and perform the compositing process (alpha blending).

[0076] The splitting unit 61 splits the low-resolution image synthesized in the combining unit 65 to generate low-resolution segmented images. For example, the splitting unit 61 splits the low-resolution image p00 shown in Figure 11(a) and Figure 15(a) to generate low-resolution segmented images p51 to p54 shown in Figure 15(b). The decision unit 62 determines the characteristics of the low-resolution segmented layer. Then, using the determined characteristics of the low-resolution segmented layer, the decision unit 62 determines a trained model to be used in the super-resolution processing of the low-resolution segmented image. As described above, the decision unit 62 determines the characteristics of the low-resolution segmented layer according to the type of low-resolution layer from which the low-resolution segmented layer is derived. Also, as described above, the decision unit 62 determines the characteristics of the low-resolution segmented layer in the same region as the low-resolution segmented image that are most reflected in the low-resolution image. Then, according to the determined characteristics, the decision unit 62 determines a trained model to be used in the super-resolution processing of the low-resolution segmented image. As shown in the segmented image information 77 of Figure 17, the association unit 63 associates the trained model determined by the determination unit 62 for each low-resolution segmented image with the low-resolution segmented image. In this case, the decision unit 62 may determine which trained model to use based on the content of the divided images, taking into consideration the processing load and image quality of each trained model as described above. Furthermore, the trained model to be used for each segmented image is not determined by the information processing device 101, but rather by the user of the information processing device 101, who makes the decision based on the content of the segmented image and the processing load and image quality of each trained model, and registers it in the segmented image information 77. The information processing device 101 may be equipped with an editing unit that uses an input device such as a keyboard to register the segmented image information 77. The writing unit 64 stores the segmented image information 77 in the storage device 102.

[0077] The processing of the arithmetic processing unit 103 of the third embodiment will be described. The arithmetic processing unit 103 of the third embodiment has the same configuration as the arithmetic processing unit 103 of the first embodiment. The arithmetic processing unit 103 of the third embodiment generates a high-resolution image by performing the same processing as the arithmetic processing unit 103 of the first embodiment. Specifically, the processing unit 103 of the third embodiment reads the segmented layer information 76 (Figure 16) from the storage device 102, selects a trained model to be used for super-resolution processing of the low-resolution segmented image, and executes the super-resolution processing.

[0078] As described above, the arithmetic processing system 100 of the third embodiment determines the trained model to be used when performing super-resolution processing on low-resolution segmented images, according to the type of low-resolution layer used to synthesize the images before segmentation of the low-resolution segmented images. The types of low-resolution layers are known information in the field of image processing. Therefore, compared to the configuration of the first embodiment, which analyzes segmented images containing multiple objects or backgrounds as they are, the information processing device 101 of the third embodiment can accurately determine the features of the segmented images. Compared to the arithmetic processing unit of the first embodiment, the arithmetic processing unit of the third embodiment can select a more suitable trained model for super-resolution processing on segmented images, thereby improving the accuracy of super-resolution processing by the arithmetic processing unit 103 using the arithmetic core.

[0079] Although the flowchart in Figure 9 illustrates the processing by the information processing device of the first embodiment, the information processing device 101 of the third embodiment can perform the following processing: in step S101, a low-resolution image is divided into low-resolution layers to generate low-resolution divided layers; in step S102, the type of divided layer is identified; in step S103, the divided image formed by combining the divided layers is associated with a model identifier; and in step S104, the divided layer information is stored in the storage device 102. Furthermore, although the flowchart in Figure 10 illustrates the processing by the arithmetic processing device 103 of the first embodiment, the arithmetic processing device 103 of the third embodiment can perform the following processing: in step S201, a low-resolution divided image is read; in step S202, a trained model corresponding to the low-resolution divided image is selected; and in step S203, super-resolution processing is performed on the low-resolution divided image using the trained model.

[0080] The processing unit 103 of this embodiment can perform super-resolution processing with high accuracy by switching the trained model applied to each processing core according to the type and characteristics of the image to be processed. Performing scene analysis, image comparison, and inference using the trained model described above in the control circuit 10 of the arithmetic processing unit 103 to determine the type and features of the image to be processed in order to select a trained model is computationally intensive and difficult. In contrast, in this embodiment, the information processing unit 101 automatically or by user judgment determines and pre-assigns an identifier for the trained model to be used for the image. Therefore, in this embodiment, the control circuit 10 of the arithmetic processing unit 103 can perform super-resolution processing with high accuracy according to the type and features of the image to be processed by simply performing processing using the trained model based on the identifier supplied from the information processing unit 101 in each processing core, without determining the type or features of the image.

[0081] As explained above, pre-trained models are provided for each super-resolution processing load (image quality). In this embodiment, depending on the image being processed, the total load of the pre-trained models associated with the segmented images and segmented layers contained in the image may exceed the processing capacity of the arithmetic processing unit 103. In that case, the control circuit 10 of the arithmetic processing unit 103 may switch to a lower-load (lower-resolution) trained model for segmented images and segmented layers that include lower-priority objects or backgrounds, so that the total load fits within the processing content of the arithmetic processing unit 103.

[0082] The arithmetic processing system 100 of this embodiment can be applied to various devices. For example, the arithmetic processing system 100 can be applied to a gaming machine. Figure 20 shows a schematic diagram of the gaming machine's configuration. As shown in Figure 20, the gaming machine U comprises a main control board (main board) 1A, a performance control board (sub-board) 2A, an external storage device 3, and a display device 4. The main control board 1A is equipped with the main control unit (main CPU) 1. The performance control board 2A is equipped with the performance control device 2 (sub-CPU). Game machine U is, for example, a pachinko game machine that uses game balls as the game medium. The main control board 1A and the performance control board 2A, the performance control board 2A and the external storage device 3, and the performance control board 2A and the display device 4 are all connected in a way that allows them to communicate with each other. The performance control device 2 executes various performances of the gaming machine U based on commands input from the main control board 1A.

[0083] External storage device 3 is an external storage device connected to a memory interface (not shown) provided by the performance control device 2, and is, for example, an SSD (Solid State Drive) or ROM. External storage device 3 functions as storage device 102 in Figures 6, 14, and 19, for example. External storage device 3 stores various performance data used for the game machine U's effects, as well as the boot loader and basic software such as the OS (Operating System) for starting the performance control device 2. The performance control device 2 reads image data from the external storage device 3 in response to a command from the main control device 1 and draws the image. The performance control device 2 uses the drawn image to create a display image to be shown on the display device 4. The performance control device 2 outputs the display image to the display device 4 and displays the image on the display device 4.

[0084] Figure 21 is a diagram showing the configuration of the performance control device. In Figure 21, the performance control device 2 comprises at least a central control CPU 110, a storage device 111, an arithmetic circuit 112, and an input / output interface 113. Each component is connected by a bus 114. An external storage device 3 is connected to the performance control device 2 via an input / output I / F 113. Furthermore, a display device 4 is connected to the performance control device 2 via an interface (not shown). The arithmetic processing unit 103 of the present invention can be configured by appropriately selecting some or all of the components described in the performance control device 2. The overall control CPU 110 controls the entire performance control device 2. For example, in Figures 6, 14, and 19, the overall control CPU 110 functions as the control unit 10. The integrated control CPU 110 receives commands from the main control unit 1 and determines the content of the performance according to the commands. The integrated control CPU 110 controls the arithmetic circuit 112 and controls the display of images to realize the determined performance content. The storage device 111 is a non-temporary recording medium such as ROM (Read Only Memory) and RAM (Random Access Memory). The storage device 111 functions as the memory unit 80 in Figures 6, 14, and 19, for example. The storage device 111 is also used as a work area by the arithmetic circuit 112 and the overall control CPU 110. The storage device 111 may store a arithmetic processing program that causes the overall control CPU 110 to function as the control unit 10. The arithmetic processing program may be stored in the external storage device 3. In this case, when the integrated control CPU 110 executes the arithmetic processing program, it reads the program from the external storage device 3 and stores it in the storage device 111. The integrated control CPU 110 then executes the program read from the storage device 111, thereby performing arithmetic processing that includes one or more of the following: reading, selection, output, integration, and synthesis.

[0085] When the arithmetic circuit 112 receives image data for performance from the overall control CPU 110, it performs super-resolution processing, including convolution. The arithmetic circuit 112 functions as the arithmetic unit 90 in Figures 6, 14, and 19, for example. The performance control device 2, having the above-described functions, can apply, for example, super-resolution processing when displaying image data on the display device 4. Furthermore, the performance control device 2 having the configuration shown in Figure 21 can be used not only in amusement machines but also in other amusement machines, game machines, digital signage, and other general equipment that have a display device. It can also be incorporated into a monitor device that connects to an external device for display. In that case, the main control unit 1 is not included in the configuration shown in Figure 21, and image data input from an external device such as a PC connected via the input / output I / F 113 can be displayed after, for example, super-resolution processing is applied to it.

[0086] Figure 22 is a block diagram showing one embodiment of a computer device. The configuration of the computer device 200 will be described with reference to Figure 22.

[0087] In Figure 22, the computer device 200 includes a control circuit 201, a storage device 202, a reading device 203, a recording medium 204, a communication interface 205, an input / output interface 206, an input device 207, and a display device 208. Each component is connected by a bus 209. The communication interface 205 is connected to a network 210. The information processing device 101 can be configured by appropriately selecting some or all of the components described in the computer device 200.

[0088] The control circuit 201 controls the entire computer device 200. The control circuit 201 is a processor such as a CPU (Central Processing Unit), a multi-core CPU, an FPGA (Field Programmable Gate Array), and a PLD (Programmable Logic Device). The control circuit 201 functions as the control unit 60, for example, in Figures 6, 14, and 19.

[0089] The storage device 202 stores various types of data. The storage device 202 can be, for example, memory such as ROM and RAM, or a hard disk (HD) or solid state drive (SSD). In Figures 6, 14, and 19, the storage device 202 functions as the storage unit 70.

[0090] Furthermore, the ROM stores programs such as the boot program. The RAM is used as the work area for the control circuit 201. The HD or SSD stores programs such as the OS, application programs, firmware, and various data. The storage device 202 may store an information processing program that enables the control circuit 201 to function as the control unit 60.

[0091] When the computer device 200 performs information processing, it reads the program stored in the memory device 202 into RAM. The computer device 200 then executes the program read into RAM using the control circuit 201, thereby performing information processing that includes one or more of the following: partitioning, decision-making, association, writing, and synthesis.

[0092] Furthermore, each of the above programs may be stored in a memory device on a server on the network 210, provided that the control circuit 201 can access it via the communication interface 205.

[0093] The reading device 203 is controlled by the control circuit 201 and performs data reading and writing to the removable recording medium 204. The reading device 203 can be, for example, an FDD (Floppy Disk Drive), CDD (Compact Disc Drive), DVDD (Digital Versatile Disk Drive), BDD (Blu-ray® Disk Drive), or USB (Universal Serial Bus).

[0094] The recording medium 204 stores various types of data. The recording medium 204 is connected to the bus 209 via a reading device 203, and data is read / written by the control circuit 201 controlling the reading device 203. The recording medium 204 stores, for example, an information processing program.

[0095] Furthermore, the recording medium 204 is a non-temporary recording medium such as an SD memory card, floppy disk, compact disc, digital versatile disc, Blu-ray disc, and flash memory. The recording medium 204 functions as a storage device 102, for example, in Figures 6, 14, and 19.

[0096] The communication interface 205 connects the computer device 200 to other devices via the network 210, enabling communication between them. The communication interface 205 may also include an interface with wireless LAN functionality and an interface with short-range wireless communication functionality.

[0097] The input / output interface 206 is connected to input devices 207, such as a keyboard, mouse, and touch panel. When signals indicating various information are input from the connected input devices 207, the input / output interface 206 outputs the input signals to the control circuit 201 via the bus 209. Conversely, when signals indicating various information output from the control circuit 201 are input to the input / output interface 206 via the bus 209, the input / output interface 206 outputs those signals to the connected devices.

[0098] The display device 208 displays various information. The display device 208 may also display information for accepting input via the touch panel. Furthermore, the input / output interface 206, input device 207, and display device 208 may function as a GUI (Graphical User Interface). This allows the computer device 200 to accept intuitive operation via a touch panel, mouse, or the like.

[0099] The network 210 is, for example, a LAN, wireless communication, or the internet, and connects the computer device 200 to other devices for communication. This embodiment is not limited to the embodiments described above, and various configurations or embodiments can be taken without departing from the spirit of this embodiment. [Explanation of Symbols]

[0100] 100 Arithmetic processing system, 10 Control circuit, 20 Arithmetic core, 21 Weight memory, 22 Data memory, 23 Address generator, 24 Weight output unit, 25 Data output unit, 26 Arithmetic unit, 27 Output memory, 28 Arithmetic result output unit, 30 Arithmetic core, 31 Weight memory, 32 Data memory, 35 Data output unit, 36 Arithmetic unit, 37 Output memory, 38 Arithmetic result output unit, 40 Arithmetic core, 41 Weight memory, 42 Data memory, 45 Data output unit, 46 Arithmetic unit, 47 Output memory, 48 Arithmetic result output unit, 50 Arithmetic core, 51 Weight memory, 52 Data memory, 55 Data output unit, 56 Arithmetic unit, 57 Output memory, 58 Arithmetic result output unit

Claims

1. Multiple computing cores, each containing multiple computing units that perform operations according to a trained model on segmented images obtained by dividing an image, A memory unit that stores multiple trained models, A selection unit that selects a pre-trained model corresponding to the segmented image on which the calculation is performed for each of the multiple calculation cores, An output unit that outputs control information corresponding to the selected trained model to each of the multiple computing cores and causes the calculation to be performed for each segmented image, A processing unit characterized by comprising:

2. The segmented images are stored in a memory device in association with the identification information of the trained model used in the calculation. The arithmetic processing unit includes a reading unit that reads the divided image and the identification information associated with the divided image from the storage device, The selection unit selects the trained model according to the identification information read out. The arithmetic processing device according to feature 1.

3. The aforementioned selection unit is Each of the aforementioned computing cores selects a pre-trained model corresponding to the characteristics of the segmented image in which the calculation is performed, The features of the aforementioned segmented image are features that correspond to the content contained in the segmented image. The aforementioned trained model is a model trained using different training datasets for each type of image. The arithmetic processing device according to feature 1.

4. The aforementioned selection unit is Each of the aforementioned computing cores selects a pre-trained model corresponding to the calculation result required by the segmented image for which the calculation is performed, The aforementioned trained model is a model that has been trained to obtain computational results of a quality appropriate to the type of image. The arithmetic processing device according to feature 1.

5. The aforementioned image is an image generated by stacking layers, The aforementioned segmented image is an image obtained by dividing the layer, The aforementioned trained model is a model trained using a different training dataset for each type of image included in the layer. The arithmetic processing device according to feature 1.

6. The aforementioned image is an image generated by stacking layers, The aforementioned segmented image is an image obtained by dividing the layer, The aforementioned trained model is a model that has been trained to obtain computation results of a quality corresponding to the type of image included in the layer. The arithmetic processing device according to feature 1.

7. The aforementioned image is an image generated by stacking layers, The features of the divided image are determined according to the features of the original layer. The arithmetic processing device according to feature 1.

8. An arithmetic processing system including an information processing device, a memory device, and an arithmetic processing device, The aforementioned information processing device is A first memory unit stores multiple trained models that have been trained using different training datasets for each type of image, A determination unit that determines a pre-trained model to be used in calculations according to the characteristics of the divided images obtained by dividing the image, The system includes an association unit that associates identification information corresponding to the determined trained model with the segmented images, The storage device stores the identification information and the divided image in association, The aforementioned arithmetic processing unit is Multiple computing cores, each including multiple computing units that perform calculations on the segmented images according to a trained model, A second storage unit that stores the aforementioned multiple trained models, A reading unit that reads the divided image and the identification information associated with the divided image from the storage device, A selection unit that selects the trained model according to the retrieved identification information, An output unit that outputs control information corresponding to the selected trained model to each of the multiple computing cores and causes the calculation to be performed for each segmented image, A computing system characterized by comprising the following features.

9. A method of arithmetic processing performed by an arithmetic processing unit, The aforementioned arithmetic processing unit is It comprises multiple computing cores, each containing multiple computing units that perform operations according to a trained model on segmented images obtained by dividing an image, and a storage unit that stores multiple trained models trained using training datasets with different features. A computation method characterized by selecting a pre-trained model for each of the multiple computation cores that performs the computation according to the characteristics of the segmented image, outputting control information according to the selected pre-trained model to each of the multiple computation cores, and causing the computation to be performed for each segmented image.

10. A calculation processing program that causes a processor in a calculation processing unit to execute a calculation processing method, The aforementioned processing unit comprises a plurality of processing cores, each including a plurality of processing units that perform calculations according to a trained model on segmented images obtained by dividing an image, and a storage unit that stores a plurality of trained models trained using training datasets with different characteristics. The aforementioned processor, A computational processing program characterized by selecting a pre-trained model for each of the multiple computational cores that corresponds to the characteristics of the segmented image on which the computation is performed, outputting control information corresponding to the selected pre-trained model to each of the multiple computational cores, and causing the computation to be performed for each segmented image.

11. A memory unit that stores multiple trained models, A determination unit that determines the pre-trained model to be used in calculations according to the divided images obtained by dividing the image, The system includes an association unit that associates identification information corresponding to the determined trained model with the segmented images, An information processing device characterized by the following:

12. An information processing method performed by an information processing device, The aforementioned information processing device includes a storage unit that stores multiple trained models, Based on the features of the segmented images obtained by dividing the image, the trained model to be used in the calculation is determined. The identification information corresponding to the determined trained model is associated with the segmented image. An information processing method characterized by the following:

13. An information processing program that causes an information processing device to execute an information processing method on a processor, The aforementioned information processing device includes a storage unit that stores multiple trained models, The aforementioned processor, Based on the features of the segmented images obtained by dividing the image, the trained model to be used in the calculation is determined. The identification information corresponding to the determined trained model is associated with the segmented image. An information processing program characterized by the following features.

Images